| iommureg.h (139825) | iommureg.h (167308) |
|---|---|
| 1/*- 2 * Copyright (c) 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This software was developed by the Computer Systems Engineering group 6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 7 * contributed to Berkeley. 8 * --- 19 unchanged lines hidden (view full) --- 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * from: @(#)sbusreg.h 8.1 (Berkeley) 6/11/93 34 * from: NetBSD: iommureg.h,v 1.6 2001/07/20 00:07:13 eeh Exp 35 * | 1/*- 2 * Copyright (c) 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This software was developed by the Computer Systems Engineering group 6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 7 * contributed to Berkeley. 8 * --- 19 unchanged lines hidden (view full) --- 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * from: @(#)sbusreg.h 8.1 (Berkeley) 6/11/93 34 * from: NetBSD: iommureg.h,v 1.6 2001/07/20 00:07:13 eeh Exp 35 * |
| 36 * $FreeBSD: head/sys/sparc64/include/iommureg.h 139825 2005-01-07 02:29:27Z imp $ | 36 * $FreeBSD: head/sys/sparc64/include/iommureg.h 167308 2007-03-07 21:13:51Z marius $ |
| 37 */ 38 39#ifndef _MACHINE_IOMMUREG_H_ 40#define _MACHINE_IOMMUREG_H_ 41 42/* | 37 */ 38 39#ifndef _MACHINE_IOMMUREG_H_ 40#define _MACHINE_IOMMUREG_H_ 41 42/* |
| 43 * UltraSPARC IOMMU registers, common to both the sbus and PCI | 43 * UltraSPARC IOMMU registers, common to both the PCI and SBus |
| 44 * controllers. 45 */ 46 47/* iommmu registers */ 48#define IMR_CTL 0x0000 /* IOMMU control register */ 49#define IMR_TSB 0x0008 /* IOMMU TSB base register */ 50#define IMR_FLUSH 0x0010 /* IOMMU flush register */ 51 --- 8 unchanged lines hidden (view full) --- 60#define ISD_PG_TAG_DIAG 0x0800 /* streaming buffer page tag diag 0..15 */ 61#define ISD_LN_TAG_DIAG 0x0900 /* streaming buffer line tag diag 0..15 */ 62 63/* streaming buffer control register */ 64#define STRBUF_EN 0x0000000000000001UL 65#define STRBUF_D 0x0000000000000002UL 66 67#define IOMMU_BITS 34 | 44 * controllers. 45 */ 46 47/* iommmu registers */ 48#define IMR_CTL 0x0000 /* IOMMU control register */ 49#define IMR_TSB 0x0008 /* IOMMU TSB base register */ 50#define IMR_FLUSH 0x0010 /* IOMMU flush register */ 51 --- 8 unchanged lines hidden (view full) --- 60#define ISD_PG_TAG_DIAG 0x0800 /* streaming buffer page tag diag 0..15 */ 61#define ISD_LN_TAG_DIAG 0x0900 /* streaming buffer line tag diag 0..15 */ 62 63/* streaming buffer control register */ 64#define STRBUF_EN 0x0000000000000001UL 65#define STRBUF_D 0x0000000000000002UL 66 67#define IOMMU_BITS 34 |
| 68#define IOMMU_MAXADDR (1UL << IOMMU_BITS) | 68#define IOMMU_MAXADDR ((1UL << IOMMU_BITS) - 1) |
| 69 70/* 71 * control register bits 72 */ 73/* Nummber of entries in IOTSB */ 74#define IOMMUCR_TSBSZ_SHIFT 16 75#define IOMMUCR_TSB1K 0x0000000000000000UL 76#define IOMMUCR_TSB2K 0x0000000000010000UL --- 58 unchanged lines hidden (view full) --- 135 136/* 137 * Number of bytes written by a stream buffer flushsync operation to indicate 138 * completion. 139 */ 140#define STRBUF_FLUSHSYNC_NBYTES STRBUF_LINESZ 141 142/* | 69 70/* 71 * control register bits 72 */ 73/* Nummber of entries in IOTSB */ 74#define IOMMUCR_TSBSZ_SHIFT 16 75#define IOMMUCR_TSB1K 0x0000000000000000UL 76#define IOMMUCR_TSB2K 0x0000000000010000UL --- 58 unchanged lines hidden (view full) --- 135 136/* 137 * Number of bytes written by a stream buffer flushsync operation to indicate 138 * completion. 139 */ 140#define STRBUF_FLUSHSYNC_NBYTES STRBUF_LINESZ 141 142/* |
| 143 * On sun4u each bus controller has a separate IOMMU. The IOMMU has | 143 * On sun4u each bus controller has a separate IOMMU. The IOMMU has |
| 144 * a TSB which must be page aligned and physically contiguous. Mappings 145 * can be of 8K IOMMU pages or 64K IOMMU pages. We use 8K for compatibility 146 * with the CPU's MMU. 147 * 148 * On sysio, psycho, and psycho+, IOMMU TSBs using 8K pages can map the 149 * following size segments: 150 * 151 * VA size VA base TSB size tsbsize --- 11 unchanged lines hidden (view full) --- 163 * this scheme to determine the IOVA base address. Instead, bits 31-29 are 164 * used to check against the Target Address Space register in the IIi and 165 * the the IOMMU is used if they hit. God knows what goes on in the IIe. 166 * 167 */ 168 169#define IOTSB_BASESZ (1024 << IOTTE_SHIFT) 170#define IOTSB_VEND (~IO_PAGE_MASK) | 144 * a TSB which must be page aligned and physically contiguous. Mappings 145 * can be of 8K IOMMU pages or 64K IOMMU pages. We use 8K for compatibility 146 * with the CPU's MMU. 147 * 148 * On sysio, psycho, and psycho+, IOMMU TSBs using 8K pages can map the 149 * following size segments: 150 * 151 * VA size VA base TSB size tsbsize --- 11 unchanged lines hidden (view full) --- 163 * this scheme to determine the IOVA base address. Instead, bits 31-29 are 164 * used to check against the Target Address Space register in the IIi and 165 * the the IOMMU is used if they hit. God knows what goes on in the IIe. 166 * 167 */ 168 169#define IOTSB_BASESZ (1024 << IOTTE_SHIFT) 170#define IOTSB_VEND (~IO_PAGE_MASK) |
| 171#define IOTSB_VSTART(sz) (u_int)(IOTSB_VEND << ((sz) + 10)) | 171#define IOTSB_VSTART(sz) (u_int)(IOTSB_VEND << ((sz) + 10)) |
| 172 173#define MAKEIOTTE(pa,w,c,s) \ 174 (((pa) & IOTTE_PAMASK) | ((w) ? IOTTE_W : 0) | \ 175 ((c) ? IOTTE_C : 0) | ((s) ? IOTTE_STREAM : 0) | \ 176 (IOTTE_V | IOTTE_8K)) 177#define IOTSBSLOT(va) \ 178 ((u_int)(((vm_offset_t)(va)) - (is->is_dvmabase)) >> IO_PAGE_SHIFT) 179 180#endif /* !_MACHINE_IOMMUREG_H_ */ | 172 173#define MAKEIOTTE(pa,w,c,s) \ 174 (((pa) & IOTTE_PAMASK) | ((w) ? IOTTE_W : 0) | \ 175 ((c) ? IOTTE_C : 0) | ((s) ? IOTTE_STREAM : 0) | \ 176 (IOTTE_V | IOTTE_8K)) 177#define IOTSBSLOT(va) \ 178 ((u_int)(((vm_offset_t)(va)) - (is->is_dvmabase)) >> IO_PAGE_SHIFT) 179 180#endif /* !_MACHINE_IOMMUREG_H_ */ |