1/*-
2 * Copyright (c) 1992, 1993
3 * The Regents of the University of California. All rights reserved.
4 *
5 * This software was developed by the Computer Systems Engineering group
6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
7 * contributed to Berkeley.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
33 * from: @(#)sbusreg.h 8.1 (Berkeley) 6/11/93
34 * from: NetBSD: iommureg.h,v 1.6 2001/07/20 00:07:13 eeh Exp
35 *
| 1/*-
2 * Copyright (c) 1992, 1993
3 * The Regents of the University of California. All rights reserved.
4 *
5 * This software was developed by the Computer Systems Engineering group
6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
7 * contributed to Berkeley.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
33 * from: @(#)sbusreg.h 8.1 (Berkeley) 6/11/93
34 * from: NetBSD: iommureg.h,v 1.6 2001/07/20 00:07:13 eeh Exp
35 *
|
36 * $FreeBSD: head/sys/sparc64/include/iommureg.h 139825 2005-01-07 02:29:27Z imp $
| 36 * $FreeBSD: head/sys/sparc64/include/iommureg.h 167308 2007-03-07 21:13:51Z marius $
|
37 */
38
39#ifndef _MACHINE_IOMMUREG_H_
40#define _MACHINE_IOMMUREG_H_
41
42/*
| 37 */
38
39#ifndef _MACHINE_IOMMUREG_H_
40#define _MACHINE_IOMMUREG_H_
41
42/*
|
43 * UltraSPARC IOMMU registers, common to both the sbus and PCI
| 43 * UltraSPARC IOMMU registers, common to both the PCI and SBus
|
44 * controllers.
45 */
46
47/* iommmu registers */
48#define IMR_CTL 0x0000 /* IOMMU control register */
49#define IMR_TSB 0x0008 /* IOMMU TSB base register */
50#define IMR_FLUSH 0x0010 /* IOMMU flush register */
51
52/* streaming buffer registers */
53#define ISR_CTL 0x0000 /* streaming buffer control reg */
54#define ISR_PGFLUSH 0x0008 /* streaming buffer page flush */
55#define ISR_FLUSHSYNC 0x0010 /* streaming buffer flush sync */
56
57/* streaming buffer diagnostics registers. */
58#define ISD_DATA_DIAG 0x0000 /* streaming buffer data RAM diag 0..127 */
59#define ISD_ERROR_DIAG 0x0400 /* streaming buffer error status diag 0..127 */
60#define ISD_PG_TAG_DIAG 0x0800 /* streaming buffer page tag diag 0..15 */
61#define ISD_LN_TAG_DIAG 0x0900 /* streaming buffer line tag diag 0..15 */
62
63/* streaming buffer control register */
64#define STRBUF_EN 0x0000000000000001UL
65#define STRBUF_D 0x0000000000000002UL
66
67#define IOMMU_BITS 34
| 44 * controllers.
45 */
46
47/* iommmu registers */
48#define IMR_CTL 0x0000 /* IOMMU control register */
49#define IMR_TSB 0x0008 /* IOMMU TSB base register */
50#define IMR_FLUSH 0x0010 /* IOMMU flush register */
51
52/* streaming buffer registers */
53#define ISR_CTL 0x0000 /* streaming buffer control reg */
54#define ISR_PGFLUSH 0x0008 /* streaming buffer page flush */
55#define ISR_FLUSHSYNC 0x0010 /* streaming buffer flush sync */
56
57/* streaming buffer diagnostics registers. */
58#define ISD_DATA_DIAG 0x0000 /* streaming buffer data RAM diag 0..127 */
59#define ISD_ERROR_DIAG 0x0400 /* streaming buffer error status diag 0..127 */
60#define ISD_PG_TAG_DIAG 0x0800 /* streaming buffer page tag diag 0..15 */
61#define ISD_LN_TAG_DIAG 0x0900 /* streaming buffer line tag diag 0..15 */
62
63/* streaming buffer control register */
64#define STRBUF_EN 0x0000000000000001UL
65#define STRBUF_D 0x0000000000000002UL
66
67#define IOMMU_BITS 34
|
68#define IOMMU_MAXADDR (1UL << IOMMU_BITS)
| 68#define IOMMU_MAXADDR ((1UL << IOMMU_BITS) - 1)
|
69
70/*
71 * control register bits
72 */
73/* Nummber of entries in IOTSB */
74#define IOMMUCR_TSBSZ_SHIFT 16
75#define IOMMUCR_TSB1K 0x0000000000000000UL
76#define IOMMUCR_TSB2K 0x0000000000010000UL
77#define IOMMUCR_TSB4K 0x0000000000020000UL
78#define IOMMUCR_TSB8K 0x0000000000030000UL
79#define IOMMUCR_TSB16K 0x0000000000040000UL
80#define IOMMUCR_TSB32K 0x0000000000050000UL
81#define IOMMUCR_TSB64K 0x0000000000060000UL
82#define IOMMUCR_TSB128K 0x0000000000070000UL
83/* Mask for above */
84#define IOMMUCR_TSBMASK 0xfffffffffff8ffffUL
85/* 8K iommu page size */
86#define IOMMUCR_8KPG 0x0000000000000000UL
87/* 64K iommu page size */
88#define IOMMUCR_64KPG 0x0000000000000004UL
89/* Diag enable */
90#define IOMMUCR_DE 0x0000000000000002UL
91/* Enable IOMMU */
92#define IOMMUCR_EN 0x0000000000000001UL
93
94/*
95 * Diagnostic register definitions.
96 */
97#define IOMMU_DTAG_VPNBITS 19
98#define IOMMU_DTAG_VPNMASK ((1 << IOMMU_DTAG_VPNBITS) - 1)
99#define IOMMU_DTAG_VPNSHIFT 13
100#define IOMMU_DTAG_ERRBITS 3
101#define IOMMU_DTAG_ERRSHIFT 22
102#define IOMMU_DTAG_ERRMASK \
103 (((1 << IOMMU_DTAG_ERRBITS) - 1) << IOMMU_DTAG_ERRSHIFT)
104
105#define IOMMU_DDATA_PGBITS 21
106#define IOMMU_DDATA_PGMASK ((1 << IOMMU_DDATA_PGBITS) - 1)
107#define IOMMU_DDATA_PGSHIFT 13
108#define IOMMU_DDATA_C (1 << 28)
109#define IOMMU_DDATA_V (1 << 30)
110
111/*
112 * IOMMU stuff
113 */
114/* Entry valid */
115#define IOTTE_V 0x8000000000000000UL
116/* 8K or 64K page? */
117#define IOTTE_64K 0x2000000000000000UL
118#define IOTTE_8K 0x0000000000000000UL
119/* Is page streamable? */
120#define IOTTE_STREAM 0x1000000000000000UL
121/* Accesses to same bus segment? */
122#define IOTTE_LOCAL 0x0800000000000000UL
123/* Let's assume this is correct */
124#define IOTTE_PAMASK 0x000001ffffffe000UL
125/* Accesses to cacheable space */
126#define IOTTE_C 0x0000000000000010UL
127/* Writeable */
128#define IOTTE_W 0x0000000000000002UL
129
130/* log2 of the IOMMU TTE size. */
131#define IOTTE_SHIFT 3
132
133/* Streaming buffer line size. */
134#define STRBUF_LINESZ 64
135
136/*
137 * Number of bytes written by a stream buffer flushsync operation to indicate
138 * completion.
139 */
140#define STRBUF_FLUSHSYNC_NBYTES STRBUF_LINESZ
141
142/*
| 69
70/*
71 * control register bits
72 */
73/* Nummber of entries in IOTSB */
74#define IOMMUCR_TSBSZ_SHIFT 16
75#define IOMMUCR_TSB1K 0x0000000000000000UL
76#define IOMMUCR_TSB2K 0x0000000000010000UL
77#define IOMMUCR_TSB4K 0x0000000000020000UL
78#define IOMMUCR_TSB8K 0x0000000000030000UL
79#define IOMMUCR_TSB16K 0x0000000000040000UL
80#define IOMMUCR_TSB32K 0x0000000000050000UL
81#define IOMMUCR_TSB64K 0x0000000000060000UL
82#define IOMMUCR_TSB128K 0x0000000000070000UL
83/* Mask for above */
84#define IOMMUCR_TSBMASK 0xfffffffffff8ffffUL
85/* 8K iommu page size */
86#define IOMMUCR_8KPG 0x0000000000000000UL
87/* 64K iommu page size */
88#define IOMMUCR_64KPG 0x0000000000000004UL
89/* Diag enable */
90#define IOMMUCR_DE 0x0000000000000002UL
91/* Enable IOMMU */
92#define IOMMUCR_EN 0x0000000000000001UL
93
94/*
95 * Diagnostic register definitions.
96 */
97#define IOMMU_DTAG_VPNBITS 19
98#define IOMMU_DTAG_VPNMASK ((1 << IOMMU_DTAG_VPNBITS) - 1)
99#define IOMMU_DTAG_VPNSHIFT 13
100#define IOMMU_DTAG_ERRBITS 3
101#define IOMMU_DTAG_ERRSHIFT 22
102#define IOMMU_DTAG_ERRMASK \
103 (((1 << IOMMU_DTAG_ERRBITS) - 1) << IOMMU_DTAG_ERRSHIFT)
104
105#define IOMMU_DDATA_PGBITS 21
106#define IOMMU_DDATA_PGMASK ((1 << IOMMU_DDATA_PGBITS) - 1)
107#define IOMMU_DDATA_PGSHIFT 13
108#define IOMMU_DDATA_C (1 << 28)
109#define IOMMU_DDATA_V (1 << 30)
110
111/*
112 * IOMMU stuff
113 */
114/* Entry valid */
115#define IOTTE_V 0x8000000000000000UL
116/* 8K or 64K page? */
117#define IOTTE_64K 0x2000000000000000UL
118#define IOTTE_8K 0x0000000000000000UL
119/* Is page streamable? */
120#define IOTTE_STREAM 0x1000000000000000UL
121/* Accesses to same bus segment? */
122#define IOTTE_LOCAL 0x0800000000000000UL
123/* Let's assume this is correct */
124#define IOTTE_PAMASK 0x000001ffffffe000UL
125/* Accesses to cacheable space */
126#define IOTTE_C 0x0000000000000010UL
127/* Writeable */
128#define IOTTE_W 0x0000000000000002UL
129
130/* log2 of the IOMMU TTE size. */
131#define IOTTE_SHIFT 3
132
133/* Streaming buffer line size. */
134#define STRBUF_LINESZ 64
135
136/*
137 * Number of bytes written by a stream buffer flushsync operation to indicate
138 * completion.
139 */
140#define STRBUF_FLUSHSYNC_NBYTES STRBUF_LINESZ
141
142/*
|
143 * On sun4u each bus controller has a separate IOMMU. The IOMMU has
| 143 * On sun4u each bus controller has a separate IOMMU. The IOMMU has
|
144 * a TSB which must be page aligned and physically contiguous. Mappings
145 * can be of 8K IOMMU pages or 64K IOMMU pages. We use 8K for compatibility
146 * with the CPU's MMU.
147 *
148 * On sysio, psycho, and psycho+, IOMMU TSBs using 8K pages can map the
149 * following size segments:
150 *
151 * VA size VA base TSB size tsbsize
152 * -------- -------- --------- -------
153 * 8MB ff800000 8K 0
154 * 16MB ff000000 16K 1
155 * 32MB fe000000 32K 2
156 * 64MB fc000000 64K 3
157 * 128MB f8000000 128K 4
158 * 256MB f0000000 256K 5
159 * 512MB e0000000 512K 6
160 * 1GB c0000000 1MB 7
161 *
162 * Unfortunately, sabres on UltraSPARC IIi and IIe processors does not use
163 * this scheme to determine the IOVA base address. Instead, bits 31-29 are
164 * used to check against the Target Address Space register in the IIi and
165 * the the IOMMU is used if they hit. God knows what goes on in the IIe.
166 *
167 */
168
169#define IOTSB_BASESZ (1024 << IOTTE_SHIFT)
170#define IOTSB_VEND (~IO_PAGE_MASK)
| 144 * a TSB which must be page aligned and physically contiguous. Mappings
145 * can be of 8K IOMMU pages or 64K IOMMU pages. We use 8K for compatibility
146 * with the CPU's MMU.
147 *
148 * On sysio, psycho, and psycho+, IOMMU TSBs using 8K pages can map the
149 * following size segments:
150 *
151 * VA size VA base TSB size tsbsize
152 * -------- -------- --------- -------
153 * 8MB ff800000 8K 0
154 * 16MB ff000000 16K 1
155 * 32MB fe000000 32K 2
156 * 64MB fc000000 64K 3
157 * 128MB f8000000 128K 4
158 * 256MB f0000000 256K 5
159 * 512MB e0000000 512K 6
160 * 1GB c0000000 1MB 7
161 *
162 * Unfortunately, sabres on UltraSPARC IIi and IIe processors does not use
163 * this scheme to determine the IOVA base address. Instead, bits 31-29 are
164 * used to check against the Target Address Space register in the IIi and
165 * the the IOMMU is used if they hit. God knows what goes on in the IIe.
166 *
167 */
168
169#define IOTSB_BASESZ (1024 << IOTTE_SHIFT)
170#define IOTSB_VEND (~IO_PAGE_MASK)
|
171#define IOTSB_VSTART(sz) (u_int)(IOTSB_VEND << ((sz) + 10))
| 171#define IOTSB_VSTART(sz) (u_int)(IOTSB_VEND << ((sz) + 10))
|
172
173#define MAKEIOTTE(pa,w,c,s) \
174 (((pa) & IOTTE_PAMASK) | ((w) ? IOTTE_W : 0) | \
175 ((c) ? IOTTE_C : 0) | ((s) ? IOTTE_STREAM : 0) | \
176 (IOTTE_V | IOTTE_8K))
177#define IOTSBSLOT(va) \
178 ((u_int)(((vm_offset_t)(va)) - (is->is_dvmabase)) >> IO_PAGE_SHIFT)
179
180#endif /* !_MACHINE_IOMMUREG_H_ */
| 172
173#define MAKEIOTTE(pa,w,c,s) \
174 (((pa) & IOTTE_PAMASK) | ((w) ? IOTTE_W : 0) | \
175 ((c) ? IOTTE_C : 0) | ((s) ? IOTTE_STREAM : 0) | \
176 (IOTTE_V | IOTTE_8K))
177#define IOTSBSLOT(va) \
178 ((u_int)(((vm_offset_t)(va)) - (is->is_dvmabase)) >> IO_PAGE_SHIFT)
179
180#endif /* !_MACHINE_IOMMUREG_H_ */
|