1/*- 2 * Copyright (c) 2012 Justin Hibbits 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 11 unchanged lines hidden (view full) --- 20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> |
28__FBSDID("$FreeBSD: stable/10/sys/powerpc/powermac/atibl.c 271205 2014-09-06 19:38:40Z jhibbits $"); |
29 30#include <sys/param.h> 31#include <sys/bus.h> 32#include <sys/systm.h> 33#include <sys/module.h> 34#include <sys/kernel.h> 35#include <sys/rman.h> 36#include <sys/sysctl.h> --- 10 unchanged lines hidden (view full) --- 47#define RADEON_LVDS_PANEL_FORMAT (1 << 3) 48#define RADEON_LVDS_RST_FM (1 << 6) 49#define RADEON_LVDS_EN (1 << 7) 50#define RADEON_LVDS_BL_MOD_LEVEL_SHIFT 8 51#define RADEON_LVDS_BL_MOD_LEVEL_MASK (0xff << 8) 52#define RADEON_LVDS_BL_MOD_EN (1 << 16) 53#define RADEON_LVDS_DIGON (1 << 18) 54#define RADEON_LVDS_BLON (1 << 19) |
55#define RADEON_LVDS_PLL_CNTL 0x02d4 56#define RADEON_LVDS_PLL_EN (1 << 16) 57#define RADEON_LVDS_PLL_RESET (1 << 17) 58#define RADEON_PIXCLKS_CNTL 0x002d 59#define RADEON_PIXCLK_LVDS_ALWAYS_ONb (1 << 14) 60#define RADEON_DISP_PWR_MAN 0x0d08 61#define RADEON_AUTO_PWRUP_EN (1 << 26) 62#define RADEON_CLOCK_CNTL_DATA 0x000c 63#define RADEON_CLOCK_CNTL_INDEX 0x0008 64#define RADEON_PLL_WR_EN (1 << 7) 65#define RADEON_CRTC_GEN_CNTL 0x0050 |
66 67struct atibl_softc { |
68 struct resource *sc_memr; |
69 int sc_level; |
70}; 71 72static void atibl_identify(driver_t *driver, device_t parent); 73static int atibl_probe(device_t dev); 74static int atibl_attach(device_t dev); 75static int atibl_setlevel(struct atibl_softc *sc, int newlevel); 76static int atibl_getlevel(struct atibl_softc *sc); |
77static int atibl_resume(device_t dev); 78static int atibl_suspend(device_t dev); |
79static int atibl_sysctl(SYSCTL_HANDLER_ARGS); 80 81static device_method_t atibl_methods[] = { 82 /* Device interface */ |
83 DEVMETHOD(device_identify, atibl_identify), 84 DEVMETHOD(device_probe, atibl_probe), 85 DEVMETHOD(device_attach, atibl_attach), 86 DEVMETHOD(device_suspend, atibl_suspend), 87 DEVMETHOD(device_resume, atibl_resume), |
88 {0, 0}, 89}; 90 91static driver_t atibl_driver = { 92 "backlight", 93 atibl_methods, 94 sizeof(struct atibl_softc) 95}; --- 50 unchanged lines hidden (view full) --- 146 device_printf(dev, "Could not alloc mem resource!\n"); 147 return (ENXIO); 148 } 149 150 ctx = device_get_sysctl_ctx(dev); 151 tree = device_get_sysctl_tree(dev); 152 153 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, |
154 "level", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 155 atibl_sysctl, "I", "Backlight level (0-100)"); |
156 157 return (0); 158} 159 |
160static uint32_t __inline 161atibl_pll_rreg(struct atibl_softc *sc, uint32_t reg) 162{ 163 uint32_t data, save, tmp; 164 165 bus_write_1(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, 166 ((reg & 0x3f) | RADEON_PLL_WR_EN)); 167 (void)bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA); 168 (void)bus_read_4(sc->sc_memr, RADEON_CRTC_GEN_CNTL); 169 170 data = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA); 171 172 /* Only necessary on R300, bt won't hurt others. */ 173 save = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX); 174 tmp = save & (~0x3f | RADEON_PLL_WR_EN); 175 bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, tmp); 176 tmp = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA); 177 bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, save); 178 179 return data; 180} 181 182static void __inline 183atibl_pll_wreg(struct atibl_softc *sc, uint32_t reg, uint32_t val) 184{ 185 uint32_t save, tmp; 186 187 bus_write_1(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, 188 ((reg & 0x3f) | RADEON_PLL_WR_EN)); 189 (void)bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA); 190 (void)bus_read_4(sc->sc_memr, RADEON_CRTC_GEN_CNTL); 191 192 bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA, val); 193 DELAY(5000); 194 195 /* Only necessary on R300, bt won't hurt others. */ 196 save = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX); 197 tmp = save & (~0x3f | RADEON_PLL_WR_EN); 198 bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, tmp); 199 tmp = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA); 200 bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, save); 201} 202 |
203static int 204atibl_setlevel(struct atibl_softc *sc, int newlevel) 205{ 206 uint32_t lvds_gen_cntl; |
207 uint32_t lvds_pll_cntl; 208 uint32_t pixclks_cntl; 209 uint32_t disp_pwr_reg; |
210 211 if (newlevel > 100) 212 newlevel = 100; 213 214 if (newlevel < 0) 215 newlevel = 0; 216 |
217 lvds_gen_cntl = bus_read_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL); |
218 |
219 if (newlevel > 0) { 220 newlevel = (newlevel * 5) / 2 + 5; 221 disp_pwr_reg = bus_read_4(sc->sc_memr, RADEON_DISP_PWR_MAN); 222 disp_pwr_reg |= RADEON_AUTO_PWRUP_EN; 223 bus_write_4(sc->sc_memr, RADEON_DISP_PWR_MAN, disp_pwr_reg); 224 lvds_pll_cntl = bus_read_4(sc->sc_memr, RADEON_LVDS_PLL_CNTL); 225 lvds_pll_cntl |= RADEON_LVDS_PLL_EN; 226 bus_write_4(sc->sc_memr, RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); 227 lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET; 228 bus_write_4(sc->sc_memr, RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); 229 DELAY(1000); 230 231 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS | 232 RADEON_LVDS_BL_MOD_LEVEL_MASK); 233 lvds_gen_cntl |= RADEON_LVDS_ON | RADEON_LVDS_EN | 234 RADEON_LVDS_DIGON | RADEON_LVDS_BLON; 235 lvds_gen_cntl |= (newlevel << RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 236 RADEON_LVDS_BL_MOD_LEVEL_MASK; 237 lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN; 238 DELAY(200000); 239 bus_write_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); 240 } else { 241 pixclks_cntl = atibl_pll_rreg(sc, RADEON_PIXCLKS_CNTL); 242 atibl_pll_wreg(sc, RADEON_PIXCLKS_CNTL, 243 pixclks_cntl & ~RADEON_PIXCLK_LVDS_ALWAYS_ONb); 244 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS; 245 lvds_gen_cntl &= ~(RADEON_LVDS_BL_MOD_EN | RADEON_LVDS_BL_MOD_LEVEL_MASK); 246 bus_write_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); 247 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN); 248 DELAY(200000); 249 bus_write_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); 250 251 atibl_pll_wreg(sc, RADEON_PIXCLKS_CNTL, pixclks_cntl); 252 DELAY(200000); 253 } 254 |
255 return (0); 256} 257 258static int 259atibl_getlevel(struct atibl_softc *sc) 260{ 261 uint32_t lvds_gen_cntl; 262 int level; 263 264 lvds_gen_cntl = bus_read_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL); 265 266 level = ((lvds_gen_cntl & RADEON_LVDS_BL_MOD_LEVEL_MASK) >> |
267 RADEON_LVDS_BL_MOD_LEVEL_SHIFT); 268 if (level != 0) 269 level = ((level - 5) * 2) / 5; |
270 271 return (level); 272} 273 274static int |
275atibl_suspend(device_t dev) 276{ 277 struct atibl_softc *sc; 278 279 sc = device_get_softc(dev); 280 281 sc->sc_level = atibl_getlevel(sc); 282 atibl_setlevel(sc, 0); 283 284 return (0); 285} 286 287static int 288atibl_resume(device_t dev) 289{ 290 struct atibl_softc *sc; 291 292 sc = device_get_softc(dev); 293 294 atibl_setlevel(sc, sc->sc_level); 295 296 return (0); 297} 298 299static int |
300atibl_sysctl(SYSCTL_HANDLER_ARGS) 301{ 302 struct atibl_softc *sc; 303 int newlevel, error; 304 305 sc = arg1; 306 307 newlevel = atibl_getlevel(sc); 308 309 error = sysctl_handle_int(oidp, &newlevel, 0, req); 310 311 if (error || !req->newptr) 312 return (error); 313 314 return (atibl_setlevel(sc, newlevel)); 315} |