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< __FBSDID("$FreeBSD: stable/10/sys/powerpc/powermac/atibl.c 255100 2013-08-31 16:31:48Z jhibbits $");
---
> __FBSDID("$FreeBSD: stable/10/sys/powerpc/powermac/atibl.c 271205 2014-09-06 19:38:40Z jhibbits $");
54a55,65
> #define RADEON_LVDS_PLL_CNTL 0x02d4
> #define RADEON_LVDS_PLL_EN (1 << 16)
> #define RADEON_LVDS_PLL_RESET (1 << 17)
> #define RADEON_PIXCLKS_CNTL 0x002d
> #define RADEON_PIXCLK_LVDS_ALWAYS_ONb (1 << 14)
> #define RADEON_DISP_PWR_MAN 0x0d08
> #define RADEON_AUTO_PWRUP_EN (1 << 26)
> #define RADEON_CLOCK_CNTL_DATA 0x000c
> #define RADEON_CLOCK_CNTL_INDEX 0x0008
> #define RADEON_PLL_WR_EN (1 << 7)
> #define RADEON_CRTC_GEN_CNTL 0x0050
57d67
< device_t dev;
58a69
> int sc_level;
65a77,78
> static int atibl_resume(device_t dev);
> static int atibl_suspend(device_t dev);
70,72c83,87
< DEVMETHOD(device_identify, atibl_identify),
< DEVMETHOD(device_probe, atibl_probe),
< DEVMETHOD(device_attach, atibl_attach),
---
> DEVMETHOD(device_identify, atibl_identify),
> DEVMETHOD(device_probe, atibl_probe),
> DEVMETHOD(device_attach, atibl_attach),
> DEVMETHOD(device_suspend, atibl_suspend),
> DEVMETHOD(device_resume, atibl_resume),
139,140c154,155
< "level", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
< atibl_sysctl, "I", "Backlight level (0-100)");
---
> "level", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
> atibl_sysctl, "I", "Backlight level (0-100)");
144a160,202
> static uint32_t __inline
> atibl_pll_rreg(struct atibl_softc *sc, uint32_t reg)
> {
> uint32_t data, save, tmp;
>
> bus_write_1(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX,
> ((reg & 0x3f) | RADEON_PLL_WR_EN));
> (void)bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA);
> (void)bus_read_4(sc->sc_memr, RADEON_CRTC_GEN_CNTL);
>
> data = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA);
>
> /* Only necessary on R300, bt won't hurt others. */
> save = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX);
> tmp = save & (~0x3f | RADEON_PLL_WR_EN);
> bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, tmp);
> tmp = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA);
> bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, save);
>
> return data;
> }
>
> static void __inline
> atibl_pll_wreg(struct atibl_softc *sc, uint32_t reg, uint32_t val)
> {
> uint32_t save, tmp;
>
> bus_write_1(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX,
> ((reg & 0x3f) | RADEON_PLL_WR_EN));
> (void)bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA);
> (void)bus_read_4(sc->sc_memr, RADEON_CRTC_GEN_CNTL);
>
> bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA, val);
> DELAY(5000);
>
> /* Only necessary on R300, bt won't hurt others. */
> save = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX);
> tmp = save & (~0x3f | RADEON_PLL_WR_EN);
> bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, tmp);
> tmp = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA);
> bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, save);
> }
>
148a207,209
> uint32_t lvds_pll_cntl;
> uint32_t pixclks_cntl;
> uint32_t disp_pwr_reg;
156d216
< newlevel = (newlevel * 5) / 2 + 5;
158,162d217
< lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN;
< lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_LEVEL_MASK;
< lvds_gen_cntl |= (newlevel << RADEON_LVDS_BL_MOD_LEVEL_SHIFT) &
< RADEON_LVDS_BL_MOD_LEVEL_MASK;
< bus_write_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
163a219,254
> if (newlevel > 0) {
> newlevel = (newlevel * 5) / 2 + 5;
> disp_pwr_reg = bus_read_4(sc->sc_memr, RADEON_DISP_PWR_MAN);
> disp_pwr_reg |= RADEON_AUTO_PWRUP_EN;
> bus_write_4(sc->sc_memr, RADEON_DISP_PWR_MAN, disp_pwr_reg);
> lvds_pll_cntl = bus_read_4(sc->sc_memr, RADEON_LVDS_PLL_CNTL);
> lvds_pll_cntl |= RADEON_LVDS_PLL_EN;
> bus_write_4(sc->sc_memr, RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
> lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
> bus_write_4(sc->sc_memr, RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
> DELAY(1000);
>
> lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS |
> RADEON_LVDS_BL_MOD_LEVEL_MASK);
> lvds_gen_cntl |= RADEON_LVDS_ON | RADEON_LVDS_EN |
> RADEON_LVDS_DIGON | RADEON_LVDS_BLON;
> lvds_gen_cntl |= (newlevel << RADEON_LVDS_BL_MOD_LEVEL_SHIFT) &
> RADEON_LVDS_BL_MOD_LEVEL_MASK;
> lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN;
> DELAY(200000);
> bus_write_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
> } else {
> pixclks_cntl = atibl_pll_rreg(sc, RADEON_PIXCLKS_CNTL);
> atibl_pll_wreg(sc, RADEON_PIXCLKS_CNTL,
> pixclks_cntl & ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
> lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
> lvds_gen_cntl &= ~(RADEON_LVDS_BL_MOD_EN | RADEON_LVDS_BL_MOD_LEVEL_MASK);
> bus_write_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
> lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN);
> DELAY(200000);
> bus_write_4(sc->sc_memr, RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
>
> atibl_pll_wreg(sc, RADEON_PIXCLKS_CNTL, pixclks_cntl);
> DELAY(200000);
> }
>
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< RADEON_LVDS_BL_MOD_LEVEL_SHIFT);
< level = ((level - 5) * 2) / 5;
---
> RADEON_LVDS_BL_MOD_LEVEL_SHIFT);
> if (level != 0)
> level = ((level - 5) * 2) / 5;
182a275,299
> atibl_suspend(device_t dev)
> {
> struct atibl_softc *sc;
>
> sc = device_get_softc(dev);
>
> sc->sc_level = atibl_getlevel(sc);
> atibl_setlevel(sc, 0);
>
> return (0);
> }
>
> static int
> atibl_resume(device_t dev)
> {
> struct atibl_softc *sc;
>
> sc = device_get_softc(dev);
>
> atibl_setlevel(sc, sc->sc_level);
>
> return (0);
> }
>
> static int