364 MMUMETHOD(mmu_zero_page, mmu_booke_zero_page),
365 MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area),
366 MMUMETHOD(mmu_zero_page_idle, mmu_booke_zero_page_idle),
367 MMUMETHOD(mmu_activate, mmu_booke_activate),
368 MMUMETHOD(mmu_deactivate, mmu_booke_deactivate),
369
370 /* Internal interfaces */
371 MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap),
372 MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped),
373 MMUMETHOD(mmu_mapdev, mmu_booke_mapdev),
374 MMUMETHOD(mmu_mapdev_attr, mmu_booke_mapdev_attr),
375 MMUMETHOD(mmu_kenter, mmu_booke_kenter),
376 MMUMETHOD(mmu_kenter_attr, mmu_booke_kenter_attr),
377 MMUMETHOD(mmu_kextract, mmu_booke_kextract),
378/* MMUMETHOD(mmu_kremove, mmu_booke_kremove), */
379 MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev),
380
381 /* dumpsys() support */
382 MMUMETHOD(mmu_dumpsys_map, mmu_booke_dumpsys_map),
383 MMUMETHOD(mmu_dumpsys_unmap, mmu_booke_dumpsys_unmap),
384 MMUMETHOD(mmu_scan_md, mmu_booke_scan_md),
385
386 { 0, 0 }
387};
388
389MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods, 0);
390
391static __inline uint32_t
392tlb_calc_wimg(vm_offset_t pa, vm_memattr_t ma)
393{
394 uint32_t attrib;
395 int i;
396
397 if (ma != VM_MEMATTR_DEFAULT) {
398 switch (ma) {
399 case VM_MEMATTR_UNCACHEABLE:
400 return (PTE_I | PTE_G);
401 case VM_MEMATTR_WRITE_COMBINING:
402 case VM_MEMATTR_WRITE_BACK:
403 case VM_MEMATTR_PREFETCHABLE:
404 return (PTE_I);
405 case VM_MEMATTR_WRITE_THROUGH:
406 return (PTE_W | PTE_M);
407 }
408 }
409
410 /*
411 * Assume the page is cache inhibited and access is guarded unless
412 * it's in our available memory array.
413 */
414 attrib = _TLB_ENTRY_IO;
415 for (i = 0; i < physmem_regions_sz; i++) {
416 if ((pa >= physmem_regions[i].mr_start) &&
417 (pa < (physmem_regions[i].mr_start +
418 physmem_regions[i].mr_size))) {
419 attrib = _TLB_ENTRY_MEM;
420 break;
421 }
422 }
423
424 return (attrib);
425}
426
427static inline void
428tlb_miss_lock(void)
429{
430#ifdef SMP
431 struct pcpu *pc;
432
433 if (!smp_started)
434 return;
435
436 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
437 if (pc != pcpup) {
438
439 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, "
440 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke_tlb_lock);
441
442 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)),
443 ("tlb_miss_lock: tried to lock self"));
444
445 tlb_lock(pc->pc_booke_tlb_lock);
446
447 CTR1(KTR_PMAP, "%s: locked", __func__);
448 }
449 }
450#endif
451}
452
453static inline void
454tlb_miss_unlock(void)
455{
456#ifdef SMP
457 struct pcpu *pc;
458
459 if (!smp_started)
460 return;
461
462 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
463 if (pc != pcpup) {
464 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d",
465 __func__, pc->pc_cpuid);
466
467 tlb_unlock(pc->pc_booke_tlb_lock);
468
469 CTR1(KTR_PMAP, "%s: unlocked", __func__);
470 }
471 }
472#endif
473}
474
475/* Return number of entries in TLB0. */
476static __inline void
477tlb0_get_tlbconf(void)
478{
479 uint32_t tlb0_cfg;
480
481 tlb0_cfg = mfspr(SPR_TLB0CFG);
482 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK;
483 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT;
484 tlb0_entries_per_way = tlb0_entries / tlb0_ways;
485}
486
487/* Initialize pool of kva ptbl buffers. */
488static void
489ptbl_init(void)
490{
491 int i;
492
493 CTR3(KTR_PMAP, "%s: s (ptbl_bufs = 0x%08x size 0x%08x)", __func__,
494 (uint32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS);
495 CTR3(KTR_PMAP, "%s: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)",
496 __func__, ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE);
497
498 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF);
499 TAILQ_INIT(&ptbl_buf_freelist);
500
501 for (i = 0; i < PTBL_BUFS; i++) {
502 ptbl_bufs[i].kva = ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE;
503 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link);
504 }
505}
506
507/* Get a ptbl_buf from the freelist. */
508static struct ptbl_buf *
509ptbl_buf_alloc(void)
510{
511 struct ptbl_buf *buf;
512
513 mtx_lock(&ptbl_buf_freelist_lock);
514 buf = TAILQ_FIRST(&ptbl_buf_freelist);
515 if (buf != NULL)
516 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link);
517 mtx_unlock(&ptbl_buf_freelist_lock);
518
519 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf);
520
521 return (buf);
522}
523
524/* Return ptbl buff to free pool. */
525static void
526ptbl_buf_free(struct ptbl_buf *buf)
527{
528
529 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf);
530
531 mtx_lock(&ptbl_buf_freelist_lock);
532 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link);
533 mtx_unlock(&ptbl_buf_freelist_lock);
534}
535
536/*
537 * Search the list of allocated ptbl bufs and find on list of allocated ptbls
538 */
539static void
540ptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl)
541{
542 struct ptbl_buf *pbuf;
543
544 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl);
545
546 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
547
548 TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link)
549 if (pbuf->kva == (vm_offset_t)ptbl) {
550 /* Remove from pmap ptbl buf list. */
551 TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link);
552
553 /* Free corresponding ptbl buf. */
554 ptbl_buf_free(pbuf);
555 break;
556 }
557}
558
559/* Allocate page table. */
560static pte_t *
561ptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx, boolean_t nosleep)
562{
563 vm_page_t mtbl[PTBL_PAGES];
564 vm_page_t m;
565 struct ptbl_buf *pbuf;
566 unsigned int pidx;
567 pte_t *ptbl;
568 int i, j;
569
570 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
571 (pmap == kernel_pmap), pdir_idx);
572
573 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
574 ("ptbl_alloc: invalid pdir_idx"));
575 KASSERT((pmap->pm_pdir[pdir_idx] == NULL),
576 ("pte_alloc: valid ptbl entry exists!"));
577
578 pbuf = ptbl_buf_alloc();
579 if (pbuf == NULL)
580 panic("pte_alloc: couldn't alloc kernel virtual memory");
581
582 ptbl = (pte_t *)pbuf->kva;
583
584 CTR2(KTR_PMAP, "%s: ptbl kva = %p", __func__, ptbl);
585
586 /* Allocate ptbl pages, this will sleep! */
587 for (i = 0; i < PTBL_PAGES; i++) {
588 pidx = (PTBL_PAGES * pdir_idx) + i;
589 while ((m = vm_page_alloc(NULL, pidx,
590 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
591 PMAP_UNLOCK(pmap);
592 rw_wunlock(&pvh_global_lock);
593 if (nosleep) {
594 ptbl_free_pmap_ptbl(pmap, ptbl);
595 for (j = 0; j < i; j++)
596 vm_page_free(mtbl[j]);
597 atomic_subtract_int(&cnt.v_wire_count, i);
598 return (NULL);
599 }
600 VM_WAIT;
601 rw_wlock(&pvh_global_lock);
602 PMAP_LOCK(pmap);
603 }
604 mtbl[i] = m;
605 }
606
607 /* Map allocated pages into kernel_pmap. */
608 mmu_booke_qenter(mmu, (vm_offset_t)ptbl, mtbl, PTBL_PAGES);
609
610 /* Zero whole ptbl. */
611 bzero((caddr_t)ptbl, PTBL_PAGES * PAGE_SIZE);
612
613 /* Add pbuf to the pmap ptbl bufs list. */
614 TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link);
615
616 return (ptbl);
617}
618
619/* Free ptbl pages and invalidate pdir entry. */
620static void
621ptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
622{
623 pte_t *ptbl;
624 vm_paddr_t pa;
625 vm_offset_t va;
626 vm_page_t m;
627 int i;
628
629 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
630 (pmap == kernel_pmap), pdir_idx);
631
632 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
633 ("ptbl_free: invalid pdir_idx"));
634
635 ptbl = pmap->pm_pdir[pdir_idx];
636
637 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl);
638
639 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl"));
640
641 /*
642 * Invalidate the pdir entry as soon as possible, so that other CPUs
643 * don't attempt to look up the page tables we are releasing.
644 */
645 mtx_lock_spin(&tlbivax_mutex);
646 tlb_miss_lock();
647
648 pmap->pm_pdir[pdir_idx] = NULL;
649
650 tlb_miss_unlock();
651 mtx_unlock_spin(&tlbivax_mutex);
652
653 for (i = 0; i < PTBL_PAGES; i++) {
654 va = ((vm_offset_t)ptbl + (i * PAGE_SIZE));
655 pa = pte_vatopa(mmu, kernel_pmap, va);
656 m = PHYS_TO_VM_PAGE(pa);
657 vm_page_free_zero(m);
658 atomic_subtract_int(&cnt.v_wire_count, 1);
659 mmu_booke_kremove(mmu, va);
660 }
661
662 ptbl_free_pmap_ptbl(pmap, ptbl);
663}
664
665/*
666 * Decrement ptbl pages hold count and attempt to free ptbl pages.
667 * Called when removing pte entry from ptbl.
668 *
669 * Return 1 if ptbl pages were freed.
670 */
671static int
672ptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
673{
674 pte_t *ptbl;
675 vm_paddr_t pa;
676 vm_page_t m;
677 int i;
678
679 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
680 (pmap == kernel_pmap), pdir_idx);
681
682 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
683 ("ptbl_unhold: invalid pdir_idx"));
684 KASSERT((pmap != kernel_pmap),
685 ("ptbl_unhold: unholding kernel ptbl!"));
686
687 ptbl = pmap->pm_pdir[pdir_idx];
688
689 //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl);
690 KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS),
691 ("ptbl_unhold: non kva ptbl"));
692
693 /* decrement hold count */
694 for (i = 0; i < PTBL_PAGES; i++) {
695 pa = pte_vatopa(mmu, kernel_pmap,
696 (vm_offset_t)ptbl + (i * PAGE_SIZE));
697 m = PHYS_TO_VM_PAGE(pa);
698 m->wire_count--;
699 }
700
701 /*
702 * Free ptbl pages if there are no pte etries in this ptbl.
703 * wire_count has the same value for all ptbl pages, so check the last
704 * page.
705 */
706 if (m->wire_count == 0) {
707 ptbl_free(mmu, pmap, pdir_idx);
708
709 //debugf("ptbl_unhold: e (freed ptbl)\n");
710 return (1);
711 }
712
713 return (0);
714}
715
716/*
717 * Increment hold count for ptbl pages. This routine is used when a new pte
718 * entry is being inserted into the ptbl.
719 */
720static void
721ptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
722{
723 vm_paddr_t pa;
724 pte_t *ptbl;
725 vm_page_t m;
726 int i;
727
728 CTR3(KTR_PMAP, "%s: pmap = %p pdir_idx = %d", __func__, pmap,
729 pdir_idx);
730
731 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
732 ("ptbl_hold: invalid pdir_idx"));
733 KASSERT((pmap != kernel_pmap),
734 ("ptbl_hold: holding kernel ptbl!"));
735
736 ptbl = pmap->pm_pdir[pdir_idx];
737
738 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl"));
739
740 for (i = 0; i < PTBL_PAGES; i++) {
741 pa = pte_vatopa(mmu, kernel_pmap,
742 (vm_offset_t)ptbl + (i * PAGE_SIZE));
743 m = PHYS_TO_VM_PAGE(pa);
744 m->wire_count++;
745 }
746}
747
748/* Allocate pv_entry structure. */
749pv_entry_t
750pv_alloc(void)
751{
752 pv_entry_t pv;
753
754 pv_entry_count++;
755 if (pv_entry_count > pv_entry_high_water)
756 pagedaemon_wakeup();
757 pv = uma_zalloc(pvzone, M_NOWAIT);
758
759 return (pv);
760}
761
762/* Free pv_entry structure. */
763static __inline void
764pv_free(pv_entry_t pve)
765{
766
767 pv_entry_count--;
768 uma_zfree(pvzone, pve);
769}
770
771
772/* Allocate and initialize pv_entry structure. */
773static void
774pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m)
775{
776 pv_entry_t pve;
777
778 //int su = (pmap == kernel_pmap);
779 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su,
780 // (u_int32_t)pmap, va, (u_int32_t)m);
781
782 pve = pv_alloc();
783 if (pve == NULL)
784 panic("pv_insert: no pv entries!");
785
786 pve->pv_pmap = pmap;
787 pve->pv_va = va;
788
789 /* add to pv_list */
790 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
791 rw_assert(&pvh_global_lock, RA_WLOCKED);
792
793 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link);
794
795 //debugf("pv_insert: e\n");
796}
797
798/* Destroy pv entry. */
799static void
800pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m)
801{
802 pv_entry_t pve;
803
804 //int su = (pmap == kernel_pmap);
805 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va);
806
807 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
808 rw_assert(&pvh_global_lock, RA_WLOCKED);
809
810 /* find pv entry */
811 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) {
812 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) {
813 /* remove from pv_list */
814 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link);
815 if (TAILQ_EMPTY(&m->md.pv_list))
816 vm_page_aflag_clear(m, PGA_WRITEABLE);
817
818 /* free pv entry struct */
819 pv_free(pve);
820 break;
821 }
822 }
823
824 //debugf("pv_remove: e\n");
825}
826
827/*
828 * Clean pte entry, try to free page table page if requested.
829 *
830 * Return 1 if ptbl pages were freed, otherwise return 0.
831 */
832static int
833pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, uint8_t flags)
834{
835 unsigned int pdir_idx = PDIR_IDX(va);
836 unsigned int ptbl_idx = PTBL_IDX(va);
837 vm_page_t m;
838 pte_t *ptbl;
839 pte_t *pte;
840
841 //int su = (pmap == kernel_pmap);
842 //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n",
843 // su, (u_int32_t)pmap, va, flags);
844
845 ptbl = pmap->pm_pdir[pdir_idx];
846 KASSERT(ptbl, ("pte_remove: null ptbl"));
847
848 pte = &ptbl[ptbl_idx];
849
850 if (pte == NULL || !PTE_ISVALID(pte))
851 return (0);
852
853 if (PTE_ISWIRED(pte))
854 pmap->pm_stats.wired_count--;
855
856 /* Handle managed entry. */
857 if (PTE_ISMANAGED(pte)) {
858 /* Get vm_page_t for mapped pte. */
859 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
860
861 if (PTE_ISMODIFIED(pte))
862 vm_page_dirty(m);
863
864 if (PTE_ISREFERENCED(pte))
865 vm_page_aflag_set(m, PGA_REFERENCED);
866
867 pv_remove(pmap, va, m);
868 }
869
870 mtx_lock_spin(&tlbivax_mutex);
871 tlb_miss_lock();
872
873 tlb0_flush_entry(va);
874 pte->flags = 0;
875 pte->rpn = 0;
876
877 tlb_miss_unlock();
878 mtx_unlock_spin(&tlbivax_mutex);
879
880 pmap->pm_stats.resident_count--;
881
882 if (flags & PTBL_UNHOLD) {
883 //debugf("pte_remove: e (unhold)\n");
884 return (ptbl_unhold(mmu, pmap, pdir_idx));
885 }
886
887 //debugf("pte_remove: e\n");
888 return (0);
889}
890
891/*
892 * Insert PTE for a given page and virtual address.
893 */
894static int
895pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags,
896 boolean_t nosleep)
897{
898 unsigned int pdir_idx = PDIR_IDX(va);
899 unsigned int ptbl_idx = PTBL_IDX(va);
900 pte_t *ptbl, *pte;
901
902 CTR4(KTR_PMAP, "%s: su = %d pmap = %p va = %p", __func__,
903 pmap == kernel_pmap, pmap, va);
904
905 /* Get the page table pointer. */
906 ptbl = pmap->pm_pdir[pdir_idx];
907
908 if (ptbl == NULL) {
909 /* Allocate page table pages. */
910 ptbl = ptbl_alloc(mmu, pmap, pdir_idx, nosleep);
911 if (ptbl == NULL) {
912 KASSERT(nosleep, ("nosleep and NULL ptbl"));
913 return (ENOMEM);
914 }
915 } else {
916 /*
917 * Check if there is valid mapping for requested
918 * va, if there is, remove it.
919 */
920 pte = &pmap->pm_pdir[pdir_idx][ptbl_idx];
921 if (PTE_ISVALID(pte)) {
922 pte_remove(mmu, pmap, va, PTBL_HOLD);
923 } else {
924 /*
925 * pte is not used, increment hold count
926 * for ptbl pages.
927 */
928 if (pmap != kernel_pmap)
929 ptbl_hold(mmu, pmap, pdir_idx);
930 }
931 }
932
933 /*
934 * Insert pv_entry into pv_list for mapped page if part of managed
935 * memory.
936 */
937 if ((m->oflags & VPO_UNMANAGED) == 0) {
938 flags |= PTE_MANAGED;
939
940 /* Create and insert pv entry. */
941 pv_insert(pmap, va, m);
942 }
943
944 pmap->pm_stats.resident_count++;
945
946 mtx_lock_spin(&tlbivax_mutex);
947 tlb_miss_lock();
948
949 tlb0_flush_entry(va);
950 if (pmap->pm_pdir[pdir_idx] == NULL) {
951 /*
952 * If we just allocated a new page table, hook it in
953 * the pdir.
954 */
955 pmap->pm_pdir[pdir_idx] = ptbl;
956 }
957 pte = &(pmap->pm_pdir[pdir_idx][ptbl_idx]);
958 pte->rpn = VM_PAGE_TO_PHYS(m) & ~PTE_PA_MASK;
959 pte->flags |= (PTE_VALID | flags);
960
961 tlb_miss_unlock();
962 mtx_unlock_spin(&tlbivax_mutex);
963 return (0);
964}
965
966/* Return the pa for the given pmap/va. */
967static vm_paddr_t
968pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va)
969{
970 vm_paddr_t pa = 0;
971 pte_t *pte;
972
973 pte = pte_find(mmu, pmap, va);
974 if ((pte != NULL) && PTE_ISVALID(pte))
975 pa = (PTE_PA(pte) | (va & PTE_PA_MASK));
976 return (pa);
977}
978
979/* Get a pointer to a PTE in a page table. */
980static pte_t *
981pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va)
982{
983 unsigned int pdir_idx = PDIR_IDX(va);
984 unsigned int ptbl_idx = PTBL_IDX(va);
985
986 KASSERT((pmap != NULL), ("pte_find: invalid pmap"));
987
988 if (pmap->pm_pdir[pdir_idx])
989 return (&(pmap->pm_pdir[pdir_idx][ptbl_idx]));
990
991 return (NULL);
992}
993
994/**************************************************************************/
995/* PMAP related */
996/**************************************************************************/
997
998/*
999 * This is called during booke_init, before the system is really initialized.
1000 */
1001static void
1002mmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend)
1003{
1004 vm_offset_t phys_kernelend;
1005 struct mem_region *mp, *mp1;
1006 int cnt, i, j;
1007 u_int s, e, sz;
1008 u_int phys_avail_count;
1009 vm_size_t physsz, hwphyssz, kstack0_sz;
1010 vm_offset_t kernel_pdir, kstack0, va;
1011 vm_paddr_t kstack0_phys;
1012 void *dpcpu;
1013 pte_t *pte;
1014
1015 debugf("mmu_booke_bootstrap: entered\n");
1016
1017 /* Initialize invalidation mutex */
1018 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN);
1019
1020 /* Read TLB0 size and associativity. */
1021 tlb0_get_tlbconf();
1022
1023 /*
1024 * Align kernel start and end address (kernel image).
1025 * Note that kernel end does not necessarily relate to kernsize.
1026 * kernsize is the size of the kernel that is actually mapped.
1027 * Also note that "start - 1" is deliberate. With SMP, the
1028 * entry point is exactly a page from the actual load address.
1029 * As such, trunc_page() has no effect and we're off by a page.
1030 * Since we always have the ELF header between the load address
1031 * and the entry point, we can safely subtract 1 to compensate.
1032 */
1033 kernstart = trunc_page(start - 1);
1034 data_start = round_page(kernelend);
1035 data_end = data_start;
1036
1037 /*
1038 * Addresses of preloaded modules (like file systems) use
1039 * physical addresses. Make sure we relocate those into
1040 * virtual addresses.
1041 */
1042 preload_addr_relocate = kernstart - kernload;
1043
1044 /* Allocate the dynamic per-cpu area. */
1045 dpcpu = (void *)data_end;
1046 data_end += DPCPU_SIZE;
1047
1048 /* Allocate space for the message buffer. */
1049 msgbufp = (struct msgbuf *)data_end;
1050 data_end += msgbufsize;
1051 debugf(" msgbufp at 0x%08x end = 0x%08x\n", (uint32_t)msgbufp,
1052 data_end);
1053
1054 data_end = round_page(data_end);
1055
1056 /* Allocate space for ptbl_bufs. */
1057 ptbl_bufs = (struct ptbl_buf *)data_end;
1058 data_end += sizeof(struct ptbl_buf) * PTBL_BUFS;
1059 debugf(" ptbl_bufs at 0x%08x end = 0x%08x\n", (uint32_t)ptbl_bufs,
1060 data_end);
1061
1062 data_end = round_page(data_end);
1063
1064 /* Allocate PTE tables for kernel KVA. */
1065 kernel_pdir = data_end;
1066 kernel_ptbls = (VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS +
1067 PDIR_SIZE - 1) / PDIR_SIZE;
1068 data_end += kernel_ptbls * PTBL_PAGES * PAGE_SIZE;
1069 debugf(" kernel ptbls: %d\n", kernel_ptbls);
1070 debugf(" kernel pdir at 0x%08x end = 0x%08x\n", kernel_pdir, data_end);
1071
1072 debugf(" data_end: 0x%08x\n", data_end);
1073 if (data_end - kernstart > kernsize) {
1074 kernsize += tlb1_mapin_region(kernstart + kernsize,
1075 kernload + kernsize, (data_end - kernstart) - kernsize);
1076 }
1077 data_end = kernstart + kernsize;
1078 debugf(" updated data_end: 0x%08x\n", data_end);
1079
1080 /*
1081 * Clear the structures - note we can only do it safely after the
1082 * possible additional TLB1 translations are in place (above) so that
1083 * all range up to the currently calculated 'data_end' is covered.
1084 */
1085 dpcpu_init(dpcpu, 0);
1086 memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE);
1087 memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE);
1088
1089 /*******************************************************/
1090 /* Set the start and end of kva. */
1091 /*******************************************************/
1092 virtual_avail = round_page(data_end);
1093 virtual_end = VM_MAX_KERNEL_ADDRESS;
1094
1095 /* Allocate KVA space for page zero/copy operations. */
1096 zero_page_va = virtual_avail;
1097 virtual_avail += PAGE_SIZE;
1098 zero_page_idle_va = virtual_avail;
1099 virtual_avail += PAGE_SIZE;
1100 copy_page_src_va = virtual_avail;
1101 virtual_avail += PAGE_SIZE;
1102 copy_page_dst_va = virtual_avail;
1103 virtual_avail += PAGE_SIZE;
1104 debugf("zero_page_va = 0x%08x\n", zero_page_va);
1105 debugf("zero_page_idle_va = 0x%08x\n", zero_page_idle_va);
1106 debugf("copy_page_src_va = 0x%08x\n", copy_page_src_va);
1107 debugf("copy_page_dst_va = 0x%08x\n", copy_page_dst_va);
1108
1109 /* Initialize page zero/copy mutexes. */
1110 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF);
1111 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF);
1112
1113 /* Allocate KVA space for ptbl bufs. */
1114 ptbl_buf_pool_vabase = virtual_avail;
1115 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE;
1116 debugf("ptbl_buf_pool_vabase = 0x%08x end = 0x%08x\n",
1117 ptbl_buf_pool_vabase, virtual_avail);
1118
1119 /* Calculate corresponding physical addresses for the kernel region. */
1120 phys_kernelend = kernload + kernsize;
1121 debugf("kernel image and allocated data:\n");
1122 debugf(" kernload = 0x%08x\n", kernload);
1123 debugf(" kernstart = 0x%08x\n", kernstart);
1124 debugf(" kernsize = 0x%08x\n", kernsize);
1125
1126 if (sizeof(phys_avail) / sizeof(phys_avail[0]) < availmem_regions_sz)
1127 panic("mmu_booke_bootstrap: phys_avail too small");
1128
1129 /*
1130 * Remove kernel physical address range from avail regions list. Page
1131 * align all regions. Non-page aligned memory isn't very interesting
1132 * to us. Also, sort the entries for ascending addresses.
1133 */
1134
1135 /* Retrieve phys/avail mem regions */
1136 mem_regions(&physmem_regions, &physmem_regions_sz,
1137 &availmem_regions, &availmem_regions_sz);
1138 sz = 0;
1139 cnt = availmem_regions_sz;
1140 debugf("processing avail regions:\n");
1141 for (mp = availmem_regions; mp->mr_size; mp++) {
1142 s = mp->mr_start;
1143 e = mp->mr_start + mp->mr_size;
1144 debugf(" %08x-%08x -> ", s, e);
1145 /* Check whether this region holds all of the kernel. */
1146 if (s < kernload && e > phys_kernelend) {
1147 availmem_regions[cnt].mr_start = phys_kernelend;
1148 availmem_regions[cnt++].mr_size = e - phys_kernelend;
1149 e = kernload;
1150 }
1151 /* Look whether this regions starts within the kernel. */
1152 if (s >= kernload && s < phys_kernelend) {
1153 if (e <= phys_kernelend)
1154 goto empty;
1155 s = phys_kernelend;
1156 }
1157 /* Now look whether this region ends within the kernel. */
1158 if (e > kernload && e <= phys_kernelend) {
1159 if (s >= kernload)
1160 goto empty;
1161 e = kernload;
1162 }
1163 /* Now page align the start and size of the region. */
1164 s = round_page(s);
1165 e = trunc_page(e);
1166 if (e < s)
1167 e = s;
1168 sz = e - s;
1169 debugf("%08x-%08x = %x\n", s, e, sz);
1170
1171 /* Check whether some memory is left here. */
1172 if (sz == 0) {
1173 empty:
1174 memmove(mp, mp + 1,
1175 (cnt - (mp - availmem_regions)) * sizeof(*mp));
1176 cnt--;
1177 mp--;
1178 continue;
1179 }
1180
1181 /* Do an insertion sort. */
1182 for (mp1 = availmem_regions; mp1 < mp; mp1++)
1183 if (s < mp1->mr_start)
1184 break;
1185 if (mp1 < mp) {
1186 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1);
1187 mp1->mr_start = s;
1188 mp1->mr_size = sz;
1189 } else {
1190 mp->mr_start = s;
1191 mp->mr_size = sz;
1192 }
1193 }
1194 availmem_regions_sz = cnt;
1195
1196 /*******************************************************/
1197 /* Steal physical memory for kernel stack from the end */
1198 /* of the first avail region */
1199 /*******************************************************/
1200 kstack0_sz = KSTACK_PAGES * PAGE_SIZE;
1201 kstack0_phys = availmem_regions[0].mr_start +
1202 availmem_regions[0].mr_size;
1203 kstack0_phys -= kstack0_sz;
1204 availmem_regions[0].mr_size -= kstack0_sz;
1205
1206 /*******************************************************/
1207 /* Fill in phys_avail table, based on availmem_regions */
1208 /*******************************************************/
1209 phys_avail_count = 0;
1210 physsz = 0;
1211 hwphyssz = 0;
1212 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
1213
1214 debugf("fill in phys_avail:\n");
1215 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) {
1216
1217 debugf(" region: 0x%08x - 0x%08x (0x%08x)\n",
1218 availmem_regions[i].mr_start,
1219 availmem_regions[i].mr_start +
1220 availmem_regions[i].mr_size,
1221 availmem_regions[i].mr_size);
1222
1223 if (hwphyssz != 0 &&
1224 (physsz + availmem_regions[i].mr_size) >= hwphyssz) {
1225 debugf(" hw.physmem adjust\n");
1226 if (physsz < hwphyssz) {
1227 phys_avail[j] = availmem_regions[i].mr_start;
1228 phys_avail[j + 1] =
1229 availmem_regions[i].mr_start +
1230 hwphyssz - physsz;
1231 physsz = hwphyssz;
1232 phys_avail_count++;
1233 }
1234 break;
1235 }
1236
1237 phys_avail[j] = availmem_regions[i].mr_start;
1238 phys_avail[j + 1] = availmem_regions[i].mr_start +
1239 availmem_regions[i].mr_size;
1240 phys_avail_count++;
1241 physsz += availmem_regions[i].mr_size;
1242 }
1243 physmem = btoc(physsz);
1244
1245 /* Calculate the last available physical address. */
1246 for (i = 0; phys_avail[i + 2] != 0; i += 2)
1247 ;
1248 Maxmem = powerpc_btop(phys_avail[i + 1]);
1249
1250 debugf("Maxmem = 0x%08lx\n", Maxmem);
1251 debugf("phys_avail_count = %d\n", phys_avail_count);
1252 debugf("physsz = 0x%08x physmem = %ld (0x%08lx)\n", physsz, physmem,
1253 physmem);
1254
1255 /*******************************************************/
1256 /* Initialize (statically allocated) kernel pmap. */
1257 /*******************************************************/
1258 PMAP_LOCK_INIT(kernel_pmap);
1259 kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE;
1260
1261 debugf("kernel_pmap = 0x%08x\n", (uint32_t)kernel_pmap);
1262 debugf("kptbl_min = %d, kernel_ptbls = %d\n", kptbl_min, kernel_ptbls);
1263 debugf("kernel pdir range: 0x%08x - 0x%08x\n",
1264 kptbl_min * PDIR_SIZE, (kptbl_min + kernel_ptbls) * PDIR_SIZE - 1);
1265
1266 /* Initialize kernel pdir */
1267 for (i = 0; i < kernel_ptbls; i++)
1268 kernel_pmap->pm_pdir[kptbl_min + i] =
1269 (pte_t *)(kernel_pdir + (i * PAGE_SIZE * PTBL_PAGES));
1270
1271 for (i = 0; i < MAXCPU; i++) {
1272 kernel_pmap->pm_tid[i] = TID_KERNEL;
1273
1274 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */
1275 tidbusy[i][0] = kernel_pmap;
1276 }
1277
1278 /*
1279 * Fill in PTEs covering kernel code and data. They are not required
1280 * for address translation, as this area is covered by static TLB1
1281 * entries, but for pte_vatopa() to work correctly with kernel area
1282 * addresses.
1283 */
1284 for (va = kernstart; va < data_end; va += PAGE_SIZE) {
1285 pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]);
1286 pte->rpn = kernload + (va - kernstart);
1287 pte->flags = PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED |
1288 PTE_VALID;
1289 }
1290 /* Mark kernel_pmap active on all CPUs */
1291 CPU_FILL(&kernel_pmap->pm_active);
1292
1293 /*
1294 * Initialize the global pv list lock.
1295 */
1296 rw_init(&pvh_global_lock, "pmap pv global");
1297
1298 /*******************************************************/
1299 /* Final setup */
1300 /*******************************************************/
1301
1302 /* Enter kstack0 into kernel map, provide guard page */
1303 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
1304 thread0.td_kstack = kstack0;
1305 thread0.td_kstack_pages = KSTACK_PAGES;
1306
1307 debugf("kstack_sz = 0x%08x\n", kstack0_sz);
1308 debugf("kstack0_phys at 0x%08x - 0x%08x\n",
1309 kstack0_phys, kstack0_phys + kstack0_sz);
1310 debugf("kstack0 at 0x%08x - 0x%08x\n", kstack0, kstack0 + kstack0_sz);
1311
1312 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz;
1313 for (i = 0; i < KSTACK_PAGES; i++) {
1314 mmu_booke_kenter(mmu, kstack0, kstack0_phys);
1315 kstack0 += PAGE_SIZE;
1316 kstack0_phys += PAGE_SIZE;
1317 }
1318
1319 debugf("virtual_avail = %08x\n", virtual_avail);
1320 debugf("virtual_end = %08x\n", virtual_end);
1321
1322 debugf("mmu_booke_bootstrap: exit\n");
1323}
1324
1325void
1326pmap_bootstrap_ap(volatile uint32_t *trcp __unused)
1327{
1328 int i;
1329
1330 /*
1331 * Finish TLB1 configuration: the BSP already set up its TLB1 and we
1332 * have the snapshot of its contents in the s/w tlb1[] table, so use
1333 * these values directly to (re)program AP's TLB1 hardware.
1334 */
1335 for (i = bp_ntlb1s; i < tlb1_idx; i++) {
1336 /* Skip invalid entries */
1337 if (!(tlb1[i].mas1 & MAS1_VALID))
1338 continue;
1339
1340 tlb1_write_entry(i);
1341 }
1342
1343 set_mas4_defaults();
1344}
1345
1346/*
1347 * Get the physical page address for the given pmap/virtual address.
1348 */
1349static vm_paddr_t
1350mmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1351{
1352 vm_paddr_t pa;
1353
1354 PMAP_LOCK(pmap);
1355 pa = pte_vatopa(mmu, pmap, va);
1356 PMAP_UNLOCK(pmap);
1357
1358 return (pa);
1359}
1360
1361/*
1362 * Extract the physical page address associated with the given
1363 * kernel virtual address.
1364 */
1365static vm_paddr_t
1366mmu_booke_kextract(mmu_t mmu, vm_offset_t va)
1367{
1368 int i;
1369
1370 /* Check TLB1 mappings */
1371 for (i = 0; i < tlb1_idx; i++) {
1372 if (!(tlb1[i].mas1 & MAS1_VALID))
1373 continue;
1374 if (va >= tlb1[i].virt && va < tlb1[i].virt + tlb1[i].size)
1375 return (tlb1[i].phys + (va - tlb1[i].virt));
1376 }
1377
1378 return (pte_vatopa(mmu, kernel_pmap, va));
1379}
1380
1381/*
1382 * Initialize the pmap module.
1383 * Called by vm_init, to initialize any structures that the pmap
1384 * system needs to map virtual memory.
1385 */
1386static void
1387mmu_booke_init(mmu_t mmu)
1388{
1389 int shpgperproc = PMAP_SHPGPERPROC;
1390
1391 /*
1392 * Initialize the address space (zone) for the pv entries. Set a
1393 * high water mark so that the system can recover from excessive
1394 * numbers of pv entries.
1395 */
1396 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL,
1397 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1398
1399 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1400 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count;
1401
1402 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
1403 pv_entry_high_water = 9 * (pv_entry_max / 10);
1404
1405 uma_zone_reserve_kva(pvzone, pv_entry_max);
1406
1407 /* Pre-fill pvzone with initial number of pv entries. */
1408 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN);
1409
1410 /* Initialize ptbl allocation. */
1411 ptbl_init();
1412}
1413
1414/*
1415 * Map a list of wired pages into kernel virtual address space. This is
1416 * intended for temporary mappings which do not need page modification or
1417 * references recorded. Existing mappings in the region are overwritten.
1418 */
1419static void
1420mmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count)
1421{
1422 vm_offset_t va;
1423
1424 va = sva;
1425 while (count-- > 0) {
1426 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
1427 va += PAGE_SIZE;
1428 m++;
1429 }
1430}
1431
1432/*
1433 * Remove page mappings from kernel virtual address space. Intended for
1434 * temporary mappings entered by mmu_booke_qenter.
1435 */
1436static void
1437mmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count)
1438{
1439 vm_offset_t va;
1440
1441 va = sva;
1442 while (count-- > 0) {
1443 mmu_booke_kremove(mmu, va);
1444 va += PAGE_SIZE;
1445 }
1446}
1447
1448/*
1449 * Map a wired page into kernel virtual address space.
1450 */
1451static void
1452mmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa)
1453{
1454
1455 mmu_booke_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT);
1456}
1457
1458static void
1459mmu_booke_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma)
1460{
1461 unsigned int pdir_idx = PDIR_IDX(va);
1462 unsigned int ptbl_idx = PTBL_IDX(va);
1463 uint32_t flags;
1464 pte_t *pte;
1465
1466 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) &&
1467 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va"));
1468
1469 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID;
1470 flags |= tlb_calc_wimg(pa, ma);
1471
1472 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]);
1473
1474 mtx_lock_spin(&tlbivax_mutex);
1475 tlb_miss_lock();
1476
1477 if (PTE_ISVALID(pte)) {
1478
1479 CTR1(KTR_PMAP, "%s: replacing entry!", __func__);
1480
1481 /* Flush entry from TLB0 */
1482 tlb0_flush_entry(va);
1483 }
1484
1485 pte->rpn = pa & ~PTE_PA_MASK;
1486 pte->flags = flags;
1487
1488 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x "
1489 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n",
1490 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags);
1491
1492 /* Flush the real memory from the instruction cache. */
1493 if ((flags & (PTE_I | PTE_G)) == 0) {
1494 __syncicache((void *)va, PAGE_SIZE);
1495 }
1496
1497 tlb_miss_unlock();
1498 mtx_unlock_spin(&tlbivax_mutex);
1499}
1500
1501/*
1502 * Remove a page from kernel page table.
1503 */
1504static void
1505mmu_booke_kremove(mmu_t mmu, vm_offset_t va)
1506{
1507 unsigned int pdir_idx = PDIR_IDX(va);
1508 unsigned int ptbl_idx = PTBL_IDX(va);
1509 pte_t *pte;
1510
1511// CTR2(KTR_PMAP,("%s: s (va = 0x%08x)\n", __func__, va));
1512
1513 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) &&
1514 (va <= VM_MAX_KERNEL_ADDRESS)),
1515 ("mmu_booke_kremove: invalid va"));
1516
1517 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]);
1518
1519 if (!PTE_ISVALID(pte)) {
1520
1521 CTR1(KTR_PMAP, "%s: invalid pte", __func__);
1522
1523 return;
1524 }
1525
1526 mtx_lock_spin(&tlbivax_mutex);
1527 tlb_miss_lock();
1528
1529 /* Invalidate entry in TLB0, update PTE. */
1530 tlb0_flush_entry(va);
1531 pte->flags = 0;
1532 pte->rpn = 0;
1533
1534 tlb_miss_unlock();
1535 mtx_unlock_spin(&tlbivax_mutex);
1536}
1537
1538/*
1539 * Initialize pmap associated with process 0.
1540 */
1541static void
1542mmu_booke_pinit0(mmu_t mmu, pmap_t pmap)
1543{
1544
1545 PMAP_LOCK_INIT(pmap);
1546 mmu_booke_pinit(mmu, pmap);
1547 PCPU_SET(curpmap, pmap);
1548}
1549
1550/*
1551 * Initialize a preallocated and zeroed pmap structure,
1552 * such as one in a vmspace structure.
1553 */
1554static void
1555mmu_booke_pinit(mmu_t mmu, pmap_t pmap)
1556{
1557 int i;
1558
1559 CTR4(KTR_PMAP, "%s: pmap = %p, proc %d '%s'", __func__, pmap,
1560 curthread->td_proc->p_pid, curthread->td_proc->p_comm);
1561
1562 KASSERT((pmap != kernel_pmap), ("pmap_pinit: initializing kernel_pmap"));
1563
1564 for (i = 0; i < MAXCPU; i++)
1565 pmap->pm_tid[i] = TID_NONE;
1566 CPU_ZERO(&kernel_pmap->pm_active);
1567 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1568 bzero(&pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES);
1569 TAILQ_INIT(&pmap->pm_ptbl_list);
1570}
1571
1572/*
1573 * Release any resources held by the given physical map.
1574 * Called when a pmap initialized by mmu_booke_pinit is being released.
1575 * Should only be called if the map contains no valid mappings.
1576 */
1577static void
1578mmu_booke_release(mmu_t mmu, pmap_t pmap)
1579{
1580
1581 KASSERT(pmap->pm_stats.resident_count == 0,
1582 ("pmap_release: pmap resident count %ld != 0",
1583 pmap->pm_stats.resident_count));
1584}
1585
1586/*
1587 * Insert the given physical page at the specified virtual address in the
1588 * target physical map with the protection requested. If specified the page
1589 * will be wired down.
1590 */
1591static int
1592mmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1593 vm_prot_t prot, u_int flags, int8_t psind)
1594{
1595 int error;
1596
1597 rw_wlock(&pvh_global_lock);
1598 PMAP_LOCK(pmap);
1599 error = mmu_booke_enter_locked(mmu, pmap, va, m, prot, flags, psind);
1600 rw_wunlock(&pvh_global_lock);
1601 PMAP_UNLOCK(pmap);
1602 return (error);
1603}
1604
1605static int
1606mmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1607 vm_prot_t prot, u_int pmap_flags, int8_t psind __unused)
1608{
1609 pte_t *pte;
1610 vm_paddr_t pa;
1611 uint32_t flags;
1612 int error, su, sync;
1613
1614 pa = VM_PAGE_TO_PHYS(m);
1615 su = (pmap == kernel_pmap);
1616 sync = 0;
1617
1618 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x "
1619 // "pa=0x%08x prot=0x%08x flags=%#x)\n",
1620 // (u_int32_t)pmap, su, pmap->pm_tid,
1621 // (u_int32_t)m, va, pa, prot, flags);
1622
1623 if (su) {
1624 KASSERT(((va >= virtual_avail) &&
1625 (va <= VM_MAX_KERNEL_ADDRESS)),
1626 ("mmu_booke_enter_locked: kernel pmap, non kernel va"));
1627 } else {
1628 KASSERT((va <= VM_MAXUSER_ADDRESS),
1629 ("mmu_booke_enter_locked: user pmap, non user va"));
1630 }
1631 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
1632 VM_OBJECT_ASSERT_LOCKED(m->object);
1633
1634 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1635
1636 /*
1637 * If there is an existing mapping, and the physical address has not
1638 * changed, must be protection or wiring change.
1639 */
1640 if (((pte = pte_find(mmu, pmap, va)) != NULL) &&
1641 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) {
1642
1643 /*
1644 * Before actually updating pte->flags we calculate and
1645 * prepare its new value in a helper var.
1646 */
1647 flags = pte->flags;
1648 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED);
1649
1650 /* Wiring change, just update stats. */
1651 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) {
1652 if (!PTE_ISWIRED(pte)) {
1653 flags |= PTE_WIRED;
1654 pmap->pm_stats.wired_count++;
1655 }
1656 } else {
1657 if (PTE_ISWIRED(pte)) {
1658 flags &= ~PTE_WIRED;
1659 pmap->pm_stats.wired_count--;
1660 }
1661 }
1662
1663 if (prot & VM_PROT_WRITE) {
1664 /* Add write permissions. */
1665 flags |= PTE_SW;
1666 if (!su)
1667 flags |= PTE_UW;
1668
1669 if ((flags & PTE_MANAGED) != 0)
1670 vm_page_aflag_set(m, PGA_WRITEABLE);
1671 } else {
1672 /* Handle modified pages, sense modify status. */
1673
1674 /*
1675 * The PTE_MODIFIED flag could be set by underlying
1676 * TLB misses since we last read it (above), possibly
1677 * other CPUs could update it so we check in the PTE
1678 * directly rather than rely on that saved local flags
1679 * copy.
1680 */
1681 if (PTE_ISMODIFIED(pte))
1682 vm_page_dirty(m);
1683 }
1684
1685 if (prot & VM_PROT_EXECUTE) {
1686 flags |= PTE_SX;
1687 if (!su)
1688 flags |= PTE_UX;
1689
1690 /*
1691 * Check existing flags for execute permissions: if we
1692 * are turning execute permissions on, icache should
1693 * be flushed.
1694 */
1695 if ((pte->flags & (PTE_UX | PTE_SX)) == 0)
1696 sync++;
1697 }
1698
1699 flags &= ~PTE_REFERENCED;
1700
1701 /*
1702 * The new flags value is all calculated -- only now actually
1703 * update the PTE.
1704 */
1705 mtx_lock_spin(&tlbivax_mutex);
1706 tlb_miss_lock();
1707
1708 tlb0_flush_entry(va);
1709 pte->flags = flags;
1710
1711 tlb_miss_unlock();
1712 mtx_unlock_spin(&tlbivax_mutex);
1713
1714 } else {
1715 /*
1716 * If there is an existing mapping, but it's for a different
1717 * physical address, pte_enter() will delete the old mapping.
1718 */
1719 //if ((pte != NULL) && PTE_ISVALID(pte))
1720 // debugf("mmu_booke_enter_locked: replace\n");
1721 //else
1722 // debugf("mmu_booke_enter_locked: new\n");
1723
1724 /* Now set up the flags and install the new mapping. */
1725 flags = (PTE_SR | PTE_VALID);
1726 flags |= PTE_M;
1727
1728 if (!su)
1729 flags |= PTE_UR;
1730
1731 if (prot & VM_PROT_WRITE) {
1732 flags |= PTE_SW;
1733 if (!su)
1734 flags |= PTE_UW;
1735
1736 if ((m->oflags & VPO_UNMANAGED) == 0)
1737 vm_page_aflag_set(m, PGA_WRITEABLE);
1738 }
1739
1740 if (prot & VM_PROT_EXECUTE) {
1741 flags |= PTE_SX;
1742 if (!su)
1743 flags |= PTE_UX;
1744 }
1745
1746 /* If its wired update stats. */
1747 if ((pmap_flags & PMAP_ENTER_WIRED) != 0)
1748 flags |= PTE_WIRED;
1749
1750 error = pte_enter(mmu, pmap, m, va, flags,
1751 (pmap_flags & PMAP_ENTER_NOSLEEP) != 0);
1752 if (error != 0)
1753 return (KERN_RESOURCE_SHORTAGE);
1754
1755 if ((flags & PMAP_ENTER_WIRED) != 0)
1756 pmap->pm_stats.wired_count++;
1757
1758 /* Flush the real memory from the instruction cache. */
1759 if (prot & VM_PROT_EXECUTE)
1760 sync++;
1761 }
1762
1763 if (sync && (su || pmap == PCPU_GET(curpmap))) {
1764 __syncicache((void *)va, PAGE_SIZE);
1765 sync = 0;
1766 }
1767
1768 return (KERN_SUCCESS);
1769}
1770
1771/*
1772 * Maps a sequence of resident pages belonging to the same object.
1773 * The sequence begins with the given page m_start. This page is
1774 * mapped at the given virtual address start. Each subsequent page is
1775 * mapped at a virtual address that is offset from start by the same
1776 * amount as the page is offset from m_start within the object. The
1777 * last page in the sequence is the page with the largest offset from
1778 * m_start that can be mapped at a virtual address less than the given
1779 * virtual address end. Not every virtual page between start and end
1780 * is mapped; only those for which a resident page exists with the
1781 * corresponding offset from m_start are mapped.
1782 */
1783static void
1784mmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start,
1785 vm_offset_t end, vm_page_t m_start, vm_prot_t prot)
1786{
1787 vm_page_t m;
1788 vm_pindex_t diff, psize;
1789
1790 VM_OBJECT_ASSERT_LOCKED(m_start->object);
1791
1792 psize = atop(end - start);
1793 m = m_start;
1794 rw_wlock(&pvh_global_lock);
1795 PMAP_LOCK(pmap);
1796 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1797 mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m,
1798 prot & (VM_PROT_READ | VM_PROT_EXECUTE),
1799 PMAP_ENTER_NOSLEEP, 0);
1800 m = TAILQ_NEXT(m, listq);
1801 }
1802 rw_wunlock(&pvh_global_lock);
1803 PMAP_UNLOCK(pmap);
1804}
1805
1806static void
1807mmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1808 vm_prot_t prot)
1809{
1810
1811 rw_wlock(&pvh_global_lock);
1812 PMAP_LOCK(pmap);
1813 mmu_booke_enter_locked(mmu, pmap, va, m,
1814 prot & (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP,
1815 0);
1816 rw_wunlock(&pvh_global_lock);
1817 PMAP_UNLOCK(pmap);
1818}
1819
1820/*
1821 * Remove the given range of addresses from the specified map.
1822 *
1823 * It is assumed that the start and end are properly rounded to the page size.
1824 */
1825static void
1826mmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva)
1827{
1828 pte_t *pte;
1829 uint8_t hold_flag;
1830
1831 int su = (pmap == kernel_pmap);
1832
1833 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n",
1834 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva);
1835
1836 if (su) {
1837 KASSERT(((va >= virtual_avail) &&
1838 (va <= VM_MAX_KERNEL_ADDRESS)),
1839 ("mmu_booke_remove: kernel pmap, non kernel va"));
1840 } else {
1841 KASSERT((va <= VM_MAXUSER_ADDRESS),
1842 ("mmu_booke_remove: user pmap, non user va"));
1843 }
1844
1845 if (PMAP_REMOVE_DONE(pmap)) {
1846 //debugf("mmu_booke_remove: e (empty)\n");
1847 return;
1848 }
1849
1850 hold_flag = PTBL_HOLD_FLAG(pmap);
1851 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag);
1852
1853 rw_wlock(&pvh_global_lock);
1854 PMAP_LOCK(pmap);
1855 for (; va < endva; va += PAGE_SIZE) {
1856 pte = pte_find(mmu, pmap, va);
1857 if ((pte != NULL) && PTE_ISVALID(pte))
1858 pte_remove(mmu, pmap, va, hold_flag);
1859 }
1860 PMAP_UNLOCK(pmap);
1861 rw_wunlock(&pvh_global_lock);
1862
1863 //debugf("mmu_booke_remove: e\n");
1864}
1865
1866/*
1867 * Remove physical page from all pmaps in which it resides.
1868 */
1869static void
1870mmu_booke_remove_all(mmu_t mmu, vm_page_t m)
1871{
1872 pv_entry_t pv, pvn;
1873 uint8_t hold_flag;
1874
1875 rw_wlock(&pvh_global_lock);
1876 for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) {
1877 pvn = TAILQ_NEXT(pv, pv_link);
1878
1879 PMAP_LOCK(pv->pv_pmap);
1880 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap);
1881 pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag);
1882 PMAP_UNLOCK(pv->pv_pmap);
1883 }
1884 vm_page_aflag_clear(m, PGA_WRITEABLE);
1885 rw_wunlock(&pvh_global_lock);
1886}
1887
1888/*
1889 * Map a range of physical addresses into kernel virtual address space.
1890 */
1891static vm_offset_t
1892mmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start,
1893 vm_paddr_t pa_end, int prot)
1894{
1895 vm_offset_t sva = *virt;
1896 vm_offset_t va = sva;
1897
1898 //debugf("mmu_booke_map: s (sva = 0x%08x pa_start = 0x%08x pa_end = 0x%08x)\n",
1899 // sva, pa_start, pa_end);
1900
1901 while (pa_start < pa_end) {
1902 mmu_booke_kenter(mmu, va, pa_start);
1903 va += PAGE_SIZE;
1904 pa_start += PAGE_SIZE;
1905 }
1906 *virt = va;
1907
1908 //debugf("mmu_booke_map: e (va = 0x%08x)\n", va);
1909 return (sva);
1910}
1911
1912/*
1913 * The pmap must be activated before it's address space can be accessed in any
1914 * way.
1915 */
1916static void
1917mmu_booke_activate(mmu_t mmu, struct thread *td)
1918{
1919 pmap_t pmap;
1920 u_int cpuid;
1921
1922 pmap = &td->td_proc->p_vmspace->vm_pmap;
1923
1924 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%08x)",
1925 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap);
1926
1927 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!"));
1928
1929 sched_pin();
1930
1931 cpuid = PCPU_GET(cpuid);
1932 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
1933 PCPU_SET(curpmap, pmap);
1934
1935 if (pmap->pm_tid[cpuid] == TID_NONE)
1936 tid_alloc(pmap);
1937
1938 /* Load PID0 register with pmap tid value. */
1939 mtspr(SPR_PID0, pmap->pm_tid[cpuid]);
1940 __asm __volatile("isync");
1941
1942 sched_unpin();
1943
1944 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__,
1945 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm);
1946}
1947
1948/*
1949 * Deactivate the specified process's address space.
1950 */
1951static void
1952mmu_booke_deactivate(mmu_t mmu, struct thread *td)
1953{
1954 pmap_t pmap;
1955
1956 pmap = &td->td_proc->p_vmspace->vm_pmap;
1957
1958 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%08x",
1959 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap);
1960
1961 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active);
1962 PCPU_SET(curpmap, NULL);
1963}
1964
1965/*
1966 * Copy the range specified by src_addr/len
1967 * from the source map to the range dst_addr/len
1968 * in the destination map.
1969 *
1970 * This routine is only advisory and need not do anything.
1971 */
1972static void
1973mmu_booke_copy(mmu_t mmu, pmap_t dst_pmap, pmap_t src_pmap,
1974 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr)
1975{
1976
1977}
1978
1979/*
1980 * Set the physical protection on the specified range of this map as requested.
1981 */
1982static void
1983mmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1984 vm_prot_t prot)
1985{
1986 vm_offset_t va;
1987 vm_page_t m;
1988 pte_t *pte;
1989
1990 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1991 mmu_booke_remove(mmu, pmap, sva, eva);
1992 return;
1993 }
1994
1995 if (prot & VM_PROT_WRITE)
1996 return;
1997
1998 PMAP_LOCK(pmap);
1999 for (va = sva; va < eva; va += PAGE_SIZE) {
2000 if ((pte = pte_find(mmu, pmap, va)) != NULL) {
2001 if (PTE_ISVALID(pte)) {
2002 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
2003
2004 mtx_lock_spin(&tlbivax_mutex);
2005 tlb_miss_lock();
2006
2007 /* Handle modified pages. */
2008 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte))
2009 vm_page_dirty(m);
2010
2011 tlb0_flush_entry(va);
2012 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED);
2013
2014 tlb_miss_unlock();
2015 mtx_unlock_spin(&tlbivax_mutex);
2016 }
2017 }
2018 }
2019 PMAP_UNLOCK(pmap);
2020}
2021
2022/*
2023 * Clear the write and modified bits in each of the given page's mappings.
2024 */
2025static void
2026mmu_booke_remove_write(mmu_t mmu, vm_page_t m)
2027{
2028 pv_entry_t pv;
2029 pte_t *pte;
2030
2031 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2032 ("mmu_booke_remove_write: page %p is not managed", m));
2033
2034 /*
2035 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
2036 * set by another thread while the object is locked. Thus,
2037 * if PGA_WRITEABLE is clear, no page table entries need updating.
2038 */
2039 VM_OBJECT_ASSERT_WLOCKED(m->object);
2040 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
2041 return;
2042 rw_wlock(&pvh_global_lock);
2043 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2044 PMAP_LOCK(pv->pv_pmap);
2045 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) {
2046 if (PTE_ISVALID(pte)) {
2047 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
2048
2049 mtx_lock_spin(&tlbivax_mutex);
2050 tlb_miss_lock();
2051
2052 /* Handle modified pages. */
2053 if (PTE_ISMODIFIED(pte))
2054 vm_page_dirty(m);
2055
2056 /* Flush mapping from TLB0. */
2057 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED);
2058
2059 tlb_miss_unlock();
2060 mtx_unlock_spin(&tlbivax_mutex);
2061 }
2062 }
2063 PMAP_UNLOCK(pv->pv_pmap);
2064 }
2065 vm_page_aflag_clear(m, PGA_WRITEABLE);
2066 rw_wunlock(&pvh_global_lock);
2067}
2068
2069static void
2070mmu_booke_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
2071{
2072 pte_t *pte;
2073 pmap_t pmap;
2074 vm_page_t m;
2075 vm_offset_t addr;
2076 vm_paddr_t pa;
2077 int active, valid;
2078
2079 va = trunc_page(va);
2080 sz = round_page(sz);
2081
2082 rw_wlock(&pvh_global_lock);
2083 pmap = PCPU_GET(curpmap);
2084 active = (pm == kernel_pmap || pm == pmap) ? 1 : 0;
2085 while (sz > 0) {
2086 PMAP_LOCK(pm);
2087 pte = pte_find(mmu, pm, va);
2088 valid = (pte != NULL && PTE_ISVALID(pte)) ? 1 : 0;
2089 if (valid)
2090 pa = PTE_PA(pte);
2091 PMAP_UNLOCK(pm);
2092 if (valid) {
2093 if (!active) {
2094 /* Create a mapping in the active pmap. */
2095 addr = 0;
2096 m = PHYS_TO_VM_PAGE(pa);
2097 PMAP_LOCK(pmap);
2098 pte_enter(mmu, pmap, m, addr,
2099 PTE_SR | PTE_VALID | PTE_UR, FALSE);
2100 __syncicache((void *)addr, PAGE_SIZE);
2101 pte_remove(mmu, pmap, addr, PTBL_UNHOLD);
2102 PMAP_UNLOCK(pmap);
2103 } else
2104 __syncicache((void *)va, PAGE_SIZE);
2105 }
2106 va += PAGE_SIZE;
2107 sz -= PAGE_SIZE;
2108 }
2109 rw_wunlock(&pvh_global_lock);
2110}
2111
2112/*
2113 * Atomically extract and hold the physical page with the given
2114 * pmap and virtual address pair if that mapping permits the given
2115 * protection.
2116 */
2117static vm_page_t
2118mmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va,
2119 vm_prot_t prot)
2120{
2121 pte_t *pte;
2122 vm_page_t m;
2123 uint32_t pte_wbit;
2124 vm_paddr_t pa;
2125
2126 m = NULL;
2127 pa = 0;
2128 PMAP_LOCK(pmap);
2129retry:
2130 pte = pte_find(mmu, pmap, va);
2131 if ((pte != NULL) && PTE_ISVALID(pte)) {
2132 if (pmap == kernel_pmap)
2133 pte_wbit = PTE_SW;
2134 else
2135 pte_wbit = PTE_UW;
2136
2137 if ((pte->flags & pte_wbit) || ((prot & VM_PROT_WRITE) == 0)) {
2138 if (vm_page_pa_tryrelock(pmap, PTE_PA(pte), &pa))
2139 goto retry;
2140 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
2141 vm_page_hold(m);
2142 }
2143 }
2144
2145 PA_UNLOCK_COND(pa);
2146 PMAP_UNLOCK(pmap);
2147 return (m);
2148}
2149
2150/*
2151 * Initialize a vm_page's machine-dependent fields.
2152 */
2153static void
2154mmu_booke_page_init(mmu_t mmu, vm_page_t m)
2155{
2156
2157 TAILQ_INIT(&m->md.pv_list);
2158}
2159
2160/*
2161 * mmu_booke_zero_page_area zeros the specified hardware page by
2162 * mapping it into virtual memory and using bzero to clear
2163 * its contents.
2164 *
2165 * off and size must reside within a single page.
2166 */
2167static void
2168mmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
2169{
2170 vm_offset_t va;
2171
2172 /* XXX KASSERT off and size are within a single page? */
2173
2174 mtx_lock(&zero_page_mutex);
2175 va = zero_page_va;
2176
2177 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m));
2178 bzero((caddr_t)va + off, size);
2179 mmu_booke_kremove(mmu, va);
2180
2181 mtx_unlock(&zero_page_mutex);
2182}
2183
2184/*
2185 * mmu_booke_zero_page zeros the specified hardware page.
2186 */
2187static void
2188mmu_booke_zero_page(mmu_t mmu, vm_page_t m)
2189{
2190
2191 mmu_booke_zero_page_area(mmu, m, 0, PAGE_SIZE);
2192}
2193
2194/*
2195 * mmu_booke_copy_page copies the specified (machine independent) page by
2196 * mapping the page into virtual memory and using memcopy to copy the page,
2197 * one machine dependent page at a time.
2198 */
2199static void
2200mmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm)
2201{
2202 vm_offset_t sva, dva;
2203
2204 sva = copy_page_src_va;
2205 dva = copy_page_dst_va;
2206
2207 mtx_lock(©_page_mutex);
2208 mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm));
2209 mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm));
2210 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE);
2211 mmu_booke_kremove(mmu, dva);
2212 mmu_booke_kremove(mmu, sva);
2213 mtx_unlock(©_page_mutex);
2214}
2215
2216static inline void
2217mmu_booke_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
2218 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
2219{
2220 void *a_cp, *b_cp;
2221 vm_offset_t a_pg_offset, b_pg_offset;
2222 int cnt;
2223
2224 mtx_lock(©_page_mutex);
2225 while (xfersize > 0) {
2226 a_pg_offset = a_offset & PAGE_MASK;
2227 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
2228 mmu_booke_kenter(mmu, copy_page_src_va,
2229 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]));
2230 a_cp = (char *)copy_page_src_va + a_pg_offset;
2231 b_pg_offset = b_offset & PAGE_MASK;
2232 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
2233 mmu_booke_kenter(mmu, copy_page_dst_va,
2234 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]));
2235 b_cp = (char *)copy_page_dst_va + b_pg_offset;
2236 bcopy(a_cp, b_cp, cnt);
2237 mmu_booke_kremove(mmu, copy_page_dst_va);
2238 mmu_booke_kremove(mmu, copy_page_src_va);
2239 a_offset += cnt;
2240 b_offset += cnt;
2241 xfersize -= cnt;
2242 }
2243 mtx_unlock(©_page_mutex);
2244}
2245
2246/*
2247 * mmu_booke_zero_page_idle zeros the specified hardware page by mapping it
2248 * into virtual memory and using bzero to clear its contents. This is intended
2249 * to be called from the vm_pagezero process only and outside of Giant. No
2250 * lock is required.
2251 */
2252static void
2253mmu_booke_zero_page_idle(mmu_t mmu, vm_page_t m)
2254{
2255 vm_offset_t va;
2256
2257 va = zero_page_idle_va;
2258 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m));
2259 bzero((caddr_t)va, PAGE_SIZE);
2260 mmu_booke_kremove(mmu, va);
2261}
2262
2263/*
2264 * Return whether or not the specified physical page was modified
2265 * in any of physical maps.
2266 */
2267static boolean_t
2268mmu_booke_is_modified(mmu_t mmu, vm_page_t m)
2269{
2270 pte_t *pte;
2271 pv_entry_t pv;
2272 boolean_t rv;
2273
2274 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2275 ("mmu_booke_is_modified: page %p is not managed", m));
2276 rv = FALSE;
2277
2278 /*
2279 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
2280 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
2281 * is clear, no PTEs can be modified.
2282 */
2283 VM_OBJECT_ASSERT_WLOCKED(m->object);
2284 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
2285 return (rv);
2286 rw_wlock(&pvh_global_lock);
2287 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2288 PMAP_LOCK(pv->pv_pmap);
2289 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2290 PTE_ISVALID(pte)) {
2291 if (PTE_ISMODIFIED(pte))
2292 rv = TRUE;
2293 }
2294 PMAP_UNLOCK(pv->pv_pmap);
2295 if (rv)
2296 break;
2297 }
2298 rw_wunlock(&pvh_global_lock);
2299 return (rv);
2300}
2301
2302/*
2303 * Return whether or not the specified virtual address is eligible
2304 * for prefault.
2305 */
2306static boolean_t
2307mmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr)
2308{
2309
2310 return (FALSE);
2311}
2312
2313/*
2314 * Return whether or not the specified physical page was referenced
2315 * in any physical maps.
2316 */
2317static boolean_t
2318mmu_booke_is_referenced(mmu_t mmu, vm_page_t m)
2319{
2320 pte_t *pte;
2321 pv_entry_t pv;
2322 boolean_t rv;
2323
2324 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2325 ("mmu_booke_is_referenced: page %p is not managed", m));
2326 rv = FALSE;
2327 rw_wlock(&pvh_global_lock);
2328 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2329 PMAP_LOCK(pv->pv_pmap);
2330 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2331 PTE_ISVALID(pte)) {
2332 if (PTE_ISREFERENCED(pte))
2333 rv = TRUE;
2334 }
2335 PMAP_UNLOCK(pv->pv_pmap);
2336 if (rv)
2337 break;
2338 }
2339 rw_wunlock(&pvh_global_lock);
2340 return (rv);
2341}
2342
2343/*
2344 * Clear the modify bits on the specified physical page.
2345 */
2346static void
2347mmu_booke_clear_modify(mmu_t mmu, vm_page_t m)
2348{
2349 pte_t *pte;
2350 pv_entry_t pv;
2351
2352 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2353 ("mmu_booke_clear_modify: page %p is not managed", m));
2354 VM_OBJECT_ASSERT_WLOCKED(m->object);
2355 KASSERT(!vm_page_xbusied(m),
2356 ("mmu_booke_clear_modify: page %p is exclusive busied", m));
2357
2358 /*
2359 * If the page is not PG_AWRITEABLE, then no PTEs can be modified.
2360 * If the object containing the page is locked and the page is not
2361 * exclusive busied, then PG_AWRITEABLE cannot be concurrently set.
2362 */
2363 if ((m->aflags & PGA_WRITEABLE) == 0)
2364 return;
2365 rw_wlock(&pvh_global_lock);
2366 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2367 PMAP_LOCK(pv->pv_pmap);
2368 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2369 PTE_ISVALID(pte)) {
2370 mtx_lock_spin(&tlbivax_mutex);
2371 tlb_miss_lock();
2372
2373 if (pte->flags & (PTE_SW | PTE_UW | PTE_MODIFIED)) {
2374 tlb0_flush_entry(pv->pv_va);
2375 pte->flags &= ~(PTE_SW | PTE_UW | PTE_MODIFIED |
2376 PTE_REFERENCED);
2377 }
2378
2379 tlb_miss_unlock();
2380 mtx_unlock_spin(&tlbivax_mutex);
2381 }
2382 PMAP_UNLOCK(pv->pv_pmap);
2383 }
2384 rw_wunlock(&pvh_global_lock);
2385}
2386
2387/*
2388 * Return a count of reference bits for a page, clearing those bits.
2389 * It is not necessary for every reference bit to be cleared, but it
2390 * is necessary that 0 only be returned when there are truly no
2391 * reference bits set.
2392 *
2393 * XXX: The exact number of bits to check and clear is a matter that
2394 * should be tested and standardized at some point in the future for
2395 * optimal aging of shared pages.
2396 */
2397static int
2398mmu_booke_ts_referenced(mmu_t mmu, vm_page_t m)
2399{
2400 pte_t *pte;
2401 pv_entry_t pv;
2402 int count;
2403
2404 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2405 ("mmu_booke_ts_referenced: page %p is not managed", m));
2406 count = 0;
2407 rw_wlock(&pvh_global_lock);
2408 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2409 PMAP_LOCK(pv->pv_pmap);
2410 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2411 PTE_ISVALID(pte)) {
2412 if (PTE_ISREFERENCED(pte)) {
2413 mtx_lock_spin(&tlbivax_mutex);
2414 tlb_miss_lock();
2415
2416 tlb0_flush_entry(pv->pv_va);
2417 pte->flags &= ~PTE_REFERENCED;
2418
2419 tlb_miss_unlock();
2420 mtx_unlock_spin(&tlbivax_mutex);
2421
2422 if (++count > 4) {
2423 PMAP_UNLOCK(pv->pv_pmap);
2424 break;
2425 }
2426 }
2427 }
2428 PMAP_UNLOCK(pv->pv_pmap);
2429 }
2430 rw_wunlock(&pvh_global_lock);
2431 return (count);
2432}
2433
2434/*
| 364 MMUMETHOD(mmu_zero_page, mmu_booke_zero_page),
365 MMUMETHOD(mmu_zero_page_area, mmu_booke_zero_page_area),
366 MMUMETHOD(mmu_zero_page_idle, mmu_booke_zero_page_idle),
367 MMUMETHOD(mmu_activate, mmu_booke_activate),
368 MMUMETHOD(mmu_deactivate, mmu_booke_deactivate),
369
370 /* Internal interfaces */
371 MMUMETHOD(mmu_bootstrap, mmu_booke_bootstrap),
372 MMUMETHOD(mmu_dev_direct_mapped,mmu_booke_dev_direct_mapped),
373 MMUMETHOD(mmu_mapdev, mmu_booke_mapdev),
374 MMUMETHOD(mmu_mapdev_attr, mmu_booke_mapdev_attr),
375 MMUMETHOD(mmu_kenter, mmu_booke_kenter),
376 MMUMETHOD(mmu_kenter_attr, mmu_booke_kenter_attr),
377 MMUMETHOD(mmu_kextract, mmu_booke_kextract),
378/* MMUMETHOD(mmu_kremove, mmu_booke_kremove), */
379 MMUMETHOD(mmu_unmapdev, mmu_booke_unmapdev),
380
381 /* dumpsys() support */
382 MMUMETHOD(mmu_dumpsys_map, mmu_booke_dumpsys_map),
383 MMUMETHOD(mmu_dumpsys_unmap, mmu_booke_dumpsys_unmap),
384 MMUMETHOD(mmu_scan_md, mmu_booke_scan_md),
385
386 { 0, 0 }
387};
388
389MMU_DEF(booke_mmu, MMU_TYPE_BOOKE, mmu_booke_methods, 0);
390
391static __inline uint32_t
392tlb_calc_wimg(vm_offset_t pa, vm_memattr_t ma)
393{
394 uint32_t attrib;
395 int i;
396
397 if (ma != VM_MEMATTR_DEFAULT) {
398 switch (ma) {
399 case VM_MEMATTR_UNCACHEABLE:
400 return (PTE_I | PTE_G);
401 case VM_MEMATTR_WRITE_COMBINING:
402 case VM_MEMATTR_WRITE_BACK:
403 case VM_MEMATTR_PREFETCHABLE:
404 return (PTE_I);
405 case VM_MEMATTR_WRITE_THROUGH:
406 return (PTE_W | PTE_M);
407 }
408 }
409
410 /*
411 * Assume the page is cache inhibited and access is guarded unless
412 * it's in our available memory array.
413 */
414 attrib = _TLB_ENTRY_IO;
415 for (i = 0; i < physmem_regions_sz; i++) {
416 if ((pa >= physmem_regions[i].mr_start) &&
417 (pa < (physmem_regions[i].mr_start +
418 physmem_regions[i].mr_size))) {
419 attrib = _TLB_ENTRY_MEM;
420 break;
421 }
422 }
423
424 return (attrib);
425}
426
427static inline void
428tlb_miss_lock(void)
429{
430#ifdef SMP
431 struct pcpu *pc;
432
433 if (!smp_started)
434 return;
435
436 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
437 if (pc != pcpup) {
438
439 CTR3(KTR_PMAP, "%s: tlb miss LOCK of CPU=%d, "
440 "tlb_lock=%p", __func__, pc->pc_cpuid, pc->pc_booke_tlb_lock);
441
442 KASSERT((pc->pc_cpuid != PCPU_GET(cpuid)),
443 ("tlb_miss_lock: tried to lock self"));
444
445 tlb_lock(pc->pc_booke_tlb_lock);
446
447 CTR1(KTR_PMAP, "%s: locked", __func__);
448 }
449 }
450#endif
451}
452
453static inline void
454tlb_miss_unlock(void)
455{
456#ifdef SMP
457 struct pcpu *pc;
458
459 if (!smp_started)
460 return;
461
462 STAILQ_FOREACH(pc, &cpuhead, pc_allcpu) {
463 if (pc != pcpup) {
464 CTR2(KTR_PMAP, "%s: tlb miss UNLOCK of CPU=%d",
465 __func__, pc->pc_cpuid);
466
467 tlb_unlock(pc->pc_booke_tlb_lock);
468
469 CTR1(KTR_PMAP, "%s: unlocked", __func__);
470 }
471 }
472#endif
473}
474
475/* Return number of entries in TLB0. */
476static __inline void
477tlb0_get_tlbconf(void)
478{
479 uint32_t tlb0_cfg;
480
481 tlb0_cfg = mfspr(SPR_TLB0CFG);
482 tlb0_entries = tlb0_cfg & TLBCFG_NENTRY_MASK;
483 tlb0_ways = (tlb0_cfg & TLBCFG_ASSOC_MASK) >> TLBCFG_ASSOC_SHIFT;
484 tlb0_entries_per_way = tlb0_entries / tlb0_ways;
485}
486
487/* Initialize pool of kva ptbl buffers. */
488static void
489ptbl_init(void)
490{
491 int i;
492
493 CTR3(KTR_PMAP, "%s: s (ptbl_bufs = 0x%08x size 0x%08x)", __func__,
494 (uint32_t)ptbl_bufs, sizeof(struct ptbl_buf) * PTBL_BUFS);
495 CTR3(KTR_PMAP, "%s: s (ptbl_buf_pool_vabase = 0x%08x size = 0x%08x)",
496 __func__, ptbl_buf_pool_vabase, PTBL_BUFS * PTBL_PAGES * PAGE_SIZE);
497
498 mtx_init(&ptbl_buf_freelist_lock, "ptbl bufs lock", NULL, MTX_DEF);
499 TAILQ_INIT(&ptbl_buf_freelist);
500
501 for (i = 0; i < PTBL_BUFS; i++) {
502 ptbl_bufs[i].kva = ptbl_buf_pool_vabase + i * PTBL_PAGES * PAGE_SIZE;
503 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, &ptbl_bufs[i], link);
504 }
505}
506
507/* Get a ptbl_buf from the freelist. */
508static struct ptbl_buf *
509ptbl_buf_alloc(void)
510{
511 struct ptbl_buf *buf;
512
513 mtx_lock(&ptbl_buf_freelist_lock);
514 buf = TAILQ_FIRST(&ptbl_buf_freelist);
515 if (buf != NULL)
516 TAILQ_REMOVE(&ptbl_buf_freelist, buf, link);
517 mtx_unlock(&ptbl_buf_freelist_lock);
518
519 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf);
520
521 return (buf);
522}
523
524/* Return ptbl buff to free pool. */
525static void
526ptbl_buf_free(struct ptbl_buf *buf)
527{
528
529 CTR2(KTR_PMAP, "%s: buf = %p", __func__, buf);
530
531 mtx_lock(&ptbl_buf_freelist_lock);
532 TAILQ_INSERT_TAIL(&ptbl_buf_freelist, buf, link);
533 mtx_unlock(&ptbl_buf_freelist_lock);
534}
535
536/*
537 * Search the list of allocated ptbl bufs and find on list of allocated ptbls
538 */
539static void
540ptbl_free_pmap_ptbl(pmap_t pmap, pte_t *ptbl)
541{
542 struct ptbl_buf *pbuf;
543
544 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl);
545
546 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
547
548 TAILQ_FOREACH(pbuf, &pmap->pm_ptbl_list, link)
549 if (pbuf->kva == (vm_offset_t)ptbl) {
550 /* Remove from pmap ptbl buf list. */
551 TAILQ_REMOVE(&pmap->pm_ptbl_list, pbuf, link);
552
553 /* Free corresponding ptbl buf. */
554 ptbl_buf_free(pbuf);
555 break;
556 }
557}
558
559/* Allocate page table. */
560static pte_t *
561ptbl_alloc(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx, boolean_t nosleep)
562{
563 vm_page_t mtbl[PTBL_PAGES];
564 vm_page_t m;
565 struct ptbl_buf *pbuf;
566 unsigned int pidx;
567 pte_t *ptbl;
568 int i, j;
569
570 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
571 (pmap == kernel_pmap), pdir_idx);
572
573 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
574 ("ptbl_alloc: invalid pdir_idx"));
575 KASSERT((pmap->pm_pdir[pdir_idx] == NULL),
576 ("pte_alloc: valid ptbl entry exists!"));
577
578 pbuf = ptbl_buf_alloc();
579 if (pbuf == NULL)
580 panic("pte_alloc: couldn't alloc kernel virtual memory");
581
582 ptbl = (pte_t *)pbuf->kva;
583
584 CTR2(KTR_PMAP, "%s: ptbl kva = %p", __func__, ptbl);
585
586 /* Allocate ptbl pages, this will sleep! */
587 for (i = 0; i < PTBL_PAGES; i++) {
588 pidx = (PTBL_PAGES * pdir_idx) + i;
589 while ((m = vm_page_alloc(NULL, pidx,
590 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
591 PMAP_UNLOCK(pmap);
592 rw_wunlock(&pvh_global_lock);
593 if (nosleep) {
594 ptbl_free_pmap_ptbl(pmap, ptbl);
595 for (j = 0; j < i; j++)
596 vm_page_free(mtbl[j]);
597 atomic_subtract_int(&cnt.v_wire_count, i);
598 return (NULL);
599 }
600 VM_WAIT;
601 rw_wlock(&pvh_global_lock);
602 PMAP_LOCK(pmap);
603 }
604 mtbl[i] = m;
605 }
606
607 /* Map allocated pages into kernel_pmap. */
608 mmu_booke_qenter(mmu, (vm_offset_t)ptbl, mtbl, PTBL_PAGES);
609
610 /* Zero whole ptbl. */
611 bzero((caddr_t)ptbl, PTBL_PAGES * PAGE_SIZE);
612
613 /* Add pbuf to the pmap ptbl bufs list. */
614 TAILQ_INSERT_TAIL(&pmap->pm_ptbl_list, pbuf, link);
615
616 return (ptbl);
617}
618
619/* Free ptbl pages and invalidate pdir entry. */
620static void
621ptbl_free(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
622{
623 pte_t *ptbl;
624 vm_paddr_t pa;
625 vm_offset_t va;
626 vm_page_t m;
627 int i;
628
629 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
630 (pmap == kernel_pmap), pdir_idx);
631
632 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
633 ("ptbl_free: invalid pdir_idx"));
634
635 ptbl = pmap->pm_pdir[pdir_idx];
636
637 CTR2(KTR_PMAP, "%s: ptbl = %p", __func__, ptbl);
638
639 KASSERT((ptbl != NULL), ("ptbl_free: null ptbl"));
640
641 /*
642 * Invalidate the pdir entry as soon as possible, so that other CPUs
643 * don't attempt to look up the page tables we are releasing.
644 */
645 mtx_lock_spin(&tlbivax_mutex);
646 tlb_miss_lock();
647
648 pmap->pm_pdir[pdir_idx] = NULL;
649
650 tlb_miss_unlock();
651 mtx_unlock_spin(&tlbivax_mutex);
652
653 for (i = 0; i < PTBL_PAGES; i++) {
654 va = ((vm_offset_t)ptbl + (i * PAGE_SIZE));
655 pa = pte_vatopa(mmu, kernel_pmap, va);
656 m = PHYS_TO_VM_PAGE(pa);
657 vm_page_free_zero(m);
658 atomic_subtract_int(&cnt.v_wire_count, 1);
659 mmu_booke_kremove(mmu, va);
660 }
661
662 ptbl_free_pmap_ptbl(pmap, ptbl);
663}
664
665/*
666 * Decrement ptbl pages hold count and attempt to free ptbl pages.
667 * Called when removing pte entry from ptbl.
668 *
669 * Return 1 if ptbl pages were freed.
670 */
671static int
672ptbl_unhold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
673{
674 pte_t *ptbl;
675 vm_paddr_t pa;
676 vm_page_t m;
677 int i;
678
679 CTR4(KTR_PMAP, "%s: pmap = %p su = %d pdir_idx = %d", __func__, pmap,
680 (pmap == kernel_pmap), pdir_idx);
681
682 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
683 ("ptbl_unhold: invalid pdir_idx"));
684 KASSERT((pmap != kernel_pmap),
685 ("ptbl_unhold: unholding kernel ptbl!"));
686
687 ptbl = pmap->pm_pdir[pdir_idx];
688
689 //debugf("ptbl_unhold: ptbl = 0x%08x\n", (u_int32_t)ptbl);
690 KASSERT(((vm_offset_t)ptbl >= VM_MIN_KERNEL_ADDRESS),
691 ("ptbl_unhold: non kva ptbl"));
692
693 /* decrement hold count */
694 for (i = 0; i < PTBL_PAGES; i++) {
695 pa = pte_vatopa(mmu, kernel_pmap,
696 (vm_offset_t)ptbl + (i * PAGE_SIZE));
697 m = PHYS_TO_VM_PAGE(pa);
698 m->wire_count--;
699 }
700
701 /*
702 * Free ptbl pages if there are no pte etries in this ptbl.
703 * wire_count has the same value for all ptbl pages, so check the last
704 * page.
705 */
706 if (m->wire_count == 0) {
707 ptbl_free(mmu, pmap, pdir_idx);
708
709 //debugf("ptbl_unhold: e (freed ptbl)\n");
710 return (1);
711 }
712
713 return (0);
714}
715
716/*
717 * Increment hold count for ptbl pages. This routine is used when a new pte
718 * entry is being inserted into the ptbl.
719 */
720static void
721ptbl_hold(mmu_t mmu, pmap_t pmap, unsigned int pdir_idx)
722{
723 vm_paddr_t pa;
724 pte_t *ptbl;
725 vm_page_t m;
726 int i;
727
728 CTR3(KTR_PMAP, "%s: pmap = %p pdir_idx = %d", __func__, pmap,
729 pdir_idx);
730
731 KASSERT((pdir_idx <= (VM_MAXUSER_ADDRESS / PDIR_SIZE)),
732 ("ptbl_hold: invalid pdir_idx"));
733 KASSERT((pmap != kernel_pmap),
734 ("ptbl_hold: holding kernel ptbl!"));
735
736 ptbl = pmap->pm_pdir[pdir_idx];
737
738 KASSERT((ptbl != NULL), ("ptbl_hold: null ptbl"));
739
740 for (i = 0; i < PTBL_PAGES; i++) {
741 pa = pte_vatopa(mmu, kernel_pmap,
742 (vm_offset_t)ptbl + (i * PAGE_SIZE));
743 m = PHYS_TO_VM_PAGE(pa);
744 m->wire_count++;
745 }
746}
747
748/* Allocate pv_entry structure. */
749pv_entry_t
750pv_alloc(void)
751{
752 pv_entry_t pv;
753
754 pv_entry_count++;
755 if (pv_entry_count > pv_entry_high_water)
756 pagedaemon_wakeup();
757 pv = uma_zalloc(pvzone, M_NOWAIT);
758
759 return (pv);
760}
761
762/* Free pv_entry structure. */
763static __inline void
764pv_free(pv_entry_t pve)
765{
766
767 pv_entry_count--;
768 uma_zfree(pvzone, pve);
769}
770
771
772/* Allocate and initialize pv_entry structure. */
773static void
774pv_insert(pmap_t pmap, vm_offset_t va, vm_page_t m)
775{
776 pv_entry_t pve;
777
778 //int su = (pmap == kernel_pmap);
779 //debugf("pv_insert: s (su = %d pmap = 0x%08x va = 0x%08x m = 0x%08x)\n", su,
780 // (u_int32_t)pmap, va, (u_int32_t)m);
781
782 pve = pv_alloc();
783 if (pve == NULL)
784 panic("pv_insert: no pv entries!");
785
786 pve->pv_pmap = pmap;
787 pve->pv_va = va;
788
789 /* add to pv_list */
790 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
791 rw_assert(&pvh_global_lock, RA_WLOCKED);
792
793 TAILQ_INSERT_TAIL(&m->md.pv_list, pve, pv_link);
794
795 //debugf("pv_insert: e\n");
796}
797
798/* Destroy pv entry. */
799static void
800pv_remove(pmap_t pmap, vm_offset_t va, vm_page_t m)
801{
802 pv_entry_t pve;
803
804 //int su = (pmap == kernel_pmap);
805 //debugf("pv_remove: s (su = %d pmap = 0x%08x va = 0x%08x)\n", su, (u_int32_t)pmap, va);
806
807 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
808 rw_assert(&pvh_global_lock, RA_WLOCKED);
809
810 /* find pv entry */
811 TAILQ_FOREACH(pve, &m->md.pv_list, pv_link) {
812 if ((pmap == pve->pv_pmap) && (va == pve->pv_va)) {
813 /* remove from pv_list */
814 TAILQ_REMOVE(&m->md.pv_list, pve, pv_link);
815 if (TAILQ_EMPTY(&m->md.pv_list))
816 vm_page_aflag_clear(m, PGA_WRITEABLE);
817
818 /* free pv entry struct */
819 pv_free(pve);
820 break;
821 }
822 }
823
824 //debugf("pv_remove: e\n");
825}
826
827/*
828 * Clean pte entry, try to free page table page if requested.
829 *
830 * Return 1 if ptbl pages were freed, otherwise return 0.
831 */
832static int
833pte_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, uint8_t flags)
834{
835 unsigned int pdir_idx = PDIR_IDX(va);
836 unsigned int ptbl_idx = PTBL_IDX(va);
837 vm_page_t m;
838 pte_t *ptbl;
839 pte_t *pte;
840
841 //int su = (pmap == kernel_pmap);
842 //debugf("pte_remove: s (su = %d pmap = 0x%08x va = 0x%08x flags = %d)\n",
843 // su, (u_int32_t)pmap, va, flags);
844
845 ptbl = pmap->pm_pdir[pdir_idx];
846 KASSERT(ptbl, ("pte_remove: null ptbl"));
847
848 pte = &ptbl[ptbl_idx];
849
850 if (pte == NULL || !PTE_ISVALID(pte))
851 return (0);
852
853 if (PTE_ISWIRED(pte))
854 pmap->pm_stats.wired_count--;
855
856 /* Handle managed entry. */
857 if (PTE_ISMANAGED(pte)) {
858 /* Get vm_page_t for mapped pte. */
859 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
860
861 if (PTE_ISMODIFIED(pte))
862 vm_page_dirty(m);
863
864 if (PTE_ISREFERENCED(pte))
865 vm_page_aflag_set(m, PGA_REFERENCED);
866
867 pv_remove(pmap, va, m);
868 }
869
870 mtx_lock_spin(&tlbivax_mutex);
871 tlb_miss_lock();
872
873 tlb0_flush_entry(va);
874 pte->flags = 0;
875 pte->rpn = 0;
876
877 tlb_miss_unlock();
878 mtx_unlock_spin(&tlbivax_mutex);
879
880 pmap->pm_stats.resident_count--;
881
882 if (flags & PTBL_UNHOLD) {
883 //debugf("pte_remove: e (unhold)\n");
884 return (ptbl_unhold(mmu, pmap, pdir_idx));
885 }
886
887 //debugf("pte_remove: e\n");
888 return (0);
889}
890
891/*
892 * Insert PTE for a given page and virtual address.
893 */
894static int
895pte_enter(mmu_t mmu, pmap_t pmap, vm_page_t m, vm_offset_t va, uint32_t flags,
896 boolean_t nosleep)
897{
898 unsigned int pdir_idx = PDIR_IDX(va);
899 unsigned int ptbl_idx = PTBL_IDX(va);
900 pte_t *ptbl, *pte;
901
902 CTR4(KTR_PMAP, "%s: su = %d pmap = %p va = %p", __func__,
903 pmap == kernel_pmap, pmap, va);
904
905 /* Get the page table pointer. */
906 ptbl = pmap->pm_pdir[pdir_idx];
907
908 if (ptbl == NULL) {
909 /* Allocate page table pages. */
910 ptbl = ptbl_alloc(mmu, pmap, pdir_idx, nosleep);
911 if (ptbl == NULL) {
912 KASSERT(nosleep, ("nosleep and NULL ptbl"));
913 return (ENOMEM);
914 }
915 } else {
916 /*
917 * Check if there is valid mapping for requested
918 * va, if there is, remove it.
919 */
920 pte = &pmap->pm_pdir[pdir_idx][ptbl_idx];
921 if (PTE_ISVALID(pte)) {
922 pte_remove(mmu, pmap, va, PTBL_HOLD);
923 } else {
924 /*
925 * pte is not used, increment hold count
926 * for ptbl pages.
927 */
928 if (pmap != kernel_pmap)
929 ptbl_hold(mmu, pmap, pdir_idx);
930 }
931 }
932
933 /*
934 * Insert pv_entry into pv_list for mapped page if part of managed
935 * memory.
936 */
937 if ((m->oflags & VPO_UNMANAGED) == 0) {
938 flags |= PTE_MANAGED;
939
940 /* Create and insert pv entry. */
941 pv_insert(pmap, va, m);
942 }
943
944 pmap->pm_stats.resident_count++;
945
946 mtx_lock_spin(&tlbivax_mutex);
947 tlb_miss_lock();
948
949 tlb0_flush_entry(va);
950 if (pmap->pm_pdir[pdir_idx] == NULL) {
951 /*
952 * If we just allocated a new page table, hook it in
953 * the pdir.
954 */
955 pmap->pm_pdir[pdir_idx] = ptbl;
956 }
957 pte = &(pmap->pm_pdir[pdir_idx][ptbl_idx]);
958 pte->rpn = VM_PAGE_TO_PHYS(m) & ~PTE_PA_MASK;
959 pte->flags |= (PTE_VALID | flags);
960
961 tlb_miss_unlock();
962 mtx_unlock_spin(&tlbivax_mutex);
963 return (0);
964}
965
966/* Return the pa for the given pmap/va. */
967static vm_paddr_t
968pte_vatopa(mmu_t mmu, pmap_t pmap, vm_offset_t va)
969{
970 vm_paddr_t pa = 0;
971 pte_t *pte;
972
973 pte = pte_find(mmu, pmap, va);
974 if ((pte != NULL) && PTE_ISVALID(pte))
975 pa = (PTE_PA(pte) | (va & PTE_PA_MASK));
976 return (pa);
977}
978
979/* Get a pointer to a PTE in a page table. */
980static pte_t *
981pte_find(mmu_t mmu, pmap_t pmap, vm_offset_t va)
982{
983 unsigned int pdir_idx = PDIR_IDX(va);
984 unsigned int ptbl_idx = PTBL_IDX(va);
985
986 KASSERT((pmap != NULL), ("pte_find: invalid pmap"));
987
988 if (pmap->pm_pdir[pdir_idx])
989 return (&(pmap->pm_pdir[pdir_idx][ptbl_idx]));
990
991 return (NULL);
992}
993
994/**************************************************************************/
995/* PMAP related */
996/**************************************************************************/
997
998/*
999 * This is called during booke_init, before the system is really initialized.
1000 */
1001static void
1002mmu_booke_bootstrap(mmu_t mmu, vm_offset_t start, vm_offset_t kernelend)
1003{
1004 vm_offset_t phys_kernelend;
1005 struct mem_region *mp, *mp1;
1006 int cnt, i, j;
1007 u_int s, e, sz;
1008 u_int phys_avail_count;
1009 vm_size_t physsz, hwphyssz, kstack0_sz;
1010 vm_offset_t kernel_pdir, kstack0, va;
1011 vm_paddr_t kstack0_phys;
1012 void *dpcpu;
1013 pte_t *pte;
1014
1015 debugf("mmu_booke_bootstrap: entered\n");
1016
1017 /* Initialize invalidation mutex */
1018 mtx_init(&tlbivax_mutex, "tlbivax", NULL, MTX_SPIN);
1019
1020 /* Read TLB0 size and associativity. */
1021 tlb0_get_tlbconf();
1022
1023 /*
1024 * Align kernel start and end address (kernel image).
1025 * Note that kernel end does not necessarily relate to kernsize.
1026 * kernsize is the size of the kernel that is actually mapped.
1027 * Also note that "start - 1" is deliberate. With SMP, the
1028 * entry point is exactly a page from the actual load address.
1029 * As such, trunc_page() has no effect and we're off by a page.
1030 * Since we always have the ELF header between the load address
1031 * and the entry point, we can safely subtract 1 to compensate.
1032 */
1033 kernstart = trunc_page(start - 1);
1034 data_start = round_page(kernelend);
1035 data_end = data_start;
1036
1037 /*
1038 * Addresses of preloaded modules (like file systems) use
1039 * physical addresses. Make sure we relocate those into
1040 * virtual addresses.
1041 */
1042 preload_addr_relocate = kernstart - kernload;
1043
1044 /* Allocate the dynamic per-cpu area. */
1045 dpcpu = (void *)data_end;
1046 data_end += DPCPU_SIZE;
1047
1048 /* Allocate space for the message buffer. */
1049 msgbufp = (struct msgbuf *)data_end;
1050 data_end += msgbufsize;
1051 debugf(" msgbufp at 0x%08x end = 0x%08x\n", (uint32_t)msgbufp,
1052 data_end);
1053
1054 data_end = round_page(data_end);
1055
1056 /* Allocate space for ptbl_bufs. */
1057 ptbl_bufs = (struct ptbl_buf *)data_end;
1058 data_end += sizeof(struct ptbl_buf) * PTBL_BUFS;
1059 debugf(" ptbl_bufs at 0x%08x end = 0x%08x\n", (uint32_t)ptbl_bufs,
1060 data_end);
1061
1062 data_end = round_page(data_end);
1063
1064 /* Allocate PTE tables for kernel KVA. */
1065 kernel_pdir = data_end;
1066 kernel_ptbls = (VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS +
1067 PDIR_SIZE - 1) / PDIR_SIZE;
1068 data_end += kernel_ptbls * PTBL_PAGES * PAGE_SIZE;
1069 debugf(" kernel ptbls: %d\n", kernel_ptbls);
1070 debugf(" kernel pdir at 0x%08x end = 0x%08x\n", kernel_pdir, data_end);
1071
1072 debugf(" data_end: 0x%08x\n", data_end);
1073 if (data_end - kernstart > kernsize) {
1074 kernsize += tlb1_mapin_region(kernstart + kernsize,
1075 kernload + kernsize, (data_end - kernstart) - kernsize);
1076 }
1077 data_end = kernstart + kernsize;
1078 debugf(" updated data_end: 0x%08x\n", data_end);
1079
1080 /*
1081 * Clear the structures - note we can only do it safely after the
1082 * possible additional TLB1 translations are in place (above) so that
1083 * all range up to the currently calculated 'data_end' is covered.
1084 */
1085 dpcpu_init(dpcpu, 0);
1086 memset((void *)ptbl_bufs, 0, sizeof(struct ptbl_buf) * PTBL_SIZE);
1087 memset((void *)kernel_pdir, 0, kernel_ptbls * PTBL_PAGES * PAGE_SIZE);
1088
1089 /*******************************************************/
1090 /* Set the start and end of kva. */
1091 /*******************************************************/
1092 virtual_avail = round_page(data_end);
1093 virtual_end = VM_MAX_KERNEL_ADDRESS;
1094
1095 /* Allocate KVA space for page zero/copy operations. */
1096 zero_page_va = virtual_avail;
1097 virtual_avail += PAGE_SIZE;
1098 zero_page_idle_va = virtual_avail;
1099 virtual_avail += PAGE_SIZE;
1100 copy_page_src_va = virtual_avail;
1101 virtual_avail += PAGE_SIZE;
1102 copy_page_dst_va = virtual_avail;
1103 virtual_avail += PAGE_SIZE;
1104 debugf("zero_page_va = 0x%08x\n", zero_page_va);
1105 debugf("zero_page_idle_va = 0x%08x\n", zero_page_idle_va);
1106 debugf("copy_page_src_va = 0x%08x\n", copy_page_src_va);
1107 debugf("copy_page_dst_va = 0x%08x\n", copy_page_dst_va);
1108
1109 /* Initialize page zero/copy mutexes. */
1110 mtx_init(&zero_page_mutex, "mmu_booke_zero_page", NULL, MTX_DEF);
1111 mtx_init(©_page_mutex, "mmu_booke_copy_page", NULL, MTX_DEF);
1112
1113 /* Allocate KVA space for ptbl bufs. */
1114 ptbl_buf_pool_vabase = virtual_avail;
1115 virtual_avail += PTBL_BUFS * PTBL_PAGES * PAGE_SIZE;
1116 debugf("ptbl_buf_pool_vabase = 0x%08x end = 0x%08x\n",
1117 ptbl_buf_pool_vabase, virtual_avail);
1118
1119 /* Calculate corresponding physical addresses for the kernel region. */
1120 phys_kernelend = kernload + kernsize;
1121 debugf("kernel image and allocated data:\n");
1122 debugf(" kernload = 0x%08x\n", kernload);
1123 debugf(" kernstart = 0x%08x\n", kernstart);
1124 debugf(" kernsize = 0x%08x\n", kernsize);
1125
1126 if (sizeof(phys_avail) / sizeof(phys_avail[0]) < availmem_regions_sz)
1127 panic("mmu_booke_bootstrap: phys_avail too small");
1128
1129 /*
1130 * Remove kernel physical address range from avail regions list. Page
1131 * align all regions. Non-page aligned memory isn't very interesting
1132 * to us. Also, sort the entries for ascending addresses.
1133 */
1134
1135 /* Retrieve phys/avail mem regions */
1136 mem_regions(&physmem_regions, &physmem_regions_sz,
1137 &availmem_regions, &availmem_regions_sz);
1138 sz = 0;
1139 cnt = availmem_regions_sz;
1140 debugf("processing avail regions:\n");
1141 for (mp = availmem_regions; mp->mr_size; mp++) {
1142 s = mp->mr_start;
1143 e = mp->mr_start + mp->mr_size;
1144 debugf(" %08x-%08x -> ", s, e);
1145 /* Check whether this region holds all of the kernel. */
1146 if (s < kernload && e > phys_kernelend) {
1147 availmem_regions[cnt].mr_start = phys_kernelend;
1148 availmem_regions[cnt++].mr_size = e - phys_kernelend;
1149 e = kernload;
1150 }
1151 /* Look whether this regions starts within the kernel. */
1152 if (s >= kernload && s < phys_kernelend) {
1153 if (e <= phys_kernelend)
1154 goto empty;
1155 s = phys_kernelend;
1156 }
1157 /* Now look whether this region ends within the kernel. */
1158 if (e > kernload && e <= phys_kernelend) {
1159 if (s >= kernload)
1160 goto empty;
1161 e = kernload;
1162 }
1163 /* Now page align the start and size of the region. */
1164 s = round_page(s);
1165 e = trunc_page(e);
1166 if (e < s)
1167 e = s;
1168 sz = e - s;
1169 debugf("%08x-%08x = %x\n", s, e, sz);
1170
1171 /* Check whether some memory is left here. */
1172 if (sz == 0) {
1173 empty:
1174 memmove(mp, mp + 1,
1175 (cnt - (mp - availmem_regions)) * sizeof(*mp));
1176 cnt--;
1177 mp--;
1178 continue;
1179 }
1180
1181 /* Do an insertion sort. */
1182 for (mp1 = availmem_regions; mp1 < mp; mp1++)
1183 if (s < mp1->mr_start)
1184 break;
1185 if (mp1 < mp) {
1186 memmove(mp1 + 1, mp1, (char *)mp - (char *)mp1);
1187 mp1->mr_start = s;
1188 mp1->mr_size = sz;
1189 } else {
1190 mp->mr_start = s;
1191 mp->mr_size = sz;
1192 }
1193 }
1194 availmem_regions_sz = cnt;
1195
1196 /*******************************************************/
1197 /* Steal physical memory for kernel stack from the end */
1198 /* of the first avail region */
1199 /*******************************************************/
1200 kstack0_sz = KSTACK_PAGES * PAGE_SIZE;
1201 kstack0_phys = availmem_regions[0].mr_start +
1202 availmem_regions[0].mr_size;
1203 kstack0_phys -= kstack0_sz;
1204 availmem_regions[0].mr_size -= kstack0_sz;
1205
1206 /*******************************************************/
1207 /* Fill in phys_avail table, based on availmem_regions */
1208 /*******************************************************/
1209 phys_avail_count = 0;
1210 physsz = 0;
1211 hwphyssz = 0;
1212 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
1213
1214 debugf("fill in phys_avail:\n");
1215 for (i = 0, j = 0; i < availmem_regions_sz; i++, j += 2) {
1216
1217 debugf(" region: 0x%08x - 0x%08x (0x%08x)\n",
1218 availmem_regions[i].mr_start,
1219 availmem_regions[i].mr_start +
1220 availmem_regions[i].mr_size,
1221 availmem_regions[i].mr_size);
1222
1223 if (hwphyssz != 0 &&
1224 (physsz + availmem_regions[i].mr_size) >= hwphyssz) {
1225 debugf(" hw.physmem adjust\n");
1226 if (physsz < hwphyssz) {
1227 phys_avail[j] = availmem_regions[i].mr_start;
1228 phys_avail[j + 1] =
1229 availmem_regions[i].mr_start +
1230 hwphyssz - physsz;
1231 physsz = hwphyssz;
1232 phys_avail_count++;
1233 }
1234 break;
1235 }
1236
1237 phys_avail[j] = availmem_regions[i].mr_start;
1238 phys_avail[j + 1] = availmem_regions[i].mr_start +
1239 availmem_regions[i].mr_size;
1240 phys_avail_count++;
1241 physsz += availmem_regions[i].mr_size;
1242 }
1243 physmem = btoc(physsz);
1244
1245 /* Calculate the last available physical address. */
1246 for (i = 0; phys_avail[i + 2] != 0; i += 2)
1247 ;
1248 Maxmem = powerpc_btop(phys_avail[i + 1]);
1249
1250 debugf("Maxmem = 0x%08lx\n", Maxmem);
1251 debugf("phys_avail_count = %d\n", phys_avail_count);
1252 debugf("physsz = 0x%08x physmem = %ld (0x%08lx)\n", physsz, physmem,
1253 physmem);
1254
1255 /*******************************************************/
1256 /* Initialize (statically allocated) kernel pmap. */
1257 /*******************************************************/
1258 PMAP_LOCK_INIT(kernel_pmap);
1259 kptbl_min = VM_MIN_KERNEL_ADDRESS / PDIR_SIZE;
1260
1261 debugf("kernel_pmap = 0x%08x\n", (uint32_t)kernel_pmap);
1262 debugf("kptbl_min = %d, kernel_ptbls = %d\n", kptbl_min, kernel_ptbls);
1263 debugf("kernel pdir range: 0x%08x - 0x%08x\n",
1264 kptbl_min * PDIR_SIZE, (kptbl_min + kernel_ptbls) * PDIR_SIZE - 1);
1265
1266 /* Initialize kernel pdir */
1267 for (i = 0; i < kernel_ptbls; i++)
1268 kernel_pmap->pm_pdir[kptbl_min + i] =
1269 (pte_t *)(kernel_pdir + (i * PAGE_SIZE * PTBL_PAGES));
1270
1271 for (i = 0; i < MAXCPU; i++) {
1272 kernel_pmap->pm_tid[i] = TID_KERNEL;
1273
1274 /* Initialize each CPU's tidbusy entry 0 with kernel_pmap */
1275 tidbusy[i][0] = kernel_pmap;
1276 }
1277
1278 /*
1279 * Fill in PTEs covering kernel code and data. They are not required
1280 * for address translation, as this area is covered by static TLB1
1281 * entries, but for pte_vatopa() to work correctly with kernel area
1282 * addresses.
1283 */
1284 for (va = kernstart; va < data_end; va += PAGE_SIZE) {
1285 pte = &(kernel_pmap->pm_pdir[PDIR_IDX(va)][PTBL_IDX(va)]);
1286 pte->rpn = kernload + (va - kernstart);
1287 pte->flags = PTE_M | PTE_SR | PTE_SW | PTE_SX | PTE_WIRED |
1288 PTE_VALID;
1289 }
1290 /* Mark kernel_pmap active on all CPUs */
1291 CPU_FILL(&kernel_pmap->pm_active);
1292
1293 /*
1294 * Initialize the global pv list lock.
1295 */
1296 rw_init(&pvh_global_lock, "pmap pv global");
1297
1298 /*******************************************************/
1299 /* Final setup */
1300 /*******************************************************/
1301
1302 /* Enter kstack0 into kernel map, provide guard page */
1303 kstack0 = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
1304 thread0.td_kstack = kstack0;
1305 thread0.td_kstack_pages = KSTACK_PAGES;
1306
1307 debugf("kstack_sz = 0x%08x\n", kstack0_sz);
1308 debugf("kstack0_phys at 0x%08x - 0x%08x\n",
1309 kstack0_phys, kstack0_phys + kstack0_sz);
1310 debugf("kstack0 at 0x%08x - 0x%08x\n", kstack0, kstack0 + kstack0_sz);
1311
1312 virtual_avail += KSTACK_GUARD_PAGES * PAGE_SIZE + kstack0_sz;
1313 for (i = 0; i < KSTACK_PAGES; i++) {
1314 mmu_booke_kenter(mmu, kstack0, kstack0_phys);
1315 kstack0 += PAGE_SIZE;
1316 kstack0_phys += PAGE_SIZE;
1317 }
1318
1319 debugf("virtual_avail = %08x\n", virtual_avail);
1320 debugf("virtual_end = %08x\n", virtual_end);
1321
1322 debugf("mmu_booke_bootstrap: exit\n");
1323}
1324
1325void
1326pmap_bootstrap_ap(volatile uint32_t *trcp __unused)
1327{
1328 int i;
1329
1330 /*
1331 * Finish TLB1 configuration: the BSP already set up its TLB1 and we
1332 * have the snapshot of its contents in the s/w tlb1[] table, so use
1333 * these values directly to (re)program AP's TLB1 hardware.
1334 */
1335 for (i = bp_ntlb1s; i < tlb1_idx; i++) {
1336 /* Skip invalid entries */
1337 if (!(tlb1[i].mas1 & MAS1_VALID))
1338 continue;
1339
1340 tlb1_write_entry(i);
1341 }
1342
1343 set_mas4_defaults();
1344}
1345
1346/*
1347 * Get the physical page address for the given pmap/virtual address.
1348 */
1349static vm_paddr_t
1350mmu_booke_extract(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1351{
1352 vm_paddr_t pa;
1353
1354 PMAP_LOCK(pmap);
1355 pa = pte_vatopa(mmu, pmap, va);
1356 PMAP_UNLOCK(pmap);
1357
1358 return (pa);
1359}
1360
1361/*
1362 * Extract the physical page address associated with the given
1363 * kernel virtual address.
1364 */
1365static vm_paddr_t
1366mmu_booke_kextract(mmu_t mmu, vm_offset_t va)
1367{
1368 int i;
1369
1370 /* Check TLB1 mappings */
1371 for (i = 0; i < tlb1_idx; i++) {
1372 if (!(tlb1[i].mas1 & MAS1_VALID))
1373 continue;
1374 if (va >= tlb1[i].virt && va < tlb1[i].virt + tlb1[i].size)
1375 return (tlb1[i].phys + (va - tlb1[i].virt));
1376 }
1377
1378 return (pte_vatopa(mmu, kernel_pmap, va));
1379}
1380
1381/*
1382 * Initialize the pmap module.
1383 * Called by vm_init, to initialize any structures that the pmap
1384 * system needs to map virtual memory.
1385 */
1386static void
1387mmu_booke_init(mmu_t mmu)
1388{
1389 int shpgperproc = PMAP_SHPGPERPROC;
1390
1391 /*
1392 * Initialize the address space (zone) for the pv entries. Set a
1393 * high water mark so that the system can recover from excessive
1394 * numbers of pv entries.
1395 */
1396 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL,
1397 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE);
1398
1399 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
1400 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count;
1401
1402 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
1403 pv_entry_high_water = 9 * (pv_entry_max / 10);
1404
1405 uma_zone_reserve_kva(pvzone, pv_entry_max);
1406
1407 /* Pre-fill pvzone with initial number of pv entries. */
1408 uma_prealloc(pvzone, PV_ENTRY_ZONE_MIN);
1409
1410 /* Initialize ptbl allocation. */
1411 ptbl_init();
1412}
1413
1414/*
1415 * Map a list of wired pages into kernel virtual address space. This is
1416 * intended for temporary mappings which do not need page modification or
1417 * references recorded. Existing mappings in the region are overwritten.
1418 */
1419static void
1420mmu_booke_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count)
1421{
1422 vm_offset_t va;
1423
1424 va = sva;
1425 while (count-- > 0) {
1426 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
1427 va += PAGE_SIZE;
1428 m++;
1429 }
1430}
1431
1432/*
1433 * Remove page mappings from kernel virtual address space. Intended for
1434 * temporary mappings entered by mmu_booke_qenter.
1435 */
1436static void
1437mmu_booke_qremove(mmu_t mmu, vm_offset_t sva, int count)
1438{
1439 vm_offset_t va;
1440
1441 va = sva;
1442 while (count-- > 0) {
1443 mmu_booke_kremove(mmu, va);
1444 va += PAGE_SIZE;
1445 }
1446}
1447
1448/*
1449 * Map a wired page into kernel virtual address space.
1450 */
1451static void
1452mmu_booke_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa)
1453{
1454
1455 mmu_booke_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT);
1456}
1457
1458static void
1459mmu_booke_kenter_attr(mmu_t mmu, vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma)
1460{
1461 unsigned int pdir_idx = PDIR_IDX(va);
1462 unsigned int ptbl_idx = PTBL_IDX(va);
1463 uint32_t flags;
1464 pte_t *pte;
1465
1466 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) &&
1467 (va <= VM_MAX_KERNEL_ADDRESS)), ("mmu_booke_kenter: invalid va"));
1468
1469 flags = PTE_SR | PTE_SW | PTE_SX | PTE_WIRED | PTE_VALID;
1470 flags |= tlb_calc_wimg(pa, ma);
1471
1472 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]);
1473
1474 mtx_lock_spin(&tlbivax_mutex);
1475 tlb_miss_lock();
1476
1477 if (PTE_ISVALID(pte)) {
1478
1479 CTR1(KTR_PMAP, "%s: replacing entry!", __func__);
1480
1481 /* Flush entry from TLB0 */
1482 tlb0_flush_entry(va);
1483 }
1484
1485 pte->rpn = pa & ~PTE_PA_MASK;
1486 pte->flags = flags;
1487
1488 //debugf("mmu_booke_kenter: pdir_idx = %d ptbl_idx = %d va=0x%08x "
1489 // "pa=0x%08x rpn=0x%08x flags=0x%08x\n",
1490 // pdir_idx, ptbl_idx, va, pa, pte->rpn, pte->flags);
1491
1492 /* Flush the real memory from the instruction cache. */
1493 if ((flags & (PTE_I | PTE_G)) == 0) {
1494 __syncicache((void *)va, PAGE_SIZE);
1495 }
1496
1497 tlb_miss_unlock();
1498 mtx_unlock_spin(&tlbivax_mutex);
1499}
1500
1501/*
1502 * Remove a page from kernel page table.
1503 */
1504static void
1505mmu_booke_kremove(mmu_t mmu, vm_offset_t va)
1506{
1507 unsigned int pdir_idx = PDIR_IDX(va);
1508 unsigned int ptbl_idx = PTBL_IDX(va);
1509 pte_t *pte;
1510
1511// CTR2(KTR_PMAP,("%s: s (va = 0x%08x)\n", __func__, va));
1512
1513 KASSERT(((va >= VM_MIN_KERNEL_ADDRESS) &&
1514 (va <= VM_MAX_KERNEL_ADDRESS)),
1515 ("mmu_booke_kremove: invalid va"));
1516
1517 pte = &(kernel_pmap->pm_pdir[pdir_idx][ptbl_idx]);
1518
1519 if (!PTE_ISVALID(pte)) {
1520
1521 CTR1(KTR_PMAP, "%s: invalid pte", __func__);
1522
1523 return;
1524 }
1525
1526 mtx_lock_spin(&tlbivax_mutex);
1527 tlb_miss_lock();
1528
1529 /* Invalidate entry in TLB0, update PTE. */
1530 tlb0_flush_entry(va);
1531 pte->flags = 0;
1532 pte->rpn = 0;
1533
1534 tlb_miss_unlock();
1535 mtx_unlock_spin(&tlbivax_mutex);
1536}
1537
1538/*
1539 * Initialize pmap associated with process 0.
1540 */
1541static void
1542mmu_booke_pinit0(mmu_t mmu, pmap_t pmap)
1543{
1544
1545 PMAP_LOCK_INIT(pmap);
1546 mmu_booke_pinit(mmu, pmap);
1547 PCPU_SET(curpmap, pmap);
1548}
1549
1550/*
1551 * Initialize a preallocated and zeroed pmap structure,
1552 * such as one in a vmspace structure.
1553 */
1554static void
1555mmu_booke_pinit(mmu_t mmu, pmap_t pmap)
1556{
1557 int i;
1558
1559 CTR4(KTR_PMAP, "%s: pmap = %p, proc %d '%s'", __func__, pmap,
1560 curthread->td_proc->p_pid, curthread->td_proc->p_comm);
1561
1562 KASSERT((pmap != kernel_pmap), ("pmap_pinit: initializing kernel_pmap"));
1563
1564 for (i = 0; i < MAXCPU; i++)
1565 pmap->pm_tid[i] = TID_NONE;
1566 CPU_ZERO(&kernel_pmap->pm_active);
1567 bzero(&pmap->pm_stats, sizeof(pmap->pm_stats));
1568 bzero(&pmap->pm_pdir, sizeof(pte_t *) * PDIR_NENTRIES);
1569 TAILQ_INIT(&pmap->pm_ptbl_list);
1570}
1571
1572/*
1573 * Release any resources held by the given physical map.
1574 * Called when a pmap initialized by mmu_booke_pinit is being released.
1575 * Should only be called if the map contains no valid mappings.
1576 */
1577static void
1578mmu_booke_release(mmu_t mmu, pmap_t pmap)
1579{
1580
1581 KASSERT(pmap->pm_stats.resident_count == 0,
1582 ("pmap_release: pmap resident count %ld != 0",
1583 pmap->pm_stats.resident_count));
1584}
1585
1586/*
1587 * Insert the given physical page at the specified virtual address in the
1588 * target physical map with the protection requested. If specified the page
1589 * will be wired down.
1590 */
1591static int
1592mmu_booke_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1593 vm_prot_t prot, u_int flags, int8_t psind)
1594{
1595 int error;
1596
1597 rw_wlock(&pvh_global_lock);
1598 PMAP_LOCK(pmap);
1599 error = mmu_booke_enter_locked(mmu, pmap, va, m, prot, flags, psind);
1600 rw_wunlock(&pvh_global_lock);
1601 PMAP_UNLOCK(pmap);
1602 return (error);
1603}
1604
1605static int
1606mmu_booke_enter_locked(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1607 vm_prot_t prot, u_int pmap_flags, int8_t psind __unused)
1608{
1609 pte_t *pte;
1610 vm_paddr_t pa;
1611 uint32_t flags;
1612 int error, su, sync;
1613
1614 pa = VM_PAGE_TO_PHYS(m);
1615 su = (pmap == kernel_pmap);
1616 sync = 0;
1617
1618 //debugf("mmu_booke_enter_locked: s (pmap=0x%08x su=%d tid=%d m=0x%08x va=0x%08x "
1619 // "pa=0x%08x prot=0x%08x flags=%#x)\n",
1620 // (u_int32_t)pmap, su, pmap->pm_tid,
1621 // (u_int32_t)m, va, pa, prot, flags);
1622
1623 if (su) {
1624 KASSERT(((va >= virtual_avail) &&
1625 (va <= VM_MAX_KERNEL_ADDRESS)),
1626 ("mmu_booke_enter_locked: kernel pmap, non kernel va"));
1627 } else {
1628 KASSERT((va <= VM_MAXUSER_ADDRESS),
1629 ("mmu_booke_enter_locked: user pmap, non user va"));
1630 }
1631 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
1632 VM_OBJECT_ASSERT_LOCKED(m->object);
1633
1634 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1635
1636 /*
1637 * If there is an existing mapping, and the physical address has not
1638 * changed, must be protection or wiring change.
1639 */
1640 if (((pte = pte_find(mmu, pmap, va)) != NULL) &&
1641 (PTE_ISVALID(pte)) && (PTE_PA(pte) == pa)) {
1642
1643 /*
1644 * Before actually updating pte->flags we calculate and
1645 * prepare its new value in a helper var.
1646 */
1647 flags = pte->flags;
1648 flags &= ~(PTE_UW | PTE_UX | PTE_SW | PTE_SX | PTE_MODIFIED);
1649
1650 /* Wiring change, just update stats. */
1651 if ((pmap_flags & PMAP_ENTER_WIRED) != 0) {
1652 if (!PTE_ISWIRED(pte)) {
1653 flags |= PTE_WIRED;
1654 pmap->pm_stats.wired_count++;
1655 }
1656 } else {
1657 if (PTE_ISWIRED(pte)) {
1658 flags &= ~PTE_WIRED;
1659 pmap->pm_stats.wired_count--;
1660 }
1661 }
1662
1663 if (prot & VM_PROT_WRITE) {
1664 /* Add write permissions. */
1665 flags |= PTE_SW;
1666 if (!su)
1667 flags |= PTE_UW;
1668
1669 if ((flags & PTE_MANAGED) != 0)
1670 vm_page_aflag_set(m, PGA_WRITEABLE);
1671 } else {
1672 /* Handle modified pages, sense modify status. */
1673
1674 /*
1675 * The PTE_MODIFIED flag could be set by underlying
1676 * TLB misses since we last read it (above), possibly
1677 * other CPUs could update it so we check in the PTE
1678 * directly rather than rely on that saved local flags
1679 * copy.
1680 */
1681 if (PTE_ISMODIFIED(pte))
1682 vm_page_dirty(m);
1683 }
1684
1685 if (prot & VM_PROT_EXECUTE) {
1686 flags |= PTE_SX;
1687 if (!su)
1688 flags |= PTE_UX;
1689
1690 /*
1691 * Check existing flags for execute permissions: if we
1692 * are turning execute permissions on, icache should
1693 * be flushed.
1694 */
1695 if ((pte->flags & (PTE_UX | PTE_SX)) == 0)
1696 sync++;
1697 }
1698
1699 flags &= ~PTE_REFERENCED;
1700
1701 /*
1702 * The new flags value is all calculated -- only now actually
1703 * update the PTE.
1704 */
1705 mtx_lock_spin(&tlbivax_mutex);
1706 tlb_miss_lock();
1707
1708 tlb0_flush_entry(va);
1709 pte->flags = flags;
1710
1711 tlb_miss_unlock();
1712 mtx_unlock_spin(&tlbivax_mutex);
1713
1714 } else {
1715 /*
1716 * If there is an existing mapping, but it's for a different
1717 * physical address, pte_enter() will delete the old mapping.
1718 */
1719 //if ((pte != NULL) && PTE_ISVALID(pte))
1720 // debugf("mmu_booke_enter_locked: replace\n");
1721 //else
1722 // debugf("mmu_booke_enter_locked: new\n");
1723
1724 /* Now set up the flags and install the new mapping. */
1725 flags = (PTE_SR | PTE_VALID);
1726 flags |= PTE_M;
1727
1728 if (!su)
1729 flags |= PTE_UR;
1730
1731 if (prot & VM_PROT_WRITE) {
1732 flags |= PTE_SW;
1733 if (!su)
1734 flags |= PTE_UW;
1735
1736 if ((m->oflags & VPO_UNMANAGED) == 0)
1737 vm_page_aflag_set(m, PGA_WRITEABLE);
1738 }
1739
1740 if (prot & VM_PROT_EXECUTE) {
1741 flags |= PTE_SX;
1742 if (!su)
1743 flags |= PTE_UX;
1744 }
1745
1746 /* If its wired update stats. */
1747 if ((pmap_flags & PMAP_ENTER_WIRED) != 0)
1748 flags |= PTE_WIRED;
1749
1750 error = pte_enter(mmu, pmap, m, va, flags,
1751 (pmap_flags & PMAP_ENTER_NOSLEEP) != 0);
1752 if (error != 0)
1753 return (KERN_RESOURCE_SHORTAGE);
1754
1755 if ((flags & PMAP_ENTER_WIRED) != 0)
1756 pmap->pm_stats.wired_count++;
1757
1758 /* Flush the real memory from the instruction cache. */
1759 if (prot & VM_PROT_EXECUTE)
1760 sync++;
1761 }
1762
1763 if (sync && (su || pmap == PCPU_GET(curpmap))) {
1764 __syncicache((void *)va, PAGE_SIZE);
1765 sync = 0;
1766 }
1767
1768 return (KERN_SUCCESS);
1769}
1770
1771/*
1772 * Maps a sequence of resident pages belonging to the same object.
1773 * The sequence begins with the given page m_start. This page is
1774 * mapped at the given virtual address start. Each subsequent page is
1775 * mapped at a virtual address that is offset from start by the same
1776 * amount as the page is offset from m_start within the object. The
1777 * last page in the sequence is the page with the largest offset from
1778 * m_start that can be mapped at a virtual address less than the given
1779 * virtual address end. Not every virtual page between start and end
1780 * is mapped; only those for which a resident page exists with the
1781 * corresponding offset from m_start are mapped.
1782 */
1783static void
1784mmu_booke_enter_object(mmu_t mmu, pmap_t pmap, vm_offset_t start,
1785 vm_offset_t end, vm_page_t m_start, vm_prot_t prot)
1786{
1787 vm_page_t m;
1788 vm_pindex_t diff, psize;
1789
1790 VM_OBJECT_ASSERT_LOCKED(m_start->object);
1791
1792 psize = atop(end - start);
1793 m = m_start;
1794 rw_wlock(&pvh_global_lock);
1795 PMAP_LOCK(pmap);
1796 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1797 mmu_booke_enter_locked(mmu, pmap, start + ptoa(diff), m,
1798 prot & (VM_PROT_READ | VM_PROT_EXECUTE),
1799 PMAP_ENTER_NOSLEEP, 0);
1800 m = TAILQ_NEXT(m, listq);
1801 }
1802 rw_wunlock(&pvh_global_lock);
1803 PMAP_UNLOCK(pmap);
1804}
1805
1806static void
1807mmu_booke_enter_quick(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m,
1808 vm_prot_t prot)
1809{
1810
1811 rw_wlock(&pvh_global_lock);
1812 PMAP_LOCK(pmap);
1813 mmu_booke_enter_locked(mmu, pmap, va, m,
1814 prot & (VM_PROT_READ | VM_PROT_EXECUTE), PMAP_ENTER_NOSLEEP,
1815 0);
1816 rw_wunlock(&pvh_global_lock);
1817 PMAP_UNLOCK(pmap);
1818}
1819
1820/*
1821 * Remove the given range of addresses from the specified map.
1822 *
1823 * It is assumed that the start and end are properly rounded to the page size.
1824 */
1825static void
1826mmu_booke_remove(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_offset_t endva)
1827{
1828 pte_t *pte;
1829 uint8_t hold_flag;
1830
1831 int su = (pmap == kernel_pmap);
1832
1833 //debugf("mmu_booke_remove: s (su = %d pmap=0x%08x tid=%d va=0x%08x endva=0x%08x)\n",
1834 // su, (u_int32_t)pmap, pmap->pm_tid, va, endva);
1835
1836 if (su) {
1837 KASSERT(((va >= virtual_avail) &&
1838 (va <= VM_MAX_KERNEL_ADDRESS)),
1839 ("mmu_booke_remove: kernel pmap, non kernel va"));
1840 } else {
1841 KASSERT((va <= VM_MAXUSER_ADDRESS),
1842 ("mmu_booke_remove: user pmap, non user va"));
1843 }
1844
1845 if (PMAP_REMOVE_DONE(pmap)) {
1846 //debugf("mmu_booke_remove: e (empty)\n");
1847 return;
1848 }
1849
1850 hold_flag = PTBL_HOLD_FLAG(pmap);
1851 //debugf("mmu_booke_remove: hold_flag = %d\n", hold_flag);
1852
1853 rw_wlock(&pvh_global_lock);
1854 PMAP_LOCK(pmap);
1855 for (; va < endva; va += PAGE_SIZE) {
1856 pte = pte_find(mmu, pmap, va);
1857 if ((pte != NULL) && PTE_ISVALID(pte))
1858 pte_remove(mmu, pmap, va, hold_flag);
1859 }
1860 PMAP_UNLOCK(pmap);
1861 rw_wunlock(&pvh_global_lock);
1862
1863 //debugf("mmu_booke_remove: e\n");
1864}
1865
1866/*
1867 * Remove physical page from all pmaps in which it resides.
1868 */
1869static void
1870mmu_booke_remove_all(mmu_t mmu, vm_page_t m)
1871{
1872 pv_entry_t pv, pvn;
1873 uint8_t hold_flag;
1874
1875 rw_wlock(&pvh_global_lock);
1876 for (pv = TAILQ_FIRST(&m->md.pv_list); pv != NULL; pv = pvn) {
1877 pvn = TAILQ_NEXT(pv, pv_link);
1878
1879 PMAP_LOCK(pv->pv_pmap);
1880 hold_flag = PTBL_HOLD_FLAG(pv->pv_pmap);
1881 pte_remove(mmu, pv->pv_pmap, pv->pv_va, hold_flag);
1882 PMAP_UNLOCK(pv->pv_pmap);
1883 }
1884 vm_page_aflag_clear(m, PGA_WRITEABLE);
1885 rw_wunlock(&pvh_global_lock);
1886}
1887
1888/*
1889 * Map a range of physical addresses into kernel virtual address space.
1890 */
1891static vm_offset_t
1892mmu_booke_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start,
1893 vm_paddr_t pa_end, int prot)
1894{
1895 vm_offset_t sva = *virt;
1896 vm_offset_t va = sva;
1897
1898 //debugf("mmu_booke_map: s (sva = 0x%08x pa_start = 0x%08x pa_end = 0x%08x)\n",
1899 // sva, pa_start, pa_end);
1900
1901 while (pa_start < pa_end) {
1902 mmu_booke_kenter(mmu, va, pa_start);
1903 va += PAGE_SIZE;
1904 pa_start += PAGE_SIZE;
1905 }
1906 *virt = va;
1907
1908 //debugf("mmu_booke_map: e (va = 0x%08x)\n", va);
1909 return (sva);
1910}
1911
1912/*
1913 * The pmap must be activated before it's address space can be accessed in any
1914 * way.
1915 */
1916static void
1917mmu_booke_activate(mmu_t mmu, struct thread *td)
1918{
1919 pmap_t pmap;
1920 u_int cpuid;
1921
1922 pmap = &td->td_proc->p_vmspace->vm_pmap;
1923
1924 CTR5(KTR_PMAP, "%s: s (td = %p, proc = '%s', id = %d, pmap = 0x%08x)",
1925 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap);
1926
1927 KASSERT((pmap != kernel_pmap), ("mmu_booke_activate: kernel_pmap!"));
1928
1929 sched_pin();
1930
1931 cpuid = PCPU_GET(cpuid);
1932 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
1933 PCPU_SET(curpmap, pmap);
1934
1935 if (pmap->pm_tid[cpuid] == TID_NONE)
1936 tid_alloc(pmap);
1937
1938 /* Load PID0 register with pmap tid value. */
1939 mtspr(SPR_PID0, pmap->pm_tid[cpuid]);
1940 __asm __volatile("isync");
1941
1942 sched_unpin();
1943
1944 CTR3(KTR_PMAP, "%s: e (tid = %d for '%s')", __func__,
1945 pmap->pm_tid[PCPU_GET(cpuid)], td->td_proc->p_comm);
1946}
1947
1948/*
1949 * Deactivate the specified process's address space.
1950 */
1951static void
1952mmu_booke_deactivate(mmu_t mmu, struct thread *td)
1953{
1954 pmap_t pmap;
1955
1956 pmap = &td->td_proc->p_vmspace->vm_pmap;
1957
1958 CTR5(KTR_PMAP, "%s: td=%p, proc = '%s', id = %d, pmap = 0x%08x",
1959 __func__, td, td->td_proc->p_comm, td->td_proc->p_pid, pmap);
1960
1961 CPU_CLR_ATOMIC(PCPU_GET(cpuid), &pmap->pm_active);
1962 PCPU_SET(curpmap, NULL);
1963}
1964
1965/*
1966 * Copy the range specified by src_addr/len
1967 * from the source map to the range dst_addr/len
1968 * in the destination map.
1969 *
1970 * This routine is only advisory and need not do anything.
1971 */
1972static void
1973mmu_booke_copy(mmu_t mmu, pmap_t dst_pmap, pmap_t src_pmap,
1974 vm_offset_t dst_addr, vm_size_t len, vm_offset_t src_addr)
1975{
1976
1977}
1978
1979/*
1980 * Set the physical protection on the specified range of this map as requested.
1981 */
1982static void
1983mmu_booke_protect(mmu_t mmu, pmap_t pmap, vm_offset_t sva, vm_offset_t eva,
1984 vm_prot_t prot)
1985{
1986 vm_offset_t va;
1987 vm_page_t m;
1988 pte_t *pte;
1989
1990 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1991 mmu_booke_remove(mmu, pmap, sva, eva);
1992 return;
1993 }
1994
1995 if (prot & VM_PROT_WRITE)
1996 return;
1997
1998 PMAP_LOCK(pmap);
1999 for (va = sva; va < eva; va += PAGE_SIZE) {
2000 if ((pte = pte_find(mmu, pmap, va)) != NULL) {
2001 if (PTE_ISVALID(pte)) {
2002 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
2003
2004 mtx_lock_spin(&tlbivax_mutex);
2005 tlb_miss_lock();
2006
2007 /* Handle modified pages. */
2008 if (PTE_ISMODIFIED(pte) && PTE_ISMANAGED(pte))
2009 vm_page_dirty(m);
2010
2011 tlb0_flush_entry(va);
2012 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED);
2013
2014 tlb_miss_unlock();
2015 mtx_unlock_spin(&tlbivax_mutex);
2016 }
2017 }
2018 }
2019 PMAP_UNLOCK(pmap);
2020}
2021
2022/*
2023 * Clear the write and modified bits in each of the given page's mappings.
2024 */
2025static void
2026mmu_booke_remove_write(mmu_t mmu, vm_page_t m)
2027{
2028 pv_entry_t pv;
2029 pte_t *pte;
2030
2031 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2032 ("mmu_booke_remove_write: page %p is not managed", m));
2033
2034 /*
2035 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
2036 * set by another thread while the object is locked. Thus,
2037 * if PGA_WRITEABLE is clear, no page table entries need updating.
2038 */
2039 VM_OBJECT_ASSERT_WLOCKED(m->object);
2040 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
2041 return;
2042 rw_wlock(&pvh_global_lock);
2043 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2044 PMAP_LOCK(pv->pv_pmap);
2045 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL) {
2046 if (PTE_ISVALID(pte)) {
2047 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
2048
2049 mtx_lock_spin(&tlbivax_mutex);
2050 tlb_miss_lock();
2051
2052 /* Handle modified pages. */
2053 if (PTE_ISMODIFIED(pte))
2054 vm_page_dirty(m);
2055
2056 /* Flush mapping from TLB0. */
2057 pte->flags &= ~(PTE_UW | PTE_SW | PTE_MODIFIED);
2058
2059 tlb_miss_unlock();
2060 mtx_unlock_spin(&tlbivax_mutex);
2061 }
2062 }
2063 PMAP_UNLOCK(pv->pv_pmap);
2064 }
2065 vm_page_aflag_clear(m, PGA_WRITEABLE);
2066 rw_wunlock(&pvh_global_lock);
2067}
2068
2069static void
2070mmu_booke_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
2071{
2072 pte_t *pte;
2073 pmap_t pmap;
2074 vm_page_t m;
2075 vm_offset_t addr;
2076 vm_paddr_t pa;
2077 int active, valid;
2078
2079 va = trunc_page(va);
2080 sz = round_page(sz);
2081
2082 rw_wlock(&pvh_global_lock);
2083 pmap = PCPU_GET(curpmap);
2084 active = (pm == kernel_pmap || pm == pmap) ? 1 : 0;
2085 while (sz > 0) {
2086 PMAP_LOCK(pm);
2087 pte = pte_find(mmu, pm, va);
2088 valid = (pte != NULL && PTE_ISVALID(pte)) ? 1 : 0;
2089 if (valid)
2090 pa = PTE_PA(pte);
2091 PMAP_UNLOCK(pm);
2092 if (valid) {
2093 if (!active) {
2094 /* Create a mapping in the active pmap. */
2095 addr = 0;
2096 m = PHYS_TO_VM_PAGE(pa);
2097 PMAP_LOCK(pmap);
2098 pte_enter(mmu, pmap, m, addr,
2099 PTE_SR | PTE_VALID | PTE_UR, FALSE);
2100 __syncicache((void *)addr, PAGE_SIZE);
2101 pte_remove(mmu, pmap, addr, PTBL_UNHOLD);
2102 PMAP_UNLOCK(pmap);
2103 } else
2104 __syncicache((void *)va, PAGE_SIZE);
2105 }
2106 va += PAGE_SIZE;
2107 sz -= PAGE_SIZE;
2108 }
2109 rw_wunlock(&pvh_global_lock);
2110}
2111
2112/*
2113 * Atomically extract and hold the physical page with the given
2114 * pmap and virtual address pair if that mapping permits the given
2115 * protection.
2116 */
2117static vm_page_t
2118mmu_booke_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va,
2119 vm_prot_t prot)
2120{
2121 pte_t *pte;
2122 vm_page_t m;
2123 uint32_t pte_wbit;
2124 vm_paddr_t pa;
2125
2126 m = NULL;
2127 pa = 0;
2128 PMAP_LOCK(pmap);
2129retry:
2130 pte = pte_find(mmu, pmap, va);
2131 if ((pte != NULL) && PTE_ISVALID(pte)) {
2132 if (pmap == kernel_pmap)
2133 pte_wbit = PTE_SW;
2134 else
2135 pte_wbit = PTE_UW;
2136
2137 if ((pte->flags & pte_wbit) || ((prot & VM_PROT_WRITE) == 0)) {
2138 if (vm_page_pa_tryrelock(pmap, PTE_PA(pte), &pa))
2139 goto retry;
2140 m = PHYS_TO_VM_PAGE(PTE_PA(pte));
2141 vm_page_hold(m);
2142 }
2143 }
2144
2145 PA_UNLOCK_COND(pa);
2146 PMAP_UNLOCK(pmap);
2147 return (m);
2148}
2149
2150/*
2151 * Initialize a vm_page's machine-dependent fields.
2152 */
2153static void
2154mmu_booke_page_init(mmu_t mmu, vm_page_t m)
2155{
2156
2157 TAILQ_INIT(&m->md.pv_list);
2158}
2159
2160/*
2161 * mmu_booke_zero_page_area zeros the specified hardware page by
2162 * mapping it into virtual memory and using bzero to clear
2163 * its contents.
2164 *
2165 * off and size must reside within a single page.
2166 */
2167static void
2168mmu_booke_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
2169{
2170 vm_offset_t va;
2171
2172 /* XXX KASSERT off and size are within a single page? */
2173
2174 mtx_lock(&zero_page_mutex);
2175 va = zero_page_va;
2176
2177 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m));
2178 bzero((caddr_t)va + off, size);
2179 mmu_booke_kremove(mmu, va);
2180
2181 mtx_unlock(&zero_page_mutex);
2182}
2183
2184/*
2185 * mmu_booke_zero_page zeros the specified hardware page.
2186 */
2187static void
2188mmu_booke_zero_page(mmu_t mmu, vm_page_t m)
2189{
2190
2191 mmu_booke_zero_page_area(mmu, m, 0, PAGE_SIZE);
2192}
2193
2194/*
2195 * mmu_booke_copy_page copies the specified (machine independent) page by
2196 * mapping the page into virtual memory and using memcopy to copy the page,
2197 * one machine dependent page at a time.
2198 */
2199static void
2200mmu_booke_copy_page(mmu_t mmu, vm_page_t sm, vm_page_t dm)
2201{
2202 vm_offset_t sva, dva;
2203
2204 sva = copy_page_src_va;
2205 dva = copy_page_dst_va;
2206
2207 mtx_lock(©_page_mutex);
2208 mmu_booke_kenter(mmu, sva, VM_PAGE_TO_PHYS(sm));
2209 mmu_booke_kenter(mmu, dva, VM_PAGE_TO_PHYS(dm));
2210 memcpy((caddr_t)dva, (caddr_t)sva, PAGE_SIZE);
2211 mmu_booke_kremove(mmu, dva);
2212 mmu_booke_kremove(mmu, sva);
2213 mtx_unlock(©_page_mutex);
2214}
2215
2216static inline void
2217mmu_booke_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
2218 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
2219{
2220 void *a_cp, *b_cp;
2221 vm_offset_t a_pg_offset, b_pg_offset;
2222 int cnt;
2223
2224 mtx_lock(©_page_mutex);
2225 while (xfersize > 0) {
2226 a_pg_offset = a_offset & PAGE_MASK;
2227 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
2228 mmu_booke_kenter(mmu, copy_page_src_va,
2229 VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]));
2230 a_cp = (char *)copy_page_src_va + a_pg_offset;
2231 b_pg_offset = b_offset & PAGE_MASK;
2232 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
2233 mmu_booke_kenter(mmu, copy_page_dst_va,
2234 VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]));
2235 b_cp = (char *)copy_page_dst_va + b_pg_offset;
2236 bcopy(a_cp, b_cp, cnt);
2237 mmu_booke_kremove(mmu, copy_page_dst_va);
2238 mmu_booke_kremove(mmu, copy_page_src_va);
2239 a_offset += cnt;
2240 b_offset += cnt;
2241 xfersize -= cnt;
2242 }
2243 mtx_unlock(©_page_mutex);
2244}
2245
2246/*
2247 * mmu_booke_zero_page_idle zeros the specified hardware page by mapping it
2248 * into virtual memory and using bzero to clear its contents. This is intended
2249 * to be called from the vm_pagezero process only and outside of Giant. No
2250 * lock is required.
2251 */
2252static void
2253mmu_booke_zero_page_idle(mmu_t mmu, vm_page_t m)
2254{
2255 vm_offset_t va;
2256
2257 va = zero_page_idle_va;
2258 mmu_booke_kenter(mmu, va, VM_PAGE_TO_PHYS(m));
2259 bzero((caddr_t)va, PAGE_SIZE);
2260 mmu_booke_kremove(mmu, va);
2261}
2262
2263/*
2264 * Return whether or not the specified physical page was modified
2265 * in any of physical maps.
2266 */
2267static boolean_t
2268mmu_booke_is_modified(mmu_t mmu, vm_page_t m)
2269{
2270 pte_t *pte;
2271 pv_entry_t pv;
2272 boolean_t rv;
2273
2274 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2275 ("mmu_booke_is_modified: page %p is not managed", m));
2276 rv = FALSE;
2277
2278 /*
2279 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
2280 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
2281 * is clear, no PTEs can be modified.
2282 */
2283 VM_OBJECT_ASSERT_WLOCKED(m->object);
2284 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
2285 return (rv);
2286 rw_wlock(&pvh_global_lock);
2287 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2288 PMAP_LOCK(pv->pv_pmap);
2289 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2290 PTE_ISVALID(pte)) {
2291 if (PTE_ISMODIFIED(pte))
2292 rv = TRUE;
2293 }
2294 PMAP_UNLOCK(pv->pv_pmap);
2295 if (rv)
2296 break;
2297 }
2298 rw_wunlock(&pvh_global_lock);
2299 return (rv);
2300}
2301
2302/*
2303 * Return whether or not the specified virtual address is eligible
2304 * for prefault.
2305 */
2306static boolean_t
2307mmu_booke_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t addr)
2308{
2309
2310 return (FALSE);
2311}
2312
2313/*
2314 * Return whether or not the specified physical page was referenced
2315 * in any physical maps.
2316 */
2317static boolean_t
2318mmu_booke_is_referenced(mmu_t mmu, vm_page_t m)
2319{
2320 pte_t *pte;
2321 pv_entry_t pv;
2322 boolean_t rv;
2323
2324 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2325 ("mmu_booke_is_referenced: page %p is not managed", m));
2326 rv = FALSE;
2327 rw_wlock(&pvh_global_lock);
2328 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2329 PMAP_LOCK(pv->pv_pmap);
2330 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2331 PTE_ISVALID(pte)) {
2332 if (PTE_ISREFERENCED(pte))
2333 rv = TRUE;
2334 }
2335 PMAP_UNLOCK(pv->pv_pmap);
2336 if (rv)
2337 break;
2338 }
2339 rw_wunlock(&pvh_global_lock);
2340 return (rv);
2341}
2342
2343/*
2344 * Clear the modify bits on the specified physical page.
2345 */
2346static void
2347mmu_booke_clear_modify(mmu_t mmu, vm_page_t m)
2348{
2349 pte_t *pte;
2350 pv_entry_t pv;
2351
2352 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2353 ("mmu_booke_clear_modify: page %p is not managed", m));
2354 VM_OBJECT_ASSERT_WLOCKED(m->object);
2355 KASSERT(!vm_page_xbusied(m),
2356 ("mmu_booke_clear_modify: page %p is exclusive busied", m));
2357
2358 /*
2359 * If the page is not PG_AWRITEABLE, then no PTEs can be modified.
2360 * If the object containing the page is locked and the page is not
2361 * exclusive busied, then PG_AWRITEABLE cannot be concurrently set.
2362 */
2363 if ((m->aflags & PGA_WRITEABLE) == 0)
2364 return;
2365 rw_wlock(&pvh_global_lock);
2366 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2367 PMAP_LOCK(pv->pv_pmap);
2368 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2369 PTE_ISVALID(pte)) {
2370 mtx_lock_spin(&tlbivax_mutex);
2371 tlb_miss_lock();
2372
2373 if (pte->flags & (PTE_SW | PTE_UW | PTE_MODIFIED)) {
2374 tlb0_flush_entry(pv->pv_va);
2375 pte->flags &= ~(PTE_SW | PTE_UW | PTE_MODIFIED |
2376 PTE_REFERENCED);
2377 }
2378
2379 tlb_miss_unlock();
2380 mtx_unlock_spin(&tlbivax_mutex);
2381 }
2382 PMAP_UNLOCK(pv->pv_pmap);
2383 }
2384 rw_wunlock(&pvh_global_lock);
2385}
2386
2387/*
2388 * Return a count of reference bits for a page, clearing those bits.
2389 * It is not necessary for every reference bit to be cleared, but it
2390 * is necessary that 0 only be returned when there are truly no
2391 * reference bits set.
2392 *
2393 * XXX: The exact number of bits to check and clear is a matter that
2394 * should be tested and standardized at some point in the future for
2395 * optimal aging of shared pages.
2396 */
2397static int
2398mmu_booke_ts_referenced(mmu_t mmu, vm_page_t m)
2399{
2400 pte_t *pte;
2401 pv_entry_t pv;
2402 int count;
2403
2404 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2405 ("mmu_booke_ts_referenced: page %p is not managed", m));
2406 count = 0;
2407 rw_wlock(&pvh_global_lock);
2408 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2409 PMAP_LOCK(pv->pv_pmap);
2410 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL &&
2411 PTE_ISVALID(pte)) {
2412 if (PTE_ISREFERENCED(pte)) {
2413 mtx_lock_spin(&tlbivax_mutex);
2414 tlb_miss_lock();
2415
2416 tlb0_flush_entry(pv->pv_va);
2417 pte->flags &= ~PTE_REFERENCED;
2418
2419 tlb_miss_unlock();
2420 mtx_unlock_spin(&tlbivax_mutex);
2421
2422 if (++count > 4) {
2423 PMAP_UNLOCK(pv->pv_pmap);
2424 break;
2425 }
2426 }
2427 }
2428 PMAP_UNLOCK(pv->pv_pmap);
2429 }
2430 rw_wunlock(&pvh_global_lock);
2431 return (count);
2432}
2433
2434/*
|
2457}
2458
2459/*
2460 * Return true if the pmap's pv is one of the first 16 pvs linked to from this
2461 * page. This count may be changed upwards or downwards in the future; it is
2462 * only necessary that true be returned for a small subset of pmaps for proper
2463 * page aging.
2464 */
2465static boolean_t
2466mmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
2467{
2468 pv_entry_t pv;
2469 int loops;
2470 boolean_t rv;
2471
2472 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2473 ("mmu_booke_page_exists_quick: page %p is not managed", m));
2474 loops = 0;
2475 rv = FALSE;
2476 rw_wlock(&pvh_global_lock);
2477 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2478 if (pv->pv_pmap == pmap) {
2479 rv = TRUE;
2480 break;
2481 }
2482 if (++loops >= 16)
2483 break;
2484 }
2485 rw_wunlock(&pvh_global_lock);
2486 return (rv);
2487}
2488
2489/*
2490 * Return the number of managed mappings to the given physical page that are
2491 * wired.
2492 */
2493static int
2494mmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m)
2495{
2496 pv_entry_t pv;
2497 pte_t *pte;
2498 int count = 0;
2499
2500 if ((m->oflags & VPO_UNMANAGED) != 0)
2501 return (count);
2502 rw_wlock(&pvh_global_lock);
2503 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2504 PMAP_LOCK(pv->pv_pmap);
2505 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL)
2506 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte))
2507 count++;
2508 PMAP_UNLOCK(pv->pv_pmap);
2509 }
2510 rw_wunlock(&pvh_global_lock);
2511 return (count);
2512}
2513
2514static int
2515mmu_booke_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2516{
2517 int i;
2518 vm_offset_t va;
2519
2520 /*
2521 * This currently does not work for entries that
2522 * overlap TLB1 entries.
2523 */
2524 for (i = 0; i < tlb1_idx; i ++) {
2525 if (tlb1_iomapped(i, pa, size, &va) == 0)
2526 return (0);
2527 }
2528
2529 return (EFAULT);
2530}
2531
2532vm_offset_t
2533mmu_booke_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs,
2534 vm_size_t *sz)
2535{
2536 vm_paddr_t pa, ppa;
2537 vm_offset_t va;
2538 vm_size_t gran;
2539
2540 /* Raw physical memory dumps don't have a virtual address. */
2541 if (md->md_vaddr == ~0UL) {
2542 /* We always map a 256MB page at 256M. */
2543 gran = 256 * 1024 * 1024;
2544 pa = md->md_paddr + ofs;
2545 ppa = pa & ~(gran - 1);
2546 ofs = pa - ppa;
2547 va = gran;
2548 tlb1_set_entry(va, ppa, gran, _TLB_ENTRY_IO);
2549 if (*sz > (gran - ofs))
2550 *sz = gran - ofs;
2551 return (va + ofs);
2552 }
2553
2554 /* Minidumps are based on virtual memory addresses. */
2555 va = md->md_vaddr + ofs;
2556 if (va >= kernstart + kernsize) {
2557 gran = PAGE_SIZE - (va & PAGE_MASK);
2558 if (*sz > gran)
2559 *sz = gran;
2560 }
2561 return (va);
2562}
2563
2564void
2565mmu_booke_dumpsys_unmap(mmu_t mmu, struct pmap_md *md, vm_size_t ofs,
2566 vm_offset_t va)
2567{
2568
2569 /* Raw physical memory dumps don't have a virtual address. */
2570 if (md->md_vaddr == ~0UL) {
2571 tlb1_idx--;
2572 tlb1[tlb1_idx].mas1 = 0;
2573 tlb1[tlb1_idx].mas2 = 0;
2574 tlb1[tlb1_idx].mas3 = 0;
2575 tlb1_write_entry(tlb1_idx);
2576 return;
2577 }
2578
2579 /* Minidumps are based on virtual memory addresses. */
2580 /* Nothing to do... */
2581}
2582
2583struct pmap_md *
2584mmu_booke_scan_md(mmu_t mmu, struct pmap_md *prev)
2585{
2586 static struct pmap_md md;
2587 pte_t *pte;
2588 vm_offset_t va;
2589
2590 if (dumpsys_minidump) {
2591 md.md_paddr = ~0UL; /* Minidumps use virtual addresses. */
2592 if (prev == NULL) {
2593 /* 1st: kernel .data and .bss. */
2594 md.md_index = 1;
2595 md.md_vaddr = trunc_page((uintptr_t)_etext);
2596 md.md_size = round_page((uintptr_t)_end) - md.md_vaddr;
2597 return (&md);
2598 }
2599 switch (prev->md_index) {
2600 case 1:
2601 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */
2602 md.md_index = 2;
2603 md.md_vaddr = data_start;
2604 md.md_size = data_end - data_start;
2605 break;
2606 case 2:
2607 /* 3rd: kernel VM. */
2608 va = prev->md_vaddr + prev->md_size;
2609 /* Find start of next chunk (from va). */
2610 while (va < virtual_end) {
2611 /* Don't dump the buffer cache. */
2612 if (va >= kmi.buffer_sva &&
2613 va < kmi.buffer_eva) {
2614 va = kmi.buffer_eva;
2615 continue;
2616 }
2617 pte = pte_find(mmu, kernel_pmap, va);
2618 if (pte != NULL && PTE_ISVALID(pte))
2619 break;
2620 va += PAGE_SIZE;
2621 }
2622 if (va < virtual_end) {
2623 md.md_vaddr = va;
2624 va += PAGE_SIZE;
2625 /* Find last page in chunk. */
2626 while (va < virtual_end) {
2627 /* Don't run into the buffer cache. */
2628 if (va == kmi.buffer_sva)
2629 break;
2630 pte = pte_find(mmu, kernel_pmap, va);
2631 if (pte == NULL || !PTE_ISVALID(pte))
2632 break;
2633 va += PAGE_SIZE;
2634 }
2635 md.md_size = va - md.md_vaddr;
2636 break;
2637 }
2638 md.md_index = 3;
2639 /* FALLTHROUGH */
2640 default:
2641 return (NULL);
2642 }
2643 } else { /* minidumps */
2644 mem_regions(&physmem_regions, &physmem_regions_sz,
2645 &availmem_regions, &availmem_regions_sz);
2646
2647 if (prev == NULL) {
2648 /* first physical chunk. */
2649 md.md_paddr = physmem_regions[0].mr_start;
2650 md.md_size = physmem_regions[0].mr_size;
2651 md.md_vaddr = ~0UL;
2652 md.md_index = 1;
2653 } else if (md.md_index < physmem_regions_sz) {
2654 md.md_paddr = physmem_regions[md.md_index].mr_start;
2655 md.md_size = physmem_regions[md.md_index].mr_size;
2656 md.md_vaddr = ~0UL;
2657 md.md_index++;
2658 } else {
2659 /* There's no next physical chunk. */
2660 return (NULL);
2661 }
2662 }
2663
2664 return (&md);
2665}
2666
2667/*
2668 * Map a set of physical memory pages into the kernel virtual address space.
2669 * Return a pointer to where it is mapped. This routine is intended to be used
2670 * for mapping device memory, NOT real memory.
2671 */
2672static void *
2673mmu_booke_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2674{
2675
2676 return (mmu_booke_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT));
2677}
2678
2679static void *
2680mmu_booke_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma)
2681{
2682 void *res;
2683 uintptr_t va;
2684 vm_size_t sz;
2685 int i;
2686
2687 /*
2688 * Check if this is premapped in TLB1. Note: this should probably also
2689 * check whether a sequence of TLB1 entries exist that match the
2690 * requirement, but now only checks the easy case.
2691 */
2692 if (ma == VM_MEMATTR_DEFAULT) {
2693 for (i = 0; i < tlb1_idx; i++) {
2694 if (!(tlb1[i].mas1 & MAS1_VALID))
2695 continue;
2696 if (pa >= tlb1[i].phys &&
2697 (pa + size) <= (tlb1[i].phys + tlb1[i].size))
2698 return (void *)(tlb1[i].virt +
2699 (pa - tlb1[i].phys));
2700 }
2701 }
2702
2703 size = roundup(size, PAGE_SIZE);
2704
2705 /*
2706 * We leave a hole for device direct mapping between the maximum user
2707 * address (0x8000000) and the minimum KVA address (0xc0000000). If
2708 * devices are in there, just map them 1:1. If not, map them to the
2709 * device mapping area about VM_MAX_KERNEL_ADDRESS. These mapped
2710 * addresses should be pulled from an allocator, but since we do not
2711 * ever free TLB1 entries, it is safe just to increment a counter.
2712 * Note that there isn't a lot of address space here (128 MB) and it
2713 * is not at all difficult to imagine running out, since that is a 4:1
2714 * compression from the 0xc0000000 - 0xf0000000 address space that gets
2715 * mapped there.
2716 */
2717 if (pa >= (VM_MAXUSER_ADDRESS + PAGE_SIZE) &&
2718 (pa + size - 1) < VM_MIN_KERNEL_ADDRESS)
2719 va = pa;
2720 else
2721 va = atomic_fetchadd_int(&tlb1_map_base, size);
2722 res = (void *)va;
2723
2724 do {
2725 sz = 1 << (ilog2(size) & ~1);
2726 if (bootverbose)
2727 printf("Wiring VA=%x to PA=%x (size=%x), "
2728 "using TLB1[%d]\n", va, pa, sz, tlb1_idx);
2729 tlb1_set_entry(va, pa, sz, tlb_calc_wimg(pa, ma));
2730 size -= sz;
2731 pa += sz;
2732 va += sz;
2733 } while (size > 0);
2734
2735 return (res);
2736}
2737
2738/*
2739 * 'Unmap' a range mapped by mmu_booke_mapdev().
2740 */
2741static void
2742mmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
2743{
2744#ifdef SUPPORTS_SHRINKING_TLB1
2745 vm_offset_t base, offset;
2746
2747 /*
2748 * Unmap only if this is inside kernel virtual space.
2749 */
2750 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) {
2751 base = trunc_page(va);
2752 offset = va & PAGE_MASK;
2753 size = roundup(offset + size, PAGE_SIZE);
2754 kva_free(base, size);
2755 }
2756#endif
2757}
2758
2759/*
2760 * mmu_booke_object_init_pt preloads the ptes for a given object into the
2761 * specified pmap. This eliminates the blast of soft faults on process startup
2762 * and immediately after an mmap.
2763 */
2764static void
2765mmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr,
2766 vm_object_t object, vm_pindex_t pindex, vm_size_t size)
2767{
2768
2769 VM_OBJECT_ASSERT_WLOCKED(object);
2770 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
2771 ("mmu_booke_object_init_pt: non-device object"));
2772}
2773
2774/*
2775 * Perform the pmap work for mincore.
2776 */
2777static int
2778mmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr,
2779 vm_paddr_t *locked_pa)
2780{
2781
2782 /* XXX: this should be implemented at some point */
2783 return (0);
2784}
2785
2786/**************************************************************************/
2787/* TID handling */
2788/**************************************************************************/
2789
2790/*
2791 * Allocate a TID. If necessary, steal one from someone else.
2792 * The new TID is flushed from the TLB before returning.
2793 */
2794static tlbtid_t
2795tid_alloc(pmap_t pmap)
2796{
2797 tlbtid_t tid;
2798 int thiscpu;
2799
2800 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap"));
2801
2802 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap);
2803
2804 thiscpu = PCPU_GET(cpuid);
2805
2806 tid = PCPU_GET(tid_next);
2807 if (tid > TID_MAX)
2808 tid = TID_MIN;
2809 PCPU_SET(tid_next, tid + 1);
2810
2811 /* If we are stealing TID then clear the relevant pmap's field */
2812 if (tidbusy[thiscpu][tid] != NULL) {
2813
2814 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid);
2815
2816 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE;
2817
2818 /* Flush all entries from TLB0 matching this TID. */
2819 tid_flush(tid);
2820 }
2821
2822 tidbusy[thiscpu][tid] = pmap;
2823 pmap->pm_tid[thiscpu] = tid;
2824 __asm __volatile("msync; isync");
2825
2826 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid,
2827 PCPU_GET(tid_next));
2828
2829 return (tid);
2830}
2831
2832/**************************************************************************/
2833/* TLB0 handling */
2834/**************************************************************************/
2835
2836static void
2837tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3,
2838 uint32_t mas7)
2839{
2840 int as;
2841 char desc[3];
2842 tlbtid_t tid;
2843 vm_size_t size;
2844 unsigned int tsize;
2845
2846 desc[2] = '\0';
2847 if (mas1 & MAS1_VALID)
2848 desc[0] = 'V';
2849 else
2850 desc[0] = ' ';
2851
2852 if (mas1 & MAS1_IPROT)
2853 desc[1] = 'P';
2854 else
2855 desc[1] = ' ';
2856
2857 as = (mas1 & MAS1_TS_MASK) ? 1 : 0;
2858 tid = MAS1_GETTID(mas1);
2859
2860 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
2861 size = 0;
2862 if (tsize)
2863 size = tsize2size(tsize);
2864
2865 debugf("%3d: (%s) [AS=%d] "
2866 "sz = 0x%08x tsz = %d tid = %d mas1 = 0x%08x "
2867 "mas2(va) = 0x%08x mas3(pa) = 0x%08x mas7 = 0x%08x\n",
2868 i, desc, as, size, tsize, tid, mas1, mas2, mas3, mas7);
2869}
2870
2871/* Convert TLB0 va and way number to tlb0[] table index. */
2872static inline unsigned int
2873tlb0_tableidx(vm_offset_t va, unsigned int way)
2874{
2875 unsigned int idx;
2876
2877 idx = (way * TLB0_ENTRIES_PER_WAY);
2878 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT;
2879 return (idx);
2880}
2881
2882/*
2883 * Invalidate TLB0 entry.
2884 */
2885static inline void
2886tlb0_flush_entry(vm_offset_t va)
2887{
2888
2889 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va);
2890
2891 mtx_assert(&tlbivax_mutex, MA_OWNED);
2892
2893 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK));
2894 __asm __volatile("isync; msync");
2895 __asm __volatile("tlbsync; msync");
2896
2897 CTR1(KTR_PMAP, "%s: e", __func__);
2898}
2899
2900/* Print out contents of the MAS registers for each TLB0 entry */
2901void
2902tlb0_print_tlbentries(void)
2903{
2904 uint32_t mas0, mas1, mas2, mas3, mas7;
2905 int entryidx, way, idx;
2906
2907 debugf("TLB0 entries:\n");
2908 for (way = 0; way < TLB0_WAYS; way ++)
2909 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) {
2910
2911 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way);
2912 mtspr(SPR_MAS0, mas0);
2913 __asm __volatile("isync");
2914
2915 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT;
2916 mtspr(SPR_MAS2, mas2);
2917
2918 __asm __volatile("isync; tlbre");
2919
2920 mas1 = mfspr(SPR_MAS1);
2921 mas2 = mfspr(SPR_MAS2);
2922 mas3 = mfspr(SPR_MAS3);
2923 mas7 = mfspr(SPR_MAS7);
2924
2925 idx = tlb0_tableidx(mas2, way);
2926 tlb_print_entry(idx, mas1, mas2, mas3, mas7);
2927 }
2928}
2929
2930/**************************************************************************/
2931/* TLB1 handling */
2932/**************************************************************************/
2933
2934/*
2935 * TLB1 mapping notes:
2936 *
2937 * TLB1[0] Kernel text and data.
2938 * TLB1[1-15] Additional kernel text and data mappings (if required), PCI
2939 * windows, other devices mappings.
2940 */
2941
2942/*
2943 * Write given entry to TLB1 hardware.
2944 * Use 32 bit pa, clear 4 high-order bits of RPN (mas7).
2945 */
2946static void
2947tlb1_write_entry(unsigned int idx)
2948{
2949 uint32_t mas0, mas7;
2950
2951 //debugf("tlb1_write_entry: s\n");
2952
2953 /* Clear high order RPN bits */
2954 mas7 = 0;
2955
2956 /* Select entry */
2957 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx);
2958 //debugf("tlb1_write_entry: mas0 = 0x%08x\n", mas0);
2959
2960 mtspr(SPR_MAS0, mas0);
2961 __asm __volatile("isync");
2962 mtspr(SPR_MAS1, tlb1[idx].mas1);
2963 __asm __volatile("isync");
2964 mtspr(SPR_MAS2, tlb1[idx].mas2);
2965 __asm __volatile("isync");
2966 mtspr(SPR_MAS3, tlb1[idx].mas3);
2967 __asm __volatile("isync");
2968 mtspr(SPR_MAS7, mas7);
2969 __asm __volatile("isync; tlbwe; isync; msync");
2970
2971 //debugf("tlb1_write_entry: e\n");
2972}
2973
2974/*
2975 * Return the largest uint value log such that 2^log <= num.
2976 */
2977static unsigned int
2978ilog2(unsigned int num)
2979{
2980 int lz;
2981
2982 __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num));
2983 return (31 - lz);
2984}
2985
2986/*
2987 * Convert TLB TSIZE value to mapped region size.
2988 */
2989static vm_size_t
2990tsize2size(unsigned int tsize)
2991{
2992
2993 /*
2994 * size = 4^tsize KB
2995 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10)
2996 */
2997
2998 return ((1 << (2 * tsize)) * 1024);
2999}
3000
3001/*
3002 * Convert region size (must be power of 4) to TLB TSIZE value.
3003 */
3004static unsigned int
3005size2tsize(vm_size_t size)
3006{
3007
3008 return (ilog2(size) / 2 - 5);
3009}
3010
3011/*
3012 * Register permanent kernel mapping in TLB1.
3013 *
3014 * Entries are created starting from index 0 (current free entry is
3015 * kept in tlb1_idx) and are not supposed to be invalidated.
3016 */
3017static int
3018tlb1_set_entry(vm_offset_t va, vm_offset_t pa, vm_size_t size,
3019 uint32_t flags)
3020{
3021 uint32_t ts, tid;
3022 int tsize, index;
3023
3024 index = atomic_fetchadd_int(&tlb1_idx, 1);
3025 if (index >= TLB1_ENTRIES) {
3026 printf("tlb1_set_entry: TLB1 full!\n");
3027 return (-1);
3028 }
3029
3030 /* Convert size to TSIZE */
3031 tsize = size2tsize(size);
3032
3033 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK;
3034 /* XXX TS is hard coded to 0 for now as we only use single address space */
3035 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK;
3036
3037 /*
3038 * Atomicity is preserved by the atomic increment above since nothing
3039 * is ever removed from tlb1.
3040 */
3041
3042 tlb1[index].phys = pa;
3043 tlb1[index].virt = va;
3044 tlb1[index].size = size;
3045 tlb1[index].mas1 = MAS1_VALID | MAS1_IPROT | ts | tid;
3046 tlb1[index].mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK);
3047 tlb1[index].mas2 = (va & MAS2_EPN_MASK) | flags;
3048
3049 /* Set supervisor RWX permission bits */
3050 tlb1[index].mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX;
3051
3052 tlb1_write_entry(index);
3053
3054 /*
3055 * XXX in general TLB1 updates should be propagated between CPUs,
3056 * since current design assumes to have the same TLB1 set-up on all
3057 * cores.
3058 */
3059 return (0);
3060}
3061
3062/*
3063 * Map in contiguous RAM region into the TLB1 using maximum of
3064 * KERNEL_REGION_MAX_TLB_ENTRIES entries.
3065 *
3066 * If necessary round up last entry size and return total size
3067 * used by all allocated entries.
3068 */
3069vm_size_t
3070tlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
3071{
3072 vm_size_t pgs[KERNEL_REGION_MAX_TLB_ENTRIES];
3073 vm_size_t mapped, pgsz, base, mask;
3074 int idx, nents;
3075
3076 /* Round up to the next 1M */
3077 size = (size + (1 << 20) - 1) & ~((1 << 20) - 1);
3078
3079 mapped = 0;
3080 idx = 0;
3081 base = va;
3082 pgsz = 64*1024*1024;
3083 while (mapped < size) {
3084 while (mapped < size && idx < KERNEL_REGION_MAX_TLB_ENTRIES) {
3085 while (pgsz > (size - mapped))
3086 pgsz >>= 2;
3087 pgs[idx++] = pgsz;
3088 mapped += pgsz;
3089 }
3090
3091 /* We under-map. Correct for this. */
3092 if (mapped < size) {
3093 while (pgs[idx - 1] == pgsz) {
3094 idx--;
3095 mapped -= pgsz;
3096 }
3097 /* XXX We may increase beyond out starting point. */
3098 pgsz <<= 2;
3099 pgs[idx++] = pgsz;
3100 mapped += pgsz;
3101 }
3102 }
3103
3104 nents = idx;
3105 mask = pgs[0] - 1;
3106 /* Align address to the boundary */
3107 if (va & mask) {
3108 va = (va + mask) & ~mask;
3109 pa = (pa + mask) & ~mask;
3110 }
3111
3112 for (idx = 0; idx < nents; idx++) {
3113 pgsz = pgs[idx];
3114 debugf("%u: %x -> %x, size=%x\n", idx, pa, va, pgsz);
3115 tlb1_set_entry(va, pa, pgsz, _TLB_ENTRY_MEM);
3116 pa += pgsz;
3117 va += pgsz;
3118 }
3119
3120 mapped = (va - base);
3121 printf("mapped size 0x%08x (wasted space 0x%08x)\n",
3122 mapped, mapped - size);
3123 return (mapped);
3124}
3125
3126/*
3127 * TLB1 initialization routine, to be called after the very first
3128 * assembler level setup done in locore.S.
3129 */
3130void
3131tlb1_init()
3132{
3133 uint32_t mas0, mas1, mas2, mas3;
3134 uint32_t tsz;
3135 u_int i;
3136
3137 if (bootinfo != NULL && bootinfo[0] != 1) {
3138 tlb1_idx = *((uint16_t *)(bootinfo + 8));
3139 } else
3140 tlb1_idx = 1;
3141
3142 /* The first entry/entries are used to map the kernel. */
3143 for (i = 0; i < tlb1_idx; i++) {
3144 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i);
3145 mtspr(SPR_MAS0, mas0);
3146 __asm __volatile("isync; tlbre");
3147
3148 mas1 = mfspr(SPR_MAS1);
3149 if ((mas1 & MAS1_VALID) == 0)
3150 continue;
3151
3152 mas2 = mfspr(SPR_MAS2);
3153 mas3 = mfspr(SPR_MAS3);
3154
3155 tlb1[i].mas1 = mas1;
3156 tlb1[i].mas2 = mfspr(SPR_MAS2);
3157 tlb1[i].mas3 = mas3;
3158 tlb1[i].virt = mas2 & MAS2_EPN_MASK;
3159 tlb1[i].phys = mas3 & MAS3_RPN;
3160
3161 if (i == 0)
3162 kernload = mas3 & MAS3_RPN;
3163
3164 tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
3165 tlb1[i].size = (tsz > 0) ? tsize2size(tsz) : 0;
3166 kernsize += tlb1[i].size;
3167 }
3168
3169#ifdef SMP
3170 bp_ntlb1s = tlb1_idx;
3171#endif
3172
3173 /* Purge the remaining entries */
3174 for (i = tlb1_idx; i < TLB1_ENTRIES; i++)
3175 tlb1_write_entry(i);
3176
3177 /* Setup TLB miss defaults */
3178 set_mas4_defaults();
3179}
3180
3181vm_offset_t
3182pmap_early_io_map(vm_paddr_t pa, vm_size_t size)
3183{
3184 vm_paddr_t pa_base;
3185 vm_offset_t va, sz;
3186 int i;
3187
3188 KASSERT(!pmap_bootstrapped, ("Do not use after PMAP is up!"));
3189
3190 for (i = 0; i < tlb1_idx; i++) {
3191 if (!(tlb1[i].mas1 & MAS1_VALID))
3192 continue;
3193 if (pa >= tlb1[i].phys && (pa + size) <=
3194 (tlb1[i].phys + tlb1[i].size))
3195 return (tlb1[i].virt + (pa - tlb1[i].phys));
3196 }
3197
3198 pa_base = trunc_page(pa);
3199 size = roundup(size + (pa - pa_base), PAGE_SIZE);
3200 tlb1_map_base = roundup2(tlb1_map_base, 1 << (ilog2(size) & ~1));
3201 va = tlb1_map_base + (pa - pa_base);
3202
3203 do {
3204 sz = 1 << (ilog2(size) & ~1);
3205 tlb1_set_entry(tlb1_map_base, pa_base, sz, _TLB_ENTRY_IO);
3206 size -= sz;
3207 pa_base += sz;
3208 tlb1_map_base += sz;
3209 } while (size > 0);
3210
3211#ifdef SMP
3212 bp_ntlb1s = tlb1_idx;
3213#endif
3214
3215 return (va);
3216}
3217
3218/*
3219 * Setup MAS4 defaults.
3220 * These values are loaded to MAS0-2 on a TLB miss.
3221 */
3222static void
3223set_mas4_defaults(void)
3224{
3225 uint32_t mas4;
3226
3227 /* Defaults: TLB0, PID0, TSIZED=4K */
3228 mas4 = MAS4_TLBSELD0;
3229 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK;
3230#ifdef SMP
3231 mas4 |= MAS4_MD;
3232#endif
3233 mtspr(SPR_MAS4, mas4);
3234 __asm __volatile("isync");
3235}
3236
3237/*
3238 * Print out contents of the MAS registers for each TLB1 entry
3239 */
3240void
3241tlb1_print_tlbentries(void)
3242{
3243 uint32_t mas0, mas1, mas2, mas3, mas7;
3244 int i;
3245
3246 debugf("TLB1 entries:\n");
3247 for (i = 0; i < TLB1_ENTRIES; i++) {
3248
3249 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i);
3250 mtspr(SPR_MAS0, mas0);
3251
3252 __asm __volatile("isync; tlbre");
3253
3254 mas1 = mfspr(SPR_MAS1);
3255 mas2 = mfspr(SPR_MAS2);
3256 mas3 = mfspr(SPR_MAS3);
3257 mas7 = mfspr(SPR_MAS7);
3258
3259 tlb_print_entry(i, mas1, mas2, mas3, mas7);
3260 }
3261}
3262
3263/*
3264 * Print out contents of the in-ram tlb1 table.
3265 */
3266void
3267tlb1_print_entries(void)
3268{
3269 int i;
3270
3271 debugf("tlb1[] table entries:\n");
3272 for (i = 0; i < TLB1_ENTRIES; i++)
3273 tlb_print_entry(i, tlb1[i].mas1, tlb1[i].mas2, tlb1[i].mas3, 0);
3274}
3275
3276/*
3277 * Return 0 if the physical IO range is encompassed by one of the
3278 * the TLB1 entries, otherwise return related error code.
3279 */
3280static int
3281tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va)
3282{
3283 uint32_t prot;
3284 vm_paddr_t pa_start;
3285 vm_paddr_t pa_end;
3286 unsigned int entry_tsize;
3287 vm_size_t entry_size;
3288
3289 *va = (vm_offset_t)NULL;
3290
3291 /* Skip invalid entries */
3292 if (!(tlb1[i].mas1 & MAS1_VALID))
3293 return (EINVAL);
3294
3295 /*
3296 * The entry must be cache-inhibited, guarded, and r/w
3297 * so it can function as an i/o page
3298 */
3299 prot = tlb1[i].mas2 & (MAS2_I | MAS2_G);
3300 if (prot != (MAS2_I | MAS2_G))
3301 return (EPERM);
3302
3303 prot = tlb1[i].mas3 & (MAS3_SR | MAS3_SW);
3304 if (prot != (MAS3_SR | MAS3_SW))
3305 return (EPERM);
3306
3307 /* The address should be within the entry range. */
3308 entry_tsize = (tlb1[i].mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
3309 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize"));
3310
3311 entry_size = tsize2size(entry_tsize);
3312 pa_start = tlb1[i].mas3 & MAS3_RPN;
3313 pa_end = pa_start + entry_size - 1;
3314
3315 if ((pa < pa_start) || ((pa + size) > pa_end))
3316 return (ERANGE);
3317
3318 /* Return virtual address of this mapping. */
3319 *va = (tlb1[i].mas2 & MAS2_EPN_MASK) + (pa - pa_start);
3320 return (0);
3321}
| 2462}
2463
2464/*
2465 * Return true if the pmap's pv is one of the first 16 pvs linked to from this
2466 * page. This count may be changed upwards or downwards in the future; it is
2467 * only necessary that true be returned for a small subset of pmaps for proper
2468 * page aging.
2469 */
2470static boolean_t
2471mmu_booke_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
2472{
2473 pv_entry_t pv;
2474 int loops;
2475 boolean_t rv;
2476
2477 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2478 ("mmu_booke_page_exists_quick: page %p is not managed", m));
2479 loops = 0;
2480 rv = FALSE;
2481 rw_wlock(&pvh_global_lock);
2482 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2483 if (pv->pv_pmap == pmap) {
2484 rv = TRUE;
2485 break;
2486 }
2487 if (++loops >= 16)
2488 break;
2489 }
2490 rw_wunlock(&pvh_global_lock);
2491 return (rv);
2492}
2493
2494/*
2495 * Return the number of managed mappings to the given physical page that are
2496 * wired.
2497 */
2498static int
2499mmu_booke_page_wired_mappings(mmu_t mmu, vm_page_t m)
2500{
2501 pv_entry_t pv;
2502 pte_t *pte;
2503 int count = 0;
2504
2505 if ((m->oflags & VPO_UNMANAGED) != 0)
2506 return (count);
2507 rw_wlock(&pvh_global_lock);
2508 TAILQ_FOREACH(pv, &m->md.pv_list, pv_link) {
2509 PMAP_LOCK(pv->pv_pmap);
2510 if ((pte = pte_find(mmu, pv->pv_pmap, pv->pv_va)) != NULL)
2511 if (PTE_ISVALID(pte) && PTE_ISWIRED(pte))
2512 count++;
2513 PMAP_UNLOCK(pv->pv_pmap);
2514 }
2515 rw_wunlock(&pvh_global_lock);
2516 return (count);
2517}
2518
2519static int
2520mmu_booke_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2521{
2522 int i;
2523 vm_offset_t va;
2524
2525 /*
2526 * This currently does not work for entries that
2527 * overlap TLB1 entries.
2528 */
2529 for (i = 0; i < tlb1_idx; i ++) {
2530 if (tlb1_iomapped(i, pa, size, &va) == 0)
2531 return (0);
2532 }
2533
2534 return (EFAULT);
2535}
2536
2537vm_offset_t
2538mmu_booke_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs,
2539 vm_size_t *sz)
2540{
2541 vm_paddr_t pa, ppa;
2542 vm_offset_t va;
2543 vm_size_t gran;
2544
2545 /* Raw physical memory dumps don't have a virtual address. */
2546 if (md->md_vaddr == ~0UL) {
2547 /* We always map a 256MB page at 256M. */
2548 gran = 256 * 1024 * 1024;
2549 pa = md->md_paddr + ofs;
2550 ppa = pa & ~(gran - 1);
2551 ofs = pa - ppa;
2552 va = gran;
2553 tlb1_set_entry(va, ppa, gran, _TLB_ENTRY_IO);
2554 if (*sz > (gran - ofs))
2555 *sz = gran - ofs;
2556 return (va + ofs);
2557 }
2558
2559 /* Minidumps are based on virtual memory addresses. */
2560 va = md->md_vaddr + ofs;
2561 if (va >= kernstart + kernsize) {
2562 gran = PAGE_SIZE - (va & PAGE_MASK);
2563 if (*sz > gran)
2564 *sz = gran;
2565 }
2566 return (va);
2567}
2568
2569void
2570mmu_booke_dumpsys_unmap(mmu_t mmu, struct pmap_md *md, vm_size_t ofs,
2571 vm_offset_t va)
2572{
2573
2574 /* Raw physical memory dumps don't have a virtual address. */
2575 if (md->md_vaddr == ~0UL) {
2576 tlb1_idx--;
2577 tlb1[tlb1_idx].mas1 = 0;
2578 tlb1[tlb1_idx].mas2 = 0;
2579 tlb1[tlb1_idx].mas3 = 0;
2580 tlb1_write_entry(tlb1_idx);
2581 return;
2582 }
2583
2584 /* Minidumps are based on virtual memory addresses. */
2585 /* Nothing to do... */
2586}
2587
2588struct pmap_md *
2589mmu_booke_scan_md(mmu_t mmu, struct pmap_md *prev)
2590{
2591 static struct pmap_md md;
2592 pte_t *pte;
2593 vm_offset_t va;
2594
2595 if (dumpsys_minidump) {
2596 md.md_paddr = ~0UL; /* Minidumps use virtual addresses. */
2597 if (prev == NULL) {
2598 /* 1st: kernel .data and .bss. */
2599 md.md_index = 1;
2600 md.md_vaddr = trunc_page((uintptr_t)_etext);
2601 md.md_size = round_page((uintptr_t)_end) - md.md_vaddr;
2602 return (&md);
2603 }
2604 switch (prev->md_index) {
2605 case 1:
2606 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */
2607 md.md_index = 2;
2608 md.md_vaddr = data_start;
2609 md.md_size = data_end - data_start;
2610 break;
2611 case 2:
2612 /* 3rd: kernel VM. */
2613 va = prev->md_vaddr + prev->md_size;
2614 /* Find start of next chunk (from va). */
2615 while (va < virtual_end) {
2616 /* Don't dump the buffer cache. */
2617 if (va >= kmi.buffer_sva &&
2618 va < kmi.buffer_eva) {
2619 va = kmi.buffer_eva;
2620 continue;
2621 }
2622 pte = pte_find(mmu, kernel_pmap, va);
2623 if (pte != NULL && PTE_ISVALID(pte))
2624 break;
2625 va += PAGE_SIZE;
2626 }
2627 if (va < virtual_end) {
2628 md.md_vaddr = va;
2629 va += PAGE_SIZE;
2630 /* Find last page in chunk. */
2631 while (va < virtual_end) {
2632 /* Don't run into the buffer cache. */
2633 if (va == kmi.buffer_sva)
2634 break;
2635 pte = pte_find(mmu, kernel_pmap, va);
2636 if (pte == NULL || !PTE_ISVALID(pte))
2637 break;
2638 va += PAGE_SIZE;
2639 }
2640 md.md_size = va - md.md_vaddr;
2641 break;
2642 }
2643 md.md_index = 3;
2644 /* FALLTHROUGH */
2645 default:
2646 return (NULL);
2647 }
2648 } else { /* minidumps */
2649 mem_regions(&physmem_regions, &physmem_regions_sz,
2650 &availmem_regions, &availmem_regions_sz);
2651
2652 if (prev == NULL) {
2653 /* first physical chunk. */
2654 md.md_paddr = physmem_regions[0].mr_start;
2655 md.md_size = physmem_regions[0].mr_size;
2656 md.md_vaddr = ~0UL;
2657 md.md_index = 1;
2658 } else if (md.md_index < physmem_regions_sz) {
2659 md.md_paddr = physmem_regions[md.md_index].mr_start;
2660 md.md_size = physmem_regions[md.md_index].mr_size;
2661 md.md_vaddr = ~0UL;
2662 md.md_index++;
2663 } else {
2664 /* There's no next physical chunk. */
2665 return (NULL);
2666 }
2667 }
2668
2669 return (&md);
2670}
2671
2672/*
2673 * Map a set of physical memory pages into the kernel virtual address space.
2674 * Return a pointer to where it is mapped. This routine is intended to be used
2675 * for mapping device memory, NOT real memory.
2676 */
2677static void *
2678mmu_booke_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2679{
2680
2681 return (mmu_booke_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT));
2682}
2683
2684static void *
2685mmu_booke_mapdev_attr(mmu_t mmu, vm_paddr_t pa, vm_size_t size, vm_memattr_t ma)
2686{
2687 void *res;
2688 uintptr_t va;
2689 vm_size_t sz;
2690 int i;
2691
2692 /*
2693 * Check if this is premapped in TLB1. Note: this should probably also
2694 * check whether a sequence of TLB1 entries exist that match the
2695 * requirement, but now only checks the easy case.
2696 */
2697 if (ma == VM_MEMATTR_DEFAULT) {
2698 for (i = 0; i < tlb1_idx; i++) {
2699 if (!(tlb1[i].mas1 & MAS1_VALID))
2700 continue;
2701 if (pa >= tlb1[i].phys &&
2702 (pa + size) <= (tlb1[i].phys + tlb1[i].size))
2703 return (void *)(tlb1[i].virt +
2704 (pa - tlb1[i].phys));
2705 }
2706 }
2707
2708 size = roundup(size, PAGE_SIZE);
2709
2710 /*
2711 * We leave a hole for device direct mapping between the maximum user
2712 * address (0x8000000) and the minimum KVA address (0xc0000000). If
2713 * devices are in there, just map them 1:1. If not, map them to the
2714 * device mapping area about VM_MAX_KERNEL_ADDRESS. These mapped
2715 * addresses should be pulled from an allocator, but since we do not
2716 * ever free TLB1 entries, it is safe just to increment a counter.
2717 * Note that there isn't a lot of address space here (128 MB) and it
2718 * is not at all difficult to imagine running out, since that is a 4:1
2719 * compression from the 0xc0000000 - 0xf0000000 address space that gets
2720 * mapped there.
2721 */
2722 if (pa >= (VM_MAXUSER_ADDRESS + PAGE_SIZE) &&
2723 (pa + size - 1) < VM_MIN_KERNEL_ADDRESS)
2724 va = pa;
2725 else
2726 va = atomic_fetchadd_int(&tlb1_map_base, size);
2727 res = (void *)va;
2728
2729 do {
2730 sz = 1 << (ilog2(size) & ~1);
2731 if (bootverbose)
2732 printf("Wiring VA=%x to PA=%x (size=%x), "
2733 "using TLB1[%d]\n", va, pa, sz, tlb1_idx);
2734 tlb1_set_entry(va, pa, sz, tlb_calc_wimg(pa, ma));
2735 size -= sz;
2736 pa += sz;
2737 va += sz;
2738 } while (size > 0);
2739
2740 return (res);
2741}
2742
2743/*
2744 * 'Unmap' a range mapped by mmu_booke_mapdev().
2745 */
2746static void
2747mmu_booke_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
2748{
2749#ifdef SUPPORTS_SHRINKING_TLB1
2750 vm_offset_t base, offset;
2751
2752 /*
2753 * Unmap only if this is inside kernel virtual space.
2754 */
2755 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= VM_MAX_KERNEL_ADDRESS)) {
2756 base = trunc_page(va);
2757 offset = va & PAGE_MASK;
2758 size = roundup(offset + size, PAGE_SIZE);
2759 kva_free(base, size);
2760 }
2761#endif
2762}
2763
2764/*
2765 * mmu_booke_object_init_pt preloads the ptes for a given object into the
2766 * specified pmap. This eliminates the blast of soft faults on process startup
2767 * and immediately after an mmap.
2768 */
2769static void
2770mmu_booke_object_init_pt(mmu_t mmu, pmap_t pmap, vm_offset_t addr,
2771 vm_object_t object, vm_pindex_t pindex, vm_size_t size)
2772{
2773
2774 VM_OBJECT_ASSERT_WLOCKED(object);
2775 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
2776 ("mmu_booke_object_init_pt: non-device object"));
2777}
2778
2779/*
2780 * Perform the pmap work for mincore.
2781 */
2782static int
2783mmu_booke_mincore(mmu_t mmu, pmap_t pmap, vm_offset_t addr,
2784 vm_paddr_t *locked_pa)
2785{
2786
2787 /* XXX: this should be implemented at some point */
2788 return (0);
2789}
2790
2791/**************************************************************************/
2792/* TID handling */
2793/**************************************************************************/
2794
2795/*
2796 * Allocate a TID. If necessary, steal one from someone else.
2797 * The new TID is flushed from the TLB before returning.
2798 */
2799static tlbtid_t
2800tid_alloc(pmap_t pmap)
2801{
2802 tlbtid_t tid;
2803 int thiscpu;
2804
2805 KASSERT((pmap != kernel_pmap), ("tid_alloc: kernel pmap"));
2806
2807 CTR2(KTR_PMAP, "%s: s (pmap = %p)", __func__, pmap);
2808
2809 thiscpu = PCPU_GET(cpuid);
2810
2811 tid = PCPU_GET(tid_next);
2812 if (tid > TID_MAX)
2813 tid = TID_MIN;
2814 PCPU_SET(tid_next, tid + 1);
2815
2816 /* If we are stealing TID then clear the relevant pmap's field */
2817 if (tidbusy[thiscpu][tid] != NULL) {
2818
2819 CTR2(KTR_PMAP, "%s: warning: stealing tid %d", __func__, tid);
2820
2821 tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE;
2822
2823 /* Flush all entries from TLB0 matching this TID. */
2824 tid_flush(tid);
2825 }
2826
2827 tidbusy[thiscpu][tid] = pmap;
2828 pmap->pm_tid[thiscpu] = tid;
2829 __asm __volatile("msync; isync");
2830
2831 CTR3(KTR_PMAP, "%s: e (%02d next = %02d)", __func__, tid,
2832 PCPU_GET(tid_next));
2833
2834 return (tid);
2835}
2836
2837/**************************************************************************/
2838/* TLB0 handling */
2839/**************************************************************************/
2840
2841static void
2842tlb_print_entry(int i, uint32_t mas1, uint32_t mas2, uint32_t mas3,
2843 uint32_t mas7)
2844{
2845 int as;
2846 char desc[3];
2847 tlbtid_t tid;
2848 vm_size_t size;
2849 unsigned int tsize;
2850
2851 desc[2] = '\0';
2852 if (mas1 & MAS1_VALID)
2853 desc[0] = 'V';
2854 else
2855 desc[0] = ' ';
2856
2857 if (mas1 & MAS1_IPROT)
2858 desc[1] = 'P';
2859 else
2860 desc[1] = ' ';
2861
2862 as = (mas1 & MAS1_TS_MASK) ? 1 : 0;
2863 tid = MAS1_GETTID(mas1);
2864
2865 tsize = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
2866 size = 0;
2867 if (tsize)
2868 size = tsize2size(tsize);
2869
2870 debugf("%3d: (%s) [AS=%d] "
2871 "sz = 0x%08x tsz = %d tid = %d mas1 = 0x%08x "
2872 "mas2(va) = 0x%08x mas3(pa) = 0x%08x mas7 = 0x%08x\n",
2873 i, desc, as, size, tsize, tid, mas1, mas2, mas3, mas7);
2874}
2875
2876/* Convert TLB0 va and way number to tlb0[] table index. */
2877static inline unsigned int
2878tlb0_tableidx(vm_offset_t va, unsigned int way)
2879{
2880 unsigned int idx;
2881
2882 idx = (way * TLB0_ENTRIES_PER_WAY);
2883 idx += (va & MAS2_TLB0_ENTRY_IDX_MASK) >> MAS2_TLB0_ENTRY_IDX_SHIFT;
2884 return (idx);
2885}
2886
2887/*
2888 * Invalidate TLB0 entry.
2889 */
2890static inline void
2891tlb0_flush_entry(vm_offset_t va)
2892{
2893
2894 CTR2(KTR_PMAP, "%s: s va=0x%08x", __func__, va);
2895
2896 mtx_assert(&tlbivax_mutex, MA_OWNED);
2897
2898 __asm __volatile("tlbivax 0, %0" :: "r"(va & MAS2_EPN_MASK));
2899 __asm __volatile("isync; msync");
2900 __asm __volatile("tlbsync; msync");
2901
2902 CTR1(KTR_PMAP, "%s: e", __func__);
2903}
2904
2905/* Print out contents of the MAS registers for each TLB0 entry */
2906void
2907tlb0_print_tlbentries(void)
2908{
2909 uint32_t mas0, mas1, mas2, mas3, mas7;
2910 int entryidx, way, idx;
2911
2912 debugf("TLB0 entries:\n");
2913 for (way = 0; way < TLB0_WAYS; way ++)
2914 for (entryidx = 0; entryidx < TLB0_ENTRIES_PER_WAY; entryidx++) {
2915
2916 mas0 = MAS0_TLBSEL(0) | MAS0_ESEL(way);
2917 mtspr(SPR_MAS0, mas0);
2918 __asm __volatile("isync");
2919
2920 mas2 = entryidx << MAS2_TLB0_ENTRY_IDX_SHIFT;
2921 mtspr(SPR_MAS2, mas2);
2922
2923 __asm __volatile("isync; tlbre");
2924
2925 mas1 = mfspr(SPR_MAS1);
2926 mas2 = mfspr(SPR_MAS2);
2927 mas3 = mfspr(SPR_MAS3);
2928 mas7 = mfspr(SPR_MAS7);
2929
2930 idx = tlb0_tableidx(mas2, way);
2931 tlb_print_entry(idx, mas1, mas2, mas3, mas7);
2932 }
2933}
2934
2935/**************************************************************************/
2936/* TLB1 handling */
2937/**************************************************************************/
2938
2939/*
2940 * TLB1 mapping notes:
2941 *
2942 * TLB1[0] Kernel text and data.
2943 * TLB1[1-15] Additional kernel text and data mappings (if required), PCI
2944 * windows, other devices mappings.
2945 */
2946
2947/*
2948 * Write given entry to TLB1 hardware.
2949 * Use 32 bit pa, clear 4 high-order bits of RPN (mas7).
2950 */
2951static void
2952tlb1_write_entry(unsigned int idx)
2953{
2954 uint32_t mas0, mas7;
2955
2956 //debugf("tlb1_write_entry: s\n");
2957
2958 /* Clear high order RPN bits */
2959 mas7 = 0;
2960
2961 /* Select entry */
2962 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(idx);
2963 //debugf("tlb1_write_entry: mas0 = 0x%08x\n", mas0);
2964
2965 mtspr(SPR_MAS0, mas0);
2966 __asm __volatile("isync");
2967 mtspr(SPR_MAS1, tlb1[idx].mas1);
2968 __asm __volatile("isync");
2969 mtspr(SPR_MAS2, tlb1[idx].mas2);
2970 __asm __volatile("isync");
2971 mtspr(SPR_MAS3, tlb1[idx].mas3);
2972 __asm __volatile("isync");
2973 mtspr(SPR_MAS7, mas7);
2974 __asm __volatile("isync; tlbwe; isync; msync");
2975
2976 //debugf("tlb1_write_entry: e\n");
2977}
2978
2979/*
2980 * Return the largest uint value log such that 2^log <= num.
2981 */
2982static unsigned int
2983ilog2(unsigned int num)
2984{
2985 int lz;
2986
2987 __asm ("cntlzw %0, %1" : "=r" (lz) : "r" (num));
2988 return (31 - lz);
2989}
2990
2991/*
2992 * Convert TLB TSIZE value to mapped region size.
2993 */
2994static vm_size_t
2995tsize2size(unsigned int tsize)
2996{
2997
2998 /*
2999 * size = 4^tsize KB
3000 * size = 4^tsize * 2^10 = 2^(2 * tsize - 10)
3001 */
3002
3003 return ((1 << (2 * tsize)) * 1024);
3004}
3005
3006/*
3007 * Convert region size (must be power of 4) to TLB TSIZE value.
3008 */
3009static unsigned int
3010size2tsize(vm_size_t size)
3011{
3012
3013 return (ilog2(size) / 2 - 5);
3014}
3015
3016/*
3017 * Register permanent kernel mapping in TLB1.
3018 *
3019 * Entries are created starting from index 0 (current free entry is
3020 * kept in tlb1_idx) and are not supposed to be invalidated.
3021 */
3022static int
3023tlb1_set_entry(vm_offset_t va, vm_offset_t pa, vm_size_t size,
3024 uint32_t flags)
3025{
3026 uint32_t ts, tid;
3027 int tsize, index;
3028
3029 index = atomic_fetchadd_int(&tlb1_idx, 1);
3030 if (index >= TLB1_ENTRIES) {
3031 printf("tlb1_set_entry: TLB1 full!\n");
3032 return (-1);
3033 }
3034
3035 /* Convert size to TSIZE */
3036 tsize = size2tsize(size);
3037
3038 tid = (TID_KERNEL << MAS1_TID_SHIFT) & MAS1_TID_MASK;
3039 /* XXX TS is hard coded to 0 for now as we only use single address space */
3040 ts = (0 << MAS1_TS_SHIFT) & MAS1_TS_MASK;
3041
3042 /*
3043 * Atomicity is preserved by the atomic increment above since nothing
3044 * is ever removed from tlb1.
3045 */
3046
3047 tlb1[index].phys = pa;
3048 tlb1[index].virt = va;
3049 tlb1[index].size = size;
3050 tlb1[index].mas1 = MAS1_VALID | MAS1_IPROT | ts | tid;
3051 tlb1[index].mas1 |= ((tsize << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK);
3052 tlb1[index].mas2 = (va & MAS2_EPN_MASK) | flags;
3053
3054 /* Set supervisor RWX permission bits */
3055 tlb1[index].mas3 = (pa & MAS3_RPN) | MAS3_SR | MAS3_SW | MAS3_SX;
3056
3057 tlb1_write_entry(index);
3058
3059 /*
3060 * XXX in general TLB1 updates should be propagated between CPUs,
3061 * since current design assumes to have the same TLB1 set-up on all
3062 * cores.
3063 */
3064 return (0);
3065}
3066
3067/*
3068 * Map in contiguous RAM region into the TLB1 using maximum of
3069 * KERNEL_REGION_MAX_TLB_ENTRIES entries.
3070 *
3071 * If necessary round up last entry size and return total size
3072 * used by all allocated entries.
3073 */
3074vm_size_t
3075tlb1_mapin_region(vm_offset_t va, vm_paddr_t pa, vm_size_t size)
3076{
3077 vm_size_t pgs[KERNEL_REGION_MAX_TLB_ENTRIES];
3078 vm_size_t mapped, pgsz, base, mask;
3079 int idx, nents;
3080
3081 /* Round up to the next 1M */
3082 size = (size + (1 << 20) - 1) & ~((1 << 20) - 1);
3083
3084 mapped = 0;
3085 idx = 0;
3086 base = va;
3087 pgsz = 64*1024*1024;
3088 while (mapped < size) {
3089 while (mapped < size && idx < KERNEL_REGION_MAX_TLB_ENTRIES) {
3090 while (pgsz > (size - mapped))
3091 pgsz >>= 2;
3092 pgs[idx++] = pgsz;
3093 mapped += pgsz;
3094 }
3095
3096 /* We under-map. Correct for this. */
3097 if (mapped < size) {
3098 while (pgs[idx - 1] == pgsz) {
3099 idx--;
3100 mapped -= pgsz;
3101 }
3102 /* XXX We may increase beyond out starting point. */
3103 pgsz <<= 2;
3104 pgs[idx++] = pgsz;
3105 mapped += pgsz;
3106 }
3107 }
3108
3109 nents = idx;
3110 mask = pgs[0] - 1;
3111 /* Align address to the boundary */
3112 if (va & mask) {
3113 va = (va + mask) & ~mask;
3114 pa = (pa + mask) & ~mask;
3115 }
3116
3117 for (idx = 0; idx < nents; idx++) {
3118 pgsz = pgs[idx];
3119 debugf("%u: %x -> %x, size=%x\n", idx, pa, va, pgsz);
3120 tlb1_set_entry(va, pa, pgsz, _TLB_ENTRY_MEM);
3121 pa += pgsz;
3122 va += pgsz;
3123 }
3124
3125 mapped = (va - base);
3126 printf("mapped size 0x%08x (wasted space 0x%08x)\n",
3127 mapped, mapped - size);
3128 return (mapped);
3129}
3130
3131/*
3132 * TLB1 initialization routine, to be called after the very first
3133 * assembler level setup done in locore.S.
3134 */
3135void
3136tlb1_init()
3137{
3138 uint32_t mas0, mas1, mas2, mas3;
3139 uint32_t tsz;
3140 u_int i;
3141
3142 if (bootinfo != NULL && bootinfo[0] != 1) {
3143 tlb1_idx = *((uint16_t *)(bootinfo + 8));
3144 } else
3145 tlb1_idx = 1;
3146
3147 /* The first entry/entries are used to map the kernel. */
3148 for (i = 0; i < tlb1_idx; i++) {
3149 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i);
3150 mtspr(SPR_MAS0, mas0);
3151 __asm __volatile("isync; tlbre");
3152
3153 mas1 = mfspr(SPR_MAS1);
3154 if ((mas1 & MAS1_VALID) == 0)
3155 continue;
3156
3157 mas2 = mfspr(SPR_MAS2);
3158 mas3 = mfspr(SPR_MAS3);
3159
3160 tlb1[i].mas1 = mas1;
3161 tlb1[i].mas2 = mfspr(SPR_MAS2);
3162 tlb1[i].mas3 = mas3;
3163 tlb1[i].virt = mas2 & MAS2_EPN_MASK;
3164 tlb1[i].phys = mas3 & MAS3_RPN;
3165
3166 if (i == 0)
3167 kernload = mas3 & MAS3_RPN;
3168
3169 tsz = (mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
3170 tlb1[i].size = (tsz > 0) ? tsize2size(tsz) : 0;
3171 kernsize += tlb1[i].size;
3172 }
3173
3174#ifdef SMP
3175 bp_ntlb1s = tlb1_idx;
3176#endif
3177
3178 /* Purge the remaining entries */
3179 for (i = tlb1_idx; i < TLB1_ENTRIES; i++)
3180 tlb1_write_entry(i);
3181
3182 /* Setup TLB miss defaults */
3183 set_mas4_defaults();
3184}
3185
3186vm_offset_t
3187pmap_early_io_map(vm_paddr_t pa, vm_size_t size)
3188{
3189 vm_paddr_t pa_base;
3190 vm_offset_t va, sz;
3191 int i;
3192
3193 KASSERT(!pmap_bootstrapped, ("Do not use after PMAP is up!"));
3194
3195 for (i = 0; i < tlb1_idx; i++) {
3196 if (!(tlb1[i].mas1 & MAS1_VALID))
3197 continue;
3198 if (pa >= tlb1[i].phys && (pa + size) <=
3199 (tlb1[i].phys + tlb1[i].size))
3200 return (tlb1[i].virt + (pa - tlb1[i].phys));
3201 }
3202
3203 pa_base = trunc_page(pa);
3204 size = roundup(size + (pa - pa_base), PAGE_SIZE);
3205 tlb1_map_base = roundup2(tlb1_map_base, 1 << (ilog2(size) & ~1));
3206 va = tlb1_map_base + (pa - pa_base);
3207
3208 do {
3209 sz = 1 << (ilog2(size) & ~1);
3210 tlb1_set_entry(tlb1_map_base, pa_base, sz, _TLB_ENTRY_IO);
3211 size -= sz;
3212 pa_base += sz;
3213 tlb1_map_base += sz;
3214 } while (size > 0);
3215
3216#ifdef SMP
3217 bp_ntlb1s = tlb1_idx;
3218#endif
3219
3220 return (va);
3221}
3222
3223/*
3224 * Setup MAS4 defaults.
3225 * These values are loaded to MAS0-2 on a TLB miss.
3226 */
3227static void
3228set_mas4_defaults(void)
3229{
3230 uint32_t mas4;
3231
3232 /* Defaults: TLB0, PID0, TSIZED=4K */
3233 mas4 = MAS4_TLBSELD0;
3234 mas4 |= (TLB_SIZE_4K << MAS4_TSIZED_SHIFT) & MAS4_TSIZED_MASK;
3235#ifdef SMP
3236 mas4 |= MAS4_MD;
3237#endif
3238 mtspr(SPR_MAS4, mas4);
3239 __asm __volatile("isync");
3240}
3241
3242/*
3243 * Print out contents of the MAS registers for each TLB1 entry
3244 */
3245void
3246tlb1_print_tlbentries(void)
3247{
3248 uint32_t mas0, mas1, mas2, mas3, mas7;
3249 int i;
3250
3251 debugf("TLB1 entries:\n");
3252 for (i = 0; i < TLB1_ENTRIES; i++) {
3253
3254 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(i);
3255 mtspr(SPR_MAS0, mas0);
3256
3257 __asm __volatile("isync; tlbre");
3258
3259 mas1 = mfspr(SPR_MAS1);
3260 mas2 = mfspr(SPR_MAS2);
3261 mas3 = mfspr(SPR_MAS3);
3262 mas7 = mfspr(SPR_MAS7);
3263
3264 tlb_print_entry(i, mas1, mas2, mas3, mas7);
3265 }
3266}
3267
3268/*
3269 * Print out contents of the in-ram tlb1 table.
3270 */
3271void
3272tlb1_print_entries(void)
3273{
3274 int i;
3275
3276 debugf("tlb1[] table entries:\n");
3277 for (i = 0; i < TLB1_ENTRIES; i++)
3278 tlb_print_entry(i, tlb1[i].mas1, tlb1[i].mas2, tlb1[i].mas3, 0);
3279}
3280
3281/*
3282 * Return 0 if the physical IO range is encompassed by one of the
3283 * the TLB1 entries, otherwise return related error code.
3284 */
3285static int
3286tlb1_iomapped(int i, vm_paddr_t pa, vm_size_t size, vm_offset_t *va)
3287{
3288 uint32_t prot;
3289 vm_paddr_t pa_start;
3290 vm_paddr_t pa_end;
3291 unsigned int entry_tsize;
3292 vm_size_t entry_size;
3293
3294 *va = (vm_offset_t)NULL;
3295
3296 /* Skip invalid entries */
3297 if (!(tlb1[i].mas1 & MAS1_VALID))
3298 return (EINVAL);
3299
3300 /*
3301 * The entry must be cache-inhibited, guarded, and r/w
3302 * so it can function as an i/o page
3303 */
3304 prot = tlb1[i].mas2 & (MAS2_I | MAS2_G);
3305 if (prot != (MAS2_I | MAS2_G))
3306 return (EPERM);
3307
3308 prot = tlb1[i].mas3 & (MAS3_SR | MAS3_SW);
3309 if (prot != (MAS3_SR | MAS3_SW))
3310 return (EPERM);
3311
3312 /* The address should be within the entry range. */
3313 entry_tsize = (tlb1[i].mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
3314 KASSERT((entry_tsize), ("tlb1_iomapped: invalid entry tsize"));
3315
3316 entry_size = tsize2size(entry_tsize);
3317 pa_start = tlb1[i].mas3 & MAS3_RPN;
3318 pa_end = pa_start + entry_size - 1;
3319
3320 if ((pa < pa_start) || ((pa + size) > pa_end))
3321 return (ERANGE);
3322
3323 /* Return virtual address of this mapping. */
3324 *va = (tlb1[i].mas2 & MAS2_EPN_MASK) + (pa - pa_start);
3325 return (0);
3326}
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