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machdep.c (259235) machdep.c (262675)
1/*-
2 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
3 * Copyright (C) 1995, 1996 TooLs GmbH.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

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50 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
51 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
52 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
53 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 * $NetBSD: machdep.c,v 1.74.2.1 2000/11/01 16:13:48 tv Exp $
55 */
56
57#include <sys/cdefs.h>
1/*-
2 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
3 * Copyright (C) 1995, 1996 TooLs GmbH.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

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50 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
51 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
52 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
53 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 * $NetBSD: machdep.c,v 1.74.2.1 2000/11/01 16:13:48 tv Exp $
55 */
56
57#include <sys/cdefs.h>
58__FBSDID("$FreeBSD: stable/10/sys/powerpc/aim/machdep.c 259235 2013-12-11 22:36:20Z andreast $");
58__FBSDID("$FreeBSD: stable/10/sys/powerpc/aim/machdep.c 262675 2014-03-02 02:35:46Z jhibbits $");
59
60#include "opt_compat.h"
61#include "opt_ddb.h"
62#include "opt_kstack_pages.h"
63#include "opt_platform.h"
64
65#include <sys/param.h>
66#include <sys/proc.h>

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137#ifdef __powerpc64__
138extern int n_slbs;
139int cacheline_size = 128;
140#else
141int cacheline_size = 32;
142#endif
143int hw_direct_map = 1;
144
59
60#include "opt_compat.h"
61#include "opt_ddb.h"
62#include "opt_kstack_pages.h"
63#include "opt_platform.h"
64
65#include <sys/param.h>
66#include <sys/proc.h>

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137#ifdef __powerpc64__
138extern int n_slbs;
139int cacheline_size = 128;
140#else
141int cacheline_size = 32;
142#endif
143int hw_direct_map = 1;
144
145extern void *ap_pcpu;
146
145struct pcpu __pcpu[MAXCPU];
146
147static struct trapframe frame0;
148
149char machine[] = "powerpc";
150SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, machine, 0, "");
151
152static void cpu_startup(void *);

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232#ifndef __powerpc64__
233/* Bits for running on 64-bit systems in 32-bit mode. */
234extern void *testppc64, *testppc64size;
235extern void *restorebridge, *restorebridgesize;
236extern void *rfid_patch, *rfi_patch1, *rfi_patch2;
237extern void *trapcode64;
238#endif
239
147struct pcpu __pcpu[MAXCPU];
148
149static struct trapframe frame0;
150
151char machine[] = "powerpc";
152SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, machine, 0, "");
153
154static void cpu_startup(void *);

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234#ifndef __powerpc64__
235/* Bits for running on 64-bit systems in 32-bit mode. */
236extern void *testppc64, *testppc64size;
237extern void *restorebridge, *restorebridgesize;
238extern void *rfid_patch, *rfi_patch1, *rfi_patch2;
239extern void *trapcode64;
240#endif
241
240#ifdef SMP
241extern void *rstcode, *rstsize;
242extern void *rstcode, *rstsize;
242#endif
243extern void *trapcode, *trapsize;
244extern void *slbtrap, *slbtrapsize;
245extern void *alitrap, *alisize;
246extern void *dsitrap, *dsisize;
247extern void *decrint, *decrsize;
248extern void *extint, *extsize;
249extern void *dblow, *dbsize;
250extern void *imisstrap, *imisssize;

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488 generictrap = &trapcode;
489 }
490
491 #else /* powerpc64 */
492 cpu_features |= PPC_FEATURE_64;
493 generictrap = &trapcode;
494 #endif
495
243extern void *trapcode, *trapsize;
244extern void *slbtrap, *slbtrapsize;
245extern void *alitrap, *alisize;
246extern void *dsitrap, *dsisize;
247extern void *decrint, *decrsize;
248extern void *extint, *extsize;
249extern void *dblow, *dbsize;
250extern void *imisstrap, *imisssize;

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488 generictrap = &trapcode;
489 }
490
491 #else /* powerpc64 */
492 cpu_features |= PPC_FEATURE_64;
493 generictrap = &trapcode;
494 #endif
495
496#ifdef SMP
497 bcopy(&rstcode, (void *)(EXC_RST + trap_offset), (size_t)&rstsize);
496 bcopy(&rstcode, (void *)(EXC_RST + trap_offset), (size_t)&rstsize);
498#else
499 bcopy(generictrap, (void *)EXC_RST, (size_t)&trapsize);
500#endif
501
502#ifdef KDB
503 bcopy(&dblow, (void *)(EXC_MCHK + trap_offset), (size_t)&dbsize);
504 bcopy(&dblow, (void *)(EXC_PGM + trap_offset), (size_t)&dbsize);
505 bcopy(&dblow, (void *)(EXC_TRC + trap_offset), (size_t)&dbsize);
506 bcopy(&dblow, (void *)(EXC_BPT + trap_offset), (size_t)&dbsize);
507#else
508 bcopy(generictrap, (void *)EXC_MCHK, (size_t)&trapsize);

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783
784uint64_t
785va_to_vsid(pmap_t pm, vm_offset_t va)
786{
787 return ((pm->pm_sr[(uintptr_t)va >> ADDR_SR_SHFT]) & SR_VSID_MASK);
788}
789
790#endif
497
498#ifdef KDB
499 bcopy(&dblow, (void *)(EXC_MCHK + trap_offset), (size_t)&dbsize);
500 bcopy(&dblow, (void *)(EXC_PGM + trap_offset), (size_t)&dbsize);
501 bcopy(&dblow, (void *)(EXC_TRC + trap_offset), (size_t)&dbsize);
502 bcopy(&dblow, (void *)(EXC_BPT + trap_offset), (size_t)&dbsize);
503#else
504 bcopy(generictrap, (void *)EXC_MCHK, (size_t)&trapsize);

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779
780uint64_t
781va_to_vsid(pmap_t pm, vm_offset_t va)
782{
783 return ((pm->pm_sr[(uintptr_t)va >> ADDR_SR_SHFT]) & SR_VSID_MASK);
784}
785
786#endif
787
788/* From p3-53 of the MPC7450 RISC Microprocessor Family Reference Manual */
789void
790flush_disable_caches(void)
791{
792 register_t msr;
793 register_t msscr0;
794 register_t cache_reg;
795 volatile uint32_t *memp;
796 uint32_t temp;
797 int i;
798 int x;
799
800 msr = mfmsr();
801 powerpc_sync();
802 mtmsr(msr & ~(PSL_EE | PSL_DR));
803 msscr0 = mfspr(SPR_MSSCR0);
804 msscr0 &= ~MSSCR0_L2PFE;
805 mtspr(SPR_MSSCR0, msscr0);
806 powerpc_sync();
807 isync();
808 __asm__ __volatile__("dssall; sync");
809 powerpc_sync();
810 isync();
811 __asm__ __volatile__("dcbf 0,%0" :: "r"(0));
812 __asm__ __volatile__("dcbf 0,%0" :: "r"(0));
813 __asm__ __volatile__("dcbf 0,%0" :: "r"(0));
814
815 /* Lock the L1 Data cache. */
816 mtspr(SPR_LDSTCR, mfspr(SPR_LDSTCR) | 0xFF);
817 powerpc_sync();
818 isync();
819
820 mtspr(SPR_LDSTCR, 0);
821
822 /*
823 * Perform this in two stages: Flush the cache starting in RAM, then do it
824 * from ROM.
825 */
826 memp = (volatile uint32_t *)0x00000000;
827 for (i = 0; i < 128 * 1024; i++) {
828 temp = *memp;
829 __asm__ __volatile__("dcbf 0,%0" :: "r"(memp));
830 memp += 32/sizeof(*memp);
831 }
832
833 memp = (volatile uint32_t *)0xfff00000;
834 x = 0xfe;
835
836 for (; x != 0xff;) {
837 mtspr(SPR_LDSTCR, x);
838 for (i = 0; i < 128; i++) {
839 temp = *memp;
840 __asm__ __volatile__("dcbf 0,%0" :: "r"(memp));
841 memp += 32/sizeof(*memp);
842 }
843 x = ((x << 1) | 1) & 0xff;
844 }
845 mtspr(SPR_LDSTCR, 0);
846
847 cache_reg = mfspr(SPR_L2CR);
848 if (cache_reg & L2CR_L2E) {
849 cache_reg &= ~(L2CR_L2IO_7450 | L2CR_L2DO_7450);
850 mtspr(SPR_L2CR, cache_reg);
851 powerpc_sync();
852 mtspr(SPR_L2CR, cache_reg | L2CR_L2HWF);
853 while (mfspr(SPR_L2CR) & L2CR_L2HWF)
854 ; /* Busy wait for cache to flush */
855 powerpc_sync();
856 cache_reg &= ~L2CR_L2E;
857 mtspr(SPR_L2CR, cache_reg);
858 powerpc_sync();
859 mtspr(SPR_L2CR, cache_reg | L2CR_L2I);
860 powerpc_sync();
861 while (mfspr(SPR_L2CR) & L2CR_L2I)
862 ; /* Busy wait for L2 cache invalidate */
863 powerpc_sync();
864 }
865
866 cache_reg = mfspr(SPR_L3CR);
867 if (cache_reg & L3CR_L3E) {
868 cache_reg &= ~(L3CR_L3IO | L3CR_L3DO);
869 mtspr(SPR_L3CR, cache_reg);
870 powerpc_sync();
871 mtspr(SPR_L3CR, cache_reg | L3CR_L3HWF);
872 while (mfspr(SPR_L3CR) & L3CR_L3HWF)
873 ; /* Busy wait for cache to flush */
874 powerpc_sync();
875 cache_reg &= ~L3CR_L3E;
876 mtspr(SPR_L3CR, cache_reg);
877 powerpc_sync();
878 mtspr(SPR_L3CR, cache_reg | L3CR_L3I);
879 powerpc_sync();
880 while (mfspr(SPR_L3CR) & L3CR_L3I)
881 ; /* Busy wait for L3 cache invalidate */
882 powerpc_sync();
883 }
884
885 mtspr(SPR_HID0, mfspr(SPR_HID0) & ~HID0_DCE);
886 powerpc_sync();
887 isync();
888
889 mtmsr(msr);
890}
891
892void
893cpu_sleep()
894{
895 static u_quad_t timebase = 0;
896 static register_t sprgs[4];
897 static register_t srrs[2];
898
899 jmp_buf resetjb;
900 struct thread *fputd;
901 struct thread *vectd;
902 register_t hid0;
903 register_t msr;
904 register_t saved_msr;
905
906 ap_pcpu = pcpup;
907
908 PCPU_SET(restore, &resetjb);
909
910 saved_msr = mfmsr();
911 fputd = PCPU_GET(fputhread);
912 vectd = PCPU_GET(vecthread);
913 if (fputd != NULL)
914 save_fpu(fputd);
915 if (vectd != NULL)
916 save_vec(vectd);
917 if (setjmp(resetjb) == 0) {
918 sprgs[0] = mfspr(SPR_SPRG0);
919 sprgs[1] = mfspr(SPR_SPRG1);
920 sprgs[2] = mfspr(SPR_SPRG2);
921 sprgs[3] = mfspr(SPR_SPRG3);
922 srrs[0] = mfspr(SPR_SRR0);
923 srrs[1] = mfspr(SPR_SRR1);
924 timebase = mftb();
925 powerpc_sync();
926 flush_disable_caches();
927 hid0 = mfspr(SPR_HID0);
928 hid0 = (hid0 & ~(HID0_DOZE | HID0_NAP)) | HID0_SLEEP;
929 powerpc_sync();
930 isync();
931 msr = mfmsr() | PSL_POW;
932 mtspr(SPR_HID0, hid0);
933 powerpc_sync();
934
935 while (1)
936 mtmsr(msr);
937 }
938 mttb(timebase);
939 PCPU_SET(curthread, curthread);
940 PCPU_SET(curpcb, curthread->td_pcb);
941 pmap_activate(curthread);
942 powerpc_sync();
943 mtspr(SPR_SPRG0, sprgs[0]);
944 mtspr(SPR_SPRG1, sprgs[1]);
945 mtspr(SPR_SPRG2, sprgs[2]);
946 mtspr(SPR_SPRG3, sprgs[3]);
947 mtspr(SPR_SRR0, srrs[0]);
948 mtspr(SPR_SRR1, srrs[1]);
949 mtmsr(saved_msr);
950 if (fputd == curthread)
951 enable_fpu(curthread);
952 if (vectd == curthread)
953 enable_vec(curthread);
954 powerpc_sync();
955}