1/*-
2 * Copyright (c) 1997, 1998-2003
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
| 1/*-
2 * Copyright (c) 1997, 1998-2003
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
|
33 */
34
35/*
36 * RealTek 8129/8139 register offsets
37 */
38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */
39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */
40#define RL_IDR2 0x0002
41#define RL_IDR3 0x0003
42#define RL_IDR4 0x0004
43#define RL_IDR5 0x0005
44 /* 0006-0007 reserved */
45#define RL_MAR0 0x0008 /* Multicast hash table */
46#define RL_MAR1 0x0009
47#define RL_MAR2 0x000A
48#define RL_MAR3 0x000B
49#define RL_MAR4 0x000C
50#define RL_MAR5 0x000D
51#define RL_MAR6 0x000E
52#define RL_MAR7 0x000F
53
54#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */
55#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */
56#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */
57#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */
58
59#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */
60#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */
61#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */
62#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */
63
64#define RL_RXADDR 0x0030 /* RX ring start address */
65#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */
66#define RL_RX_EARLY_STAT 0x0036 /* RX early status */
67#define RL_COMMAND 0x0037 /* command register */
68#define RL_CURRXADDR 0x0038 /* current address of packet read */
69#define RL_CURRXBUF 0x003A /* current RX buffer address */
70#define RL_IMR 0x003C /* interrupt mask register */
71#define RL_ISR 0x003E /* interrupt status register */
72#define RL_TXCFG 0x0040 /* transmit config */
73#define RL_RXCFG 0x0044 /* receive config */
74#define RL_TIMERCNT 0x0048 /* timer count register */
75#define RL_MISSEDPKT 0x004C /* missed packet counter */
76#define RL_EECMD 0x0050 /* EEPROM command register */
77#define RL_CFG0 0x0051 /* config register #0 */
78#define RL_CFG1 0x0052 /* config register #1 */
79#define RL_CFG2 0x0053 /* config register #2 */
80#define RL_CFG3 0x0054 /* config register #3 */
81#define RL_CFG4 0x0055 /* config register #4 */
82#define RL_CFG5 0x0056 /* config register #5 */
83 /* 0057 reserved */
84#define RL_MEDIASTAT 0x0058 /* media status register (8139) */
85 /* 0059-005A reserved */
86#define RL_MII 0x005A /* 8129 chip only */
87#define RL_HALTCLK 0x005B
88#define RL_MULTIINTR 0x005C /* multiple interrupt */
89#define RL_PCIREV 0x005E /* PCI revision value */
90 /* 005F reserved */
91#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */
92
93/* Direct PHY access registers only available on 8139 */
94#define RL_BMCR 0x0062 /* PHY basic mode control */
95#define RL_BMSR 0x0064 /* PHY basic mode status */
96#define RL_ANAR 0x0066 /* PHY autoneg advert */
97#define RL_LPAR 0x0068 /* PHY link partner ability */
98#define RL_ANER 0x006A /* PHY autoneg expansion */
99
100#define RL_DISCCNT 0x006C /* disconnect counter */
101#define RL_FALSECAR 0x006E /* false carrier counter */
102#define RL_NWAYTST 0x0070 /* NWAY test register */
103#define RL_RX_ER 0x0072 /* RX_ER counter */
104#define RL_CSCFG 0x0074 /* CS configuration register */
105
106/*
107 * When operating in special C+ mode, some of the registers in an
108 * 8139C+ chip have different definitions. These are also used for
109 * the 8169 gigE chip.
110 */
111#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */
112#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */
113#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */
114#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */
115#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */
116#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */
117#define RL_CFG2 0x0053
118#define RL_TIMERINT 0x0054 /* interrupt on timer expire */
119#define RL_TXSTART 0x00D9 /* 8 bits */
120#define RL_CPLUS_CMD 0x00E0 /* 16 bits */
121#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */
122#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */
123#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */
124
125/*
126 * Registers specific to the 8169 gigE chip
127 */
128#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */
129#define RL_PHYAR 0x0060
130#define RL_TBICSR 0x0064
131#define RL_TBI_ANAR 0x0068
132#define RL_TBI_LPAR 0x006A
133#define RL_GMEDIASTAT 0x006C /* 8 bits */
134#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */
135#define RL_GTXSTART 0x0038 /* 8 bits */
136
137/*
138 * TX config register bits
139 */
140#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */
141#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */
142#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */
143#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */
144#define RL_TXCFG_IFG2 0x00080000 /* 8169 only */
145#define RL_TXCFG_IFG 0x03000000 /* interframe gap */
146#define RL_TXCFG_HWREV 0x7CC00000
147
148#define RL_LOOPTEST_OFF 0x00000000
149#define RL_LOOPTEST_ON 0x00020000
150#define RL_LOOPTEST_ON_CPLUS 0x00060000
151
152/* Known revision codes. */
153
154#define RL_HWREV_8169 0x00000000
155#define RL_HWREV_8110S 0x00800000
156#define RL_HWREV_8169S 0x04000000
157#define RL_HWREV_8169_8110SB 0x10000000
158#define RL_HWREV_8169_8110SC 0x18000000
159#define RL_HWREV_8168_SPIN1 0x30000000
160#define RL_HWREV_8100E 0x30800000
161#define RL_HWREV_8101E 0x34000000
162#define RL_HWREV_8168_SPIN2 0x38000000
163#define RL_HWREV_8168_SPIN3 0x38400000
164#define RL_HWREV_8139 0x60000000
165#define RL_HWREV_8139A 0x70000000
166#define RL_HWREV_8139AG 0x70800000
167#define RL_HWREV_8139B 0x78000000
168#define RL_HWREV_8130 0x7C000000
169#define RL_HWREV_8139C 0x74000000
170#define RL_HWREV_8139D 0x74400000
171#define RL_HWREV_8139CPLUS 0x74800000
172#define RL_HWREV_8101 0x74c00000
173#define RL_HWREV_8100 0x78800000
174
175#define RL_TXDMA_16BYTES 0x00000000
176#define RL_TXDMA_32BYTES 0x00000100
177#define RL_TXDMA_64BYTES 0x00000200
178#define RL_TXDMA_128BYTES 0x00000300
179#define RL_TXDMA_256BYTES 0x00000400
180#define RL_TXDMA_512BYTES 0x00000500
181#define RL_TXDMA_1024BYTES 0x00000600
182#define RL_TXDMA_2048BYTES 0x00000700
183
184/*
185 * Transmit descriptor status register bits.
186 */
187#define RL_TXSTAT_LENMASK 0x00001FFF
188#define RL_TXSTAT_OWN 0x00002000
189#define RL_TXSTAT_TX_UNDERRUN 0x00004000
190#define RL_TXSTAT_TX_OK 0x00008000
191#define RL_TXSTAT_EARLY_THRESH 0x003F0000
192#define RL_TXSTAT_COLLCNT 0x0F000000
193#define RL_TXSTAT_CARR_HBEAT 0x10000000
194#define RL_TXSTAT_OUTOFWIN 0x20000000
195#define RL_TXSTAT_TXABRT 0x40000000
196#define RL_TXSTAT_CARRLOSS 0x80000000
197
198/*
199 * Interrupt status register bits.
200 */
201#define RL_ISR_RX_OK 0x0001
202#define RL_ISR_RX_ERR 0x0002
203#define RL_ISR_TX_OK 0x0004
204#define RL_ISR_TX_ERR 0x0008
205#define RL_ISR_RX_OVERRUN 0x0010
206#define RL_ISR_PKT_UNDERRUN 0x0020
207#define RL_ISR_LINKCHG 0x0020 /* 8169 only */
208#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */
209#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */
210#define RL_ISR_SWI 0x0100 /* C+ only */
211#define RL_ISR_CABLE_LEN_CHGD 0x2000
212#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */
213#define RL_ISR_TIMEOUT_EXPIRED 0x4000
214#define RL_ISR_SYSTEM_ERR 0x8000
215
216#define RL_INTRS \
217 (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \
218 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \
219 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR)
220
221#ifdef RE_TX_MODERATION
222#define RL_INTRS_CPLUS \
223 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \
224 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \
225 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED)
226#else
227#define RL_INTRS_CPLUS \
228 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|RL_ISR_TX_OK| \
229 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \
230 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED)
231#endif
232
233/*
234 * Media status register. (8139 only)
235 */
236#define RL_MEDIASTAT_RXPAUSE 0x01
237#define RL_MEDIASTAT_TXPAUSE 0x02
238#define RL_MEDIASTAT_LINK 0x04
239#define RL_MEDIASTAT_SPEED10 0x08
240#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */
241#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */
242
243/*
244 * Receive config register.
245 */
246#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */
247#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */
248#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */
249#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */
250#define RL_RXCFG_RX_RUNT 0x00000010
251#define RL_RXCFG_RX_ERRPKT 0x00000020
252#define RL_RXCFG_WRAP 0x00000080
253#define RL_RXCFG_MAXDMA 0x00000700
254#define RL_RXCFG_BUFSZ 0x00001800
255#define RL_RXCFG_FIFOTHRESH 0x0000E000
256#define RL_RXCFG_EARLYTHRESH 0x07000000
257
258#define RL_RXDMA_16BYTES 0x00000000
259#define RL_RXDMA_32BYTES 0x00000100
260#define RL_RXDMA_64BYTES 0x00000200
261#define RL_RXDMA_128BYTES 0x00000300
262#define RL_RXDMA_256BYTES 0x00000400
263#define RL_RXDMA_512BYTES 0x00000500
264#define RL_RXDMA_1024BYTES 0x00000600
265#define RL_RXDMA_UNLIMITED 0x00000700
266
267#define RL_RXBUF_8 0x00000000
268#define RL_RXBUF_16 0x00000800
269#define RL_RXBUF_32 0x00001000
270#define RL_RXBUF_64 0x00001800
271
272#define RL_RXFIFO_16BYTES 0x00000000
273#define RL_RXFIFO_32BYTES 0x00002000
274#define RL_RXFIFO_64BYTES 0x00004000
275#define RL_RXFIFO_128BYTES 0x00006000
276#define RL_RXFIFO_256BYTES 0x00008000
277#define RL_RXFIFO_512BYTES 0x0000A000
278#define RL_RXFIFO_1024BYTES 0x0000C000
279#define RL_RXFIFO_NOTHRESH 0x0000E000
280
281/*
282 * Bits in RX status header (included with RX'ed packet
283 * in ring buffer).
284 */
285#define RL_RXSTAT_RXOK 0x00000001
286#define RL_RXSTAT_ALIGNERR 0x00000002
287#define RL_RXSTAT_CRCERR 0x00000004
288#define RL_RXSTAT_GIANT 0x00000008
289#define RL_RXSTAT_RUNT 0x00000010
290#define RL_RXSTAT_BADSYM 0x00000020
291#define RL_RXSTAT_BROAD 0x00002000
292#define RL_RXSTAT_INDIV 0x00004000
293#define RL_RXSTAT_MULTI 0x00008000
294#define RL_RXSTAT_LENMASK 0xFFFF0000
295
296#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */
297/*
298 * Command register.
299 */
300#define RL_CMD_EMPTY_RXBUF 0x0001
301#define RL_CMD_TX_ENB 0x0004
302#define RL_CMD_RX_ENB 0x0008
303#define RL_CMD_RESET 0x0010
304
305/*
306 * EEPROM control register
307 */
308#define RL_EE_DATAOUT 0x01 /* Data out */
309#define RL_EE_DATAIN 0x02 /* Data in */
310#define RL_EE_CLK 0x04 /* clock */
311#define RL_EE_SEL 0x08 /* chip select */
312#define RL_EE_MODE (0x40|0x80)
313
314#define RL_EEMODE_OFF 0x00
315#define RL_EEMODE_AUTOLOAD 0x40
316#define RL_EEMODE_PROGRAM 0x80
317#define RL_EEMODE_WRITECFG (0x80|0x40)
318
319/* 9346 EEPROM commands */
320#define RL_9346_ADDR_LEN 6 /* 93C46 1K: 128x16 */
321#define RL_9356_ADDR_LEN 8 /* 93C56 2K: 256x16 */
322
323#define RL_9346_WRITE 0x5
324#define RL_9346_READ 0x6
325#define RL_9346_ERASE 0x7
326#define RL_9346_EWEN 0x4
327#define RL_9346_EWEN_ADDR 0x30
328#define RL_9456_EWDS 0x4
329#define RL_9346_EWDS_ADDR 0x00
330
331#define RL_EECMD_WRITE 0x140
332#define RL_EECMD_READ_6BIT 0x180
333#define RL_EECMD_READ_8BIT 0x600
334#define RL_EECMD_ERASE 0x1c0
335
336#define RL_EE_ID 0x00
337#define RL_EE_PCI_VID 0x01
338#define RL_EE_PCI_DID 0x02
339/* Location of station address inside EEPROM */
340#define RL_EE_EADDR 0x07
341
342/*
343 * MII register (8129 only)
344 */
345#define RL_MII_CLK 0x01
346#define RL_MII_DATAIN 0x02
347#define RL_MII_DATAOUT 0x04
348#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */
349
350/*
351 * Config 0 register
352 */
353#define RL_CFG0_ROM0 0x01
354#define RL_CFG0_ROM1 0x02
355#define RL_CFG0_ROM2 0x04
356#define RL_CFG0_PL0 0x08
357#define RL_CFG0_PL1 0x10
358#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */
359#define RL_CFG0_PCS 0x40
360#define RL_CFG0_SCR 0x80
361
362/*
363 * Config 1 register
364 */
365#define RL_CFG1_PWRDWN 0x01
366#define RL_CFG1_PME 0x01
367#define RL_CFG1_SLEEP 0x02
368#define RL_CFG1_VPDEN 0x02
369#define RL_CFG1_IOMAP 0x04
370#define RL_CFG1_MEMMAP 0x08
371#define RL_CFG1_RSVD 0x10
372#define RL_CFG1_LWACT 0x10
373#define RL_CFG1_DRVLOAD 0x20
374#define RL_CFG1_LED0 0x40
375#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */
376#define RL_CFG1_LED1 0x80
377
378/*
379 * Config 2 register
380 */
381#define RL_CFG2_PCI33MHZ 0x00
382#define RL_CFG2_PCI66MHZ 0x01
383#define RL_CFG2_PCI64BIT 0x08
384#define RL_CFG2_AUXPWR 0x10
385#define RL_CFG2_MSI 0x20
386
387/*
388 * Config 3 register
389 */
390#define RL_CFG3_GRANTSEL 0x80
391#define RL_CFG3_WOL_MAGIC 0x20
392#define RL_CFG3_WOL_LINK 0x10
393#define RL_CFG3_FAST_B2B 0x01
394
395/*
396 * Config 4 register
397 */
398#define RL_CFG4_LWPTN 0x04
399#define RL_CFG4_LWPME 0x10
400
401/*
402 * Config 5 register
403 */
404#define RL_CFG5_WOL_BCAST 0x40
405#define RL_CFG5_WOL_MCAST 0x20
406#define RL_CFG5_WOL_UCAST 0x10
407#define RL_CFG5_WOL_LANWAKE 0x02
408#define RL_CFG5_PME_STS 0x01
409
410/*
411 * 8139C+ register definitions
412 */
413
414/* RL_DUMPSTATS_LO register */
415
416#define RL_DUMPSTATS_START 0x00000008
417
418/* Transmit start register */
419
420#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */
421#define RL_TXSTART_START 0x40 /* start normal queue transmit */
422#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */
423
424/*
425 * Config 2 register, 8139C+/8169/8169S/8110S only
426 */
427#define RL_CFG2_BUSFREQ 0x07
428#define RL_CFG2_BUSWIDTH 0x08
429#define RL_CFG2_AUXPWRSTS 0x10
430
431#define RL_BUSFREQ_33MHZ 0x00
432#define RL_BUSFREQ_66MHZ 0x01
433
434#define RL_BUSWIDTH_32BITS 0x00
435#define RL_BUSWIDTH_64BITS 0x08
436
437/* C+ mode command register */
438
439#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */
440#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */
441#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */
442#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */
443#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */
444#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */
445
446/* C+ early transmit threshold */
447
448#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */
449
450/*
451 * Gigabit PHY access register (8169 only)
452 */
453
454#define RL_PHYAR_PHYDATA 0x0000FFFF
455#define RL_PHYAR_PHYREG 0x001F0000
456#define RL_PHYAR_BUSY 0x80000000
457
458/*
459 * Gigabit media status (8169 only)
460 */
461#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */
462#define RL_GMEDIASTAT_LINK 0x02 /* link up */
463#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */
464#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */
465#define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */
466#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */
467#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */
468#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */
469
470/*
471 * The RealTek doesn't use a fragment-based descriptor mechanism.
472 * Instead, there are only four register sets, each or which represents
473 * one 'descriptor.' Basically, each TX descriptor is just a contiguous
474 * packet buffer (32-bit aligned!) and we place the buffer addresses in
475 * the registers so the chip knows where they are.
476 *
477 * We can sort of kludge together the same kind of buffer management
478 * used in previous drivers, but we have to do buffer copies almost all
479 * the time, so it doesn't really buy us much.
480 *
481 * For reception, there's just one large buffer where the chip stores
482 * all received packets.
483 */
484
485#define RL_RX_BUF_SZ RL_RXBUF_64
486#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13))
487#define RL_TX_LIST_CNT 4
488#define RL_MIN_FRAMELEN 60
489#define RL_TXTHRESH(x) ((x) << 11)
490#define RL_TX_THRESH_INIT 96
491#define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH
492#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED
493#define RL_TX_MAXDMA RL_TXDMA_2048BYTES
494
495#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ)
496#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA)
497
498#define RL_ETHER_ALIGN 2
499
500/*
501 * re(4) hardware ip4csum-tx could be mangled with 28 bytes or less IP packets.
502 */
503#define RL_IP4CSUMTX_MINLEN 28
504#define RL_IP4CSUMTX_PADLEN (ETHER_HDR_LEN + RL_IP4CSUMTX_MINLEN)
505
506struct rl_chain_data {
507 uint16_t cur_rx;
508 uint8_t *rl_rx_buf;
509 uint8_t *rl_rx_buf_ptr;
510 bus_dmamap_t rl_rx_dmamap;
511
512 struct mbuf *rl_tx_chain[RL_TX_LIST_CNT];
513 bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT];
514 uint8_t last_tx;
515 uint8_t cur_tx;
516};
517
518#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT)
519#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0)
520#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0)
521#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx])
522#define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx])
523#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0)
524#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0)
525#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx])
526#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx])
527
528struct rl_type {
529 uint16_t rl_vid;
530 uint16_t rl_did;
531 int rl_basetype;
532 char *rl_name;
533};
534
535struct rl_hwrev {
536 uint32_t rl_rev;
537 int rl_type;
538 char *rl_desc;
539};
540
541struct rl_mii_frame {
542 uint8_t mii_stdelim;
543 uint8_t mii_opcode;
544 uint8_t mii_phyaddr;
545 uint8_t mii_regaddr;
546 uint8_t mii_turnaround;
547 uint16_t mii_data;
548};
549
550/*
551 * MII constants
552 */
553#define RL_MII_STARTDELIM 0x01
554#define RL_MII_READOP 0x02
555#define RL_MII_WRITEOP 0x01
556#define RL_MII_TURNAROUND 0x02
557
558#define RL_8129 1
559#define RL_8139 2
560#define RL_8139CPLUS 3
561#define RL_8169 4
562
563#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \
564 (x)->rl_type == RL_8169)
565
566/*
567 * The 8139C+ and 8160 gigE chips support descriptor-based TX
568 * and RX. In fact, they even support TCP large send. Descriptors
569 * must be allocated in contiguous blocks that are aligned on a
570 * 256-byte boundary. The rings can hold a maximum of 64 descriptors.
571 */
572
573/*
574 * RX/TX descriptor definition. When large send mode is enabled, the
575 * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and
576 * the checksum offload bits are disabled. The structure layout is
577 * the same for RX and TX descriptors
578 */
579
580struct rl_desc {
581 uint32_t rl_cmdstat;
582 uint32_t rl_vlanctl;
583 uint32_t rl_bufaddr_lo;
584 uint32_t rl_bufaddr_hi;
585};
586
587#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF
588#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */
589#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */
590#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */
591#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */
592#define RL_TDESC_CMD_MSSVAL_SHIFT 16 /* Large send MSS value shift */
593#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */
594#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */
595#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */
596#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */
597#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */
598
599#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */
600#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */
601
602/*
603 * Error bits are valid only on the last descriptor of a frame
604 * (i.e. RL_TDESC_CMD_EOF == 1)
605 */
606
607#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */
608#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */
609#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */
610#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */
611#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */
612#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */
613#define RL_TDESC_STAT_OWN 0x80000000
614
615/*
616 * RX descriptor cmd/vlan definitions
617 */
618
619#define RL_RDESC_CMD_EOR 0x40000000
620#define RL_RDESC_CMD_OWN 0x80000000
621#define RL_RDESC_CMD_BUFLEN 0x00001FFF
622
623#define RL_RDESC_STAT_OWN 0x80000000
624#define RL_RDESC_STAT_EOR 0x40000000
625#define RL_RDESC_STAT_SOF 0x20000000
626#define RL_RDESC_STAT_EOF 0x10000000
627#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */
628#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */
629#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */
630#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */
631#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */
632#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */
633#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */
634#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */
635#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */
636#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */
637#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */
638#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */
639#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */
640#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */
641#define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */
642#define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */
643#define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \
644 RL_RDESC_STAT_CRCERR)
645
646#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available
647 (rl_vlandata valid)*/
648#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */
649
650#define RL_PROTOID_NONIP 0x00000000
651#define RL_PROTOID_TCPIP 0x00010000
652#define RL_PROTOID_UDPIP 0x00020000
653#define RL_PROTOID_IP 0x00030000
654#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \
655 RL_PROTOID_TCPIP)
656#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \
657 RL_PROTOID_UDPIP)
658
659/*
660 * Statistics counter structure (8139C+ and 8169 only)
661 */
662struct rl_stats {
663 uint32_t rl_tx_pkts_lo;
664 uint32_t rl_tx_pkts_hi;
665 uint32_t rl_tx_errs_lo;
666 uint32_t rl_tx_errs_hi;
667 uint32_t rl_tx_errs;
668 uint16_t rl_missed_pkts;
669 uint16_t rl_rx_framealign_errs;
670 uint32_t rl_tx_onecoll;
671 uint32_t rl_tx_multicolls;
672 uint32_t rl_rx_ucasts_hi;
673 uint32_t rl_rx_ucasts_lo;
674 uint32_t rl_rx_bcasts_lo;
675 uint32_t rl_rx_bcasts_hi;
676 uint32_t rl_rx_mcasts;
677 uint16_t rl_tx_aborts;
678 uint16_t rl_rx_underruns;
679};
680
681/*
682 * Rx/Tx descriptor parameters (8139C+ and 8169 only)
683 *
684 * 8139C+
685 * Number of descriptors supported : up to 64
686 * Descriptor alignment : 256 bytes
687 * Tx buffer : At least 4 bytes in length.
688 * Rx buffer : At least 8 bytes in length and 8 bytes alignment required.
689 *
690 * 8169
691 * Number of descriptors supported : up to 1024
692 * Descriptor alignment : 256 bytes
693 * Tx buffer : At least 4 bytes in length.
694 * Rx buffer : At least 8 bytes in length and 8 bytes alignment required.
695 */
696#ifndef __NO_STRICT_ALIGNMENT
697#define RE_FIXUP_RX 1
698#endif
699
700#define RL_8169_TX_DESC_CNT 256
701#define RL_8169_RX_DESC_CNT 256
702#define RL_8139_TX_DESC_CNT 64
703#define RL_8139_RX_DESC_CNT 64
704#define RL_TX_DESC_CNT RL_8169_TX_DESC_CNT
705#define RL_RX_DESC_CNT RL_8169_RX_DESC_CNT
706#define RL_NTXSEGS 32
707
708#define RL_RING_ALIGN 256
709#define RL_IFQ_MAXLEN 512
710#define RL_TX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1))
711#define RL_TX_DESC_PRV(sc,x) ((x - 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1))
712#define RL_RX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_rx_desc_cnt - 1))
713#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN)
714#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask)
715#define RL_PKTSZ(x) ((x)/* >> 3*/)
716#ifdef RE_FIXUP_RX
717#define RE_ETHER_ALIGN sizeof(uint64_t)
718#define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN)
719#else
720#define RE_ETHER_ALIGN 0
721#define RE_RX_DESC_BUFLEN MCLBYTES
722#endif
723
724#define RL_MSI_MESSAGES 2
725
726#define RL_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF)
727#define RL_ADDR_HI(y) ((uint64_t) (y) >> 32)
728
729/* see comment in dev/re/if_re.c */
730#define RL_JUMBO_FRAMELEN 7440
731#define RL_JUMBO_MTU (RL_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
732#define RL_MAX_FRAMELEN \
733 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
734
735struct rl_txdesc {
736 struct mbuf *tx_m;
737 bus_dmamap_t tx_dmamap;
738};
739
740struct rl_rxdesc {
741 struct mbuf *rx_m;
742 bus_dmamap_t rx_dmamap;
743 bus_size_t rx_size;
744};
745
746struct rl_list_data {
747 struct rl_txdesc rl_tx_desc[RL_TX_DESC_CNT];
748 struct rl_rxdesc rl_rx_desc[RL_RX_DESC_CNT];
749 int rl_tx_desc_cnt;
750 int rl_rx_desc_cnt;
751 int rl_tx_prodidx;
752 int rl_rx_prodidx;
753 int rl_tx_considx;
754 int rl_tx_free;
755 bus_dma_tag_t rl_tx_mtag; /* mbuf TX mapping tag */
756 bus_dma_tag_t rl_rx_mtag; /* mbuf RX mapping tag */
757 bus_dmamap_t rl_rx_sparemap;
758 bus_dma_tag_t rl_stag; /* stats mapping tag */
759 bus_dmamap_t rl_smap; /* stats map */
760 struct rl_stats *rl_stats;
761 bus_addr_t rl_stats_addr;
762 bus_dma_tag_t rl_rx_list_tag;
763 bus_dmamap_t rl_rx_list_map;
764 struct rl_desc *rl_rx_list;
765 bus_addr_t rl_rx_list_addr;
766 bus_dma_tag_t rl_tx_list_tag;
767 bus_dmamap_t rl_tx_list_map;
768 struct rl_desc *rl_tx_list;
769 bus_addr_t rl_tx_list_addr;
770};
771
772struct rl_softc {
773 struct ifnet *rl_ifp; /* interface info */
774 bus_space_handle_t rl_bhandle; /* bus space handle */
775 bus_space_tag_t rl_btag; /* bus space tag */
776 device_t rl_dev;
777 struct resource *rl_res;
778 struct resource *rl_irq[RL_MSI_MESSAGES];
779 void *rl_intrhand[RL_MSI_MESSAGES];
780 device_t rl_miibus;
781 bus_dma_tag_t rl_parent_tag;
782 bus_dma_tag_t rl_tag;
783 uint8_t rl_type;
784 int rl_eecmd_read;
785 int rl_eewidth;
786 uint8_t rl_stats_no_timeout;
787 int rl_txthresh;
788 struct rl_chain_data rl_cdata;
789 struct rl_list_data rl_ldata;
790 struct callout rl_stat_callout;
791 int rl_watchdog_timer;
792 struct mtx rl_mtx;
793 struct mbuf *rl_head;
794 struct mbuf *rl_tail;
795 uint32_t rl_hwrev;
796 uint32_t rl_rxlenmask;
797 int rl_testmode;
798 int rl_if_flags;
799 int suspended; /* 0 = normal 1 = suspended */
800#ifdef DEVICE_POLLING
801 int rxcycles;
802#endif
803
804 struct task rl_txtask;
805 struct task rl_inttask;
806
807 int rl_txstart;
808 int rl_link;
809 int rl_msi;
810};
811
812#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx)
813#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx)
814#define RL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rl_mtx, MA_OWNED)
815
816/*
817 * register space access macros
818 */
819#define CSR_WRITE_STREAM_4(sc, reg, val) \
820 bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val)
821#define CSR_WRITE_4(sc, reg, val) \
822 bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val)
823#define CSR_WRITE_2(sc, reg, val) \
824 bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val)
825#define CSR_WRITE_1(sc, reg, val) \
826 bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val)
827
828#define CSR_READ_4(sc, reg) \
829 bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg)
830#define CSR_READ_2(sc, reg) \
831 bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg)
832#define CSR_READ_1(sc, reg) \
833 bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg)
834
835#define CSR_SETBIT_1(sc, offset, val) \
836 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val))
837
838#define CSR_CLRBIT_1(sc, offset, val) \
839 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val))
840
841#define CSR_SETBIT_2(sc, offset, val) \
842 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val))
843
844#define CSR_CLRBIT_2(sc, offset, val) \
845 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val))
846
847#define CSR_SETBIT_4(sc, offset, val) \
848 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val))
849
850#define CSR_CLRBIT_4(sc, offset, val) \
851 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val))
852
853#define RL_TIMEOUT 1000
854
855/*
856 * General constants that are fun to know.
857 *
858 * RealTek PCI vendor ID
859 */
860#define RT_VENDORID 0x10EC
861
862/*
863 * RealTek chip device IDs.
864 */
| 33 */
34
35/*
36 * RealTek 8129/8139 register offsets
37 */
38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */
39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */
40#define RL_IDR2 0x0002
41#define RL_IDR3 0x0003
42#define RL_IDR4 0x0004
43#define RL_IDR5 0x0005
44 /* 0006-0007 reserved */
45#define RL_MAR0 0x0008 /* Multicast hash table */
46#define RL_MAR1 0x0009
47#define RL_MAR2 0x000A
48#define RL_MAR3 0x000B
49#define RL_MAR4 0x000C
50#define RL_MAR5 0x000D
51#define RL_MAR6 0x000E
52#define RL_MAR7 0x000F
53
54#define RL_TXSTAT0 0x0010 /* status of TX descriptor 0 */
55#define RL_TXSTAT1 0x0014 /* status of TX descriptor 1 */
56#define RL_TXSTAT2 0x0018 /* status of TX descriptor 2 */
57#define RL_TXSTAT3 0x001C /* status of TX descriptor 3 */
58
59#define RL_TXADDR0 0x0020 /* address of TX descriptor 0 */
60#define RL_TXADDR1 0x0024 /* address of TX descriptor 1 */
61#define RL_TXADDR2 0x0028 /* address of TX descriptor 2 */
62#define RL_TXADDR3 0x002C /* address of TX descriptor 3 */
63
64#define RL_RXADDR 0x0030 /* RX ring start address */
65#define RL_RX_EARLY_BYTES 0x0034 /* RX early byte count */
66#define RL_RX_EARLY_STAT 0x0036 /* RX early status */
67#define RL_COMMAND 0x0037 /* command register */
68#define RL_CURRXADDR 0x0038 /* current address of packet read */
69#define RL_CURRXBUF 0x003A /* current RX buffer address */
70#define RL_IMR 0x003C /* interrupt mask register */
71#define RL_ISR 0x003E /* interrupt status register */
72#define RL_TXCFG 0x0040 /* transmit config */
73#define RL_RXCFG 0x0044 /* receive config */
74#define RL_TIMERCNT 0x0048 /* timer count register */
75#define RL_MISSEDPKT 0x004C /* missed packet counter */
76#define RL_EECMD 0x0050 /* EEPROM command register */
77#define RL_CFG0 0x0051 /* config register #0 */
78#define RL_CFG1 0x0052 /* config register #1 */
79#define RL_CFG2 0x0053 /* config register #2 */
80#define RL_CFG3 0x0054 /* config register #3 */
81#define RL_CFG4 0x0055 /* config register #4 */
82#define RL_CFG5 0x0056 /* config register #5 */
83 /* 0057 reserved */
84#define RL_MEDIASTAT 0x0058 /* media status register (8139) */
85 /* 0059-005A reserved */
86#define RL_MII 0x005A /* 8129 chip only */
87#define RL_HALTCLK 0x005B
88#define RL_MULTIINTR 0x005C /* multiple interrupt */
89#define RL_PCIREV 0x005E /* PCI revision value */
90 /* 005F reserved */
91#define RL_TXSTAT_ALL 0x0060 /* TX status of all descriptors */
92
93/* Direct PHY access registers only available on 8139 */
94#define RL_BMCR 0x0062 /* PHY basic mode control */
95#define RL_BMSR 0x0064 /* PHY basic mode status */
96#define RL_ANAR 0x0066 /* PHY autoneg advert */
97#define RL_LPAR 0x0068 /* PHY link partner ability */
98#define RL_ANER 0x006A /* PHY autoneg expansion */
99
100#define RL_DISCCNT 0x006C /* disconnect counter */
101#define RL_FALSECAR 0x006E /* false carrier counter */
102#define RL_NWAYTST 0x0070 /* NWAY test register */
103#define RL_RX_ER 0x0072 /* RX_ER counter */
104#define RL_CSCFG 0x0074 /* CS configuration register */
105
106/*
107 * When operating in special C+ mode, some of the registers in an
108 * 8139C+ chip have different definitions. These are also used for
109 * the 8169 gigE chip.
110 */
111#define RL_DUMPSTATS_LO 0x0010 /* counter dump command register */
112#define RL_DUMPSTATS_HI 0x0014 /* counter dump command register */
113#define RL_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */
114#define RL_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */
115#define RL_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte alignment */
116#define RL_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte alignment */
117#define RL_CFG2 0x0053
118#define RL_TIMERINT 0x0054 /* interrupt on timer expire */
119#define RL_TXSTART 0x00D9 /* 8 bits */
120#define RL_CPLUS_CMD 0x00E0 /* 16 bits */
121#define RL_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */
122#define RL_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */
123#define RL_EARLY_TX_THRESH 0x00EC /* 8 bits */
124
125/*
126 * Registers specific to the 8169 gigE chip
127 */
128#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */
129#define RL_PHYAR 0x0060
130#define RL_TBICSR 0x0064
131#define RL_TBI_ANAR 0x0068
132#define RL_TBI_LPAR 0x006A
133#define RL_GMEDIASTAT 0x006C /* 8 bits */
134#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */
135#define RL_GTXSTART 0x0038 /* 8 bits */
136
137/*
138 * TX config register bits
139 */
140#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */
141#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */
142#define RL_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */
143#define RL_TXCFG_LOOPBKTST 0x00060000 /* loopback test */
144#define RL_TXCFG_IFG2 0x00080000 /* 8169 only */
145#define RL_TXCFG_IFG 0x03000000 /* interframe gap */
146#define RL_TXCFG_HWREV 0x7CC00000
147
148#define RL_LOOPTEST_OFF 0x00000000
149#define RL_LOOPTEST_ON 0x00020000
150#define RL_LOOPTEST_ON_CPLUS 0x00060000
151
152/* Known revision codes. */
153
154#define RL_HWREV_8169 0x00000000
155#define RL_HWREV_8110S 0x00800000
156#define RL_HWREV_8169S 0x04000000
157#define RL_HWREV_8169_8110SB 0x10000000
158#define RL_HWREV_8169_8110SC 0x18000000
159#define RL_HWREV_8168_SPIN1 0x30000000
160#define RL_HWREV_8100E 0x30800000
161#define RL_HWREV_8101E 0x34000000
162#define RL_HWREV_8168_SPIN2 0x38000000
163#define RL_HWREV_8168_SPIN3 0x38400000
164#define RL_HWREV_8139 0x60000000
165#define RL_HWREV_8139A 0x70000000
166#define RL_HWREV_8139AG 0x70800000
167#define RL_HWREV_8139B 0x78000000
168#define RL_HWREV_8130 0x7C000000
169#define RL_HWREV_8139C 0x74000000
170#define RL_HWREV_8139D 0x74400000
171#define RL_HWREV_8139CPLUS 0x74800000
172#define RL_HWREV_8101 0x74c00000
173#define RL_HWREV_8100 0x78800000
174
175#define RL_TXDMA_16BYTES 0x00000000
176#define RL_TXDMA_32BYTES 0x00000100
177#define RL_TXDMA_64BYTES 0x00000200
178#define RL_TXDMA_128BYTES 0x00000300
179#define RL_TXDMA_256BYTES 0x00000400
180#define RL_TXDMA_512BYTES 0x00000500
181#define RL_TXDMA_1024BYTES 0x00000600
182#define RL_TXDMA_2048BYTES 0x00000700
183
184/*
185 * Transmit descriptor status register bits.
186 */
187#define RL_TXSTAT_LENMASK 0x00001FFF
188#define RL_TXSTAT_OWN 0x00002000
189#define RL_TXSTAT_TX_UNDERRUN 0x00004000
190#define RL_TXSTAT_TX_OK 0x00008000
191#define RL_TXSTAT_EARLY_THRESH 0x003F0000
192#define RL_TXSTAT_COLLCNT 0x0F000000
193#define RL_TXSTAT_CARR_HBEAT 0x10000000
194#define RL_TXSTAT_OUTOFWIN 0x20000000
195#define RL_TXSTAT_TXABRT 0x40000000
196#define RL_TXSTAT_CARRLOSS 0x80000000
197
198/*
199 * Interrupt status register bits.
200 */
201#define RL_ISR_RX_OK 0x0001
202#define RL_ISR_RX_ERR 0x0002
203#define RL_ISR_TX_OK 0x0004
204#define RL_ISR_TX_ERR 0x0008
205#define RL_ISR_RX_OVERRUN 0x0010
206#define RL_ISR_PKT_UNDERRUN 0x0020
207#define RL_ISR_LINKCHG 0x0020 /* 8169 only */
208#define RL_ISR_FIFO_OFLOW 0x0040 /* 8139 only */
209#define RL_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */
210#define RL_ISR_SWI 0x0100 /* C+ only */
211#define RL_ISR_CABLE_LEN_CHGD 0x2000
212#define RL_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */
213#define RL_ISR_TIMEOUT_EXPIRED 0x4000
214#define RL_ISR_SYSTEM_ERR 0x8000
215
216#define RL_INTRS \
217 (RL_ISR_TX_OK|RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \
218 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \
219 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR)
220
221#ifdef RE_TX_MODERATION
222#define RL_INTRS_CPLUS \
223 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR| \
224 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \
225 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED)
226#else
227#define RL_INTRS_CPLUS \
228 (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|RL_ISR_TX_OK| \
229 RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW| \
230 RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED)
231#endif
232
233/*
234 * Media status register. (8139 only)
235 */
236#define RL_MEDIASTAT_RXPAUSE 0x01
237#define RL_MEDIASTAT_TXPAUSE 0x02
238#define RL_MEDIASTAT_LINK 0x04
239#define RL_MEDIASTAT_SPEED10 0x08
240#define RL_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */
241#define RL_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */
242
243/*
244 * Receive config register.
245 */
246#define RL_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */
247#define RL_RXCFG_RX_INDIV 0x00000002 /* match filter */
248#define RL_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */
249#define RL_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */
250#define RL_RXCFG_RX_RUNT 0x00000010
251#define RL_RXCFG_RX_ERRPKT 0x00000020
252#define RL_RXCFG_WRAP 0x00000080
253#define RL_RXCFG_MAXDMA 0x00000700
254#define RL_RXCFG_BUFSZ 0x00001800
255#define RL_RXCFG_FIFOTHRESH 0x0000E000
256#define RL_RXCFG_EARLYTHRESH 0x07000000
257
258#define RL_RXDMA_16BYTES 0x00000000
259#define RL_RXDMA_32BYTES 0x00000100
260#define RL_RXDMA_64BYTES 0x00000200
261#define RL_RXDMA_128BYTES 0x00000300
262#define RL_RXDMA_256BYTES 0x00000400
263#define RL_RXDMA_512BYTES 0x00000500
264#define RL_RXDMA_1024BYTES 0x00000600
265#define RL_RXDMA_UNLIMITED 0x00000700
266
267#define RL_RXBUF_8 0x00000000
268#define RL_RXBUF_16 0x00000800
269#define RL_RXBUF_32 0x00001000
270#define RL_RXBUF_64 0x00001800
271
272#define RL_RXFIFO_16BYTES 0x00000000
273#define RL_RXFIFO_32BYTES 0x00002000
274#define RL_RXFIFO_64BYTES 0x00004000
275#define RL_RXFIFO_128BYTES 0x00006000
276#define RL_RXFIFO_256BYTES 0x00008000
277#define RL_RXFIFO_512BYTES 0x0000A000
278#define RL_RXFIFO_1024BYTES 0x0000C000
279#define RL_RXFIFO_NOTHRESH 0x0000E000
280
281/*
282 * Bits in RX status header (included with RX'ed packet
283 * in ring buffer).
284 */
285#define RL_RXSTAT_RXOK 0x00000001
286#define RL_RXSTAT_ALIGNERR 0x00000002
287#define RL_RXSTAT_CRCERR 0x00000004
288#define RL_RXSTAT_GIANT 0x00000008
289#define RL_RXSTAT_RUNT 0x00000010
290#define RL_RXSTAT_BADSYM 0x00000020
291#define RL_RXSTAT_BROAD 0x00002000
292#define RL_RXSTAT_INDIV 0x00004000
293#define RL_RXSTAT_MULTI 0x00008000
294#define RL_RXSTAT_LENMASK 0xFFFF0000
295
296#define RL_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */
297/*
298 * Command register.
299 */
300#define RL_CMD_EMPTY_RXBUF 0x0001
301#define RL_CMD_TX_ENB 0x0004
302#define RL_CMD_RX_ENB 0x0008
303#define RL_CMD_RESET 0x0010
304
305/*
306 * EEPROM control register
307 */
308#define RL_EE_DATAOUT 0x01 /* Data out */
309#define RL_EE_DATAIN 0x02 /* Data in */
310#define RL_EE_CLK 0x04 /* clock */
311#define RL_EE_SEL 0x08 /* chip select */
312#define RL_EE_MODE (0x40|0x80)
313
314#define RL_EEMODE_OFF 0x00
315#define RL_EEMODE_AUTOLOAD 0x40
316#define RL_EEMODE_PROGRAM 0x80
317#define RL_EEMODE_WRITECFG (0x80|0x40)
318
319/* 9346 EEPROM commands */
320#define RL_9346_ADDR_LEN 6 /* 93C46 1K: 128x16 */
321#define RL_9356_ADDR_LEN 8 /* 93C56 2K: 256x16 */
322
323#define RL_9346_WRITE 0x5
324#define RL_9346_READ 0x6
325#define RL_9346_ERASE 0x7
326#define RL_9346_EWEN 0x4
327#define RL_9346_EWEN_ADDR 0x30
328#define RL_9456_EWDS 0x4
329#define RL_9346_EWDS_ADDR 0x00
330
331#define RL_EECMD_WRITE 0x140
332#define RL_EECMD_READ_6BIT 0x180
333#define RL_EECMD_READ_8BIT 0x600
334#define RL_EECMD_ERASE 0x1c0
335
336#define RL_EE_ID 0x00
337#define RL_EE_PCI_VID 0x01
338#define RL_EE_PCI_DID 0x02
339/* Location of station address inside EEPROM */
340#define RL_EE_EADDR 0x07
341
342/*
343 * MII register (8129 only)
344 */
345#define RL_MII_CLK 0x01
346#define RL_MII_DATAIN 0x02
347#define RL_MII_DATAOUT 0x04
348#define RL_MII_DIR 0x80 /* 0 == input, 1 == output */
349
350/*
351 * Config 0 register
352 */
353#define RL_CFG0_ROM0 0x01
354#define RL_CFG0_ROM1 0x02
355#define RL_CFG0_ROM2 0x04
356#define RL_CFG0_PL0 0x08
357#define RL_CFG0_PL1 0x10
358#define RL_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */
359#define RL_CFG0_PCS 0x40
360#define RL_CFG0_SCR 0x80
361
362/*
363 * Config 1 register
364 */
365#define RL_CFG1_PWRDWN 0x01
366#define RL_CFG1_PME 0x01
367#define RL_CFG1_SLEEP 0x02
368#define RL_CFG1_VPDEN 0x02
369#define RL_CFG1_IOMAP 0x04
370#define RL_CFG1_MEMMAP 0x08
371#define RL_CFG1_RSVD 0x10
372#define RL_CFG1_LWACT 0x10
373#define RL_CFG1_DRVLOAD 0x20
374#define RL_CFG1_LED0 0x40
375#define RL_CFG1_FULLDUPLEX 0x40 /* 8129 only */
376#define RL_CFG1_LED1 0x80
377
378/*
379 * Config 2 register
380 */
381#define RL_CFG2_PCI33MHZ 0x00
382#define RL_CFG2_PCI66MHZ 0x01
383#define RL_CFG2_PCI64BIT 0x08
384#define RL_CFG2_AUXPWR 0x10
385#define RL_CFG2_MSI 0x20
386
387/*
388 * Config 3 register
389 */
390#define RL_CFG3_GRANTSEL 0x80
391#define RL_CFG3_WOL_MAGIC 0x20
392#define RL_CFG3_WOL_LINK 0x10
393#define RL_CFG3_FAST_B2B 0x01
394
395/*
396 * Config 4 register
397 */
398#define RL_CFG4_LWPTN 0x04
399#define RL_CFG4_LWPME 0x10
400
401/*
402 * Config 5 register
403 */
404#define RL_CFG5_WOL_BCAST 0x40
405#define RL_CFG5_WOL_MCAST 0x20
406#define RL_CFG5_WOL_UCAST 0x10
407#define RL_CFG5_WOL_LANWAKE 0x02
408#define RL_CFG5_PME_STS 0x01
409
410/*
411 * 8139C+ register definitions
412 */
413
414/* RL_DUMPSTATS_LO register */
415
416#define RL_DUMPSTATS_START 0x00000008
417
418/* Transmit start register */
419
420#define RL_TXSTART_SWI 0x01 /* generate TX interrupt */
421#define RL_TXSTART_START 0x40 /* start normal queue transmit */
422#define RL_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */
423
424/*
425 * Config 2 register, 8139C+/8169/8169S/8110S only
426 */
427#define RL_CFG2_BUSFREQ 0x07
428#define RL_CFG2_BUSWIDTH 0x08
429#define RL_CFG2_AUXPWRSTS 0x10
430
431#define RL_BUSFREQ_33MHZ 0x00
432#define RL_BUSFREQ_66MHZ 0x01
433
434#define RL_BUSWIDTH_32BITS 0x00
435#define RL_BUSWIDTH_64BITS 0x08
436
437/* C+ mode command register */
438
439#define RL_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */
440#define RL_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */
441#define RL_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */
442#define RL_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */
443#define RL_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */
444#define RL_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */
445
446/* C+ early transmit threshold */
447
448#define RL_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */
449
450/*
451 * Gigabit PHY access register (8169 only)
452 */
453
454#define RL_PHYAR_PHYDATA 0x0000FFFF
455#define RL_PHYAR_PHYREG 0x001F0000
456#define RL_PHYAR_BUSY 0x80000000
457
458/*
459 * Gigabit media status (8169 only)
460 */
461#define RL_GMEDIASTAT_FDX 0x01 /* full duplex */
462#define RL_GMEDIASTAT_LINK 0x02 /* link up */
463#define RL_GMEDIASTAT_10MBPS 0x04 /* 10mps link */
464#define RL_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */
465#define RL_GMEDIASTAT_1000MBPS 0x10 /* gigE link */
466#define RL_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */
467#define RL_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */
468#define RL_GMEDIASTAT_TBI 0x80 /* TBI enabled */
469
470/*
471 * The RealTek doesn't use a fragment-based descriptor mechanism.
472 * Instead, there are only four register sets, each or which represents
473 * one 'descriptor.' Basically, each TX descriptor is just a contiguous
474 * packet buffer (32-bit aligned!) and we place the buffer addresses in
475 * the registers so the chip knows where they are.
476 *
477 * We can sort of kludge together the same kind of buffer management
478 * used in previous drivers, but we have to do buffer copies almost all
479 * the time, so it doesn't really buy us much.
480 *
481 * For reception, there's just one large buffer where the chip stores
482 * all received packets.
483 */
484
485#define RL_RX_BUF_SZ RL_RXBUF_64
486#define RL_RXBUFLEN (1 << ((RL_RX_BUF_SZ >> 11) + 13))
487#define RL_TX_LIST_CNT 4
488#define RL_MIN_FRAMELEN 60
489#define RL_TXTHRESH(x) ((x) << 11)
490#define RL_TX_THRESH_INIT 96
491#define RL_RX_FIFOTHRESH RL_RXFIFO_NOTHRESH
492#define RL_RX_MAXDMA RL_RXDMA_UNLIMITED
493#define RL_TX_MAXDMA RL_TXDMA_2048BYTES
494
495#define RL_RXCFG_CONFIG (RL_RX_FIFOTHRESH|RL_RX_MAXDMA|RL_RX_BUF_SZ)
496#define RL_TXCFG_CONFIG (RL_TXCFG_IFG|RL_TX_MAXDMA)
497
498#define RL_ETHER_ALIGN 2
499
500/*
501 * re(4) hardware ip4csum-tx could be mangled with 28 bytes or less IP packets.
502 */
503#define RL_IP4CSUMTX_MINLEN 28
504#define RL_IP4CSUMTX_PADLEN (ETHER_HDR_LEN + RL_IP4CSUMTX_MINLEN)
505
506struct rl_chain_data {
507 uint16_t cur_rx;
508 uint8_t *rl_rx_buf;
509 uint8_t *rl_rx_buf_ptr;
510 bus_dmamap_t rl_rx_dmamap;
511
512 struct mbuf *rl_tx_chain[RL_TX_LIST_CNT];
513 bus_dmamap_t rl_tx_dmamap[RL_TX_LIST_CNT];
514 uint8_t last_tx;
515 uint8_t cur_tx;
516};
517
518#define RL_INC(x) (x = (x + 1) % RL_TX_LIST_CNT)
519#define RL_CUR_TXADDR(x) ((x->rl_cdata.cur_tx * 4) + RL_TXADDR0)
520#define RL_CUR_TXSTAT(x) ((x->rl_cdata.cur_tx * 4) + RL_TXSTAT0)
521#define RL_CUR_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.cur_tx])
522#define RL_CUR_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.cur_tx])
523#define RL_LAST_TXADDR(x) ((x->rl_cdata.last_tx * 4) + RL_TXADDR0)
524#define RL_LAST_TXSTAT(x) ((x->rl_cdata.last_tx * 4) + RL_TXSTAT0)
525#define RL_LAST_TXMBUF(x) (x->rl_cdata.rl_tx_chain[x->rl_cdata.last_tx])
526#define RL_LAST_DMAMAP(x) (x->rl_cdata.rl_tx_dmamap[x->rl_cdata.last_tx])
527
528struct rl_type {
529 uint16_t rl_vid;
530 uint16_t rl_did;
531 int rl_basetype;
532 char *rl_name;
533};
534
535struct rl_hwrev {
536 uint32_t rl_rev;
537 int rl_type;
538 char *rl_desc;
539};
540
541struct rl_mii_frame {
542 uint8_t mii_stdelim;
543 uint8_t mii_opcode;
544 uint8_t mii_phyaddr;
545 uint8_t mii_regaddr;
546 uint8_t mii_turnaround;
547 uint16_t mii_data;
548};
549
550/*
551 * MII constants
552 */
553#define RL_MII_STARTDELIM 0x01
554#define RL_MII_READOP 0x02
555#define RL_MII_WRITEOP 0x01
556#define RL_MII_TURNAROUND 0x02
557
558#define RL_8129 1
559#define RL_8139 2
560#define RL_8139CPLUS 3
561#define RL_8169 4
562
563#define RL_ISCPLUS(x) ((x)->rl_type == RL_8139CPLUS || \
564 (x)->rl_type == RL_8169)
565
566/*
567 * The 8139C+ and 8160 gigE chips support descriptor-based TX
568 * and RX. In fact, they even support TCP large send. Descriptors
569 * must be allocated in contiguous blocks that are aligned on a
570 * 256-byte boundary. The rings can hold a maximum of 64 descriptors.
571 */
572
573/*
574 * RX/TX descriptor definition. When large send mode is enabled, the
575 * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and
576 * the checksum offload bits are disabled. The structure layout is
577 * the same for RX and TX descriptors
578 */
579
580struct rl_desc {
581 uint32_t rl_cmdstat;
582 uint32_t rl_vlanctl;
583 uint32_t rl_bufaddr_lo;
584 uint32_t rl_bufaddr_hi;
585};
586
587#define RL_TDESC_CMD_FRAGLEN 0x0000FFFF
588#define RL_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */
589#define RL_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */
590#define RL_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */
591#define RL_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */
592#define RL_TDESC_CMD_MSSVAL_SHIFT 16 /* Large send MSS value shift */
593#define RL_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */
594#define RL_TDESC_CMD_EOF 0x10000000 /* end of frame marker */
595#define RL_TDESC_CMD_SOF 0x20000000 /* start of frame marker */
596#define RL_TDESC_CMD_EOR 0x40000000 /* end of ring marker */
597#define RL_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */
598
599#define RL_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */
600#define RL_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */
601
602/*
603 * Error bits are valid only on the last descriptor of a frame
604 * (i.e. RL_TDESC_CMD_EOF == 1)
605 */
606
607#define RL_TDESC_STAT_COLCNT 0x000F0000 /* collision count */
608#define RL_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */
609#define RL_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */
610#define RL_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */
611#define RL_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */
612#define RL_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occured */
613#define RL_TDESC_STAT_OWN 0x80000000
614
615/*
616 * RX descriptor cmd/vlan definitions
617 */
618
619#define RL_RDESC_CMD_EOR 0x40000000
620#define RL_RDESC_CMD_OWN 0x80000000
621#define RL_RDESC_CMD_BUFLEN 0x00001FFF
622
623#define RL_RDESC_STAT_OWN 0x80000000
624#define RL_RDESC_STAT_EOR 0x40000000
625#define RL_RDESC_STAT_SOF 0x20000000
626#define RL_RDESC_STAT_EOF 0x10000000
627#define RL_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */
628#define RL_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */
629#define RL_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */
630#define RL_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */
631#define RL_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */
632#define RL_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */
633#define RL_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */
634#define RL_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */
635#define RL_RDESC_STAT_RUNT 0x00080000 /* runt packet received */
636#define RL_RDESC_STAT_CRCERR 0x00040000 /* CRC error */
637#define RL_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */
638#define RL_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */
639#define RL_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */
640#define RL_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */
641#define RL_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */
642#define RL_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */
643#define RL_RDESC_STAT_ERRS (RL_RDESC_STAT_GIANT|RL_RDESC_STAT_RUNT| \
644 RL_RDESC_STAT_CRCERR)
645
646#define RL_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available
647 (rl_vlandata valid)*/
648#define RL_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */
649
650#define RL_PROTOID_NONIP 0x00000000
651#define RL_PROTOID_TCPIP 0x00010000
652#define RL_PROTOID_UDPIP 0x00020000
653#define RL_PROTOID_IP 0x00030000
654#define RL_TCPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \
655 RL_PROTOID_TCPIP)
656#define RL_UDPPKT(x) (((x) & RL_RDESC_STAT_PROTOID) == \
657 RL_PROTOID_UDPIP)
658
659/*
660 * Statistics counter structure (8139C+ and 8169 only)
661 */
662struct rl_stats {
663 uint32_t rl_tx_pkts_lo;
664 uint32_t rl_tx_pkts_hi;
665 uint32_t rl_tx_errs_lo;
666 uint32_t rl_tx_errs_hi;
667 uint32_t rl_tx_errs;
668 uint16_t rl_missed_pkts;
669 uint16_t rl_rx_framealign_errs;
670 uint32_t rl_tx_onecoll;
671 uint32_t rl_tx_multicolls;
672 uint32_t rl_rx_ucasts_hi;
673 uint32_t rl_rx_ucasts_lo;
674 uint32_t rl_rx_bcasts_lo;
675 uint32_t rl_rx_bcasts_hi;
676 uint32_t rl_rx_mcasts;
677 uint16_t rl_tx_aborts;
678 uint16_t rl_rx_underruns;
679};
680
681/*
682 * Rx/Tx descriptor parameters (8139C+ and 8169 only)
683 *
684 * 8139C+
685 * Number of descriptors supported : up to 64
686 * Descriptor alignment : 256 bytes
687 * Tx buffer : At least 4 bytes in length.
688 * Rx buffer : At least 8 bytes in length and 8 bytes alignment required.
689 *
690 * 8169
691 * Number of descriptors supported : up to 1024
692 * Descriptor alignment : 256 bytes
693 * Tx buffer : At least 4 bytes in length.
694 * Rx buffer : At least 8 bytes in length and 8 bytes alignment required.
695 */
696#ifndef __NO_STRICT_ALIGNMENT
697#define RE_FIXUP_RX 1
698#endif
699
700#define RL_8169_TX_DESC_CNT 256
701#define RL_8169_RX_DESC_CNT 256
702#define RL_8139_TX_DESC_CNT 64
703#define RL_8139_RX_DESC_CNT 64
704#define RL_TX_DESC_CNT RL_8169_TX_DESC_CNT
705#define RL_RX_DESC_CNT RL_8169_RX_DESC_CNT
706#define RL_NTXSEGS 32
707
708#define RL_RING_ALIGN 256
709#define RL_IFQ_MAXLEN 512
710#define RL_TX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1))
711#define RL_TX_DESC_PRV(sc,x) ((x - 1) & ((sc)->rl_ldata.rl_tx_desc_cnt - 1))
712#define RL_RX_DESC_NXT(sc,x) ((x + 1) & ((sc)->rl_ldata.rl_rx_desc_cnt - 1))
713#define RL_OWN(x) (le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN)
714#define RL_RXBYTES(x) (le32toh((x)->rl_cmdstat) & sc->rl_rxlenmask)
715#define RL_PKTSZ(x) ((x)/* >> 3*/)
716#ifdef RE_FIXUP_RX
717#define RE_ETHER_ALIGN sizeof(uint64_t)
718#define RE_RX_DESC_BUFLEN (MCLBYTES - RE_ETHER_ALIGN)
719#else
720#define RE_ETHER_ALIGN 0
721#define RE_RX_DESC_BUFLEN MCLBYTES
722#endif
723
724#define RL_MSI_MESSAGES 2
725
726#define RL_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF)
727#define RL_ADDR_HI(y) ((uint64_t) (y) >> 32)
728
729/* see comment in dev/re/if_re.c */
730#define RL_JUMBO_FRAMELEN 7440
731#define RL_JUMBO_MTU (RL_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
732#define RL_MAX_FRAMELEN \
733 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN)
734
735struct rl_txdesc {
736 struct mbuf *tx_m;
737 bus_dmamap_t tx_dmamap;
738};
739
740struct rl_rxdesc {
741 struct mbuf *rx_m;
742 bus_dmamap_t rx_dmamap;
743 bus_size_t rx_size;
744};
745
746struct rl_list_data {
747 struct rl_txdesc rl_tx_desc[RL_TX_DESC_CNT];
748 struct rl_rxdesc rl_rx_desc[RL_RX_DESC_CNT];
749 int rl_tx_desc_cnt;
750 int rl_rx_desc_cnt;
751 int rl_tx_prodidx;
752 int rl_rx_prodidx;
753 int rl_tx_considx;
754 int rl_tx_free;
755 bus_dma_tag_t rl_tx_mtag; /* mbuf TX mapping tag */
756 bus_dma_tag_t rl_rx_mtag; /* mbuf RX mapping tag */
757 bus_dmamap_t rl_rx_sparemap;
758 bus_dma_tag_t rl_stag; /* stats mapping tag */
759 bus_dmamap_t rl_smap; /* stats map */
760 struct rl_stats *rl_stats;
761 bus_addr_t rl_stats_addr;
762 bus_dma_tag_t rl_rx_list_tag;
763 bus_dmamap_t rl_rx_list_map;
764 struct rl_desc *rl_rx_list;
765 bus_addr_t rl_rx_list_addr;
766 bus_dma_tag_t rl_tx_list_tag;
767 bus_dmamap_t rl_tx_list_map;
768 struct rl_desc *rl_tx_list;
769 bus_addr_t rl_tx_list_addr;
770};
771
772struct rl_softc {
773 struct ifnet *rl_ifp; /* interface info */
774 bus_space_handle_t rl_bhandle; /* bus space handle */
775 bus_space_tag_t rl_btag; /* bus space tag */
776 device_t rl_dev;
777 struct resource *rl_res;
778 struct resource *rl_irq[RL_MSI_MESSAGES];
779 void *rl_intrhand[RL_MSI_MESSAGES];
780 device_t rl_miibus;
781 bus_dma_tag_t rl_parent_tag;
782 bus_dma_tag_t rl_tag;
783 uint8_t rl_type;
784 int rl_eecmd_read;
785 int rl_eewidth;
786 uint8_t rl_stats_no_timeout;
787 int rl_txthresh;
788 struct rl_chain_data rl_cdata;
789 struct rl_list_data rl_ldata;
790 struct callout rl_stat_callout;
791 int rl_watchdog_timer;
792 struct mtx rl_mtx;
793 struct mbuf *rl_head;
794 struct mbuf *rl_tail;
795 uint32_t rl_hwrev;
796 uint32_t rl_rxlenmask;
797 int rl_testmode;
798 int rl_if_flags;
799 int suspended; /* 0 = normal 1 = suspended */
800#ifdef DEVICE_POLLING
801 int rxcycles;
802#endif
803
804 struct task rl_txtask;
805 struct task rl_inttask;
806
807 int rl_txstart;
808 int rl_link;
809 int rl_msi;
810};
811
812#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx)
813#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx)
814#define RL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rl_mtx, MA_OWNED)
815
816/*
817 * register space access macros
818 */
819#define CSR_WRITE_STREAM_4(sc, reg, val) \
820 bus_space_write_stream_4(sc->rl_btag, sc->rl_bhandle, reg, val)
821#define CSR_WRITE_4(sc, reg, val) \
822 bus_space_write_4(sc->rl_btag, sc->rl_bhandle, reg, val)
823#define CSR_WRITE_2(sc, reg, val) \
824 bus_space_write_2(sc->rl_btag, sc->rl_bhandle, reg, val)
825#define CSR_WRITE_1(sc, reg, val) \
826 bus_space_write_1(sc->rl_btag, sc->rl_bhandle, reg, val)
827
828#define CSR_READ_4(sc, reg) \
829 bus_space_read_4(sc->rl_btag, sc->rl_bhandle, reg)
830#define CSR_READ_2(sc, reg) \
831 bus_space_read_2(sc->rl_btag, sc->rl_bhandle, reg)
832#define CSR_READ_1(sc, reg) \
833 bus_space_read_1(sc->rl_btag, sc->rl_bhandle, reg)
834
835#define CSR_SETBIT_1(sc, offset, val) \
836 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val))
837
838#define CSR_CLRBIT_1(sc, offset, val) \
839 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val))
840
841#define CSR_SETBIT_2(sc, offset, val) \
842 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val))
843
844#define CSR_CLRBIT_2(sc, offset, val) \
845 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val))
846
847#define CSR_SETBIT_4(sc, offset, val) \
848 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) | (val))
849
850#define CSR_CLRBIT_4(sc, offset, val) \
851 CSR_WRITE_4(sc, offset, CSR_READ_4(sc, offset) & ~(val))
852
853#define RL_TIMEOUT 1000
854
855/*
856 * General constants that are fun to know.
857 *
858 * RealTek PCI vendor ID
859 */
860#define RT_VENDORID 0x10EC
861
862/*
863 * RealTek chip device IDs.
864 */
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