| pte.h (209645) | pte.h (209805) |
|---|---|
| 1/*- 2 * Copyright (c) 2004-2010 Juli Mallett <jmallett@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * | 1/*- 2 * Copyright (c) 2004-2010 Juli Mallett <jmallett@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * |
| 26 * $FreeBSD: head/sys/mips/include/pte.h 209645 2010-07-02 12:01:46Z jchandra $ | 26 * $FreeBSD: head/sys/mips/include/pte.h 209805 2010-07-08 14:49:55Z jchandra $ |
| 27 */ 28 29#ifndef _MACHINE_PTE_H_ 30#define _MACHINE_PTE_H_ 31 | 27 */ 28 29#ifndef _MACHINE_PTE_H_ 30#define _MACHINE_PTE_H_ 31 |
| 32#ifndef _LOCORE 33/* pt_entry_t is 32 bit for now, has to be made 64 bit for n64 */ 34typedef uint32_t pt_entry_t; 35typedef pt_entry_t *pd_entry_t; 36#endif 37 |
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| 32/* 33 * TLB and PTE management. Most things operate within the context of 34 * EntryLo0,1, and begin with TLBLO_. Things which work with EntryHi 35 * start with TLBHI_. PTE bits begin with PTE_. 36 * 37 * Note that we use the same size VM and TLB pages. 38 */ 39#define TLB_PAGE_SHIFT (PAGE_SHIFT) --- 20 unchanged lines hidden (view full) --- 60#define TLBLO_PFN_SHIFT (6) 61#define TLBLO_PFN_MASK (0x3FFFFFC0) 62#define TLBLO_PA_TO_PFN(pa) ((((pa) >> TLB_PAGE_SHIFT) << TLBLO_PFN_SHIFT) & TLBLO_PFN_MASK) 63#define TLBLO_PFN_TO_PA(pfn) ((vm_paddr_t)((pfn) >> TLBLO_PFN_SHIFT) << TLB_PAGE_SHIFT) 64#define TLBLO_PTE_TO_PFN(pte) ((pte) & TLBLO_PFN_MASK) 65#define TLBLO_PTE_TO_PA(pte) (TLBLO_PFN_TO_PA(TLBLO_PTE_TO_PFN((pte)))) 66 67/* | 38/* 39 * TLB and PTE management. Most things operate within the context of 40 * EntryLo0,1, and begin with TLBLO_. Things which work with EntryHi 41 * start with TLBHI_. PTE bits begin with PTE_. 42 * 43 * Note that we use the same size VM and TLB pages. 44 */ 45#define TLB_PAGE_SHIFT (PAGE_SHIFT) --- 20 unchanged lines hidden (view full) --- 66#define TLBLO_PFN_SHIFT (6) 67#define TLBLO_PFN_MASK (0x3FFFFFC0) 68#define TLBLO_PA_TO_PFN(pa) ((((pa) >> TLB_PAGE_SHIFT) << TLBLO_PFN_SHIFT) & TLBLO_PFN_MASK) 69#define TLBLO_PFN_TO_PA(pfn) ((vm_paddr_t)((pfn) >> TLBLO_PFN_SHIFT) << TLB_PAGE_SHIFT) 70#define TLBLO_PTE_TO_PFN(pte) ((pte) & TLBLO_PFN_MASK) 71#define TLBLO_PTE_TO_PA(pte) (TLBLO_PFN_TO_PA(TLBLO_PTE_TO_PFN((pte)))) 72 73/* |
| 74 * XXX This comment is not correct for anything more modern than R4K. 75 * |
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| 68 * VPN for EntryHi register. Upper two bits select user, supervisor, 69 * or kernel. Bits 61 to 40 copy bit 63. VPN2 is bits 39 and down to 70 * as low as 13, down to PAGE_SHIFT, to index 2 TLB pages*. From bit 12 71 * to bit 8 there is a 5-bit 0 field. Low byte is ASID. 72 * | 76 * VPN for EntryHi register. Upper two bits select user, supervisor, 77 * or kernel. Bits 61 to 40 copy bit 63. VPN2 is bits 39 and down to 78 * as low as 13, down to PAGE_SHIFT, to index 2 TLB pages*. From bit 12 79 * to bit 8 there is a 5-bit 0 field. Low byte is ASID. 80 * |
| 81 * XXX This comment is not correct for FreeBSD. |
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| 73 * Note that in FreeBSD, we map 2 TLB pages is equal to 1 VM page. 74 */ 75#define TLBHI_ASID_MASK (0xff) 76#define TLBHI_PAGE_MASK (2 * PAGE_SIZE - 1) 77#define TLBHI_ENTRY(va, asid) (((va) & ~TLBHI_PAGE_MASK) | ((asid) & TLBHI_ASID_MASK)) 78 | 82 * Note that in FreeBSD, we map 2 TLB pages is equal to 1 VM page. 83 */ 84#define TLBHI_ASID_MASK (0xff) 85#define TLBHI_PAGE_MASK (2 * PAGE_SIZE - 1) 86#define TLBHI_ENTRY(va, asid) (((va) & ~TLBHI_PAGE_MASK) | ((asid) & TLBHI_ASID_MASK)) 87 |
| 79#ifndef _LOCORE 80typedef uint32_t pt_entry_t; 81typedef pt_entry_t *pd_entry_t; 82#endif 83 84#define PDESIZE sizeof(pd_entry_t) /* for assembly files */ 85#define PTESIZE sizeof(pt_entry_t) /* for assembly files */ 86 | |
| 87/* 88 * TLB flags managed in hardware: 89 * C: Cache attribute. 90 * D: Dirty bit. This means a page is writable. It is not 91 * set at first, and a write is trapped, and the dirty 92 * bit is set. See also PTE_RO. 93 * V: Valid bit. Obvious, isn't it? 94 * G: Global bit. This means that this mapping is present --- 39 unchanged lines hidden --- | 88/* 89 * TLB flags managed in hardware: 90 * C: Cache attribute. 91 * D: Dirty bit. This means a page is writable. It is not 92 * set at first, and a write is trapped, and the dirty 93 * bit is set. See also PTE_RO. 94 * V: Valid bit. Obvious, isn't it? 95 * G: Global bit. This means that this mapping is present --- 39 unchanged lines hidden --- |