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< * $FreeBSD: head/sys/mips/include/asm.h 204557 2010-03-02 07:27:30Z imp $
---
> * $FreeBSD: head/sys/mips/include/asm.h 206717 2010-04-17 01:17:31Z jmallett $
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< /*
< * Endian-independent assembly-code aliases for unaligned memory accesses.
< */
< #if BYTE_ORDER == LITTLE_ENDIAN
< #define LWLO lwl
< #define LWHI lwr
< #define SWLO swl
< #define SWHI swr
< #endif
<
< #if BYTE_ORDER == BIG_ENDIAN
< #define LWLO lwr
< #define LWHI lwl
< #define SWLO swr
< #define SWHI swl
< #endif
<
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> *
> * XXX Do we really need to disable interrupts?
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< PTR_LA s0, _C_LABEL(disableintr) ;\
< jalr s0 ;\
< nop ;\
< move a0, v0 ;\
---
> mfc0 t0, MIPS_COP_0_STATUS ;\
> and a0, t0, MIPS_SR_INT_IE ;\
> xor t0, a0, t0 ;\
> mtc0 t0, MIPS_COP_0_STATUS ;\
> COP0_SYNC ;\
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< lw s3, PC_CURPCB(s1) ;\
< lw s1, PC_CURTHREAD(s1) ;\
---
> PTR_L s3, PC_CURPCB(s1) ;\
> PTR_L s1, PC_CURTHREAD(s1) ;\
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< PTR_LA s0, _C_LABEL(restoreintr) ;\
< jalr s0 ;\
< nop ;\
---
> mfc0 t0, MIPS_COP_0_STATUS ;\
> or t0, a0, t0 ;\
> mtc0 t0, MIPS_COP_0_STATUS ;\
> COP0_SYNC ;\
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< j 44b ;\
---
> j 44b ;\
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> * Endian-independent assembly-code aliases for unaligned memory accesses.
> */
> #if _BYTE_ORDER == _LITTLE_ENDIAN
> # define LWHI lwr
> # define LWLO lwl
> # define SWHI swr
> # define SWLO swl
> # if SZREG == 4
> # define REG_LHI lwr
> # define REG_LLO lwl
> # define REG_SHI swr
> # define REG_SLO swl
> # else
> # define REG_LHI ldr
> # define REG_LLO ldl
> # define REG_SHI sdr
> # define REG_SLO sdl
> # endif
> #endif
>
> #if _BYTE_ORDER == _BIG_ENDIAN
> # define LWHI lwl
> # define LWLO lwr
> # define SWHI swl
> # define SWLO swr
> # if SZREG == 4
> # define REG_LHI lwl
> # define REG_LLO lwr
> # define REG_SHI swl
> # define REG_SLO swr
> # else
> # define REG_LHI ldl
> # define REG_LLO ldr
> # define REG_SHI sdl
> # define REG_SLO sdr
> # endif
> #endif
>
> /*
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> #define PTR_LI li
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> #define PTR_LI dli
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< lw reg, _C_LABEL(pcpup);
---
> PTR_L reg, _C_LABEL(pcpup);