| octeon_pcmap_regs.h (204778) | octeon_pcmap_regs.h (206721) |
|---|---|
| 1/***********************license start*************** 2 * Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: --- 27 unchanged lines hidden (view full) --- 36 * 37 ***********************license end**************************************/ 38 39/* 40 * This product includes software developed by the University of 41 * California, Berkeley and its contributors." 42 */ 43 | 1/***********************license start*************** 2 * Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: --- 27 unchanged lines hidden (view full) --- 36 * 37 ***********************license end**************************************/ 38 39/* 40 * This product includes software developed by the University of 41 * California, Berkeley and its contributors." 42 */ 43 |
| 44/* $FreeBSD: head/sys/mips/cavium/octeon_pcmap_regs.h 204778 2010-03-05 22:48:34Z jmallett $ */ | 44/* $FreeBSD: head/sys/mips/cavium/octeon_pcmap_regs.h 206721 2010-04-17 03:08:13Z jmallett $ */ |
| 45 46#ifndef __OCTEON_PCMAP_REGS_H__ 47#define __OCTEON_PCMAP_REGS_H__ 48 49#include "opt_cputype.h" 50 51#define OCTEON_CACHE_LINE_SIZE 0x80 /* 128 bytes cache line size */ 52#define IS_OCTEON_ALIGNED(p) (!((u_long)(p) & 0x7f)) 53#define OCTEON_ALIGN(p) (((u_long)(p) + ((OCTEON_CACHE_LINE_SIZE) - 1)) & ~((OCTEON_CACHE_LINE_SIZE) - 1)) 54 55#ifndef LOCORE 56 | 45 46#ifndef __OCTEON_PCMAP_REGS_H__ 47#define __OCTEON_PCMAP_REGS_H__ 48 49#include "opt_cputype.h" 50 51#define OCTEON_CACHE_LINE_SIZE 0x80 /* 128 bytes cache line size */ 52#define IS_OCTEON_ALIGNED(p) (!((u_long)(p) & 0x7f)) 53#define OCTEON_ALIGN(p) (((u_long)(p) + ((OCTEON_CACHE_LINE_SIZE) - 1)) & ~((OCTEON_CACHE_LINE_SIZE) - 1)) 54 55#ifndef LOCORE 56 |
| 57/* XXXimp: From Cavium's include/pcpu.h, need to port that over */ 58#ifndef OCTEON_SMP 59#define OCTEON_CORE_ID 0 60#else 61extern struct pcpu *cpuid_to_pcpu[]; 62#define OCTEON_CORE_ID (mips_rd_coreid()) 63#endif 64 | |
| 65/* 66 * Utility inlines & macros 67 */ 68 69/* turn the variable name into a string */ 70#define OCTEON_TMP_STR(x) OCTEON_TMP_STR2(x) 71#define OCTEON_TMP_STR2(x) #x 72 --- 246 unchanged lines hidden (view full) --- 319 OCTEON_REG_OFFSET)) 320 321#define OCTEON_SCR_SCRATCH 8 322#define OCTEON_SCRATCH_0 16 323#define OCTEON_SCRATCH_1 24 324#define OCTEON_SCRATCH_2 32 325 326 | 57/* 58 * Utility inlines & macros 59 */ 60 61/* turn the variable name into a string */ 62#define OCTEON_TMP_STR(x) OCTEON_TMP_STR2(x) 63#define OCTEON_TMP_STR2(x) #x 64 --- 246 unchanged lines hidden (view full) --- 311 OCTEON_REG_OFFSET)) 312 313#define OCTEON_SCR_SCRATCH 8 314#define OCTEON_SCRATCH_0 16 315#define OCTEON_SCRATCH_1 24 316#define OCTEON_SCRATCH_2 32 317 318 |
| 327static inline uint64_t oct_mf_chord (void) 328{ 329 uint64_t dest; | |
| 330 | 319 |
| 331 __asm __volatile ( ".set push\n" 332 ".set noreorder\n" 333 ".set noat\n" 334 ".set mips64\n" 335 "dmfc2 $1, 0x400\n" 336 "move %0, $1\n" 337 ".set pop\n" 338 : "=r" (dest) : : "$1"); 339 return dest; 340} 341 342 343#define MIPS64_DMFCz(cop,regnum,cp0reg,select) \ 344 .word (0x40200000 | (cop << 25) | (regnum << 16) | (cp0reg << 11) | select) 345 346 347#define mips64_getcpz_xstr(s) mips64_getcpz_str(s) 348#define mips64_getcpz_str(s) #s 349 350#define mips64_dgetcpz(cop,cpzreg,sel,val_ptr) \ 351 ({ __asm __volatile( \ 352 ".set push\n" \ 353 ".set mips3\n" \ 354 ".set noreorder\n" \ 355 ".set noat\n" \ 356 mips64_getcpz_xstr(MIPS64_DMFCz(cop,1,cpzreg,sel)) "\n" \ 357 "nop\n" \ 358 "nop\n" \ 359 "nop\n" \ 360 "nop\n" \ 361 "sd $1,0(%0)\n" \ 362 ".set pop" \ 363 : /* no outputs */ : "r" (val_ptr) : "$1"); \ 364 }) 365 366 367#define mips64_dgetcp2(cp2reg,sel,retval_ptr) \ 368 mips64_dgetcpz(2,cp2reg,sel,retval_ptr) 369 370 371#define OCTEON_MF_CHORD(dest) mips64_dgetcp2(0x400, 0, &dest) 372 373 374 375#define OCTEON_RDHWR(result, regstr) \ 376 __asm __volatile ( \ 377 ".set mips3\n" \ 378 "rdhwr %0,$" OCTEON_TMP_STR(regstr) "\n" \ 379 ".set mips\n" \ 380 : "=d" (result)); 381 382#define CVMX_MF_CHORD(dest) OCTEON_RDHWR(dest, 30) 383 | |
| 384#define OCTEON_CHORD_HEX(dest_ptr) \ 385 ({ __asm __volatile( \ 386 ".set push\n" \ 387 ".set mips3\n" \ 388 ".set noreorder\n" \ 389 ".set noat\n" \ 390 ".word 0x7c02f03b \n"\ 391 "nop\n" \ 392 "nop\n" \ 393 "nop\n" \ 394 "nop\n" \ 395 "sd $2,0(%0)\n" \ 396 ".set pop" \ 397 : /* no outputs */ : "r" (dest_ptr) : "$2"); \ 398 }) 399 | 320#define OCTEON_CHORD_HEX(dest_ptr) \ 321 ({ __asm __volatile( \ 322 ".set push\n" \ 323 ".set mips3\n" \ 324 ".set noreorder\n" \ 325 ".set noat\n" \ 326 ".word 0x7c02f03b \n"\ 327 "nop\n" \ 328 "nop\n" \ 329 "nop\n" \ 330 "nop\n" \ 331 "sd $2,0(%0)\n" \ 332 ".set pop" \ 333 : /* no outputs */ : "r" (dest_ptr) : "$2"); \ 334 }) 335 |
| 400 401 402#define OCTEON_MF_CHORD_BAD(dest) \ 403 __asm __volatile ( \ 404 ".set mips3\n" \ 405 "dmfc2 %0, 0x400\n" \ 406 ".set mips0\n" \ 407 : "=&r" (dest) : ) 408 | |
| 409static inline uint64_t oct_scratch_read64 (uint64_t address) 410{ 411 return(*((volatile uint64_t *)(OCTEON_SCRATCH_BASE + address))); 412} 413 414static inline void oct_scratch_write64 (uint64_t address, uint64_t value) 415{ 416 *((volatile uint64_t *)(OCTEON_SCRATCH_BASE + address)) = value; 417} 418 419 | 336static inline uint64_t oct_scratch_read64 (uint64_t address) 337{ 338 return(*((volatile uint64_t *)(OCTEON_SCRATCH_BASE + address))); 339} 340 341static inline void oct_scratch_write64 (uint64_t address, uint64_t value) 342{ 343 *((volatile uint64_t *)(OCTEON_SCRATCH_BASE + address)) = value; 344} 345 346 |
| 420#define OCTEON_READ_CSR32(addr, val) \ 421 addr_ptr = addr; \ 422 oct_read_32_ptr(&addr_ptr, &val); 423 424#define OCTEON_WRITE_CSR32(addr, val, val_dummy) \ 425 addr_ptr = addr; \ 426 oct_write_32_ptr(&addr_ptr, &val); \ 427 oct_read64(OCTEON_MIO_BOOT_BIST_STAT); 428 429 430 | |
| 431/* 432 * Octeon Address Space Definitions 433 */ 434typedef enum { 435 OCTEON_MIPS_SPACE_XKSEG = 3LL, 436 OCTEON_MIPS_SPACE_XKPHYS = 2LL, 437 OCTEON_MIPS_SPACE_XSSEG = 1LL, 438 OCTEON_MIPS_SPACE_XUSEG = 0LL --- 347 unchanged lines hidden (view full) --- 786 * 787 * Direct to Board Support level. 788 */ 789extern void octeon_led_write_char(int char_position, char val); 790extern void octeon_led_write_hexchar(int char_position, char hexval); 791extern void octeon_led_write_hex(uint32_t wl); 792extern void octeon_led_write_string(const char *str); 793extern void octeon_reset(void); | 347/* 348 * Octeon Address Space Definitions 349 */ 350typedef enum { 351 OCTEON_MIPS_SPACE_XKSEG = 3LL, 352 OCTEON_MIPS_SPACE_XKPHYS = 2LL, 353 OCTEON_MIPS_SPACE_XSSEG = 1LL, 354 OCTEON_MIPS_SPACE_XUSEG = 0LL --- 347 unchanged lines hidden (view full) --- 702 * 703 * Direct to Board Support level. 704 */ 705extern void octeon_led_write_char(int char_position, char val); 706extern void octeon_led_write_hexchar(int char_position, char hexval); 707extern void octeon_led_write_hex(uint32_t wl); 708extern void octeon_led_write_string(const char *str); 709extern void octeon_reset(void); |
| 794extern void octeon_uart_write_byte(int uart_index, uint8_t ch); 795extern void octeon_uart_write_string(int uart_index, const char *str); 796extern void octeon_uart_write_hex(uint32_t wl); 797extern void octeon_uart_write_hex2(uint32_t wl, uint32_t wh); 798extern void octeon_wait_uart_flush(int uart_index, uint8_t ch); 799extern void octeon_uart_write_byte0(uint8_t ch); | |
| 800extern void octeon_led_write_char0(char val); 801extern void octeon_led_run_wheel(int *pos, int led_position); 802extern void octeon_debug_symbol(void); 803extern void mips_disable_interrupt_controls(void); 804extern uint32_t octeon_cpu_clock; 805extern uint64_t octeon_dram; 806extern uint32_t octeon_bd_ver, octeon_board_rev_major, octeon_board_rev_minor, octeon_board_type; 807extern uint8_t octeon_mac_addr[6]; --- 189 unchanged lines hidden --- | 710extern void octeon_led_write_char0(char val); 711extern void octeon_led_run_wheel(int *pos, int led_position); 712extern void octeon_debug_symbol(void); 713extern void mips_disable_interrupt_controls(void); 714extern uint32_t octeon_cpu_clock; 715extern uint64_t octeon_dram; 716extern uint32_t octeon_bd_ver, octeon_board_rev_major, octeon_board_rev_minor, octeon_board_type; 717extern uint8_t octeon_mac_addr[6]; --- 189 unchanged lines hidden --- |