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octeon_machdep.c (205048) octeon_machdep.c (206721)
1/*-
2 * Copyright (c) 2006 Wojciech A. Koszek <wkoszek@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 9 unchanged lines hidden (view full) ---

18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
1/*-
2 * Copyright (c) 2006 Wojciech A. Koszek <wkoszek@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 9 unchanged lines hidden (view full) ---

18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/mips/cavium/octeon_machdep.c 205048 2010-03-11 22:25:53Z jmallett $
26 * $FreeBSD: head/sys/mips/cavium/octeon_machdep.c 206721 2010-04-17 03:08:13Z jmallett $
27 */
28#include <sys/cdefs.h>
27 */
28#include <sys/cdefs.h>
29__FBSDID("$FreeBSD: head/sys/mips/cavium/octeon_machdep.c 205048 2010-03-11 22:25:53Z jmallett $");
29__FBSDID("$FreeBSD: head/sys/mips/cavium/octeon_machdep.c 206721 2010-04-17 03:08:13Z jmallett $");
30
31#include <sys/param.h>
32#include <sys/conf.h>
33#include <sys/kernel.h>
34#include <sys/systm.h>
35#include <sys/imgact.h>
36#include <sys/bio.h>
37#include <sys/buf.h>

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106 * Perform a board-level soft-reset.
107 */
108void
109platform_reset(void)
110{
111 oct_write64(OCTEON_CIU_SOFT_RST, 1);
112}
113
30
31#include <sys/param.h>
32#include <sys/conf.h>
33#include <sys/kernel.h>
34#include <sys/systm.h>
35#include <sys/imgact.h>
36#include <sys/bio.h>
37#include <sys/buf.h>

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106 * Perform a board-level soft-reset.
107 */
108void
109platform_reset(void)
110{
111 oct_write64(OCTEON_CIU_SOFT_RST, 1);
112}
113
114
115static inline uint32_t
116octeon_disable_interrupts(void)
117{
118 uint32_t status_bits;
119
120 status_bits = mips_rd_status();
121 mips_wr_status(status_bits & ~MIPS_SR_INT_IE);
122 return (status_bits);
123}
124
125
126static inline void
127octeon_set_interrupts(uint32_t status_bits)
128{
129 mips_wr_status(status_bits);
130}
131
132
133void
134octeon_led_write_char(int char_position, char val)
135{
136 uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8);
137
138 if (!octeon_board_real())
139 return;
140

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198{
199 if (!octeon_board_real())
200 return;
201 octeon_led_write_char(led_position, progress[*prog_count]);
202 *prog_count += 1;
203 *prog_count &= 0x7;
204}
205
114void
115octeon_led_write_char(int char_position, char val)
116{
117 uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8);
118
119 if (!octeon_board_real())
120 return;
121

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179{
180 if (!octeon_board_real())
181 return;
182 octeon_led_write_char(led_position, progress[*prog_count]);
183 *prog_count += 1;
184 *prog_count &= 0x7;
185}
186
206#define LSR_DATAREADY 0x01 /* Data ready */
207#define LSR_THRE 0x20 /* Transmit holding register empty */
208#define LSR_TEMT 0x40 /* Transmitter Empty. THR, TSR & FIFO */
209#define USR_TXFIFO_NOTFULL 0x02 /* Uart TX FIFO Not full */
210
211/*
212 * octeon_uart_write_byte
213 *
214 * Put out a single byte off of uart port.
215 */
216
217void
187void
218octeon_uart_write_byte(int uart_index, uint8_t ch)
219{
220 uint64_t val, val2;
221 if (uart_index < 0 || uart_index > 1)
222 return;
223
224 while (1) {
225 val = oct_read64(OCTEON_MIO_UART0_LSR + (uart_index * 0x400));
226 val2 = oct_read64(OCTEON_MIO_UART0_USR + (uart_index * 0x400));
227 if ((((uint8_t) val) & LSR_THRE) ||
228 (((uint8_t) val2) & USR_TXFIFO_NOTFULL)) {
229 break;
230 }
231 }
232
233 /* Write the byte */
234 oct_write8(OCTEON_MIO_UART0_THR + (uart_index * 0x400), (uint64_t) ch);
235
236 /* Force Flush the IOBus */
237 oct_read64(OCTEON_MIO_BOOT_BIST_STAT);
238}
239
240
241void
242octeon_uart_write_byte0(uint8_t ch)
243{
244 uint64_t val, val2;
245
246 while (1) {
247 val = oct_read64(OCTEON_MIO_UART0_LSR);
248 val2 = oct_read64(OCTEON_MIO_UART0_USR);
249 if ((((uint8_t) val) & LSR_THRE) ||
250 (((uint8_t) val2) & USR_TXFIFO_NOTFULL)) {
251 break;
252 }
253 }
254
255 /* Write the byte */
256 oct_write8(OCTEON_MIO_UART0_THR, (uint64_t) ch);
257
258 /* Force Flush the IOBus */
259 oct_read64(OCTEON_MIO_BOOT_BIST_STAT);
260}
261
262/*
263 * octeon_uart_write_string
264 *
265 */
266void
267octeon_uart_write_string(int uart_index, const char *str)
268{
269 /* Just loop writing one byte at a time */
270
271 while (*str) {
272 octeon_uart_write_byte(uart_index, *str);
273 if (*str == '\n') {
274 octeon_uart_write_byte(uart_index, '\r');
275 }
276 str++;
277 }
278}
279
280static char wstr[30];
281
282void
283octeon_led_write_hex(uint32_t wl)
284{
285 char nbuf[80];
286
287 sprintf(nbuf, "%X", wl);
288 octeon_led_write_string(nbuf);
289}
290
291
188octeon_led_write_hex(uint32_t wl)
189{
190 char nbuf[80];
191
192 sprintf(nbuf, "%X", wl);
193 octeon_led_write_string(nbuf);
194}
195
196
292void octeon_uart_write_hex2(uint32_t wl, uint32_t wh)
293{
294 sprintf(wstr, "0x%X-0x%X ", wh, wl);
295 octeon_uart_write_string(0, wstr);
296}
297
298void
299octeon_uart_write_hex(uint32_t wl)
300{
301 sprintf(wstr, " 0x%X ", wl);
302 octeon_uart_write_string(0, wstr);
303}
304
305/*
197/*
306 * octeon_wait_uart_flush
307 */
308void
309octeon_wait_uart_flush(int uart_index, uint8_t ch)
310{
311 uint64_t val;
312 int64_t val3;
313 uint32_t cpu_status_bits;
314
315 if (uart_index < 0 || uart_index > 1)
316 return;
317
318 cpu_status_bits = octeon_disable_interrupts();
319 /* Force Flush the IOBus */
320 oct_read64(OCTEON_MIO_BOOT_BIST_STAT);
321 for (val3 = 0xfffffffff; val3 > 0; val3--) {
322 val = oct_read64(OCTEON_MIO_UART0_LSR + (uart_index * 0x400));
323 if (((uint8_t) val) & LSR_TEMT)
324 break;
325 }
326 octeon_set_interrupts(cpu_status_bits);
327}
328
329
330/*
331 * octeon_debug_symbol
332 *
333 * Does nothing.
334 * Used to mark the point for simulator to begin tracing
335 */
336void
337octeon_debug_symbol(void)
338{

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445uint64_t
446ciu_get_en_reg_addr_new(int corenum, int intx, int enx, int ciu_ip)
447{
448 uint64_t ciu_intr_reg_addr = OCTEON_CIU_ENABLE_BASE_ADDR;
449
450 /* XXX kasserts? */
451 if (enx < CIU_EN_0 || enx > CIU_EN_1) {
452 printf("%s: invalid enx value %d, should be %d or %d\n",
198 * octeon_debug_symbol
199 *
200 * Does nothing.
201 * Used to mark the point for simulator to begin tracing
202 */
203void
204octeon_debug_symbol(void)
205{

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312uint64_t
313ciu_get_en_reg_addr_new(int corenum, int intx, int enx, int ciu_ip)
314{
315 uint64_t ciu_intr_reg_addr = OCTEON_CIU_ENABLE_BASE_ADDR;
316
317 /* XXX kasserts? */
318 if (enx < CIU_EN_0 || enx > CIU_EN_1) {
319 printf("%s: invalid enx value %d, should be %d or %d\n",
453 __FUNCTION__, enx, CIU_EN_0, CIU_EN_1);
320 __func__, enx, CIU_EN_0, CIU_EN_1);
454 return 0;
455 }
456 if (intx < CIU_INT_0 || intx > CIU_INT_1) {
457 printf("%s: invalid intx value %d, should be %d or %d\n",
321 return 0;
322 }
323 if (intx < CIU_INT_0 || intx > CIU_INT_1) {
324 printf("%s: invalid intx value %d, should be %d or %d\n",
458 __FUNCTION__, enx, CIU_INT_0, CIU_INT_1);
325 __func__, enx, CIU_INT_0, CIU_INT_1);
459 return 0;
460 }
461 if (ciu_ip < CIU_MIPS_IP2 || ciu_ip > CIU_MIPS_IP3) {
462 printf("%s: invalid ciu_ip value %d, should be %d or %d\n",
326 return 0;
327 }
328 if (ciu_ip < CIU_MIPS_IP2 || ciu_ip > CIU_MIPS_IP3) {
329 printf("%s: invalid ciu_ip value %d, should be %d or %d\n",
463 __FUNCTION__, ciu_ip, CIU_MIPS_IP2, CIU_MIPS_IP3);
330 __func__, ciu_ip, CIU_MIPS_IP2, CIU_MIPS_IP3);
464 return 0;
465 }
466
467 ciu_intr_reg_addr += (enx * 0x8);
468 ciu_intr_reg_addr += (ciu_ip * 0x10);
469 ciu_intr_reg_addr += (intx * 0x20);
470 return (ciu_intr_reg_addr);
471}

--- 40 unchanged lines hidden (view full) ---

512 core_num = octeon_get_core_num();
513 }
514
515#ifdef DEBUG_CIU_SUM
516 printf(" CIU: core %u clear sum IntX %u Enx %u Bits: 0x%llX\n",
517 core_num, intx, enx, write_bits);
518#endif
519
331 return 0;
332 }
333
334 ciu_intr_reg_addr += (enx * 0x8);
335 ciu_intr_reg_addr += (ciu_ip * 0x10);
336 ciu_intr_reg_addr += (intx * 0x20);
337 return (ciu_intr_reg_addr);
338}

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379 core_num = octeon_get_core_num();
380 }
381
382#ifdef DEBUG_CIU_SUM
383 printf(" CIU: core %u clear sum IntX %u Enx %u Bits: 0x%llX\n",
384 core_num, intx, enx, write_bits);
385#endif
386
520 cpu_status_bits = octeon_disable_interrupts();
387 cpu_status_bits = intr_disable();
521
522 ciu_intr_sum_reg_addr = ciu_get_intr_sum_reg_addr(core_num, intx, enx);
523
524#ifdef DEBUG_CIU_SUM
525 ciu_intr_sum_bits = oct_read64(ciu_intr_sum_reg_addr); /* unneeded dummy read */
526 printf(" CIU: status: 0x%X reg_addr: 0x%llX Val: 0x%llX -> 0x%llX",
527 cpu_status_bits, ciu_intr_sum_reg_addr, ciu_intr_sum_bits,
528 ciu_intr_sum_bits | write_bits);
529#endif
530
531 oct_write64(ciu_intr_sum_reg_addr, write_bits);
532 oct_read64(OCTEON_MIO_BOOT_BIST_STAT); /* Bus Barrier */
533
534#ifdef DEBUG_CIU_SUM
535 printf(" Readback: 0x%llX\n\n ", (uint64_t) oct_read64(ciu_intr_sum_reg_addr));
536#endif
537
388
389 ciu_intr_sum_reg_addr = ciu_get_intr_sum_reg_addr(core_num, intx, enx);
390
391#ifdef DEBUG_CIU_SUM
392 ciu_intr_sum_bits = oct_read64(ciu_intr_sum_reg_addr); /* unneeded dummy read */
393 printf(" CIU: status: 0x%X reg_addr: 0x%llX Val: 0x%llX -> 0x%llX",
394 cpu_status_bits, ciu_intr_sum_reg_addr, ciu_intr_sum_bits,
395 ciu_intr_sum_bits | write_bits);
396#endif
397
398 oct_write64(ciu_intr_sum_reg_addr, write_bits);
399 oct_read64(OCTEON_MIO_BOOT_BIST_STAT); /* Bus Barrier */
400
401#ifdef DEBUG_CIU_SUM
402 printf(" Readback: 0x%llX\n\n ", (uint64_t) oct_read64(ciu_intr_sum_reg_addr));
403#endif
404
538 octeon_set_interrupts(cpu_status_bits);
405 intr_restore(cpu_status_bits);
539}
540
541/*
542 * ciu_disable_intr
543 */
544void
545ciu_disable_intr(int core_num, int intx, int enx)
546{
547 uint32_t cpu_status_bits;
548 uint64_t ciu_intr_reg_addr;
549
550 if (core_num == CIU_THIS_CORE)
551 core_num = octeon_get_core_num();
552
406}
407
408/*
409 * ciu_disable_intr
410 */
411void
412ciu_disable_intr(int core_num, int intx, int enx)
413{
414 uint32_t cpu_status_bits;
415 uint64_t ciu_intr_reg_addr;
416
417 if (core_num == CIU_THIS_CORE)
418 core_num = octeon_get_core_num();
419
553 cpu_status_bits = octeon_disable_interrupts();
420 cpu_status_bits = intr_disable();
554
555 ciu_intr_reg_addr = ciu_get_intr_en_reg_addr(core_num, intx, enx);
556
557 oct_read64(ciu_intr_reg_addr); /* Dummy read */
558
559 oct_write64(ciu_intr_reg_addr, 0LL);
560 oct_read64(OCTEON_MIO_BOOT_BIST_STAT); /* Bus Barrier */
561
421
422 ciu_intr_reg_addr = ciu_get_intr_en_reg_addr(core_num, intx, enx);
423
424 oct_read64(ciu_intr_reg_addr); /* Dummy read */
425
426 oct_write64(ciu_intr_reg_addr, 0LL);
427 oct_read64(OCTEON_MIO_BOOT_BIST_STAT); /* Bus Barrier */
428
562 octeon_set_interrupts(cpu_status_bits);
429 intr_restore(cpu_status_bits);
563}
564
565void
566ciu_dump_interrutps_enabled(int core_num, int intx, int enx, int ciu_ip)
567{
568
569 uint64_t ciu_intr_reg_addr;
570 uint64_t ciu_intr_bits;

--- 4 unchanged lines hidden (view full) ---

575
576#ifndef OCTEON_SMP_1
577 ciu_intr_reg_addr = ciu_get_intr_en_reg_addr(core_num, intx, enx);
578#else
579 ciu_intr_reg_addr = ciu_get_en_reg_addr_new(core_num, intx, enx, ciu_ip);
580#endif
581
582 if (!ciu_intr_reg_addr) {
430}
431
432void
433ciu_dump_interrutps_enabled(int core_num, int intx, int enx, int ciu_ip)
434{
435
436 uint64_t ciu_intr_reg_addr;
437 uint64_t ciu_intr_bits;

--- 4 unchanged lines hidden (view full) ---

442
443#ifndef OCTEON_SMP_1
444 ciu_intr_reg_addr = ciu_get_intr_en_reg_addr(core_num, intx, enx);
445#else
446 ciu_intr_reg_addr = ciu_get_en_reg_addr_new(core_num, intx, enx, ciu_ip);
447#endif
448
449 if (!ciu_intr_reg_addr) {
583 printf("Bad call to %s\n", __FUNCTION__);
450 printf("Bad call to %s\n", __func__);
584 while(1);
585 return;
586 }
587
588 ciu_intr_bits = oct_read64(ciu_intr_reg_addr);
589 printf(" CIU core %d int: %d en: %d ip: %d Add: %#llx enabled: %#llx SR: %x\n",
590 core_num, intx, enx, ciu_ip, (unsigned long long)ciu_intr_reg_addr,
591 (unsigned long long)ciu_intr_bits, mips_rd_status());

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607
608//#define DEBUG_CIU_EN 1
609
610#ifdef DEBUG_CIU_EN
611 printf(" CIU: core %u enabling Intx %u Enx %u IP %d Bits: 0x%llX\n",
612 core_num, intx, enx, ciu_ip, set_these_interrupt_bits);
613#endif
614
451 while(1);
452 return;
453 }
454
455 ciu_intr_bits = oct_read64(ciu_intr_reg_addr);
456 printf(" CIU core %d int: %d en: %d ip: %d Add: %#llx enabled: %#llx SR: %x\n",
457 core_num, intx, enx, ciu_ip, (unsigned long long)ciu_intr_reg_addr,
458 (unsigned long long)ciu_intr_bits, mips_rd_status());

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474
475//#define DEBUG_CIU_EN 1
476
477#ifdef DEBUG_CIU_EN
478 printf(" CIU: core %u enabling Intx %u Enx %u IP %d Bits: 0x%llX\n",
479 core_num, intx, enx, ciu_ip, set_these_interrupt_bits);
480#endif
481
615 cpu_status_bits = octeon_disable_interrupts();
482 cpu_status_bits = intr_disable();
616
617#ifndef OCTEON_SMP_1
618 ciu_intr_reg_addr = ciu_get_intr_en_reg_addr(core_num, intx, enx);
619#else
620 ciu_intr_reg_addr = ciu_get_en_reg_addr_new(core_num, intx, enx, ciu_ip);
621#endif
622
623 if (!ciu_intr_reg_addr) {
483
484#ifndef OCTEON_SMP_1
485 ciu_intr_reg_addr = ciu_get_intr_en_reg_addr(core_num, intx, enx);
486#else
487 ciu_intr_reg_addr = ciu_get_en_reg_addr_new(core_num, intx, enx, ciu_ip);
488#endif
489
490 if (!ciu_intr_reg_addr) {
624 printf("Bad call to %s\n", __FUNCTION__);
491 printf("Bad call to %s\n", __func__);
625 while(1);
626 return; /* XXX */
627 }
628
629 ciu_intr_bits = oct_read64(ciu_intr_reg_addr);
630
631#ifdef DEBUG_CIU_EN
632 printf(" CIU: status: 0x%X reg_addr: 0x%llX Val: 0x%llX -> 0x%llX",
633 cpu_status_bits, ciu_intr_reg_addr, ciu_intr_bits, ciu_intr_bits | set_these_interrupt_bits);
634#endif
635 ciu_intr_bits |= set_these_interrupt_bits;
636 oct_write64(ciu_intr_reg_addr, ciu_intr_bits);
492 while(1);
493 return; /* XXX */
494 }
495
496 ciu_intr_bits = oct_read64(ciu_intr_reg_addr);
497
498#ifdef DEBUG_CIU_EN
499 printf(" CIU: status: 0x%X reg_addr: 0x%llX Val: 0x%llX -> 0x%llX",
500 cpu_status_bits, ciu_intr_reg_addr, ciu_intr_bits, ciu_intr_bits | set_these_interrupt_bits);
501#endif
502 ciu_intr_bits |= set_these_interrupt_bits;
503 oct_write64(ciu_intr_reg_addr, ciu_intr_bits);
637#ifdef OCTEON_SMP
504#ifdef SMP
638 mips_wbflush();
639#endif
640 oct_read64(OCTEON_MIO_BOOT_BIST_STAT); /* Bus Barrier */
641
642#ifdef DEBUG_CIU_EN
643 printf(" Readback: 0x%llX\n\n ",
644 (uint64_t)oct_read64(ciu_intr_reg_addr));
645#endif
646
505 mips_wbflush();
506#endif
507 oct_read64(OCTEON_MIO_BOOT_BIST_STAT); /* Bus Barrier */
508
509#ifdef DEBUG_CIU_EN
510 printf(" Readback: 0x%llX\n\n ",
511 (uint64_t)oct_read64(ciu_intr_reg_addr));
512#endif
513
647 octeon_set_interrupts(cpu_status_bits);
514 intr_restore(cpu_status_bits);
648}
649
650unsigned long
651octeon_get_clock_rate(void)
652{
653 return octeon_cpu_clock;
654}
655
656static void
657octeon_memory_init(void)
658{
659 uint32_t realmem_bytes;
660
661 if (octeon_board_real()) {
515}
516
517unsigned long
518octeon_get_clock_rate(void)
519{
520 return octeon_cpu_clock;
521}
522
523static void
524octeon_memory_init(void)
525{
526 uint32_t realmem_bytes;
527
528 if (octeon_board_real()) {
662 printf("octeon_dram == %jx\n", (intmax_t)octeon_dram);
663 printf("reduced to ram: %u MB", (uint32_t)octeon_dram >> 20);
664
665 realmem_bytes = (octeon_dram - PAGE_SIZE);
666 realmem_bytes &= ~(PAGE_SIZE - 1);
529 realmem_bytes = (octeon_dram - PAGE_SIZE);
530 realmem_bytes &= ~(PAGE_SIZE - 1);
667 printf("Real memory bytes is %x\n", realmem_bytes);
668 } else {
669 /* Simulator we limit to 96 meg */
670 realmem_bytes = (96 << 20);
671 }
672 /* phys_avail regions are in bytes */
673 phys_avail[0] = (MIPS_KSEG0_TO_PHYS((vm_offset_t)&end) + PAGE_SIZE) & ~(PAGE_SIZE - 1);
674 if (octeon_board_real()) {
675 if (realmem_bytes > OCTEON_DRAM_FIRST_256_END)
676 phys_avail[1] = OCTEON_DRAM_FIRST_256_END;
677 else
678 phys_avail[1] = realmem_bytes;
679 realmem_bytes -= OCTEON_DRAM_FIRST_256_END;
680 realmem_bytes &= ~(PAGE_SIZE - 1);
531 } else {
532 /* Simulator we limit to 96 meg */
533 realmem_bytes = (96 << 20);
534 }
535 /* phys_avail regions are in bytes */
536 phys_avail[0] = (MIPS_KSEG0_TO_PHYS((vm_offset_t)&end) + PAGE_SIZE) & ~(PAGE_SIZE - 1);
537 if (octeon_board_real()) {
538 if (realmem_bytes > OCTEON_DRAM_FIRST_256_END)
539 phys_avail[1] = OCTEON_DRAM_FIRST_256_END;
540 else
541 phys_avail[1] = realmem_bytes;
542 realmem_bytes -= OCTEON_DRAM_FIRST_256_END;
543 realmem_bytes &= ~(PAGE_SIZE - 1);
681 printf("phys_avail[0] = %#lx phys_avail[1] = %#lx\n",
682 (long)phys_avail[0], (long)phys_avail[1]);
683 } else {
684 /* Simulator gets 96Meg period. */
685 phys_avail[1] = (96 << 20);
686 }
687 /*-
688 * Octeon Memory looks as follows:
689 * PA
690 * 0000 0000 to 0x0 0000 0000 0000

--- 9 unchanged lines hidden (view full) ---

700 physmem = btoc(phys_avail[1] - phys_avail[0]);
701 if ((octeon_board_real()) &&
702 (realmem_bytes > OCTEON_DRAM_FIRST_256_END)) {
703 /* take out the upper non-cached 1/2 */
704 realmem_bytes -= OCTEON_DRAM_FIRST_256_END;
705 realmem_bytes &= ~(PAGE_SIZE - 1);
706 /* Now map the rest of the memory */
707 phys_avail[2] = 0x20000000;
544 } else {
545 /* Simulator gets 96Meg period. */
546 phys_avail[1] = (96 << 20);
547 }
548 /*-
549 * Octeon Memory looks as follows:
550 * PA
551 * 0000 0000 to 0x0 0000 0000 0000

--- 9 unchanged lines hidden (view full) ---

561 physmem = btoc(phys_avail[1] - phys_avail[0]);
562 if ((octeon_board_real()) &&
563 (realmem_bytes > OCTEON_DRAM_FIRST_256_END)) {
564 /* take out the upper non-cached 1/2 */
565 realmem_bytes -= OCTEON_DRAM_FIRST_256_END;
566 realmem_bytes &= ~(PAGE_SIZE - 1);
567 /* Now map the rest of the memory */
568 phys_avail[2] = 0x20000000;
708 printf("realmem_bytes is now at %x\n", realmem_bytes);
709 phys_avail[3] = ((uint32_t) 0x20000000 + realmem_bytes);
569 phys_avail[3] = ((uint32_t) 0x20000000 + realmem_bytes);
710 printf("Next block of memory goes from %#lx to %#lx\n",
711 (long)phys_avail[2], (long)phys_avail[3]);
712 physmem += btoc(phys_avail[3] - phys_avail[2]);
570 physmem += btoc(phys_avail[3] - phys_avail[2]);
713 } else {
714 printf("realmem_bytes is %d\n", realmem_bytes);
715 }
716 realmem = physmem;
717
718 printf("Total DRAM Size %#X\n", (uint32_t) octeon_dram);
719 printf("Bank 0 = %#08lX -> %#08lX\n", (long)phys_avail[0], (long)phys_avail[1]);
720 printf("Bank 1 = %#08lX -> %#08lX\n", (long)phys_avail[2], (long)phys_avail[3]);
571 }
572 realmem = physmem;
573
574 printf("Total DRAM Size %#X\n", (uint32_t) octeon_dram);
575 printf("Bank 0 = %#08lX -> %#08lX\n", (long)phys_avail[0], (long)phys_avail[1]);
576 printf("Bank 1 = %#08lX -> %#08lX\n", (long)phys_avail[2], (long)phys_avail[3]);
721 printf("physmem: %#lx\n", physmem);
722
723 Maxmem = physmem;
724
725}
726
727void
728platform_start(__register_t a0, __register_t a1, __register_t a2 __unused,
729 __register_t a3)
730{
731 uint64_t platform_counter_freq;
732

--- 22 unchanged lines hidden (view full) ---

755 mips_proc0_init();
756 mutex_init();
757 kdb_init();
758#ifdef KDB
759 if (boothowto & RB_KDB)
760 kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
761#endif
762 platform_counter_freq = octeon_get_clock_rate();
577}
578
579void
580platform_start(__register_t a0, __register_t a1, __register_t a2 __unused,
581 __register_t a3)
582{
583 uint64_t platform_counter_freq;
584

--- 22 unchanged lines hidden (view full) ---

607 mips_proc0_init();
608 mutex_init();
609 kdb_init();
610#ifdef KDB
611 if (boothowto & RB_KDB)
612 kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
613#endif
614 platform_counter_freq = octeon_get_clock_rate();
763 mips_timer_init_params(platform_counter_freq, 1);
615 mips_timer_init_params(platform_counter_freq, 0);
616
617#ifdef SMP
618 /*
619 * Clear any pending IPIs and enable the IPI interrupt.
620 */
621 oct_write64(OCTEON_CIU_MBOX_CLRX(0), 0xffffffff);
622 ciu_enable_interrupts(0, CIU_INT_1, CIU_EN_0, OCTEON_CIU_ENABLE_MBOX_INTR, CIU_MIPS_IP3);
623#endif
764}
765
766/* impSTART: This stuff should move back into the Cavium SDK */
767/*
768 ****************************************************************************************
769 *
770 * APP/BOOT DESCRIPTOR STUFF
771 *

--- 205 unchanged lines hidden (view full) ---

977 if (app_desc_ptr->desc_version >= 6)
978 bad_desc = octeon_process_app_desc_ver_6();
979 }
980 if (bad_desc)
981 octeon_process_app_desc_ver_unknown();
982
983 printf("Boot Descriptor Ver: %u -> %u/%u",
984 octeon_bd_ver, octeon_cvmx_bd_ver/100, octeon_cvmx_bd_ver%100);
624}
625
626/* impSTART: This stuff should move back into the Cavium SDK */
627/*
628 ****************************************************************************************
629 *
630 * APP/BOOT DESCRIPTOR STUFF
631 *

--- 205 unchanged lines hidden (view full) ---

837 if (app_desc_ptr->desc_version >= 6)
838 bad_desc = octeon_process_app_desc_ver_6();
839 }
840 if (bad_desc)
841 octeon_process_app_desc_ver_unknown();
842
843 printf("Boot Descriptor Ver: %u -> %u/%u",
844 octeon_bd_ver, octeon_cvmx_bd_ver/100, octeon_cvmx_bd_ver%100);
985 printf(" CPU clock: %uMHz\n", octeon_cpu_clock/1000000);
845 printf(" CPU clock: %uMHz Core Mask: %#x\n", octeon_cpu_clock/1000000, octeon_core_mask);
986 printf(" Dram: %u MB", (uint32_t)(octeon_dram >> 20));
987 printf(" Board Type: %u Revision: %u/%u\n",
988 octeon_board_type, octeon_board_rev_major, octeon_board_rev_minor);
989 printf(" Octeon Chip: %u Rev %u/%u",
990 octeon_chip_type, octeon_chip_rev_major, octeon_chip_rev_minor);
991
992 printf(" Mac Address %02X.%02X.%02X.%02X.%02X.%02X (%d)\n",
993 octeon_mac_addr[0], octeon_mac_addr[1], octeon_mac_addr[2],
994 octeon_mac_addr[3], octeon_mac_addr[4], octeon_mac_addr[5],
995 octeon_mac_addr_count);
996}
997/* impEND: This stuff should move back into the Cavium SDK */
846 printf(" Dram: %u MB", (uint32_t)(octeon_dram >> 20));
847 printf(" Board Type: %u Revision: %u/%u\n",
848 octeon_board_type, octeon_board_rev_major, octeon_board_rev_minor);
849 printf(" Octeon Chip: %u Rev %u/%u",
850 octeon_chip_type, octeon_chip_rev_major, octeon_chip_rev_minor);
851
852 printf(" Mac Address %02X.%02X.%02X.%02X.%02X.%02X (%d)\n",
853 octeon_mac_addr[0], octeon_mac_addr[1], octeon_mac_addr[2],
854 octeon_mac_addr[3], octeon_mac_addr[4], octeon_mac_addr[5],
855 octeon_mac_addr_count);
856}
857/* impEND: This stuff should move back into the Cavium SDK */