1/***********************license start***************
2 * Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
3 * reserved.
| 1/*-
2 * Copyright (c) 2004-2010 Juli Mallett <jmallett@FreeBSD.org>
3 * All rights reserved.
|
4 *
| 4 *
|
| 5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
|
5 *
| 13 *
|
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met:
| 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
|
9 *
| 25 *
|
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * * Neither the name of Cavium Networks nor the names of
19 * its contributors may be used to endorse or promote products
20 * derived from this software without specific prior written
21 * permission.
22 *
23 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
24 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
25 * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
26 * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
27 * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
28 * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
29 * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
30 * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
31 * POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT
32 * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
33 *
34 *
35 * For any questions regarding licensing please contact marketing@caviumnetworks.com
36 *
37 ***********************license end**************************************/
| 26 * $FreeBSD: head/sys/mips/cavium/asm_octeon.S 206721 2010-04-17 03:08:13Z jmallett $
27 */
|
38
| 28
|
39/* $FreeBSD: head/sys/mips/cavium/asm_octeon.S 203130 2010-01-28 20:46:40Z imp $ */
40
| |
41#include <machine/asm.h>
| 29#include <machine/asm.h>
|
42#include <machine/cache_r4k.h>
43#include <machine/cpuregs.h>
44#include <machine/param.h>
45#include <machine/pte.h>
| |
46
| 30
|
47#include "assym.s"
48
| 31 .set noreorder
|
49
| 32
|
50
51#define CPU_DISABLE_INTERRUPTS(reg, reg2, reg3) \
52 mfc0 reg, MIPS_COP_0_STATUS; \
53 nop; \
54 move reg3, reg; \
55 li reg2, ~MIPS_SR_INT_IE; \
56 and reg, reg2, reg; \
57 mtc0 reg, MIPS_COP_0_STATUS; \
58 COP0_SYNC
59
60
61
62#define CPU_ENABLE_INTERRUPTS(reg, reg3) \
63 mfc0 reg, MIPS_COP_0_STATUS; \
64 nop; \
65 or reg, reg, reg3; \
66 mtc0 reg, MIPS_COP_0_STATUS; \
67 COP0_SYNC
68
69
70#define PUSHR(reg) \
71 addiu sp,sp,-16 ; \
72 sd reg, 8(sp) ; \
73 nop ;
74
75#define POPR(reg) \
76 ld reg, 8(sp) ; \
77 addiu sp,sp,16 ; \
78 nop ;
79
80
81
82
| 33#ifdef SMP
|
83/*
| 34/*
|
84 * octeon_ciu_get_interrupt_reg_addr
85 *
86 * Given Int-X, En-X combination, return the CIU Interrupt Enable Register addr
87 * a0 = ciu Int-X: 0/1
88 * a1 = ciu EN-0: 0/1
| 35 * This function must be implemented in assembly because it is called early
36 * in AP boot without a valid stack.
|
89 */
| 37 */
|
90LEAF(octeon_ciu_get_interrupt_reg_addr)
91 .set noreorder
92 .set mips3
| 38LEAF(platform_processor_id)
39 .set push
40 .set mips32r2
41 jr ra
42 rdhwr v0, $0
43 .set pop
44END(platform_processor_id)
|
93
| 45
|
94 beqz a0, ciu_get_interrupt_reg_addr_Int_0
95 nop
96
97ciu_get_interrupt_reg_addr_Int_1:
98 beqz a1, ciu_get_interrupt_reg_addr_Int_1_En_0
99 nop
100
101ciu_get_interrupt_reg_addr_Int_1_En1:
102 li a0, OCTEON_CIU_ADDR_HI
103 dsll32 a0, a0, 0
104 nop
105 ori a0, OCTEON_CIU_EN1_INT1_LO
106 j ciu_get_interrupt_reg_addr_ret
107 nop
108
109ciu_get_interrupt_reg_addr_Int_1_En_0:
110 li a0, OCTEON_CIU_ADDR_HI
111 dsll32 a0, a0, 0
112 nop
113 ori a0, OCTEON_CIU_EN0_INT1_LO
114 j ciu_get_interrupt_reg_addr_ret
115 nop
116
117ciu_get_interrupt_reg_addr_Int_0:
118 beqz a1, ciu_get_interrupt_reg_addr_Int_0_En_0
119 nop
120
121ciu_get_interrupt_reg_addr_Int_0_En_1:
122 li a0, OCTEON_CIU_ADDR_HI
123 dsll32 a0, a0, 0
124 nop
125 ori a0, OCTEON_CIU_EN1_INT0_LO
126 j ciu_get_interrupt_reg_addr_ret
127 nop
128
129ciu_get_interrupt_reg_addr_Int_0_En_0:
130 li a0, OCTEON_CIU_ADDR_HI
131 dsll32 a0, a0, 0
132 nop
133 ori a0, OCTEON_CIU_EN0_INT0_LO
134
135
136ciu_get_interrupt_reg_addr_ret:
137 j ra
138 nop
139
140 .set mips0
141 .set reorder
142END(octeon_ciu_get_interrupt_reg_addr)
143
144
145
| |
146/*
| 46/*
|
147 * octeon_ciu_mask_all_interrupts
148 *
149 * a0 = ciu Interrupt-X: 0/1
150 * a1 = ciu Enable-X: 0/1
| 47 * Called on APs to wait until they are told to launch.
|
151 */
| 48 */
|
152LEAF(octeon_ciu_mask_all_interrupts)
153 .set noreorder
154 .set mips3
| 49LEAF(octeon_ap_wait)
50 jal platform_processor_id
51 nop
|
155
| 52
|
156 PUSHR(ra)
157 PUSHR(s0)
158
159 move t0, a0
160 move t1, a1
161 li a0, MIPS_SR_INT_IE
162 CPU_DISABLE_INTERRUPTS(a2, a1, s0)
163 move a0, t0
164 move t1, a1
165 jal octeon_ciu_get_interrupt_reg_addr
166 nop
167 ld a2, 0(a0) # Dummy read
168 nop
169 move a2, zero # Clear all
170 sd a2, 0(a0) # Write new Enable bits
171 nop
172 CPU_ENABLE_INTERRUPTS(a2, s0)
| 531: ll t0, octeon_ap_boot
54 bne v0, t0, 1b
55 nop
|
173
| 56
|
174 POPR(s0)
175 POPR(ra)
176 j ra # Return
177 nop # (bd slot)
| 57 move t0, zero
58 sc t0, octeon_ap_boot
|
178
| 59
|
179 .set mips0
180 .set reorder
181END(octeon_ciu_mask_all_interrupts)
| 60 beqz t0, 1b
61 nop
|
182
| 62
|
| 63 j mpentry
64 nop
65END(octeon_ap_wait)
66#endif
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| |