| vmparam.h (219741) | vmparam.h (219808) |
|---|---|
| 1/*- 2 * Copyright (c) 1988 University of Utah. 3 * Copyright (c) 1992, 1993 4 * The Regents of the University of California. All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * the Systems Programming Group of the University of Utah Computer 8 * Science Department and Ralph Campbell. --- 21 unchanged lines hidden (view full) --- 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * from: Utah $Hdr: vmparam.h 1.16 91/01/18$ 35 * 36 * @(#)vmparam.h 8.2 (Berkeley) 4/22/94 37 * | 1/*- 2 * Copyright (c) 1988 University of Utah. 3 * Copyright (c) 1992, 1993 4 * The Regents of the University of California. All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * the Systems Programming Group of the University of Utah Computer 8 * Science Department and Ralph Campbell. --- 21 unchanged lines hidden (view full) --- 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * from: Utah $Hdr: vmparam.h 1.16 91/01/18$ 35 * 36 * @(#)vmparam.h 8.2 (Berkeley) 4/22/94 37 * |
| 38 * $FreeBSD: head/sys/ia64/include/vmparam.h 219741 2011-03-18 15:36:28Z marcel $ | 38 * $FreeBSD: head/sys/ia64/include/vmparam.h 219808 2011-03-21 01:09:50Z marcel $ |
| 39 */ 40 41#ifndef _MACHINE_VMPARAM_H_ 42#define _MACHINE_VMPARAM_H_ 43 44/* | 39 */ 40 41#ifndef _MACHINE_VMPARAM_H_ 42#define _MACHINE_VMPARAM_H_ 43 44/* |
| 45 * USRSTACK is the top (end) of the user stack. Immediately above the user 46 * stack resides the syscall gateway page. 47 */ 48#define USRSTACK VM_MAXUSER_ADDRESS 49 50/* | |
| 51 * Virtual memory related constants, all in bytes 52 */ 53#ifndef MAXTSIZ 54#define MAXTSIZ (1<<30) /* max text size (1G) */ 55#endif 56#ifndef DFLDSIZ 57#define DFLDSIZ (1<<27) /* initial data size (128M) */ 58#endif --- 58 unchanged lines hidden (view full) --- 117 118/* 119 * Disable superpage reservations. 120 */ 121#ifndef VM_NRESERVLEVEL 122#define VM_NRESERVLEVEL 0 123#endif 124 | 45 * Virtual memory related constants, all in bytes 46 */ 47#ifndef MAXTSIZ 48#define MAXTSIZ (1<<30) /* max text size (1G) */ 49#endif 50#ifndef DFLDSIZ 51#define DFLDSIZ (1<<27) /* initial data size (128M) */ 52#endif --- 58 unchanged lines hidden (view full) --- 111 112/* 113 * Disable superpage reservations. 114 */ 115#ifndef VM_NRESERVLEVEL 116#define VM_NRESERVLEVEL 0 117#endif 118 |
| 119#define IA64_VM_MINKERN_REGION 4 120 |
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| 125/* 126 * Manipulating region bits of an address. 127 */ 128#define IA64_RR_BASE(n) (((uint64_t) (n)) << 61) 129#define IA64_RR_MASK(x) ((x) & ((1L << 61) - 1)) 130 131#define IA64_PHYS_TO_RR7(x) ((x) | IA64_RR_BASE(7)) 132 133/* 134 * The Itanium architecture defines that all implementations support at 135 * least 51 virtual address bits (i.e. IMPL_VA_MSB=50). The unimplemented 136 * bits are sign-extended from VA{IMPL_VA_MSB}. As such, there's a gap in 137 * the virtual address range, which extends at most from 0x0004000000000000 138 * to 0x1ffbffffffffffff. We define the top half of a region in terms of 139 * this worst-case gap. 140 */ | 121/* 122 * Manipulating region bits of an address. 123 */ 124#define IA64_RR_BASE(n) (((uint64_t) (n)) << 61) 125#define IA64_RR_MASK(x) ((x) & ((1L << 61) - 1)) 126 127#define IA64_PHYS_TO_RR7(x) ((x) | IA64_RR_BASE(7)) 128 129/* 130 * The Itanium architecture defines that all implementations support at 131 * least 51 virtual address bits (i.e. IMPL_VA_MSB=50). The unimplemented 132 * bits are sign-extended from VA{IMPL_VA_MSB}. As such, there's a gap in 133 * the virtual address range, which extends at most from 0x0004000000000000 134 * to 0x1ffbffffffffffff. We define the top half of a region in terms of 135 * this worst-case gap. 136 */ |
| 141#define IA64_REGION_TOP_HALF 0x1ffc000000000000 | 137#define IA64_REGION_GAP_START 0x0004000000000000 138#define IA64_REGION_GAP_EXTEND 0x1ffc000000000000 |
| 142 143/* 144 * Page size of the identity mappings in region 7. 145 */ 146#ifndef LOG2_ID_PAGE_SIZE 147#define LOG2_ID_PAGE_SIZE 28 /* 256M */ 148#endif 149 150#define IA64_ID_PAGE_SHIFT (LOG2_ID_PAGE_SIZE) 151#define IA64_ID_PAGE_SIZE (1<<(LOG2_ID_PAGE_SIZE)) 152#define IA64_ID_PAGE_MASK (IA64_ID_PAGE_SIZE-1) 153 | 139 140/* 141 * Page size of the identity mappings in region 7. 142 */ 143#ifndef LOG2_ID_PAGE_SIZE 144#define LOG2_ID_PAGE_SIZE 28 /* 256M */ 145#endif 146 147#define IA64_ID_PAGE_SHIFT (LOG2_ID_PAGE_SIZE) 148#define IA64_ID_PAGE_SIZE (1<<(LOG2_ID_PAGE_SIZE)) 149#define IA64_ID_PAGE_MASK (IA64_ID_PAGE_SIZE-1) 150 |
| 154#define IA64_BACKINGSTORE IA64_RR_BASE(4) | |
| 155 156/* 157 * Parameters for Pre-Boot Virtual Memory (PBVM). 158 * The kernel, its modules and metadata are loaded in the PBVM by the loader. 159 * The PBVM consists of pages for which the mapping is maintained in a page 160 * table. The page table is at least 1 EFI page large (i.e. 4KB), but can be 161 * larger to accommodate more PBVM. The maximum page table size is 1MB. With 162 * 8 bytes per page table entry, this means that the PBVM has at least 512 --- 9 unchanged lines hidden (view full) --- 172 * The kernel is given the PA and size of the page table that provides the 173 * mapping of the PBVM. The page table itself is assumed to be mapped at a 174 * known virtual address and using a single translation wired into the CPU. 175 * As such, the page table is assumed to be a power of 2 and naturally aligned. 176 * The kernel also assumes that a good portion of the kernel text is mapped 177 * and wired into the CPU, but does not assume that the mapping covers the 178 * whole of PBVM. 179 */ | 151 152/* 153 * Parameters for Pre-Boot Virtual Memory (PBVM). 154 * The kernel, its modules and metadata are loaded in the PBVM by the loader. 155 * The PBVM consists of pages for which the mapping is maintained in a page 156 * table. The page table is at least 1 EFI page large (i.e. 4KB), but can be 157 * larger to accommodate more PBVM. The maximum page table size is 1MB. With 158 * 8 bytes per page table entry, this means that the PBVM has at least 512 --- 9 unchanged lines hidden (view full) --- 168 * The kernel is given the PA and size of the page table that provides the 169 * mapping of the PBVM. The page table itself is assumed to be mapped at a 170 * known virtual address and using a single translation wired into the CPU. 171 * As such, the page table is assumed to be a power of 2 and naturally aligned. 172 * The kernel also assumes that a good portion of the kernel text is mapped 173 * and wired into the CPU, but does not assume that the mapping covers the 174 * whole of PBVM. 175 */ |
| 180#define IA64_PBVM_RR 4 | 176#define IA64_PBVM_RR IA64_VM_MINKERN_REGION |
| 181#define IA64_PBVM_BASE \ | 177#define IA64_PBVM_BASE \ |
| 182 (IA64_RR_BASE(IA64_PBVM_RR) + IA64_REGION_TOP_HALF) | 178 (IA64_RR_BASE(IA64_PBVM_RR) + IA64_REGION_GAP_EXTEND) |
| 183 184#define IA64_PBVM_PGTBL_MAXSZ 1048576 185#define IA64_PBVM_PGTBL \ 186 (IA64_RR_BASE(IA64_PBVM_RR + 1) - IA64_PBVM_PGTBL_MAXSZ) 187 188#define IA64_PBVM_PAGE_SHIFT 16 /* 64KB */ 189#define IA64_PBVM_PAGE_SIZE (1 << IA64_PBVM_PAGE_SHIFT) 190#define IA64_PBVM_PAGE_MASK (IA64_PBVM_PAGE_SIZE - 1) 191 192/* 193 * Mach derived constants 194 */ 195 196/* user/kernel map constants */ | 179 180#define IA64_PBVM_PGTBL_MAXSZ 1048576 181#define IA64_PBVM_PGTBL \ 182 (IA64_RR_BASE(IA64_PBVM_RR + 1) - IA64_PBVM_PGTBL_MAXSZ) 183 184#define IA64_PBVM_PAGE_SHIFT 16 /* 64KB */ 185#define IA64_PBVM_PAGE_SIZE (1 << IA64_PBVM_PAGE_SHIFT) 186#define IA64_PBVM_PAGE_MASK (IA64_PBVM_PAGE_SIZE - 1) 187 188/* 189 * Mach derived constants 190 */ 191 192/* user/kernel map constants */ |
| 197#define VM_MIN_ADDRESS 0 198#define VM_MAXUSER_ADDRESS IA64_RR_BASE(5) 199#define VM_GATEWAY_SIZE PAGE_SIZE 200#define VM_MIN_KERNEL_ADDRESS (VM_MAXUSER_ADDRESS + VM_GATEWAY_SIZE) 201#define VM_MAX_KERNEL_ADDRESS (IA64_RR_BASE(6) - 1) | 193#define VM_MIN_ADDRESS 0 194#define VM_MAXUSER_ADDRESS IA64_RR_BASE(IA64_VM_MINKERN_REGION) 195#define VM_MIN_KERNEL_ADDRESS IA64_RR_BASE(IA64_VM_MINKERN_REGION + 1) 196#define VM_MAX_KERNEL_ADDRESS (IA64_RR_BASE(IA64_VM_MINKERN_REGION + 2) - 1) |
| 202#define VM_MAX_ADDRESS ~0UL 203 204#define KERNBASE VM_MAXUSER_ADDRESS 205 | 197#define VM_MAX_ADDRESS ~0UL 198 199#define KERNBASE VM_MAXUSER_ADDRESS 200 |
| 201/* 202 * USRSTACK is the top (end) of the user stack. Immediately above the user 203 * stack resides the syscall gateway page. 204 */ 205#define USRSTACK VM_MAXUSER_ADDRESS 206#define IA64_BACKINGSTORE (USRSTACK - (2 * MAXSSIZ) - PAGE_SIZE) 207 |
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| 206/* virtual sizes (bytes) for various kernel submaps */ 207#ifndef VM_KMEM_SIZE 208#define VM_KMEM_SIZE (12 * 1024 * 1024) 209#endif 210 211/* 212 * How many physical pages per KVA page allocated. 213 * min(max(max(VM_KMEM_SIZE, Physical memory/VM_KMEM_SIZE_SCALE), --- 13 unchanged lines hidden --- | 208/* virtual sizes (bytes) for various kernel submaps */ 209#ifndef VM_KMEM_SIZE 210#define VM_KMEM_SIZE (12 * 1024 * 1024) 211#endif 212 213/* 214 * How many physical pages per KVA page allocated. 215 * min(max(max(VM_KMEM_SIZE, Physical memory/VM_KMEM_SIZE_SCALE), --- 13 unchanged lines hidden --- |