21
22/*
23 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188RU/RTL8192CU.
24 */
25
26#include <sys/param.h>
27#include <sys/sockio.h>
28#include <sys/sysctl.h>
29#include <sys/lock.h>
30#include <sys/mutex.h>
31#include <sys/mbuf.h>
32#include <sys/kernel.h>
33#include <sys/socket.h>
34#include <sys/systm.h>
35#include <sys/malloc.h>
36#include <sys/module.h>
37#include <sys/bus.h>
38#include <sys/endian.h>
39#include <sys/linker.h>
40#include <sys/firmware.h>
41#include <sys/kdb.h>
42
43#include <machine/bus.h>
44#include <machine/resource.h>
45#include <sys/rman.h>
46
47#include <net/bpf.h>
48#include <net/if.h>
49#include <net/if_arp.h>
50#include <net/ethernet.h>
51#include <net/if_dl.h>
52#include <net/if_media.h>
53#include <net/if_types.h>
54
55#include <netinet/in.h>
56#include <netinet/in_systm.h>
57#include <netinet/in_var.h>
58#include <netinet/if_ether.h>
59#include <netinet/ip.h>
60
61#include <net80211/ieee80211_var.h>
62#include <net80211/ieee80211_regdomain.h>
63#include <net80211/ieee80211_radiotap.h>
64#include <net80211/ieee80211_ratectl.h>
65
66#include <dev/usb/usb.h>
67#include <dev/usb/usbdi.h>
68#include "usbdevs.h"
69
70#define USB_DEBUG_VAR urtwn_debug
71#include <dev/usb/usb_debug.h>
72
73#include <dev/usb/wlan/if_urtwnreg.h>
74
75#ifdef USB_DEBUG
76static int urtwn_debug = 0;
77
78SYSCTL_NODE(_hw_usb, OID_AUTO, urtwn, CTLFLAG_RW, 0, "USB urtwn");
79SYSCTL_INT(_hw_usb_urtwn, OID_AUTO, debug, CTLFLAG_RW, &urtwn_debug, 0,
80 "Debug level");
81#endif
82
83#define URTWN_RSSI(r) (r) - 110
84#define IEEE80211_HAS_ADDR4(wh) \
85 (((wh)->i_fc[1] & IEEE80211_FC1_DIR_MASK) == IEEE80211_FC1_DIR_DSTODS)
86
87/* various supported device vendors/products */
88static const STRUCT_USB_HOST_ID urtwn_devs[] = {
89#define URTWN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) }
90 URTWN_DEV(ABOCOM, RTL8188CU_1),
91 URTWN_DEV(ABOCOM, RTL8188CU_2),
92 URTWN_DEV(ABOCOM, RTL8192CU),
93 URTWN_DEV(ASUS, RTL8192CU),
94 URTWN_DEV(AZUREWAVE, RTL8188CE_1),
95 URTWN_DEV(AZUREWAVE, RTL8188CE_2),
96 URTWN_DEV(AZUREWAVE, RTL8188CU),
97 URTWN_DEV(BELKIN, F7D2102),
98 URTWN_DEV(BELKIN, RTL8188CU),
99 URTWN_DEV(BELKIN, RTL8192CU),
100 URTWN_DEV(CHICONY, RTL8188CUS_1),
101 URTWN_DEV(CHICONY, RTL8188CUS_2),
102 URTWN_DEV(CHICONY, RTL8188CUS_3),
103 URTWN_DEV(CHICONY, RTL8188CUS_4),
104 URTWN_DEV(CHICONY, RTL8188CUS_5),
105 URTWN_DEV(COREGA, RTL8192CU),
106 URTWN_DEV(DLINK, RTL8188CU),
107 URTWN_DEV(DLINK, RTL8192CU_1),
108 URTWN_DEV(DLINK, RTL8192CU_2),
109 URTWN_DEV(DLINK, RTL8192CU_3),
110 URTWN_DEV(DLINK, DWA131B),
111 URTWN_DEV(EDIMAX, EW7811UN),
112 URTWN_DEV(EDIMAX, RTL8192CU),
113 URTWN_DEV(FEIXUN, RTL8188CU),
114 URTWN_DEV(FEIXUN, RTL8192CU),
115 URTWN_DEV(GUILLEMOT, HWNUP150),
116 URTWN_DEV(HAWKING, RTL8192CU),
117 URTWN_DEV(HP3, RTL8188CU),
118 URTWN_DEV(NETGEAR, WNA1000M),
119 URTWN_DEV(NETGEAR, RTL8192CU),
120 URTWN_DEV(NETGEAR4, RTL8188CU),
121 URTWN_DEV(NOVATECH, RTL8188CU),
122 URTWN_DEV(PLANEX2, RTL8188CU_1),
123 URTWN_DEV(PLANEX2, RTL8188CU_2),
124 URTWN_DEV(PLANEX2, RTL8188CU_3),
125 URTWN_DEV(PLANEX2, RTL8188CU_4),
126 URTWN_DEV(PLANEX2, RTL8188CUS),
127 URTWN_DEV(PLANEX2, RTL8192CU),
128 URTWN_DEV(REALTEK, RTL8188CE_0),
129 URTWN_DEV(REALTEK, RTL8188CE_1),
130 URTWN_DEV(REALTEK, RTL8188CTV),
131 URTWN_DEV(REALTEK, RTL8188CU_0),
132 URTWN_DEV(REALTEK, RTL8188CU_1),
133 URTWN_DEV(REALTEK, RTL8188CU_2),
134 URTWN_DEV(REALTEK, RTL8188CU_COMBO),
135 URTWN_DEV(REALTEK, RTL8188CUS),
136 URTWN_DEV(REALTEK, RTL8188RU_1),
137 URTWN_DEV(REALTEK, RTL8188RU_2),
138 URTWN_DEV(REALTEK, RTL8191CU),
139 URTWN_DEV(REALTEK, RTL8192CE),
140 URTWN_DEV(REALTEK, RTL8192CU),
141 URTWN_DEV(SITECOMEU, RTL8188CU_1),
142 URTWN_DEV(SITECOMEU, RTL8188CU_2),
143 URTWN_DEV(SITECOMEU, RTL8192CU),
144 URTWN_DEV(TRENDNET, RTL8188CU),
145 URTWN_DEV(TRENDNET, RTL8192CU),
146 URTWN_DEV(ZYXEL, RTL8192CU),
147#undef URTWN_DEV
148};
149
150static device_probe_t urtwn_match;
151static device_attach_t urtwn_attach;
152static device_detach_t urtwn_detach;
153
154static usb_callback_t urtwn_bulk_tx_callback;
155static usb_callback_t urtwn_bulk_rx_callback;
156
157static usb_error_t urtwn_do_request(struct urtwn_softc *sc,
158 struct usb_device_request *req, void *data);
159static struct ieee80211vap *urtwn_vap_create(struct ieee80211com *,
160 const char [IFNAMSIZ], int, enum ieee80211_opmode, int,
161 const uint8_t [IEEE80211_ADDR_LEN],
162 const uint8_t [IEEE80211_ADDR_LEN]);
163static void urtwn_vap_delete(struct ieee80211vap *);
164static struct mbuf * urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int,
165 int *);
166static struct mbuf * urtwn_rxeof(struct usb_xfer *, struct urtwn_data *,
167 int *, int8_t *);
168static void urtwn_txeof(struct usb_xfer *, struct urtwn_data *);
169static int urtwn_alloc_list(struct urtwn_softc *,
170 struct urtwn_data[], int, int);
171static int urtwn_alloc_rx_list(struct urtwn_softc *);
172static int urtwn_alloc_tx_list(struct urtwn_softc *);
173static void urtwn_free_tx_list(struct urtwn_softc *);
174static void urtwn_free_rx_list(struct urtwn_softc *);
175static void urtwn_free_list(struct urtwn_softc *,
176 struct urtwn_data data[], int);
177static struct urtwn_data * _urtwn_getbuf(struct urtwn_softc *);
178static struct urtwn_data * urtwn_getbuf(struct urtwn_softc *);
179static int urtwn_write_region_1(struct urtwn_softc *, uint16_t,
180 uint8_t *, int);
181static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t);
182static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t);
183static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t);
184static int urtwn_read_region_1(struct urtwn_softc *, uint16_t,
185 uint8_t *, int);
186static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t);
187static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t);
188static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t);
189static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t,
190 const void *, int);
191static void urtwn_rf_write(struct urtwn_softc *, int, uint8_t,
192 uint32_t);
193static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t);
194static int urtwn_llt_write(struct urtwn_softc *, uint32_t,
195 uint32_t);
196static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t);
197static void urtwn_efuse_read(struct urtwn_softc *);
198static int urtwn_read_chipid(struct urtwn_softc *);
199static void urtwn_read_rom(struct urtwn_softc *);
200static int urtwn_ra_init(struct urtwn_softc *);
201static void urtwn_tsf_sync_enable(struct urtwn_softc *);
202static void urtwn_set_led(struct urtwn_softc *, int, int);
203static int urtwn_newstate(struct ieee80211vap *,
204 enum ieee80211_state, int);
205static void urtwn_watchdog(void *);
206static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t);
207static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *);
208static int urtwn_tx_start(struct urtwn_softc *,
209 struct ieee80211_node *, struct mbuf *,
210 struct urtwn_data *);
211static void urtwn_start(struct ifnet *);
212static int urtwn_ioctl(struct ifnet *, u_long, caddr_t);
213static int urtwn_power_on(struct urtwn_softc *);
214static int urtwn_llt_init(struct urtwn_softc *);
215static void urtwn_fw_reset(struct urtwn_softc *);
216static int urtwn_fw_loadpage(struct urtwn_softc *, int,
217 const uint8_t *, int);
218static int urtwn_load_firmware(struct urtwn_softc *);
219static int urtwn_dma_init(struct urtwn_softc *);
220static void urtwn_mac_init(struct urtwn_softc *);
221static void urtwn_bb_init(struct urtwn_softc *);
222static void urtwn_rf_init(struct urtwn_softc *);
223static void urtwn_cam_init(struct urtwn_softc *);
224static void urtwn_pa_bias_init(struct urtwn_softc *);
225static void urtwn_rxfilter_init(struct urtwn_softc *);
226static void urtwn_edca_init(struct urtwn_softc *);
227static void urtwn_write_txpower(struct urtwn_softc *, int,
228 uint16_t[]);
229static void urtwn_get_txpower(struct urtwn_softc *, int,
230 struct ieee80211_channel *,
231 struct ieee80211_channel *, uint16_t[]);
232static void urtwn_set_txpower(struct urtwn_softc *,
233 struct ieee80211_channel *,
234 struct ieee80211_channel *);
235static void urtwn_scan_start(struct ieee80211com *);
236static void urtwn_scan_end(struct ieee80211com *);
237static void urtwn_set_channel(struct ieee80211com *);
238static void urtwn_set_chan(struct urtwn_softc *,
239 struct ieee80211_channel *,
240 struct ieee80211_channel *);
241static void urtwn_update_mcast(struct ifnet *);
242static void urtwn_iq_calib(struct urtwn_softc *);
243static void urtwn_lc_calib(struct urtwn_softc *);
244static void urtwn_init(void *);
245static void urtwn_init_locked(void *);
246static void urtwn_stop(struct ifnet *, int);
247static void urtwn_stop_locked(struct ifnet *, int);
248static void urtwn_abort_xfers(struct urtwn_softc *);
249static int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *,
250 const struct ieee80211_bpf_params *);
251
252/* Aliases. */
253#define urtwn_bb_write urtwn_write_4
254#define urtwn_bb_read urtwn_read_4
255
256static const struct usb_config urtwn_config[URTWN_N_TRANSFER] = {
257 [URTWN_BULK_RX] = {
258 .type = UE_BULK,
259 .endpoint = UE_ADDR_ANY,
260 .direction = UE_DIR_IN,
261 .bufsize = URTWN_RXBUFSZ,
262 .flags = {
263 .pipe_bof = 1,
264 .short_xfer_ok = 1
265 },
266 .callback = urtwn_bulk_rx_callback,
267 },
268 [URTWN_BULK_TX_BE] = {
269 .type = UE_BULK,
270 .endpoint = 0x03,
271 .direction = UE_DIR_OUT,
272 .bufsize = URTWN_TXBUFSZ,
273 .flags = {
274 .ext_buffer = 1,
275 .pipe_bof = 1,
276 .force_short_xfer = 1
277 },
278 .callback = urtwn_bulk_tx_callback,
279 .timeout = URTWN_TX_TIMEOUT, /* ms */
280 },
281 [URTWN_BULK_TX_BK] = {
282 .type = UE_BULK,
283 .endpoint = 0x03,
284 .direction = UE_DIR_OUT,
285 .bufsize = URTWN_TXBUFSZ,
286 .flags = {
287 .ext_buffer = 1,
288 .pipe_bof = 1,
289 .force_short_xfer = 1,
290 },
291 .callback = urtwn_bulk_tx_callback,
292 .timeout = URTWN_TX_TIMEOUT, /* ms */
293 },
294 [URTWN_BULK_TX_VI] = {
295 .type = UE_BULK,
296 .endpoint = 0x02,
297 .direction = UE_DIR_OUT,
298 .bufsize = URTWN_TXBUFSZ,
299 .flags = {
300 .ext_buffer = 1,
301 .pipe_bof = 1,
302 .force_short_xfer = 1
303 },
304 .callback = urtwn_bulk_tx_callback,
305 .timeout = URTWN_TX_TIMEOUT, /* ms */
306 },
307 [URTWN_BULK_TX_VO] = {
308 .type = UE_BULK,
309 .endpoint = 0x02,
310 .direction = UE_DIR_OUT,
311 .bufsize = URTWN_TXBUFSZ,
312 .flags = {
313 .ext_buffer = 1,
314 .pipe_bof = 1,
315 .force_short_xfer = 1
316 },
317 .callback = urtwn_bulk_tx_callback,
318 .timeout = URTWN_TX_TIMEOUT, /* ms */
319 },
320};
321
322static int
323urtwn_match(device_t self)
324{
325 struct usb_attach_arg *uaa = device_get_ivars(self);
326
327 if (uaa->usb_mode != USB_MODE_HOST)
328 return (ENXIO);
329 if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX)
330 return (ENXIO);
331 if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX)
332 return (ENXIO);
333
334 return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa));
335}
336
337static int
338urtwn_attach(device_t self)
339{
340 struct usb_attach_arg *uaa = device_get_ivars(self);
341 struct urtwn_softc *sc = device_get_softc(self);
342 struct ifnet *ifp;
343 struct ieee80211com *ic;
344 uint8_t iface_index, bands;
345 int error;
346
347 device_set_usb_desc(self);
348 sc->sc_udev = uaa->device;
349 sc->sc_dev = self;
350
351 mtx_init(&sc->sc_mtx, device_get_nameunit(self),
352 MTX_NETWORK_LOCK, MTX_DEF);
353 callout_init(&sc->sc_watchdog_ch, 0);
354
355 iface_index = URTWN_IFACE_INDEX;
356 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer,
357 urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_mtx);
358 if (error) {
359 device_printf(self, "could not allocate USB transfers, "
360 "err=%s\n", usbd_errstr(error));
361 goto detach;
362 }
363
364 URTWN_LOCK(sc);
365
366 error = urtwn_read_chipid(sc);
367 if (error) {
368 device_printf(sc->sc_dev, "unsupported test chip\n");
369 URTWN_UNLOCK(sc);
370 goto detach;
371 }
372
373 /* Determine number of Tx/Rx chains. */
374 if (sc->chip & URTWN_CHIP_92C) {
375 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2;
376 sc->nrxchains = 2;
377 } else {
378 sc->ntxchains = 1;
379 sc->nrxchains = 1;
380 }
381 urtwn_read_rom(sc);
382
383 device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n",
384 (sc->chip & URTWN_CHIP_92C) ? "8192CU" :
385 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" :
386 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" :
387 "8188CUS", sc->ntxchains, sc->nrxchains);
388
389 URTWN_UNLOCK(sc);
390
391 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211);
392 if (ifp == NULL) {
393 device_printf(sc->sc_dev, "can not if_alloc()\n");
394 goto detach;
395 }
396 ic = ifp->if_l2com;
397
398 ifp->if_softc = sc;
399 if_initname(ifp, "urtwn", device_get_unit(sc->sc_dev));
400 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
401 ifp->if_init = urtwn_init;
402 ifp->if_ioctl = urtwn_ioctl;
403 ifp->if_start = urtwn_start;
404 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
405 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
406 IFQ_SET_READY(&ifp->if_snd);
407
408 ic->ic_ifp = ifp;
409 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
410 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
411
412 /* set device capabilities */
413 ic->ic_caps =
414 IEEE80211_C_STA /* station mode */
415 | IEEE80211_C_MONITOR /* monitor mode */
416 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
417 | IEEE80211_C_SHSLOT /* short slot time supported */
418 | IEEE80211_C_BGSCAN /* capable of bg scanning */
419 | IEEE80211_C_WPA /* 802.11i */
420 ;
421
422 ic->ic_cryptocaps =
423 IEEE80211_CRYPTO_WEP |
424 IEEE80211_CRYPTO_AES_CCM |
425 IEEE80211_CRYPTO_TKIPMIC |
426 IEEE80211_CRYPTO_TKIP;
427
428 bands = 0;
429 setbit(&bands, IEEE80211_MODE_11B);
430 setbit(&bands, IEEE80211_MODE_11G);
431 ieee80211_init_channels(ic, NULL, &bands);
432
433 ieee80211_ifattach(ic, sc->sc_bssid);
434 ic->ic_raw_xmit = urtwn_raw_xmit;
435 ic->ic_scan_start = urtwn_scan_start;
436 ic->ic_scan_end = urtwn_scan_end;
437 ic->ic_set_channel = urtwn_set_channel;
438
439 ic->ic_vap_create = urtwn_vap_create;
440 ic->ic_vap_delete = urtwn_vap_delete;
441 ic->ic_update_mcast = urtwn_update_mcast;
442
443 ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr,
444 sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT,
445 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap),
446 URTWN_RX_RADIOTAP_PRESENT);
447
448 if (bootverbose)
449 ieee80211_announce(ic);
450
451 return (0);
452
453detach:
454 urtwn_detach(self);
455 return (ENXIO); /* failure */
456}
457
458static int
459urtwn_detach(device_t self)
460{
461 struct urtwn_softc *sc = device_get_softc(self);
462 struct ifnet *ifp = sc->sc_ifp;
463 struct ieee80211com *ic = ifp->if_l2com;
464
465 if (!device_is_attached(self))
466 return (0);
467
468 urtwn_stop(ifp, 1);
469
470 callout_drain(&sc->sc_watchdog_ch);
471
472 /* stop all USB transfers */
473 usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER);
474 ieee80211_ifdetach(ic);
475
476 urtwn_free_tx_list(sc);
477 urtwn_free_rx_list(sc);
478
479 if_free(ifp);
480 mtx_destroy(&sc->sc_mtx);
481
482 return (0);
483}
484
485static void
486urtwn_free_tx_list(struct urtwn_softc *sc)
487{
488 urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT);
489}
490
491static void
492urtwn_free_rx_list(struct urtwn_softc *sc)
493{
494 urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT);
495}
496
497static void
498urtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata)
499{
500 int i;
501
502 for (i = 0; i < ndata; i++) {
503 struct urtwn_data *dp = &data[i];
504
505 if (dp->buf != NULL) {
506 free(dp->buf, M_USBDEV);
507 dp->buf = NULL;
508 }
509 if (dp->ni != NULL) {
510 ieee80211_free_node(dp->ni);
511 dp->ni = NULL;
512 }
513 }
514}
515
516static usb_error_t
517urtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req,
518 void *data)
519{
520 usb_error_t err;
521 int ntries = 10;
522
523 URTWN_ASSERT_LOCKED(sc);
524
525 while (ntries--) {
526 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx,
527 req, data, 0, NULL, 250 /* ms */);
528 if (err == 0)
529 break;
530
531 DPRINTFN(1, "Control request failed, %s (retrying)\n",
532 usbd_errstr(err));
533 usb_pause_mtx(&sc->sc_mtx, hz / 100);
534 }
535 return (err);
536}
537
538static struct ieee80211vap *
539urtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
540 enum ieee80211_opmode opmode, int flags,
541 const uint8_t bssid[IEEE80211_ADDR_LEN],
542 const uint8_t mac[IEEE80211_ADDR_LEN])
543{
544 struct urtwn_vap *uvp;
545 struct ieee80211vap *vap;
546
547 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */
548 return (NULL);
549
550 uvp = (struct urtwn_vap *) malloc(sizeof(struct urtwn_vap),
551 M_80211_VAP, M_NOWAIT | M_ZERO);
552 if (uvp == NULL)
553 return (NULL);
554 vap = &uvp->vap;
555 /* enable s/w bmiss handling for sta mode */
556 ieee80211_vap_setup(ic, vap, name, unit, opmode,
557 flags | IEEE80211_CLONE_NOBEACONS, bssid, mac);
558
559 /* override state transition machine */
560 uvp->newstate = vap->iv_newstate;
561 vap->iv_newstate = urtwn_newstate;
562
563 /* complete setup */
564 ieee80211_vap_attach(vap, ieee80211_media_change,
565 ieee80211_media_status);
566 ic->ic_opmode = opmode;
567 return (vap);
568}
569
570static void
571urtwn_vap_delete(struct ieee80211vap *vap)
572{
573 struct urtwn_vap *uvp = URTWN_VAP(vap);
574
575 ieee80211_vap_detach(vap);
576 free(uvp, M_80211_VAP);
577}
578
579static struct mbuf *
580urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen, int *rssi_p)
581{
582 struct ifnet *ifp = sc->sc_ifp;
583 struct ieee80211com *ic = ifp->if_l2com;
584 struct ieee80211_frame *wh;
585 struct mbuf *m;
586 struct r92c_rx_stat *stat;
587 uint32_t rxdw0, rxdw3;
588 uint8_t rate;
589 int8_t rssi = 0;
590 int infosz;
591
592 /*
593 * don't pass packets to the ieee80211 framework if the driver isn't
594 * RUNNING.
595 */
596 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
597 return (NULL);
598
599 stat = (struct r92c_rx_stat *)buf;
600 rxdw0 = le32toh(stat->rxdw0);
601 rxdw3 = le32toh(stat->rxdw3);
602
603 if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) {
604 /*
605 * This should not happen since we setup our Rx filter
606 * to not receive these frames.
607 */
608 ifp->if_ierrors++;
609 return (NULL);
610 }
611
612 rate = MS(rxdw3, R92C_RXDW3_RATE);
613 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8;
614
615 /* Get RSSI from PHY status descriptor if present. */
616 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) {
617 rssi = urtwn_get_rssi(sc, rate, &stat[1]);
618 /* Update our average RSSI. */
619 urtwn_update_avgrssi(sc, rate, rssi);
620 /*
621 * Convert the RSSI to a range that will be accepted
622 * by net80211.
623 */
624 rssi = URTWN_RSSI(rssi);
625 }
626
627 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
628 if (m == NULL) {
629 device_printf(sc->sc_dev, "could not create RX mbuf\n");
630 return (NULL);
631 }
632
633 /* Finalize mbuf. */
634 m->m_pkthdr.rcvif = ifp;
635 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz);
636 memcpy(mtod(m, uint8_t *), wh, pktlen);
637 m->m_pkthdr.len = m->m_len = pktlen;
638
639 if (ieee80211_radiotap_active(ic)) {
640 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap;
641
642 tap->wr_flags = 0;
643 /* Map HW rate index to 802.11 rate. */
644 if (!(rxdw3 & R92C_RXDW3_HT)) {
645 switch (rate) {
646 /* CCK. */
647 case 0: tap->wr_rate = 2; break;
648 case 1: tap->wr_rate = 4; break;
649 case 2: tap->wr_rate = 11; break;
650 case 3: tap->wr_rate = 22; break;
651 /* OFDM. */
652 case 4: tap->wr_rate = 12; break;
653 case 5: tap->wr_rate = 18; break;
654 case 6: tap->wr_rate = 24; break;
655 case 7: tap->wr_rate = 36; break;
656 case 8: tap->wr_rate = 48; break;
657 case 9: tap->wr_rate = 72; break;
658 case 10: tap->wr_rate = 96; break;
659 case 11: tap->wr_rate = 108; break;
660 }
661 } else if (rate >= 12) { /* MCS0~15. */
662 /* Bit 7 set means HT MCS instead of rate. */
663 tap->wr_rate = 0x80 | (rate - 12);
664 }
665 tap->wr_dbm_antsignal = rssi;
666 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq);
667 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags);
668 }
669
670 *rssi_p = rssi;
671
672 return (m);
673}
674
675static struct mbuf *
676urtwn_rxeof(struct usb_xfer *xfer, struct urtwn_data *data, int *rssi,
677 int8_t *nf)
678{
679 struct urtwn_softc *sc = data->sc;
680 struct ifnet *ifp = sc->sc_ifp;
681 struct r92c_rx_stat *stat;
682 struct mbuf *m, *m0 = NULL, *prevm = NULL;
683 uint32_t rxdw0;
684 uint8_t *buf;
685 int len, totlen, pktlen, infosz, npkts;
686
687 usbd_xfer_status(xfer, &len, NULL, NULL, NULL);
688
689 if (len < sizeof(*stat)) {
690 ifp->if_ierrors++;
691 return (NULL);
692 }
693
694 buf = data->buf;
695 /* Get the number of encapsulated frames. */
696 stat = (struct r92c_rx_stat *)buf;
697 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT);
698 DPRINTFN(6, "Rx %d frames in one chunk\n", npkts);
699
700 /* Process all of them. */
701 while (npkts-- > 0) {
702 if (len < sizeof(*stat))
703 break;
704 stat = (struct r92c_rx_stat *)buf;
705 rxdw0 = le32toh(stat->rxdw0);
706
707 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN);
708 if (pktlen == 0)
709 break;
710
711 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8;
712
713 /* Make sure everything fits in xfer. */
714 totlen = sizeof(*stat) + infosz + pktlen;
715 if (totlen > len)
716 break;
717
718 m = urtwn_rx_frame(sc, buf, pktlen, rssi);
719 if (m0 == NULL)
720 m0 = m;
721 if (prevm == NULL)
722 prevm = m;
723 else {
724 prevm->m_next = m;
725 prevm = m;
726 }
727
728 /* Next chunk is 128-byte aligned. */
729 totlen = (totlen + 127) & ~127;
730 buf += totlen;
731 len -= totlen;
732 }
733
734 return (m0);
735}
736
737static void
738urtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error)
739{
740 struct urtwn_softc *sc = usbd_xfer_softc(xfer);
741 struct ifnet *ifp = sc->sc_ifp;
742 struct ieee80211com *ic = ifp->if_l2com;
743 struct ieee80211_frame *wh;
744 struct ieee80211_node *ni;
745 struct mbuf *m = NULL, *next;
746 struct urtwn_data *data;
747 int8_t nf;
748 int rssi = 1;
749
750 URTWN_ASSERT_LOCKED(sc);
751
752 switch (USB_GET_STATE(xfer)) {
753 case USB_ST_TRANSFERRED:
754 data = STAILQ_FIRST(&sc->sc_rx_active);
755 if (data == NULL)
756 goto tr_setup;
757 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next);
758 m = urtwn_rxeof(xfer, data, &rssi, &nf);
759 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next);
760 /* FALLTHROUGH */
761 case USB_ST_SETUP:
762tr_setup:
763 data = STAILQ_FIRST(&sc->sc_rx_inactive);
764 if (data == NULL) {
765 KASSERT(m == NULL, ("mbuf isn't NULL"));
766 return;
767 }
768 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next);
769 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next);
770 usbd_xfer_set_frame_data(xfer, 0, data->buf,
771 usbd_xfer_max_len(xfer));
772 usbd_transfer_submit(xfer);
773
774 /*
775 * To avoid LOR we should unlock our private mutex here to call
776 * ieee80211_input() because here is at the end of a USB
777 * callback and safe to unlock.
778 */
779 URTWN_UNLOCK(sc);
780 while (m != NULL) {
781 next = m->m_next;
782 m->m_next = NULL;
783 wh = mtod(m, struct ieee80211_frame *);
784 ni = ieee80211_find_rxnode(ic,
785 (struct ieee80211_frame_min *)wh);
786 nf = URTWN_NOISE_FLOOR;
787 if (ni != NULL) {
788 (void)ieee80211_input(ni, m, rssi, nf);
789 ieee80211_free_node(ni);
790 } else
791 (void)ieee80211_input_all(ic, m, rssi, nf);
792 m = next;
793 }
794 URTWN_LOCK(sc);
795 break;
796 default:
797 /* needs it to the inactive queue due to a error. */
798 data = STAILQ_FIRST(&sc->sc_rx_active);
799 if (data != NULL) {
800 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next);
801 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next);
802 }
803 if (error != USB_ERR_CANCELLED) {
804 usbd_xfer_set_stall(xfer);
805 ifp->if_ierrors++;
806 goto tr_setup;
807 }
808 break;
809 }
810}
811
812static void
813urtwn_txeof(struct usb_xfer *xfer, struct urtwn_data *data)
814{
815 struct urtwn_softc *sc = usbd_xfer_softc(xfer);
816 struct ifnet *ifp = sc->sc_ifp;
817 struct mbuf *m;
818
819 URTWN_ASSERT_LOCKED(sc);
820
821 /*
822 * Do any tx complete callback. Note this must be done before releasing
823 * the node reference.
824 */
825 if (data->m) {
826 m = data->m;
827 if (m->m_flags & M_TXCB) {
828 /* XXX status? */
829 ieee80211_process_callback(data->ni, m, 0);
830 }
831 m_freem(m);
832 data->m = NULL;
833 }
834 if (data->ni) {
835 ieee80211_free_node(data->ni);
836 data->ni = NULL;
837 }
838 sc->sc_txtimer = 0;
839 ifp->if_opackets++;
840 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
841}
842
843static void
844urtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error)
845{
846 struct urtwn_softc *sc = usbd_xfer_softc(xfer);
847 struct ifnet *ifp = sc->sc_ifp;
848 struct urtwn_data *data;
849
850 URTWN_ASSERT_LOCKED(sc);
851
852 switch (USB_GET_STATE(xfer)){
853 case USB_ST_TRANSFERRED:
854 data = STAILQ_FIRST(&sc->sc_tx_active);
855 if (data == NULL)
856 goto tr_setup;
857 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next);
858 urtwn_txeof(xfer, data);
859 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next);
860 /* FALLTHROUGH */
861 case USB_ST_SETUP:
862tr_setup:
863 data = STAILQ_FIRST(&sc->sc_tx_pending);
864 if (data == NULL) {
865 DPRINTF("%s: empty pending queue\n", __func__);
866 return;
867 }
868 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next);
869 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next);
870
871 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen);
872 usbd_transfer_submit(xfer);
873
874 URTWN_UNLOCK(sc);
875 urtwn_start(ifp);
876 URTWN_LOCK(sc);
877 break;
878 default:
879 data = STAILQ_FIRST(&sc->sc_tx_active);
880 if (data == NULL)
881 goto tr_setup;
882 if (data->ni != NULL) {
883 ieee80211_free_node(data->ni);
884 data->ni = NULL;
885 ifp->if_oerrors++;
886 }
887 if (error != USB_ERR_CANCELLED) {
888 usbd_xfer_set_stall(xfer);
889 goto tr_setup;
890 }
891 break;
892 }
893}
894
895static struct urtwn_data *
896_urtwn_getbuf(struct urtwn_softc *sc)
897{
898 struct urtwn_data *bf;
899
900 bf = STAILQ_FIRST(&sc->sc_tx_inactive);
901 if (bf != NULL)
902 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next);
903 else
904 bf = NULL;
905 if (bf == NULL)
906 DPRINTF("%s: %s\n", __func__, "out of xmit buffers");
907 return (bf);
908}
909
910static struct urtwn_data *
911urtwn_getbuf(struct urtwn_softc *sc)
912{
913 struct urtwn_data *bf;
914
915 URTWN_ASSERT_LOCKED(sc);
916
917 bf = _urtwn_getbuf(sc);
918 if (bf == NULL) {
919 struct ifnet *ifp = sc->sc_ifp;
920 DPRINTF("%s: stop queue\n", __func__);
921 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
922 }
923 return (bf);
924}
925
926static int
927urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf,
928 int len)
929{
930 usb_device_request_t req;
931
932 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
933 req.bRequest = R92C_REQ_REGS;
934 USETW(req.wValue, addr);
935 USETW(req.wIndex, 0);
936 USETW(req.wLength, len);
937 return (urtwn_do_request(sc, &req, buf));
938}
939
940static void
941urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val)
942{
943 urtwn_write_region_1(sc, addr, &val, 1);
944}
945
946
947static void
948urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val)
949{
950 val = htole16(val);
951 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 2);
952}
953
954static void
955urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val)
956{
957 val = htole32(val);
958 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 4);
959}
960
961static int
962urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf,
963 int len)
964{
965 usb_device_request_t req;
966
967 req.bmRequestType = UT_READ_VENDOR_DEVICE;
968 req.bRequest = R92C_REQ_REGS;
969 USETW(req.wValue, addr);
970 USETW(req.wIndex, 0);
971 USETW(req.wLength, len);
972 return (urtwn_do_request(sc, &req, buf));
973}
974
975static uint8_t
976urtwn_read_1(struct urtwn_softc *sc, uint16_t addr)
977{
978 uint8_t val;
979
980 if (urtwn_read_region_1(sc, addr, &val, 1) != 0)
981 return (0xff);
982 return (val);
983}
984
985static uint16_t
986urtwn_read_2(struct urtwn_softc *sc, uint16_t addr)
987{
988 uint16_t val;
989
990 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0)
991 return (0xffff);
992 return (le16toh(val));
993}
994
995static uint32_t
996urtwn_read_4(struct urtwn_softc *sc, uint16_t addr)
997{
998 uint32_t val;
999
1000 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0)
1001 return (0xffffffff);
1002 return (le32toh(val));
1003}
1004
1005static int
1006urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len)
1007{
1008 struct r92c_fw_cmd cmd;
1009 int ntries;
1010
1011 /* Wait for current FW box to be empty. */
1012 for (ntries = 0; ntries < 100; ntries++) {
1013 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur)))
1014 break;
1015 DELAY(1);
1016 }
1017 if (ntries == 100) {
1018 device_printf(sc->sc_dev,
1019 "could not send firmware command\n");
1020 return (ETIMEDOUT);
1021 }
1022 memset(&cmd, 0, sizeof(cmd));
1023 cmd.id = id;
1024 if (len > 3)
1025 cmd.id |= R92C_CMD_FLAG_EXT;
1026 KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n"));
1027 memcpy(cmd.msg, buf, len);
1028
1029 /* Write the first word last since that will trigger the FW. */
1030 urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur),
1031 (uint8_t *)&cmd + 4, 2);
1032 urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur),
1033 (uint8_t *)&cmd + 0, 4);
1034
1035 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX;
1036 return (0);
1037}
1038
1039static void
1040urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val)
1041{
1042 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain),
1043 SM(R92C_LSSI_PARAM_ADDR, addr) |
1044 SM(R92C_LSSI_PARAM_DATA, val));
1045}
1046
1047static uint32_t
1048urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr)
1049{
1050 uint32_t reg[R92C_MAX_CHAINS], val;
1051
1052 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0));
1053 if (chain != 0)
1054 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain));
1055
1056 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0),
1057 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE);
1058 DELAY(1000);
1059
1060 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain),
1061 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) |
1062 R92C_HSSI_PARAM2_READ_EDGE);
1063 DELAY(1000);
1064
1065 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0),
1066 reg[0] | R92C_HSSI_PARAM2_READ_EDGE);
1067 DELAY(1000);
1068
1069 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI)
1070 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain));
1071 else
1072 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain));
1073 return (MS(val, R92C_LSSI_READBACK_DATA));
1074}
1075
1076static int
1077urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data)
1078{
1079 int ntries;
1080
1081 urtwn_write_4(sc, R92C_LLT_INIT,
1082 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) |
1083 SM(R92C_LLT_INIT_ADDR, addr) |
1084 SM(R92C_LLT_INIT_DATA, data));
1085 /* Wait for write operation to complete. */
1086 for (ntries = 0; ntries < 20; ntries++) {
1087 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) ==
1088 R92C_LLT_INIT_OP_NO_ACTIVE)
1089 return (0);
1090 DELAY(5);
1091 }
1092 return (ETIMEDOUT);
1093}
1094
1095static uint8_t
1096urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr)
1097{
1098 uint32_t reg;
1099 int ntries;
1100
1101 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL);
1102 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr);
1103 reg &= ~R92C_EFUSE_CTRL_VALID;
1104 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg);
1105 /* Wait for read operation to complete. */
1106 for (ntries = 0; ntries < 100; ntries++) {
1107 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL);
1108 if (reg & R92C_EFUSE_CTRL_VALID)
1109 return (MS(reg, R92C_EFUSE_CTRL_DATA));
1110 DELAY(5);
1111 }
1112 device_printf(sc->sc_dev,
1113 "could not read efuse byte at address 0x%x\n", addr);
1114 return (0xff);
1115}
1116
1117static void
1118urtwn_efuse_read(struct urtwn_softc *sc)
1119{
1120 uint8_t *rom = (uint8_t *)&sc->rom;
1121 uint16_t addr = 0;
1122 uint32_t reg;
1123 uint8_t off, msk;
1124 int i;
1125
1126 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL);
1127 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) {
1128 urtwn_write_2(sc, R92C_SYS_ISO_CTRL,
1129 reg | R92C_SYS_ISO_CTRL_PWC_EV12V);
1130 }
1131 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN);
1132 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) {
1133 urtwn_write_2(sc, R92C_SYS_FUNC_EN,
1134 reg | R92C_SYS_FUNC_EN_ELDR);
1135 }
1136 reg = urtwn_read_2(sc, R92C_SYS_CLKR);
1137 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) !=
1138 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) {
1139 urtwn_write_2(sc, R92C_SYS_CLKR,
1140 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M);
1141 }
1142 memset(&sc->rom, 0xff, sizeof(sc->rom));
1143 while (addr < 512) {
1144 reg = urtwn_efuse_read_1(sc, addr);
1145 if (reg == 0xff)
1146 break;
1147 addr++;
1148 off = reg >> 4;
1149 msk = reg & 0xf;
1150 for (i = 0; i < 4; i++) {
1151 if (msk & (1 << i))
1152 continue;
1153 rom[off * 8 + i * 2 + 0] =
1154 urtwn_efuse_read_1(sc, addr);
1155 addr++;
1156 rom[off * 8 + i * 2 + 1] =
1157 urtwn_efuse_read_1(sc, addr);
1158 addr++;
1159 }
1160 }
1161#ifdef URTWN_DEBUG
1162 if (urtwn_debug >= 2) {
1163 /* Dump ROM content. */
1164 printf("\n");
1165 for (i = 0; i < sizeof(sc->rom); i++)
1166 printf("%02x:", rom[i]);
1167 printf("\n");
1168 }
1169#endif
1170}
1171
1172static int
1173urtwn_read_chipid(struct urtwn_softc *sc)
1174{
1175 uint32_t reg;
1176
1177 reg = urtwn_read_4(sc, R92C_SYS_CFG);
1178 if (reg & R92C_SYS_CFG_TRP_VAUX_EN)
1179 return (EIO);
1180
1181 if (reg & R92C_SYS_CFG_TYPE_92C) {
1182 sc->chip |= URTWN_CHIP_92C;
1183 /* Check if it is a castrated 8192C. */
1184 if (MS(urtwn_read_4(sc, R92C_HPON_FSM),
1185 R92C_HPON_FSM_CHIP_BONDING_ID) ==
1186 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R)
1187 sc->chip |= URTWN_CHIP_92C_1T2R;
1188 }
1189 if (reg & R92C_SYS_CFG_VENDOR_UMC) {
1190 sc->chip |= URTWN_CHIP_UMC;
1191 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0)
1192 sc->chip |= URTWN_CHIP_UMC_A_CUT;
1193 }
1194 return (0);
1195}
1196
1197static void
1198urtwn_read_rom(struct urtwn_softc *sc)
1199{
1200 struct r92c_rom *rom = &sc->rom;
1201
1202 /* Read full ROM image. */
1203 urtwn_efuse_read(sc);
1204
1205 /* XXX Weird but this is what the vendor driver does. */
1206 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa);
1207 DPRINTF("PA setting=0x%x\n", sc->pa_setting);
1208
1209 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE);
1210
1211 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY);
1212 DPRINTF("regulatory type=%d\n", sc->regulatory);
1213
1214 IEEE80211_ADDR_COPY(sc->sc_bssid, rom->macaddr);
1215}
1216
1217/*
1218 * Initialize rate adaptation in firmware.
1219 */
1220static int
1221urtwn_ra_init(struct urtwn_softc *sc)
1222{
1223 static const uint8_t map[] =
1224 { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 };
1225 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
1226 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
1227 struct ieee80211_node *ni;
1228 struct ieee80211_rateset *rs;
1229 struct r92c_fw_cmd_macid_cfg cmd;
1230 uint32_t rates, basicrates;
1231 uint8_t mode;
1232 int maxrate, maxbasicrate, error, i, j;
1233
1234 ni = ieee80211_ref_node(vap->iv_bss);
1235 rs = &ni->ni_rates;
1236
1237 /* Get normal and basic rates mask. */
1238 rates = basicrates = 0;
1239 maxrate = maxbasicrate = 0;
1240 for (i = 0; i < rs->rs_nrates; i++) {
1241 /* Convert 802.11 rate to HW rate index. */
1242 for (j = 0; j < nitems(map); j++)
1243 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j])
1244 break;
1245 if (j == nitems(map)) /* Unknown rate, skip. */
1246 continue;
1247 rates |= 1 << j;
1248 if (j > maxrate)
1249 maxrate = j;
1250 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) {
1251 basicrates |= 1 << j;
1252 if (j > maxbasicrate)
1253 maxbasicrate = j;
1254 }
1255 }
1256 if (ic->ic_curmode == IEEE80211_MODE_11B)
1257 mode = R92C_RAID_11B;
1258 else
1259 mode = R92C_RAID_11BG;
1260 DPRINTF("mode=0x%x rates=0x%08x, basicrates=0x%08x\n",
1261 mode, rates, basicrates);
1262
1263 /* Set rates mask for group addressed frames. */
1264 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID;
1265 cmd.mask = htole32(mode << 28 | basicrates);
1266 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd));
1267 if (error != 0) {
1268 ieee80211_free_node(ni);
1269 device_printf(sc->sc_dev,
1270 "could not add broadcast station\n");
1271 return (error);
1272 }
1273 /* Set initial MRR rate. */
1274 DPRINTF("maxbasicrate=%d\n", maxbasicrate);
1275 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC),
1276 maxbasicrate);
1277
1278 /* Set rates mask for unicast frames. */
1279 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID;
1280 cmd.mask = htole32(mode << 28 | rates);
1281 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd));
1282 if (error != 0) {
1283 ieee80211_free_node(ni);
1284 device_printf(sc->sc_dev, "could not add BSS station\n");
1285 return (error);
1286 }
1287 /* Set initial MRR rate. */
1288 DPRINTF("maxrate=%d\n", maxrate);
1289 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS),
1290 maxrate);
1291
1292 /* Indicate highest supported rate. */
1293 ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1];
1294 ieee80211_free_node(ni);
1295
1296 return (0);
1297}
1298
1299void
1300urtwn_tsf_sync_enable(struct urtwn_softc *sc)
1301{
1302 struct ifnet *ifp = sc->sc_ifp;
1303 struct ieee80211com *ic = ifp->if_l2com;
1304 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
1305 struct ieee80211_node *ni = vap->iv_bss;
1306
1307 uint64_t tsf;
1308
1309 /* Enable TSF synchronization. */
1310 urtwn_write_1(sc, R92C_BCN_CTRL,
1311 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0);
1312
1313 urtwn_write_1(sc, R92C_BCN_CTRL,
1314 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN);
1315
1316 /* Set initial TSF. */
1317 memcpy(&tsf, ni->ni_tstamp.data, 8);
1318 tsf = le64toh(tsf);
1319 tsf = tsf - (tsf % (vap->iv_bss->ni_intval * IEEE80211_DUR_TU));
1320 tsf -= IEEE80211_DUR_TU;
1321 urtwn_write_4(sc, R92C_TSFTR + 0, tsf);
1322 urtwn_write_4(sc, R92C_TSFTR + 4, tsf >> 32);
1323
1324 urtwn_write_1(sc, R92C_BCN_CTRL,
1325 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN);
1326}
1327
1328static void
1329urtwn_set_led(struct urtwn_softc *sc, int led, int on)
1330{
1331 uint8_t reg;
1332
1333 if (led == URTWN_LED_LINK) {
1334 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70;
1335 if (!on)
1336 reg |= R92C_LEDCFG0_DIS;
1337 urtwn_write_1(sc, R92C_LEDCFG0, reg);
1338 sc->ledlink = on; /* Save LED state. */
1339 }
1340}
1341
1342static int
1343urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
1344{
1345 struct urtwn_vap *uvp = URTWN_VAP(vap);
1346 struct ieee80211com *ic = vap->iv_ic;
1347 struct urtwn_softc *sc = ic->ic_ifp->if_softc;
1348 struct ieee80211_node *ni;
1349 enum ieee80211_state ostate;
1350 uint32_t reg;
1351
1352 ostate = vap->iv_state;
1353 DPRINTF("%s -> %s\n", ieee80211_state_name[ostate],
1354 ieee80211_state_name[nstate]);
1355
1356 IEEE80211_UNLOCK(ic);
1357 URTWN_LOCK(sc);
1358 callout_stop(&sc->sc_watchdog_ch);
1359
1360 if (ostate == IEEE80211_S_RUN) {
1361 /* Turn link LED off. */
1362 urtwn_set_led(sc, URTWN_LED_LINK, 0);
1363
1364 /* Set media status to 'No Link'. */
1365 reg = urtwn_read_4(sc, R92C_CR);
1366 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_NOLINK);
1367 urtwn_write_4(sc, R92C_CR, reg);
1368
1369 /* Stop Rx of data frames. */
1370 urtwn_write_2(sc, R92C_RXFLTMAP2, 0);
1371
1372 /* Rest TSF. */
1373 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03);
1374
1375 /* Disable TSF synchronization. */
1376 urtwn_write_1(sc, R92C_BCN_CTRL,
1377 urtwn_read_1(sc, R92C_BCN_CTRL) |
1378 R92C_BCN_CTRL_DIS_TSF_UDT0);
1379
1380 /* Reset EDCA parameters. */
1381 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217);
1382 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317);
1383 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320);
1384 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444);
1385 }
1386
1387 switch (nstate) {
1388 case IEEE80211_S_INIT:
1389 /* Turn link LED off. */
1390 urtwn_set_led(sc, URTWN_LED_LINK, 0);
1391 break;
1392 case IEEE80211_S_SCAN:
1393 if (ostate != IEEE80211_S_SCAN) {
1394 /* Allow Rx from any BSSID. */
1395 urtwn_write_4(sc, R92C_RCR,
1396 urtwn_read_4(sc, R92C_RCR) &
1397 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN));
1398
1399 /* Set gain for scanning. */
1400 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0));
1401 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20);
1402 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg);
1403
1404 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));
1405 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20);
1406 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg);
1407 }
1408
1409 /* Make link LED blink during scan. */
1410 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink);
1411
1412 /* Pause AC Tx queues. */
1413 urtwn_write_1(sc, R92C_TXPAUSE,
1414 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f);
1415
1416 urtwn_set_chan(sc, ic->ic_curchan, NULL);
1417 break;
1418 case IEEE80211_S_AUTH:
1419 /* Set initial gain under link. */
1420 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0));
1421 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32);
1422 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg);
1423
1424 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));
1425 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32);
1426 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg);
1427
1428 urtwn_set_chan(sc, ic->ic_curchan, NULL);
1429 break;
1430 case IEEE80211_S_RUN:
1431 if (vap->iv_opmode == IEEE80211_M_MONITOR) {
1432 /* Enable Rx of data frames. */
1433 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff);
1434
1435 /* Turn link LED on. */
1436 urtwn_set_led(sc, URTWN_LED_LINK, 1);
1437 break;
1438 }
1439
1440 ni = ieee80211_ref_node(vap->iv_bss);
1441 /* Set media status to 'Associated'. */
1442 reg = urtwn_read_4(sc, R92C_CR);
1443 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA);
1444 urtwn_write_4(sc, R92C_CR, reg);
1445
1446 /* Set BSSID. */
1447 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0]));
1448 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4]));
1449
1450 if (ic->ic_curmode == IEEE80211_MODE_11B)
1451 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0);
1452 else /* 802.11b/g */
1453 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3);
1454
1455 /* Enable Rx of data frames. */
1456 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff);
1457
1458 /* Flush all AC queues. */
1459 urtwn_write_1(sc, R92C_TXPAUSE, 0);
1460
1461 /* Set beacon interval. */
1462 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval);
1463
1464 /* Allow Rx from our BSSID only. */
1465 urtwn_write_4(sc, R92C_RCR,
1466 urtwn_read_4(sc, R92C_RCR) |
1467 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN);
1468
1469 /* Enable TSF synchronization. */
1470 urtwn_tsf_sync_enable(sc);
1471
1472 urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10);
1473 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10);
1474 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10);
1475 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10);
1476 urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10);
1477 urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10);
1478
1479 /* Intialize rate adaptation. */
1480 urtwn_ra_init(sc);
1481 /* Turn link LED on. */
1482 urtwn_set_led(sc, URTWN_LED_LINK, 1);
1483
1484 sc->avg_pwdb = -1; /* Reset average RSSI. */
1485 /* Reset temperature calibration state machine. */
1486 sc->thcal_state = 0;
1487 sc->thcal_lctemp = 0;
1488 ieee80211_free_node(ni);
1489 break;
1490 default:
1491 break;
1492 }
1493 URTWN_UNLOCK(sc);
1494 IEEE80211_LOCK(ic);
1495 return(uvp->newstate(vap, nstate, arg));
1496}
1497
1498static void
1499urtwn_watchdog(void *arg)
1500{
1501 struct urtwn_softc *sc = arg;
1502 struct ifnet *ifp = sc->sc_ifp;
1503
1504 if (sc->sc_txtimer > 0) {
1505 if (--sc->sc_txtimer == 0) {
1506 device_printf(sc->sc_dev, "device timeout\n");
1507 ifp->if_oerrors++;
1508 return;
1509 }
1510 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc);
1511 }
1512}
1513
1514static void
1515urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi)
1516{
1517 int pwdb;
1518
1519 /* Convert antenna signal to percentage. */
1520 if (rssi <= -100 || rssi >= 20)
1521 pwdb = 0;
1522 else if (rssi >= 0)
1523 pwdb = 100;
1524 else
1525 pwdb = 100 + rssi;
1526 if (rate <= 3) {
1527 /* CCK gain is smaller than OFDM/MCS gain. */
1528 pwdb += 6;
1529 if (pwdb > 100)
1530 pwdb = 100;
1531 if (pwdb <= 14)
1532 pwdb -= 4;
1533 else if (pwdb <= 26)
1534 pwdb -= 8;
1535 else if (pwdb <= 34)
1536 pwdb -= 6;
1537 else if (pwdb <= 42)
1538 pwdb -= 2;
1539 }
1540 if (sc->avg_pwdb == -1) /* Init. */
1541 sc->avg_pwdb = pwdb;
1542 else if (sc->avg_pwdb < pwdb)
1543 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1;
1544 else
1545 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20);
1546 DPRINTFN(4, "PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb);
1547}
1548
1549static int8_t
1550urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt)
1551{
1552 static const int8_t cckoff[] = { 16, -12, -26, -46 };
1553 struct r92c_rx_phystat *phy;
1554 struct r92c_rx_cck *cck;
1555 uint8_t rpt;
1556 int8_t rssi;
1557
1558 if (rate <= 3) {
1559 cck = (struct r92c_rx_cck *)physt;
1560 if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) {
1561 rpt = (cck->agc_rpt >> 5) & 0x3;
1562 rssi = (cck->agc_rpt & 0x1f) << 1;
1563 } else {
1564 rpt = (cck->agc_rpt >> 6) & 0x3;
1565 rssi = cck->agc_rpt & 0x3e;
1566 }
1567 rssi = cckoff[rpt] - rssi;
1568 } else { /* OFDM/HT. */
1569 phy = (struct r92c_rx_phystat *)physt;
1570 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110;
1571 }
1572 return (rssi);
1573}
1574
1575static int
1576urtwn_tx_start(struct urtwn_softc *sc, struct ieee80211_node *ni,
1577 struct mbuf *m0, struct urtwn_data *data)
1578{
1579 struct ifnet *ifp = sc->sc_ifp;
1580 struct ieee80211_frame *wh;
1581 struct ieee80211_key *k;
1582 struct ieee80211com *ic = ifp->if_l2com;
1583 struct ieee80211vap *vap = ni->ni_vap;
1584 struct usb_xfer *xfer;
1585 struct r92c_tx_desc *txd;
1586 uint8_t raid, type;
1587 uint16_t sum;
1588 int i, hasqos, xferlen;
1589 struct usb_xfer *urtwn_pipes[4] = {
1590 sc->sc_xfer[URTWN_BULK_TX_BE],
1591 sc->sc_xfer[URTWN_BULK_TX_BK],
1592 sc->sc_xfer[URTWN_BULK_TX_VI],
1593 sc->sc_xfer[URTWN_BULK_TX_VO]
1594 };
1595
1596 URTWN_ASSERT_LOCKED(sc);
1597
1598 /*
1599 * Software crypto.
1600 */
1601 wh = mtod(m0, struct ieee80211_frame *);
1602 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
1603 k = ieee80211_crypto_encap(ni, m0);
1604 if (k == NULL) {
1605 device_printf(sc->sc_dev,
1606 "ieee80211_crypto_encap returns NULL.\n");
1607 /* XXX we don't expect the fragmented frames */
1608 m_freem(m0);
1609 return (ENOBUFS);
1610 }
1611
1612 /* in case packet header moved, reset pointer */
1613 wh = mtod(m0, struct ieee80211_frame *);
1614 }
1615
1616 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) {
1617 case IEEE80211_FC0_TYPE_CTL:
1618 case IEEE80211_FC0_TYPE_MGT:
1619 xfer = sc->sc_xfer[URTWN_BULK_TX_VO];
1620 break;
1621 default:
1622 KASSERT(M_WME_GETAC(m0) < 4,
1623 ("unsupported WME pipe %d", M_WME_GETAC(m0)));
1624 xfer = urtwn_pipes[M_WME_GETAC(m0)];
1625 break;
1626 }
1627
1628 hasqos = 0;
1629
1630 /* Fill Tx descriptor. */
1631 txd = (struct r92c_tx_desc *)data->buf;
1632 memset(txd, 0, sizeof(*txd));
1633
1634 txd->txdw0 |= htole32(
1635 SM(R92C_TXDW0_PKTLEN, m0->m_pkthdr.len) |
1636 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) |
1637 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG);
1638 if (IEEE80211_IS_MULTICAST(wh->i_addr1))
1639 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST);
1640
1641 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
1642 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) &&
1643 type == IEEE80211_FC0_TYPE_DATA) {
1644 if (ic->ic_curmode == IEEE80211_MODE_11B)
1645 raid = R92C_RAID_11B;
1646 else
1647 raid = R92C_RAID_11BG;
1648 txd->txdw1 |= htole32(
1649 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) |
1650 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) |
1651 SM(R92C_TXDW1_RAID, raid) |
1652 R92C_TXDW1_AGGBK);
1653
1654 if (ic->ic_flags & IEEE80211_F_USEPROT) {
1655 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) {
1656 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF |
1657 R92C_TXDW4_HWRTSEN);
1658 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) {
1659 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN |
1660 R92C_TXDW4_HWRTSEN);
1661 }
1662 }
1663 /* Send RTS at OFDM24. */
1664 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8));
1665 txd->txdw5 |= htole32(0x0001ff00);
1666 /* Send data at OFDM54. */
1667 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11));
1668 } else {
1669 txd->txdw1 |= htole32(
1670 SM(R92C_TXDW1_MACID, 0) |
1671 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) |
1672 SM(R92C_TXDW1_RAID, R92C_RAID_11B));
1673
1674 /* Force CCK1. */
1675 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE);
1676 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0));
1677 }
1678 /* Set sequence number (already little endian). */
1679 txd->txdseq |= *(uint16_t *)wh->i_seq;
1680
1681 if (!hasqos) {
1682 /* Use HW sequence numbering for non-QoS frames. */
1683 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ);
1684 txd->txdseq |= htole16(0x8000);
1685 } else
1686 txd->txdw4 |= htole32(R92C_TXDW4_QOS);
1687
1688 /* Compute Tx descriptor checksum. */
1689 sum = 0;
1690 for (i = 0; i < sizeof(*txd) / 2; i++)
1691 sum ^= ((uint16_t *)txd)[i];
1692 txd->txdsum = sum; /* NB: already little endian. */
1693
1694 if (ieee80211_radiotap_active_vap(vap)) {
1695 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap;
1696
1697 tap->wt_flags = 0;
1698 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq);
1699 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags);
1700 ieee80211_radiotap_tx(vap, m0);
1701 }
1702
1703 xferlen = sizeof(*txd) + m0->m_pkthdr.len;
1704 m_copydata(m0, 0, m0->m_pkthdr.len, (caddr_t)&txd[1]);
1705
1706 data->buflen = xferlen;
1707 data->ni = ni;
1708 data->m = m0;
1709
1710 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next);
1711 usbd_transfer_start(xfer);
1712 return (0);
1713}
1714
1715static void
1716urtwn_start(struct ifnet *ifp)
1717{
1718 struct urtwn_softc *sc = ifp->if_softc;
1719 struct ieee80211_node *ni;
1720 struct mbuf *m;
1721 struct urtwn_data *bf;
1722
1723 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1724 return;
1725
1726 URTWN_LOCK(sc);
1727 for (;;) {
1728 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
1729 if (m == NULL)
1730 break;
1731 bf = urtwn_getbuf(sc);
1732 if (bf == NULL) {
1733 IFQ_DRV_PREPEND(&ifp->if_snd, m);
1734 break;
1735 }
1736 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
1737 m->m_pkthdr.rcvif = NULL;
1738
1739 if (urtwn_tx_start(sc, ni, m, bf) != 0) {
1740 ifp->if_oerrors++;
1741 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next);
1742 ieee80211_free_node(ni);
1743 break;
1744 }
1745
1746 sc->sc_txtimer = 5;
1747 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc);
1748 }
1749 URTWN_UNLOCK(sc);
1750}
1751
1752static int
1753urtwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1754{
1755 struct ieee80211com *ic = ifp->if_l2com;
1756 struct ifreq *ifr = (struct ifreq *) data;
1757 int error = 0, startall = 0;
1758
1759 switch (cmd) {
1760 case SIOCSIFFLAGS:
1761 if (ifp->if_flags & IFF_UP) {
1762 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1763 urtwn_init(ifp->if_softc);
1764 startall = 1;
1765 }
1766 } else {
1767 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1768 urtwn_stop(ifp, 1);
1769 }
1770 if (startall)
1771 ieee80211_start_all(ic);
1772 break;
1773 case SIOCGIFMEDIA:
1774 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd);
1775 break;
1776 case SIOCGIFADDR:
1777 error = ether_ioctl(ifp, cmd, data);
1778 break;
1779 default:
1780 error = EINVAL;
1781 break;
1782 }
1783 return (error);
1784}
1785
1786static int
1787urtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[],
1788 int ndata, int maxsz)
1789{
1790 int i, error;
1791
1792 for (i = 0; i < ndata; i++) {
1793 struct urtwn_data *dp = &data[i];
1794 dp->sc = sc;
1795 dp->m = NULL;
1796 dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT);
1797 if (dp->buf == NULL) {
1798 device_printf(sc->sc_dev,
1799 "could not allocate buffer\n");
1800 error = ENOMEM;
1801 goto fail;
1802 }
1803 dp->ni = NULL;
1804 }
1805
1806 return (0);
1807fail:
1808 urtwn_free_list(sc, data, ndata);
1809 return (error);
1810}
1811
1812static int
1813urtwn_alloc_rx_list(struct urtwn_softc *sc)
1814{
1815 int error, i;
1816
1817 error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT,
1818 URTWN_RXBUFSZ);
1819 if (error != 0)
1820 return (error);
1821
1822 STAILQ_INIT(&sc->sc_rx_active);
1823 STAILQ_INIT(&sc->sc_rx_inactive);
1824
1825 for (i = 0; i < URTWN_RX_LIST_COUNT; i++)
1826 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next);
1827
1828 return (0);
1829}
1830
1831static int
1832urtwn_alloc_tx_list(struct urtwn_softc *sc)
1833{
1834 int error, i;
1835
1836 error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT,
1837 URTWN_TXBUFSZ);
1838 if (error != 0)
1839 return (error);
1840
1841 STAILQ_INIT(&sc->sc_tx_active);
1842 STAILQ_INIT(&sc->sc_tx_inactive);
1843 STAILQ_INIT(&sc->sc_tx_pending);
1844
1845 for (i = 0; i < URTWN_TX_LIST_COUNT; i++)
1846 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next);
1847
1848 return (0);
1849}
1850
1851static int
1852urtwn_power_on(struct urtwn_softc *sc)
1853{
1854 uint32_t reg;
1855 int ntries;
1856
1857 /* Wait for autoload done bit. */
1858 for (ntries = 0; ntries < 1000; ntries++) {
1859 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN)
1860 break;
1861 DELAY(5);
1862 }
1863 if (ntries == 1000) {
1864 device_printf(sc->sc_dev,
1865 "timeout waiting for chip autoload\n");
1866 return (ETIMEDOUT);
1867 }
1868
1869 /* Unlock ISO/CLK/Power control register. */
1870 urtwn_write_1(sc, R92C_RSV_CTRL, 0);
1871 /* Move SPS into PWM mode. */
1872 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b);
1873 DELAY(100);
1874
1875 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL);
1876 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) {
1877 urtwn_write_1(sc, R92C_LDOV12D_CTRL,
1878 reg | R92C_LDOV12D_CTRL_LDV12_EN);
1879 DELAY(100);
1880 urtwn_write_1(sc, R92C_SYS_ISO_CTRL,
1881 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) &
1882 ~R92C_SYS_ISO_CTRL_MD2PP);
1883 }
1884
1885 /* Auto enable WLAN. */
1886 urtwn_write_2(sc, R92C_APS_FSMCO,
1887 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC);
1888 for (ntries = 0; ntries < 1000; ntries++) {
1889 if (urtwn_read_2(sc, R92C_APS_FSMCO) &
1890 R92C_APS_FSMCO_APFM_ONMAC)
1891 break;
1892 DELAY(5);
1893 }
1894 if (ntries == 1000) {
1895 device_printf(sc->sc_dev,
1896 "timeout waiting for MAC auto ON\n");
1897 return (ETIMEDOUT);
1898 }
1899
1900 /* Enable radio, GPIO and LED functions. */
1901 urtwn_write_2(sc, R92C_APS_FSMCO,
1902 R92C_APS_FSMCO_AFSM_HSUS |
1903 R92C_APS_FSMCO_PDN_EN |
1904 R92C_APS_FSMCO_PFM_ALDN);
1905 /* Release RF digital isolation. */
1906 urtwn_write_2(sc, R92C_SYS_ISO_CTRL,
1907 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR);
1908
1909 /* Initialize MAC. */
1910 urtwn_write_1(sc, R92C_APSD_CTRL,
1911 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF);
1912 for (ntries = 0; ntries < 200; ntries++) {
1913 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) &
1914 R92C_APSD_CTRL_OFF_STATUS))
1915 break;
1916 DELAY(5);
1917 }
1918 if (ntries == 200) {
1919 device_printf(sc->sc_dev,
1920 "timeout waiting for MAC initialization\n");
1921 return (ETIMEDOUT);
1922 }
1923
1924 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
1925 reg = urtwn_read_2(sc, R92C_CR);
1926 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
1927 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN |
1928 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN |
1929 R92C_CR_ENSEC;
1930 urtwn_write_2(sc, R92C_CR, reg);
1931
1932 urtwn_write_1(sc, 0xfe10, 0x19);
1933 return (0);
1934}
1935
1936static int
1937urtwn_llt_init(struct urtwn_softc *sc)
1938{
1939 int i, error;
1940
1941 /* Reserve pages [0; R92C_TX_PAGE_COUNT]. */
1942 for (i = 0; i < R92C_TX_PAGE_COUNT; i++) {
1943 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0)
1944 return (error);
1945 }
1946 /* NB: 0xff indicates end-of-list. */
1947 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0)
1948 return (error);
1949 /*
1950 * Use pages [R92C_TX_PAGE_COUNT + 1; R92C_TXPKTBUF_COUNT - 1]
1951 * as ring buffer.
1952 */
1953 for (++i; i < R92C_TXPKTBUF_COUNT - 1; i++) {
1954 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0)
1955 return (error);
1956 }
1957 /* Make the last page point to the beginning of the ring buffer. */
1958 error = urtwn_llt_write(sc, i, R92C_TX_PAGE_COUNT + 1);
1959 return (error);
1960}
1961
1962static void
1963urtwn_fw_reset(struct urtwn_softc *sc)
1964{
1965 uint16_t reg;
1966 int ntries;
1967
1968 /* Tell 8051 to reset itself. */
1969 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20);
1970
1971 /* Wait until 8051 resets by itself. */
1972 for (ntries = 0; ntries < 100; ntries++) {
1973 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN);
1974 if (!(reg & R92C_SYS_FUNC_EN_CPUEN))
1975 return;
1976 DELAY(50);
1977 }
1978 /* Force 8051 reset. */
1979 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN);
1980}
1981
1982static int
1983urtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len)
1984{
1985 uint32_t reg;
1986 int off, mlen, error = 0;
1987
1988 reg = urtwn_read_4(sc, R92C_MCUFWDL);
1989 reg = RW(reg, R92C_MCUFWDL_PAGE, page);
1990 urtwn_write_4(sc, R92C_MCUFWDL, reg);
1991
1992 off = R92C_FW_START_ADDR;
1993 while (len > 0) {
1994 if (len > 196)
1995 mlen = 196;
1996 else if (len > 4)
1997 mlen = 4;
1998 else
1999 mlen = 1;
2000 /* XXX fix this deconst */
2001 error = urtwn_write_region_1(sc, off,
2002 __DECONST(uint8_t *, buf), mlen);
2003 if (error != 0)
2004 break;
2005 off += mlen;
2006 buf += mlen;
2007 len -= mlen;
2008 }
2009 return (error);
2010}
2011
2012static int
2013urtwn_load_firmware(struct urtwn_softc *sc)
2014{
2015 const struct firmware *fw;
2016 const struct r92c_fw_hdr *hdr;
2017 const char *imagename;
2018 const u_char *ptr;
2019 size_t len;
2020 uint32_t reg;
2021 int mlen, ntries, page, error;
2022
2023 /* Read firmware image from the filesystem. */
2024 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) ==
2025 URTWN_CHIP_UMC_A_CUT)
2026 imagename = "urtwn-rtl8192cfwU";
2027 else
2028 imagename = "urtwn-rtl8192cfwT";
2029
2030 fw = firmware_get(imagename);
2031 if (fw == NULL) {
2032 device_printf(sc->sc_dev,
2033 "failed loadfirmware of file %s\n", imagename);
2034 return (ENOENT);
2035 }
2036
2037 len = fw->datasize;
2038
2039 if (len < sizeof(*hdr)) {
2040 device_printf(sc->sc_dev, "firmware too short\n");
2041 error = EINVAL;
2042 goto fail;
2043 }
2044 ptr = fw->data;
2045 hdr = (const struct r92c_fw_hdr *)ptr;
2046 /* Check if there is a valid FW header and skip it. */
2047 if ((le16toh(hdr->signature) >> 4) == 0x88c ||
2048 (le16toh(hdr->signature) >> 4) == 0x92c) {
2049 DPRINTF("FW V%d.%d %02d-%02d %02d:%02d\n",
2050 le16toh(hdr->version), le16toh(hdr->subversion),
2051 hdr->month, hdr->date, hdr->hour, hdr->minute);
2052 ptr += sizeof(*hdr);
2053 len -= sizeof(*hdr);
2054 }
2055
2056 if (urtwn_read_1(sc, R92C_MCUFWDL) & 0x80) {
2057 urtwn_fw_reset(sc);
2058 urtwn_write_1(sc, R92C_MCUFWDL, 0);
2059 }
2060 urtwn_write_2(sc, R92C_SYS_FUNC_EN,
2061 urtwn_read_2(sc, R92C_SYS_FUNC_EN) |
2062 R92C_SYS_FUNC_EN_CPUEN);
2063 urtwn_write_1(sc, R92C_MCUFWDL,
2064 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN);
2065 urtwn_write_1(sc, R92C_MCUFWDL + 2,
2066 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08);
2067
2068 for (page = 0; len > 0; page++) {
2069 mlen = min(len, R92C_FW_PAGE_SIZE);
2070 error = urtwn_fw_loadpage(sc, page, ptr, mlen);
2071 if (error != 0) {
2072 device_printf(sc->sc_dev,
2073 "could not load firmware page\n");
2074 goto fail;
2075 }
2076 ptr += mlen;
2077 len -= mlen;
2078 }
2079 urtwn_write_1(sc, R92C_MCUFWDL,
2080 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN);
2081 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0);
2082
2083 /* Wait for checksum report. */
2084 for (ntries = 0; ntries < 1000; ntries++) {
2085 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT)
2086 break;
2087 DELAY(5);
2088 }
2089 if (ntries == 1000) {
2090 device_printf(sc->sc_dev,
2091 "timeout waiting for checksum report\n");
2092 error = ETIMEDOUT;
2093 goto fail;
2094 }
2095
2096 reg = urtwn_read_4(sc, R92C_MCUFWDL);
2097 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY;
2098 urtwn_write_4(sc, R92C_MCUFWDL, reg);
2099 /* Wait for firmware readiness. */
2100 for (ntries = 0; ntries < 1000; ntries++) {
2101 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY)
2102 break;
2103 DELAY(5);
2104 }
2105 if (ntries == 1000) {
2106 device_printf(sc->sc_dev,
2107 "timeout waiting for firmware readiness\n");
2108 error = ETIMEDOUT;
2109 goto fail;
2110 }
2111fail:
2112 firmware_put(fw, FIRMWARE_UNLOAD);
2113 return (error);
2114}
2115
2116static int
2117urtwn_dma_init(struct urtwn_softc *sc)
2118{
2119 int hashq, hasnq, haslq, nqueues, nqpages, nrempages;
2120 uint32_t reg;
2121 int error;
2122
2123 /* Initialize LLT table. */
2124 error = urtwn_llt_init(sc);
2125 if (error != 0)
2126 return (error);
2127
2128 /* Get Tx queues to USB endpoints mapping. */
2129 hashq = hasnq = haslq = 0;
2130 reg = urtwn_read_2(sc, R92C_USB_EP + 1);
2131 DPRINTFN(2, "USB endpoints mapping 0x%x\n", reg);
2132 if (MS(reg, R92C_USB_EP_HQ) != 0)
2133 hashq = 1;
2134 if (MS(reg, R92C_USB_EP_NQ) != 0)
2135 hasnq = 1;
2136 if (MS(reg, R92C_USB_EP_LQ) != 0)
2137 haslq = 1;
2138 nqueues = hashq + hasnq + haslq;
2139 if (nqueues == 0)
2140 return (EIO);
2141 /* Get the number of pages for each queue. */
2142 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues;
2143 /* The remaining pages are assigned to the high priority queue. */
2144 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues;
2145
2146 /* Set number of pages for normal priority queue. */
2147 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0);
2148 urtwn_write_4(sc, R92C_RQPN,
2149 /* Set number of pages for public queue. */
2150 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) |
2151 /* Set number of pages for high priority queue. */
2152 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) |
2153 /* Set number of pages for low priority queue. */
2154 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) |
2155 /* Load values. */
2156 R92C_RQPN_LD);
2157
2158 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY);
2159 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY);
2160 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY);
2161 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY);
2162 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY);
2163
2164 /* Set queue to USB pipe mapping. */
2165 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL);
2166 reg &= ~R92C_TRXDMA_CTRL_QMAP_M;
2167 if (nqueues == 1) {
2168 if (hashq)
2169 reg |= R92C_TRXDMA_CTRL_QMAP_HQ;
2170 else if (hasnq)
2171 reg |= R92C_TRXDMA_CTRL_QMAP_NQ;
2172 else
2173 reg |= R92C_TRXDMA_CTRL_QMAP_LQ;
2174 } else if (nqueues == 2) {
2175 /* All 2-endpoints configs have a high priority queue. */
2176 if (!hashq)
2177 return (EIO);
2178 if (hasnq)
2179 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ;
2180 else
2181 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ;
2182 } else
2183 reg |= R92C_TRXDMA_CTRL_QMAP_3EP;
2184 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg);
2185
2186 /* Set Tx/Rx transfer page boundary. */
2187 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff);
2188
2189 /* Set Tx/Rx transfer page size. */
2190 urtwn_write_1(sc, R92C_PBP,
2191 SM(R92C_PBP_PSRX, R92C_PBP_128) |
2192 SM(R92C_PBP_PSTX, R92C_PBP_128));
2193 return (0);
2194}
2195
2196static void
2197urtwn_mac_init(struct urtwn_softc *sc)
2198{
2199 int i;
2200
2201 /* Write MAC initialization values. */
2202 for (i = 0; i < nitems(rtl8192cu_mac); i++)
2203 urtwn_write_1(sc, rtl8192cu_mac[i].reg, rtl8192cu_mac[i].val);
2204}
2205
2206static void
2207urtwn_bb_init(struct urtwn_softc *sc)
2208{
2209 const struct urtwn_bb_prog *prog;
2210 uint32_t reg;
2211 int i;
2212
2213 /* Enable BB and RF. */
2214 urtwn_write_2(sc, R92C_SYS_FUNC_EN,
2215 urtwn_read_2(sc, R92C_SYS_FUNC_EN) |
2216 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST |
2217 R92C_SYS_FUNC_EN_DIO_RF);
2218
2219 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83);
2220
2221 urtwn_write_1(sc, R92C_RF_CTRL,
2222 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB);
2223 urtwn_write_1(sc, R92C_SYS_FUNC_EN,
2224 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD |
2225 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB);
2226
2227 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f);
2228 urtwn_write_1(sc, 0x15, 0xe9);
2229 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80);
2230
2231 /* Select BB programming based on board type. */
2232 if (!(sc->chip & URTWN_CHIP_92C)) {
2233 if (sc->board_type == R92C_BOARD_TYPE_MINICARD)
2234 prog = &rtl8188ce_bb_prog;
2235 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA)
2236 prog = &rtl8188ru_bb_prog;
2237 else
2238 prog = &rtl8188cu_bb_prog;
2239 } else {
2240 if (sc->board_type == R92C_BOARD_TYPE_MINICARD)
2241 prog = &rtl8192ce_bb_prog;
2242 else
2243 prog = &rtl8192cu_bb_prog;
2244 }
2245 /* Write BB initialization values. */
2246 for (i = 0; i < prog->count; i++) {
2247 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]);
2248 DELAY(1);
2249 }
2250
2251 if (sc->chip & URTWN_CHIP_92C_1T2R) {
2252 /* 8192C 1T only configuration. */
2253 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO);
2254 reg = (reg & ~0x00000003) | 0x2;
2255 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg);
2256
2257 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO);
2258 reg = (reg & ~0x00300033) | 0x00200022;
2259 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg);
2260
2261 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING);
2262 reg = (reg & ~0xff000000) | 0x45 << 24;
2263 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg);
2264
2265 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA);
2266 reg = (reg & ~0x000000ff) | 0x23;
2267 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg);
2268
2269 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1);
2270 reg = (reg & ~0x00000030) | 1 << 4;
2271 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg);
2272
2273 reg = urtwn_bb_read(sc, 0xe74);
2274 reg = (reg & ~0x0c000000) | 2 << 26;
2275 urtwn_bb_write(sc, 0xe74, reg);
2276 reg = urtwn_bb_read(sc, 0xe78);
2277 reg = (reg & ~0x0c000000) | 2 << 26;
2278 urtwn_bb_write(sc, 0xe78, reg);
2279 reg = urtwn_bb_read(sc, 0xe7c);
2280 reg = (reg & ~0x0c000000) | 2 << 26;
2281 urtwn_bb_write(sc, 0xe7c, reg);
2282 reg = urtwn_bb_read(sc, 0xe80);
2283 reg = (reg & ~0x0c000000) | 2 << 26;
2284 urtwn_bb_write(sc, 0xe80, reg);
2285 reg = urtwn_bb_read(sc, 0xe88);
2286 reg = (reg & ~0x0c000000) | 2 << 26;
2287 urtwn_bb_write(sc, 0xe88, reg);
2288 }
2289
2290 /* Write AGC values. */
2291 for (i = 0; i < prog->agccount; i++) {
2292 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE,
2293 prog->agcvals[i]);
2294 DELAY(1);
2295 }
2296
2297 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) &
2298 R92C_HSSI_PARAM2_CCK_HIPWR)
2299 sc->sc_flags |= URTWN_FLAG_CCK_HIPWR;
2300}
2301
2302void
2303urtwn_rf_init(struct urtwn_softc *sc)
2304{
2305 const struct urtwn_rf_prog *prog;
2306 uint32_t reg, type;
2307 int i, j, idx, off;
2308
2309 /* Select RF programming based on board type. */
2310 if (!(sc->chip & URTWN_CHIP_92C)) {
2311 if (sc->board_type == R92C_BOARD_TYPE_MINICARD)
2312 prog = rtl8188ce_rf_prog;
2313 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA)
2314 prog = rtl8188ru_rf_prog;
2315 else
2316 prog = rtl8188cu_rf_prog;
2317 } else
2318 prog = rtl8192ce_rf_prog;
2319
2320 for (i = 0; i < sc->nrxchains; i++) {
2321 /* Save RF_ENV control type. */
2322 idx = i / 2;
2323 off = (i % 2) * 16;
2324 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));
2325 type = (reg >> off) & 0x10;
2326
2327 /* Set RF_ENV enable. */
2328 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i));
2329 reg |= 0x100000;
2330 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg);
2331 DELAY(1);
2332 /* Set RF_ENV output high. */
2333 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i));
2334 reg |= 0x10;
2335 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg);
2336 DELAY(1);
2337 /* Set address and data lengths of RF registers. */
2338 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i));
2339 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH;
2340 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg);
2341 DELAY(1);
2342 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i));
2343 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH;
2344 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg);
2345 DELAY(1);
2346
2347 /* Write RF initialization values for this chain. */
2348 for (j = 0; j < prog[i].count; j++) {
2349 if (prog[i].regs[j] >= 0xf9 &&
2350 prog[i].regs[j] <= 0xfe) {
2351 /*
2352 * These are fake RF registers offsets that
2353 * indicate a delay is required.
2354 */
2355 usb_pause_mtx(&sc->sc_mtx, 50);
2356 continue;
2357 }
2358 urtwn_rf_write(sc, i, prog[i].regs[j],
2359 prog[i].vals[j]);
2360 DELAY(1);
2361 }
2362
2363 /* Restore RF_ENV control type. */
2364 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));
2365 reg &= ~(0x10 << off) | (type << off);
2366 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg);
2367
2368 /* Cache RF register CHNLBW. */
2369 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW);
2370 }
2371
2372 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) ==
2373 URTWN_CHIP_UMC_A_CUT) {
2374 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255);
2375 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00);
2376 }
2377}
2378
2379static void
2380urtwn_cam_init(struct urtwn_softc *sc)
2381{
2382 /* Invalidate all CAM entries. */
2383 urtwn_write_4(sc, R92C_CAMCMD,
2384 R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR);
2385}
2386
2387static void
2388urtwn_pa_bias_init(struct urtwn_softc *sc)
2389{
2390 uint8_t reg;
2391 int i;
2392
2393 for (i = 0; i < sc->nrxchains; i++) {
2394 if (sc->pa_setting & (1 << i))
2395 continue;
2396 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406);
2397 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406);
2398 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406);
2399 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406);
2400 }
2401 if (!(sc->pa_setting & 0x10)) {
2402 reg = urtwn_read_1(sc, 0x16);
2403 reg = (reg & ~0xf0) | 0x90;
2404 urtwn_write_1(sc, 0x16, reg);
2405 }
2406}
2407
2408static void
2409urtwn_rxfilter_init(struct urtwn_softc *sc)
2410{
2411 /* Initialize Rx filter. */
2412 /* TODO: use better filter for monitor mode. */
2413 urtwn_write_4(sc, R92C_RCR,
2414 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB |
2415 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL |
2416 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS);
2417 /* Accept all multicast frames. */
2418 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff);
2419 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff);
2420 /* Accept all management frames. */
2421 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff);
2422 /* Reject all control frames. */
2423 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000);
2424 /* Accept all data frames. */
2425 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff);
2426}
2427
2428static void
2429urtwn_edca_init(struct urtwn_softc *sc)
2430{
2431 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a);
2432 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a);
2433 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a);
2434 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a);
2435 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b);
2436 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f);
2437 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324);
2438 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226);
2439}
2440
2441void
2442urtwn_write_txpower(struct urtwn_softc *sc, int chain,
2443 uint16_t power[URTWN_RIDX_COUNT])
2444{
2445 uint32_t reg;
2446
2447 /* Write per-CCK rate Tx power. */
2448 if (chain == 0) {
2449 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32);
2450 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]);
2451 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg);
2452 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
2453 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]);
2454 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]);
2455 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]);
2456 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);
2457 } else {
2458 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32);
2459 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]);
2460 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]);
2461 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]);
2462 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg);
2463 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
2464 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]);
2465 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);
2466 }
2467 /* Write per-OFDM rate Tx power. */
2468 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain),
2469 SM(R92C_TXAGC_RATE06, power[ 4]) |
2470 SM(R92C_TXAGC_RATE09, power[ 5]) |
2471 SM(R92C_TXAGC_RATE12, power[ 6]) |
2472 SM(R92C_TXAGC_RATE18, power[ 7]));
2473 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain),
2474 SM(R92C_TXAGC_RATE24, power[ 8]) |
2475 SM(R92C_TXAGC_RATE36, power[ 9]) |
2476 SM(R92C_TXAGC_RATE48, power[10]) |
2477 SM(R92C_TXAGC_RATE54, power[11]));
2478 /* Write per-MCS Tx power. */
2479 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain),
2480 SM(R92C_TXAGC_MCS00, power[12]) |
2481 SM(R92C_TXAGC_MCS01, power[13]) |
2482 SM(R92C_TXAGC_MCS02, power[14]) |
2483 SM(R92C_TXAGC_MCS03, power[15]));
2484 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain),
2485 SM(R92C_TXAGC_MCS04, power[16]) |
2486 SM(R92C_TXAGC_MCS05, power[17]) |
2487 SM(R92C_TXAGC_MCS06, power[18]) |
2488 SM(R92C_TXAGC_MCS07, power[19]));
2489 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain),
2490 SM(R92C_TXAGC_MCS08, power[20]) |
2491 SM(R92C_TXAGC_MCS08, power[21]) |
2492 SM(R92C_TXAGC_MCS10, power[22]) |
2493 SM(R92C_TXAGC_MCS11, power[23]));
2494 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain),
2495 SM(R92C_TXAGC_MCS12, power[24]) |
2496 SM(R92C_TXAGC_MCS13, power[25]) |
2497 SM(R92C_TXAGC_MCS14, power[26]) |
2498 SM(R92C_TXAGC_MCS15, power[27]));
2499}
2500
2501void
2502urtwn_get_txpower(struct urtwn_softc *sc, int chain,
2503 struct ieee80211_channel *c, struct ieee80211_channel *extc,
2504 uint16_t power[URTWN_RIDX_COUNT])
2505{
2506 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
2507 struct r92c_rom *rom = &sc->rom;
2508 uint16_t cckpow, ofdmpow, htpow, diff, max;
2509 const struct urtwn_txpwr *base;
2510 int ridx, chan, group;
2511
2512 /* Determine channel group. */
2513 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */
2514 if (chan <= 3)
2515 group = 0;
2516 else if (chan <= 9)
2517 group = 1;
2518 else
2519 group = 2;
2520
2521 /* Get original Tx power based on board type and RF chain. */
2522 if (!(sc->chip & URTWN_CHIP_92C)) {
2523 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA)
2524 base = &rtl8188ru_txagc[chain];
2525 else
2526 base = &rtl8192cu_txagc[chain];
2527 } else
2528 base = &rtl8192cu_txagc[chain];
2529
2530 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0]));
2531 if (sc->regulatory == 0) {
2532 for (ridx = 0; ridx <= 3; ridx++)
2533 power[ridx] = base->pwr[0][ridx];
2534 }
2535 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) {
2536 if (sc->regulatory == 3) {
2537 power[ridx] = base->pwr[0][ridx];
2538 /* Apply vendor limits. */
2539 if (extc != NULL)
2540 max = rom->ht40_max_pwr[group];
2541 else
2542 max = rom->ht20_max_pwr[group];
2543 max = (max >> (chain * 4)) & 0xf;
2544 if (power[ridx] > max)
2545 power[ridx] = max;
2546 } else if (sc->regulatory == 1) {
2547 if (extc == NULL)
2548 power[ridx] = base->pwr[group][ridx];
2549 } else if (sc->regulatory != 2)
2550 power[ridx] = base->pwr[0][ridx];
2551 }
2552
2553 /* Compute per-CCK rate Tx power. */
2554 cckpow = rom->cck_tx_pwr[chain][group];
2555 for (ridx = 0; ridx <= 3; ridx++) {
2556 power[ridx] += cckpow;
2557 if (power[ridx] > R92C_MAX_TX_PWR)
2558 power[ridx] = R92C_MAX_TX_PWR;
2559 }
2560
2561 htpow = rom->ht40_1s_tx_pwr[chain][group];
2562 if (sc->ntxchains > 1) {
2563 /* Apply reduction for 2 spatial streams. */
2564 diff = rom->ht40_2s_tx_pwr_diff[group];
2565 diff = (diff >> (chain * 4)) & 0xf;
2566 htpow = (htpow > diff) ? htpow - diff : 0;
2567 }
2568
2569 /* Compute per-OFDM rate Tx power. */
2570 diff = rom->ofdm_tx_pwr_diff[group];
2571 diff = (diff >> (chain * 4)) & 0xf;
2572 ofdmpow = htpow + diff; /* HT->OFDM correction. */
2573 for (ridx = 4; ridx <= 11; ridx++) {
2574 power[ridx] += ofdmpow;
2575 if (power[ridx] > R92C_MAX_TX_PWR)
2576 power[ridx] = R92C_MAX_TX_PWR;
2577 }
2578
2579 /* Compute per-MCS Tx power. */
2580 if (extc == NULL) {
2581 diff = rom->ht20_tx_pwr_diff[group];
2582 diff = (diff >> (chain * 4)) & 0xf;
2583 htpow += diff; /* HT40->HT20 correction. */
2584 }
2585 for (ridx = 12; ridx <= 27; ridx++) {
2586 power[ridx] += htpow;
2587 if (power[ridx] > R92C_MAX_TX_PWR)
2588 power[ridx] = R92C_MAX_TX_PWR;
2589 }
2590#ifdef URTWN_DEBUG
2591 if (urtwn_debug >= 4) {
2592 /* Dump per-rate Tx power values. */
2593 printf("Tx power for chain %d:\n", chain);
2594 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++)
2595 printf("Rate %d = %u\n", ridx, power[ridx]);
2596 }
2597#endif
2598}
2599
2600void
2601urtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c,
2602 struct ieee80211_channel *extc)
2603{
2604 uint16_t power[URTWN_RIDX_COUNT];
2605 int i;
2606
2607 for (i = 0; i < sc->ntxchains; i++) {
2608 /* Compute per-rate Tx power values. */
2609 urtwn_get_txpower(sc, i, c, extc, power);
2610 /* Write per-rate Tx power values to hardware. */
2611 urtwn_write_txpower(sc, i, power);
2612 }
2613}
2614
2615static void
2616urtwn_scan_start(struct ieee80211com *ic)
2617{
2618 /* XXX do nothing? */
2619}
2620
2621static void
2622urtwn_scan_end(struct ieee80211com *ic)
2623{
2624 /* XXX do nothing? */
2625}
2626
2627static void
2628urtwn_set_channel(struct ieee80211com *ic)
2629{
2630 struct urtwn_softc *sc = ic->ic_ifp->if_softc;
2631
2632 URTWN_LOCK(sc);
2633 urtwn_set_chan(sc, ic->ic_curchan, NULL);
2634 URTWN_UNLOCK(sc);
2635}
2636
2637static void
2638urtwn_update_mcast(struct ifnet *ifp)
2639{
2640 /* XXX do nothing? */
2641}
2642
2643static void
2644urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c,
2645 struct ieee80211_channel *extc)
2646{
2647 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
2648 uint32_t reg;
2649 u_int chan;
2650 int i;
2651
2652 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */
2653 if (chan == 0 || chan == IEEE80211_CHAN_ANY) {
2654 device_printf(sc->sc_dev,
2655 "%s: invalid channel %x\n", __func__, chan);
2656 return;
2657 }
2658
2659 /* Set Tx power for this new channel. */
2660 urtwn_set_txpower(sc, c, extc);
2661
2662 for (i = 0; i < sc->nrxchains; i++) {
2663 urtwn_rf_write(sc, i, R92C_RF_CHNLBW,
2664 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan));
2665 }
2666#ifndef IEEE80211_NO_HT
2667 if (extc != NULL) {
2668 /* Is secondary channel below or above primary? */
2669 int prichlo = c->ic_freq < extc->ic_freq;
2670
2671 urtwn_write_1(sc, R92C_BWOPMODE,
2672 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ);
2673
2674 reg = urtwn_read_1(sc, R92C_RRSR + 2);
2675 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5;
2676 urtwn_write_1(sc, R92C_RRSR + 2, reg);
2677
2678 urtwn_bb_write(sc, R92C_FPGA0_RFMOD,
2679 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ);
2680 urtwn_bb_write(sc, R92C_FPGA1_RFMOD,
2681 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ);
2682
2683 /* Set CCK side band. */
2684 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM);
2685 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4;
2686 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg);
2687
2688 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF);
2689 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10;
2690 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg);
2691
2692 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2,
2693 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) &
2694 ~R92C_FPGA0_ANAPARAM2_CBW20);
2695
2696 reg = urtwn_bb_read(sc, 0x818);
2697 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26;
2698 urtwn_bb_write(sc, 0x818, reg);
2699
2700 /* Select 40MHz bandwidth. */
2701 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW,
2702 (sc->rf_chnlbw[0] & ~0xfff) | chan);
2703 } else
2704#endif
2705 {
2706 urtwn_write_1(sc, R92C_BWOPMODE,
2707 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ);
2708
2709 urtwn_bb_write(sc, R92C_FPGA0_RFMOD,
2710 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ);
2711 urtwn_bb_write(sc, R92C_FPGA1_RFMOD,
2712 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ);
2713
2714 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2,
2715 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) |
2716 R92C_FPGA0_ANAPARAM2_CBW20);
2717
2718 /* Select 20MHz bandwidth. */
2719 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW,
2720 (sc->rf_chnlbw[0] & ~0xfff) | R92C_RF_CHNLBW_BW20 | chan);
2721 }
2722}
2723
2724static void
2725urtwn_iq_calib(struct urtwn_softc *sc)
2726{
2727 /* TODO */
2728}
2729
2730static void
2731urtwn_lc_calib(struct urtwn_softc *sc)
2732{
2733 uint32_t rf_ac[2];
2734 uint8_t txmode;
2735 int i;
2736
2737 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3);
2738 if ((txmode & 0x70) != 0) {
2739 /* Disable all continuous Tx. */
2740 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70);
2741
2742 /* Set RF mode to standby mode. */
2743 for (i = 0; i < sc->nrxchains; i++) {
2744 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC);
2745 urtwn_rf_write(sc, i, R92C_RF_AC,
2746 RW(rf_ac[i], R92C_RF_AC_MODE,
2747 R92C_RF_AC_MODE_STANDBY));
2748 }
2749 } else {
2750 /* Block all Tx queues. */
2751 urtwn_write_1(sc, R92C_TXPAUSE, 0xff);
2752 }
2753 /* Start calibration. */
2754 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW,
2755 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART);
2756
2757 /* Give calibration the time to complete. */
2758 usb_pause_mtx(&sc->sc_mtx, 100);
2759
2760 /* Restore configuration. */
2761 if ((txmode & 0x70) != 0) {
2762 /* Restore Tx mode. */
2763 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode);
2764 /* Restore RF mode. */
2765 for (i = 0; i < sc->nrxchains; i++)
2766 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]);
2767 } else {
2768 /* Unblock all Tx queues. */
2769 urtwn_write_1(sc, R92C_TXPAUSE, 0x00);
2770 }
2771}
2772
2773static void
2774urtwn_init_locked(void *arg)
2775{
2776 struct urtwn_softc *sc = arg;
2777 struct ifnet *ifp = sc->sc_ifp;
2778 uint32_t reg;
2779 int error;
2780
2781 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2782 urtwn_stop_locked(ifp, 0);
2783
2784 /* Init firmware commands ring. */
2785 sc->fwcur = 0;
2786
2787 /* Allocate Tx/Rx buffers. */
2788 error = urtwn_alloc_rx_list(sc);
2789 if (error != 0)
2790 goto fail;
2791
2792 error = urtwn_alloc_tx_list(sc);
2793 if (error != 0)
2794 goto fail;
2795
2796 /* Power on adapter. */
2797 error = urtwn_power_on(sc);
2798 if (error != 0)
2799 goto fail;
2800
2801 /* Initialize DMA. */
2802 error = urtwn_dma_init(sc);
2803 if (error != 0)
2804 goto fail;
2805
2806 /* Set info size in Rx descriptors (in 64-bit words). */
2807 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4);
2808
2809 /* Init interrupts. */
2810 urtwn_write_4(sc, R92C_HISR, 0xffffffff);
2811 urtwn_write_4(sc, R92C_HIMR, 0xffffffff);
2812
2813 /* Set MAC address. */
2814 urtwn_write_region_1(sc, R92C_MACID, IF_LLADDR(ifp),
2815 IEEE80211_ADDR_LEN);
2816
2817 /* Set initial network type. */
2818 reg = urtwn_read_4(sc, R92C_CR);
2819 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA);
2820 urtwn_write_4(sc, R92C_CR, reg);
2821
2822 urtwn_rxfilter_init(sc);
2823
2824 reg = urtwn_read_4(sc, R92C_RRSR);
2825 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M);
2826 urtwn_write_4(sc, R92C_RRSR, reg);
2827
2828 /* Set short/long retry limits. */
2829 urtwn_write_2(sc, R92C_RL,
2830 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30));
2831
2832 /* Initialize EDCA parameters. */
2833 urtwn_edca_init(sc);
2834
2835 /* Setup rate fallback. */
2836 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000);
2837 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404);
2838 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201);
2839 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605);
2840
2841 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL,
2842 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) |
2843 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW);
2844 /* Set ACK timeout. */
2845 urtwn_write_1(sc, R92C_ACKTO, 0x40);
2846
2847 /* Setup USB aggregation. */
2848 reg = urtwn_read_4(sc, R92C_TDECTRL);
2849 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6);
2850 urtwn_write_4(sc, R92C_TDECTRL, reg);
2851 urtwn_write_1(sc, R92C_TRXDMA_CTRL,
2852 urtwn_read_1(sc, R92C_TRXDMA_CTRL) |
2853 R92C_TRXDMA_CTRL_RXDMA_AGG_EN);
2854 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION,
2855 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) |
2856 R92C_USB_SPECIAL_OPTION_AGG_EN);
2857 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48);
2858 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4);
2859 urtwn_write_1(sc, R92C_USB_AGG_TH, 8);
2860 urtwn_write_1(sc, R92C_USB_AGG_TO, 6);
2861
2862 /* Initialize beacon parameters. */
2863 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404);
2864 urtwn_write_1(sc, R92C_DRVERLYINT, 0x05);
2865 urtwn_write_1(sc, R92C_BCNDMATIM, 0x02);
2866 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f);
2867
2868 /* Setup AMPDU aggregation. */
2869 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */
2870 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16);
2871 urtwn_write_2(sc, 0x4ca, 0x0708);
2872
2873 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff);
2874 urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0);
2875
2876 /* Load 8051 microcode. */
2877 error = urtwn_load_firmware(sc);
2878 if (error != 0)
2879 goto fail;
2880
2881 /* Initialize MAC/BB/RF blocks. */
2882 urtwn_mac_init(sc);
2883 urtwn_bb_init(sc);
2884 urtwn_rf_init(sc);
2885
2886 /* Turn CCK and OFDM blocks on. */
2887 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD);
2888 reg |= R92C_RFMOD_CCK_EN;
2889 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg);
2890 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD);
2891 reg |= R92C_RFMOD_OFDM_EN;
2892 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg);
2893
2894 /* Clear per-station keys table. */
2895 urtwn_cam_init(sc);
2896
2897 /* Enable hardware sequence numbering. */
2898 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff);
2899
2900 /* Perform LO and IQ calibrations. */
2901 urtwn_iq_calib(sc);
2902 /* Perform LC calibration. */
2903 urtwn_lc_calib(sc);
2904
2905 /* Fix USB interference issue. */
2906 urtwn_write_1(sc, 0xfe40, 0xe0);
2907 urtwn_write_1(sc, 0xfe41, 0x8d);
2908 urtwn_write_1(sc, 0xfe42, 0x80);
2909
2910 urtwn_pa_bias_init(sc);
2911
2912 /* Initialize GPIO setting. */
2913 urtwn_write_1(sc, R92C_GPIO_MUXCFG,
2914 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT);
2915
2916 /* Fix for lower temperature. */
2917 urtwn_write_1(sc, 0x15, 0xe9);
2918
2919 usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]);
2920
2921 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2922 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2923
2924 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc);
2925fail:
2926 return;
2927}
2928
2929static void
2930urtwn_init(void *arg)
2931{
2932 struct urtwn_softc *sc = arg;
2933
2934 URTWN_LOCK(sc);
2935 urtwn_init_locked(arg);
2936 URTWN_UNLOCK(sc);
2937}
2938
2939static void
2940urtwn_stop_locked(struct ifnet *ifp, int disable)
2941{
2942 struct urtwn_softc *sc = ifp->if_softc;
2943
2944 (void)disable;
2945 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2946
2947 callout_stop(&sc->sc_watchdog_ch);
2948 urtwn_abort_xfers(sc);
2949}
2950
2951static void
2952urtwn_stop(struct ifnet *ifp, int disable)
2953{
2954 struct urtwn_softc *sc = ifp->if_softc;
2955
2956 URTWN_LOCK(sc);
2957 urtwn_stop_locked(ifp, disable);
2958 URTWN_UNLOCK(sc);
2959}
2960
2961static void
2962urtwn_abort_xfers(struct urtwn_softc *sc)
2963{
2964 int i;
2965
2966 URTWN_ASSERT_LOCKED(sc);
2967
2968 /* abort any pending transfers */
2969 for (i = 0; i < URTWN_N_TRANSFER; i++)
2970 usbd_transfer_stop(sc->sc_xfer[i]);
2971}
2972
2973static int
2974urtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
2975 const struct ieee80211_bpf_params *params)
2976{
2977 struct ieee80211com *ic = ni->ni_ic;
2978 struct ifnet *ifp = ic->ic_ifp;
2979 struct urtwn_softc *sc = ifp->if_softc;
2980 struct urtwn_data *bf;
2981
2982 /* prevent management frames from being sent if we're not ready */
2983 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
2984 m_freem(m);
2985 ieee80211_free_node(ni);
2986 return (ENETDOWN);
2987 }
2988 URTWN_LOCK(sc);
2989 bf = urtwn_getbuf(sc);
2990 if (bf == NULL) {
2991 ieee80211_free_node(ni);
2992 m_freem(m);
2993 URTWN_UNLOCK(sc);
2994 return (ENOBUFS);
2995 }
2996
2997 ifp->if_opackets++;
2998 if (urtwn_tx_start(sc, ni, m, bf) != 0) {
2999 ieee80211_free_node(ni);
3000 ifp->if_oerrors++;
3001 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next);
3002 URTWN_UNLOCK(sc);
3003 return (EIO);
3004 }
3005 URTWN_UNLOCK(sc);
3006
3007 sc->sc_txtimer = 5;
3008 return (0);
3009}
3010
3011static device_method_t urtwn_methods[] = {
3012 /* Device interface */
3013 DEVMETHOD(device_probe, urtwn_match),
3014 DEVMETHOD(device_attach, urtwn_attach),
3015 DEVMETHOD(device_detach, urtwn_detach),
3016
3017 { 0, 0 }
3018};
3019
3020static driver_t urtwn_driver = {
3021 "urtwn",
3022 urtwn_methods,
3023 sizeof(struct urtwn_softc)
3024};
3025
3026static devclass_t urtwn_devclass;
3027
3028DRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL);
3029MODULE_DEPEND(urtwn, usb, 1, 1, 1);
3030MODULE_DEPEND(urtwn, wlan, 1, 1, 1);
3031MODULE_DEPEND(urtwn, firmware, 1, 1, 1);
| 21
22/*
23 * Driver for Realtek RTL8188CE-VAU/RTL8188CUS/RTL8188RU/RTL8192CU.
24 */
25
26#include <sys/param.h>
27#include <sys/sockio.h>
28#include <sys/sysctl.h>
29#include <sys/lock.h>
30#include <sys/mutex.h>
31#include <sys/mbuf.h>
32#include <sys/kernel.h>
33#include <sys/socket.h>
34#include <sys/systm.h>
35#include <sys/malloc.h>
36#include <sys/module.h>
37#include <sys/bus.h>
38#include <sys/endian.h>
39#include <sys/linker.h>
40#include <sys/firmware.h>
41#include <sys/kdb.h>
42
43#include <machine/bus.h>
44#include <machine/resource.h>
45#include <sys/rman.h>
46
47#include <net/bpf.h>
48#include <net/if.h>
49#include <net/if_arp.h>
50#include <net/ethernet.h>
51#include <net/if_dl.h>
52#include <net/if_media.h>
53#include <net/if_types.h>
54
55#include <netinet/in.h>
56#include <netinet/in_systm.h>
57#include <netinet/in_var.h>
58#include <netinet/if_ether.h>
59#include <netinet/ip.h>
60
61#include <net80211/ieee80211_var.h>
62#include <net80211/ieee80211_regdomain.h>
63#include <net80211/ieee80211_radiotap.h>
64#include <net80211/ieee80211_ratectl.h>
65
66#include <dev/usb/usb.h>
67#include <dev/usb/usbdi.h>
68#include "usbdevs.h"
69
70#define USB_DEBUG_VAR urtwn_debug
71#include <dev/usb/usb_debug.h>
72
73#include <dev/usb/wlan/if_urtwnreg.h>
74
75#ifdef USB_DEBUG
76static int urtwn_debug = 0;
77
78SYSCTL_NODE(_hw_usb, OID_AUTO, urtwn, CTLFLAG_RW, 0, "USB urtwn");
79SYSCTL_INT(_hw_usb_urtwn, OID_AUTO, debug, CTLFLAG_RW, &urtwn_debug, 0,
80 "Debug level");
81#endif
82
83#define URTWN_RSSI(r) (r) - 110
84#define IEEE80211_HAS_ADDR4(wh) \
85 (((wh)->i_fc[1] & IEEE80211_FC1_DIR_MASK) == IEEE80211_FC1_DIR_DSTODS)
86
87/* various supported device vendors/products */
88static const STRUCT_USB_HOST_ID urtwn_devs[] = {
89#define URTWN_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) }
90 URTWN_DEV(ABOCOM, RTL8188CU_1),
91 URTWN_DEV(ABOCOM, RTL8188CU_2),
92 URTWN_DEV(ABOCOM, RTL8192CU),
93 URTWN_DEV(ASUS, RTL8192CU),
94 URTWN_DEV(AZUREWAVE, RTL8188CE_1),
95 URTWN_DEV(AZUREWAVE, RTL8188CE_2),
96 URTWN_DEV(AZUREWAVE, RTL8188CU),
97 URTWN_DEV(BELKIN, F7D2102),
98 URTWN_DEV(BELKIN, RTL8188CU),
99 URTWN_DEV(BELKIN, RTL8192CU),
100 URTWN_DEV(CHICONY, RTL8188CUS_1),
101 URTWN_DEV(CHICONY, RTL8188CUS_2),
102 URTWN_DEV(CHICONY, RTL8188CUS_3),
103 URTWN_DEV(CHICONY, RTL8188CUS_4),
104 URTWN_DEV(CHICONY, RTL8188CUS_5),
105 URTWN_DEV(COREGA, RTL8192CU),
106 URTWN_DEV(DLINK, RTL8188CU),
107 URTWN_DEV(DLINK, RTL8192CU_1),
108 URTWN_DEV(DLINK, RTL8192CU_2),
109 URTWN_DEV(DLINK, RTL8192CU_3),
110 URTWN_DEV(DLINK, DWA131B),
111 URTWN_DEV(EDIMAX, EW7811UN),
112 URTWN_DEV(EDIMAX, RTL8192CU),
113 URTWN_DEV(FEIXUN, RTL8188CU),
114 URTWN_DEV(FEIXUN, RTL8192CU),
115 URTWN_DEV(GUILLEMOT, HWNUP150),
116 URTWN_DEV(HAWKING, RTL8192CU),
117 URTWN_DEV(HP3, RTL8188CU),
118 URTWN_DEV(NETGEAR, WNA1000M),
119 URTWN_DEV(NETGEAR, RTL8192CU),
120 URTWN_DEV(NETGEAR4, RTL8188CU),
121 URTWN_DEV(NOVATECH, RTL8188CU),
122 URTWN_DEV(PLANEX2, RTL8188CU_1),
123 URTWN_DEV(PLANEX2, RTL8188CU_2),
124 URTWN_DEV(PLANEX2, RTL8188CU_3),
125 URTWN_DEV(PLANEX2, RTL8188CU_4),
126 URTWN_DEV(PLANEX2, RTL8188CUS),
127 URTWN_DEV(PLANEX2, RTL8192CU),
128 URTWN_DEV(REALTEK, RTL8188CE_0),
129 URTWN_DEV(REALTEK, RTL8188CE_1),
130 URTWN_DEV(REALTEK, RTL8188CTV),
131 URTWN_DEV(REALTEK, RTL8188CU_0),
132 URTWN_DEV(REALTEK, RTL8188CU_1),
133 URTWN_DEV(REALTEK, RTL8188CU_2),
134 URTWN_DEV(REALTEK, RTL8188CU_COMBO),
135 URTWN_DEV(REALTEK, RTL8188CUS),
136 URTWN_DEV(REALTEK, RTL8188RU_1),
137 URTWN_DEV(REALTEK, RTL8188RU_2),
138 URTWN_DEV(REALTEK, RTL8191CU),
139 URTWN_DEV(REALTEK, RTL8192CE),
140 URTWN_DEV(REALTEK, RTL8192CU),
141 URTWN_DEV(SITECOMEU, RTL8188CU_1),
142 URTWN_DEV(SITECOMEU, RTL8188CU_2),
143 URTWN_DEV(SITECOMEU, RTL8192CU),
144 URTWN_DEV(TRENDNET, RTL8188CU),
145 URTWN_DEV(TRENDNET, RTL8192CU),
146 URTWN_DEV(ZYXEL, RTL8192CU),
147#undef URTWN_DEV
148};
149
150static device_probe_t urtwn_match;
151static device_attach_t urtwn_attach;
152static device_detach_t urtwn_detach;
153
154static usb_callback_t urtwn_bulk_tx_callback;
155static usb_callback_t urtwn_bulk_rx_callback;
156
157static usb_error_t urtwn_do_request(struct urtwn_softc *sc,
158 struct usb_device_request *req, void *data);
159static struct ieee80211vap *urtwn_vap_create(struct ieee80211com *,
160 const char [IFNAMSIZ], int, enum ieee80211_opmode, int,
161 const uint8_t [IEEE80211_ADDR_LEN],
162 const uint8_t [IEEE80211_ADDR_LEN]);
163static void urtwn_vap_delete(struct ieee80211vap *);
164static struct mbuf * urtwn_rx_frame(struct urtwn_softc *, uint8_t *, int,
165 int *);
166static struct mbuf * urtwn_rxeof(struct usb_xfer *, struct urtwn_data *,
167 int *, int8_t *);
168static void urtwn_txeof(struct usb_xfer *, struct urtwn_data *);
169static int urtwn_alloc_list(struct urtwn_softc *,
170 struct urtwn_data[], int, int);
171static int urtwn_alloc_rx_list(struct urtwn_softc *);
172static int urtwn_alloc_tx_list(struct urtwn_softc *);
173static void urtwn_free_tx_list(struct urtwn_softc *);
174static void urtwn_free_rx_list(struct urtwn_softc *);
175static void urtwn_free_list(struct urtwn_softc *,
176 struct urtwn_data data[], int);
177static struct urtwn_data * _urtwn_getbuf(struct urtwn_softc *);
178static struct urtwn_data * urtwn_getbuf(struct urtwn_softc *);
179static int urtwn_write_region_1(struct urtwn_softc *, uint16_t,
180 uint8_t *, int);
181static void urtwn_write_1(struct urtwn_softc *, uint16_t, uint8_t);
182static void urtwn_write_2(struct urtwn_softc *, uint16_t, uint16_t);
183static void urtwn_write_4(struct urtwn_softc *, uint16_t, uint32_t);
184static int urtwn_read_region_1(struct urtwn_softc *, uint16_t,
185 uint8_t *, int);
186static uint8_t urtwn_read_1(struct urtwn_softc *, uint16_t);
187static uint16_t urtwn_read_2(struct urtwn_softc *, uint16_t);
188static uint32_t urtwn_read_4(struct urtwn_softc *, uint16_t);
189static int urtwn_fw_cmd(struct urtwn_softc *, uint8_t,
190 const void *, int);
191static void urtwn_rf_write(struct urtwn_softc *, int, uint8_t,
192 uint32_t);
193static uint32_t urtwn_rf_read(struct urtwn_softc *, int, uint8_t);
194static int urtwn_llt_write(struct urtwn_softc *, uint32_t,
195 uint32_t);
196static uint8_t urtwn_efuse_read_1(struct urtwn_softc *, uint16_t);
197static void urtwn_efuse_read(struct urtwn_softc *);
198static int urtwn_read_chipid(struct urtwn_softc *);
199static void urtwn_read_rom(struct urtwn_softc *);
200static int urtwn_ra_init(struct urtwn_softc *);
201static void urtwn_tsf_sync_enable(struct urtwn_softc *);
202static void urtwn_set_led(struct urtwn_softc *, int, int);
203static int urtwn_newstate(struct ieee80211vap *,
204 enum ieee80211_state, int);
205static void urtwn_watchdog(void *);
206static void urtwn_update_avgrssi(struct urtwn_softc *, int, int8_t);
207static int8_t urtwn_get_rssi(struct urtwn_softc *, int, void *);
208static int urtwn_tx_start(struct urtwn_softc *,
209 struct ieee80211_node *, struct mbuf *,
210 struct urtwn_data *);
211static void urtwn_start(struct ifnet *);
212static int urtwn_ioctl(struct ifnet *, u_long, caddr_t);
213static int urtwn_power_on(struct urtwn_softc *);
214static int urtwn_llt_init(struct urtwn_softc *);
215static void urtwn_fw_reset(struct urtwn_softc *);
216static int urtwn_fw_loadpage(struct urtwn_softc *, int,
217 const uint8_t *, int);
218static int urtwn_load_firmware(struct urtwn_softc *);
219static int urtwn_dma_init(struct urtwn_softc *);
220static void urtwn_mac_init(struct urtwn_softc *);
221static void urtwn_bb_init(struct urtwn_softc *);
222static void urtwn_rf_init(struct urtwn_softc *);
223static void urtwn_cam_init(struct urtwn_softc *);
224static void urtwn_pa_bias_init(struct urtwn_softc *);
225static void urtwn_rxfilter_init(struct urtwn_softc *);
226static void urtwn_edca_init(struct urtwn_softc *);
227static void urtwn_write_txpower(struct urtwn_softc *, int,
228 uint16_t[]);
229static void urtwn_get_txpower(struct urtwn_softc *, int,
230 struct ieee80211_channel *,
231 struct ieee80211_channel *, uint16_t[]);
232static void urtwn_set_txpower(struct urtwn_softc *,
233 struct ieee80211_channel *,
234 struct ieee80211_channel *);
235static void urtwn_scan_start(struct ieee80211com *);
236static void urtwn_scan_end(struct ieee80211com *);
237static void urtwn_set_channel(struct ieee80211com *);
238static void urtwn_set_chan(struct urtwn_softc *,
239 struct ieee80211_channel *,
240 struct ieee80211_channel *);
241static void urtwn_update_mcast(struct ifnet *);
242static void urtwn_iq_calib(struct urtwn_softc *);
243static void urtwn_lc_calib(struct urtwn_softc *);
244static void urtwn_init(void *);
245static void urtwn_init_locked(void *);
246static void urtwn_stop(struct ifnet *, int);
247static void urtwn_stop_locked(struct ifnet *, int);
248static void urtwn_abort_xfers(struct urtwn_softc *);
249static int urtwn_raw_xmit(struct ieee80211_node *, struct mbuf *,
250 const struct ieee80211_bpf_params *);
251
252/* Aliases. */
253#define urtwn_bb_write urtwn_write_4
254#define urtwn_bb_read urtwn_read_4
255
256static const struct usb_config urtwn_config[URTWN_N_TRANSFER] = {
257 [URTWN_BULK_RX] = {
258 .type = UE_BULK,
259 .endpoint = UE_ADDR_ANY,
260 .direction = UE_DIR_IN,
261 .bufsize = URTWN_RXBUFSZ,
262 .flags = {
263 .pipe_bof = 1,
264 .short_xfer_ok = 1
265 },
266 .callback = urtwn_bulk_rx_callback,
267 },
268 [URTWN_BULK_TX_BE] = {
269 .type = UE_BULK,
270 .endpoint = 0x03,
271 .direction = UE_DIR_OUT,
272 .bufsize = URTWN_TXBUFSZ,
273 .flags = {
274 .ext_buffer = 1,
275 .pipe_bof = 1,
276 .force_short_xfer = 1
277 },
278 .callback = urtwn_bulk_tx_callback,
279 .timeout = URTWN_TX_TIMEOUT, /* ms */
280 },
281 [URTWN_BULK_TX_BK] = {
282 .type = UE_BULK,
283 .endpoint = 0x03,
284 .direction = UE_DIR_OUT,
285 .bufsize = URTWN_TXBUFSZ,
286 .flags = {
287 .ext_buffer = 1,
288 .pipe_bof = 1,
289 .force_short_xfer = 1,
290 },
291 .callback = urtwn_bulk_tx_callback,
292 .timeout = URTWN_TX_TIMEOUT, /* ms */
293 },
294 [URTWN_BULK_TX_VI] = {
295 .type = UE_BULK,
296 .endpoint = 0x02,
297 .direction = UE_DIR_OUT,
298 .bufsize = URTWN_TXBUFSZ,
299 .flags = {
300 .ext_buffer = 1,
301 .pipe_bof = 1,
302 .force_short_xfer = 1
303 },
304 .callback = urtwn_bulk_tx_callback,
305 .timeout = URTWN_TX_TIMEOUT, /* ms */
306 },
307 [URTWN_BULK_TX_VO] = {
308 .type = UE_BULK,
309 .endpoint = 0x02,
310 .direction = UE_DIR_OUT,
311 .bufsize = URTWN_TXBUFSZ,
312 .flags = {
313 .ext_buffer = 1,
314 .pipe_bof = 1,
315 .force_short_xfer = 1
316 },
317 .callback = urtwn_bulk_tx_callback,
318 .timeout = URTWN_TX_TIMEOUT, /* ms */
319 },
320};
321
322static int
323urtwn_match(device_t self)
324{
325 struct usb_attach_arg *uaa = device_get_ivars(self);
326
327 if (uaa->usb_mode != USB_MODE_HOST)
328 return (ENXIO);
329 if (uaa->info.bConfigIndex != URTWN_CONFIG_INDEX)
330 return (ENXIO);
331 if (uaa->info.bIfaceIndex != URTWN_IFACE_INDEX)
332 return (ENXIO);
333
334 return (usbd_lookup_id_by_uaa(urtwn_devs, sizeof(urtwn_devs), uaa));
335}
336
337static int
338urtwn_attach(device_t self)
339{
340 struct usb_attach_arg *uaa = device_get_ivars(self);
341 struct urtwn_softc *sc = device_get_softc(self);
342 struct ifnet *ifp;
343 struct ieee80211com *ic;
344 uint8_t iface_index, bands;
345 int error;
346
347 device_set_usb_desc(self);
348 sc->sc_udev = uaa->device;
349 sc->sc_dev = self;
350
351 mtx_init(&sc->sc_mtx, device_get_nameunit(self),
352 MTX_NETWORK_LOCK, MTX_DEF);
353 callout_init(&sc->sc_watchdog_ch, 0);
354
355 iface_index = URTWN_IFACE_INDEX;
356 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer,
357 urtwn_config, URTWN_N_TRANSFER, sc, &sc->sc_mtx);
358 if (error) {
359 device_printf(self, "could not allocate USB transfers, "
360 "err=%s\n", usbd_errstr(error));
361 goto detach;
362 }
363
364 URTWN_LOCK(sc);
365
366 error = urtwn_read_chipid(sc);
367 if (error) {
368 device_printf(sc->sc_dev, "unsupported test chip\n");
369 URTWN_UNLOCK(sc);
370 goto detach;
371 }
372
373 /* Determine number of Tx/Rx chains. */
374 if (sc->chip & URTWN_CHIP_92C) {
375 sc->ntxchains = (sc->chip & URTWN_CHIP_92C_1T2R) ? 1 : 2;
376 sc->nrxchains = 2;
377 } else {
378 sc->ntxchains = 1;
379 sc->nrxchains = 1;
380 }
381 urtwn_read_rom(sc);
382
383 device_printf(sc->sc_dev, "MAC/BB RTL%s, RF 6052 %dT%dR\n",
384 (sc->chip & URTWN_CHIP_92C) ? "8192CU" :
385 (sc->board_type == R92C_BOARD_TYPE_HIGHPA) ? "8188RU" :
386 (sc->board_type == R92C_BOARD_TYPE_MINICARD) ? "8188CE-VAU" :
387 "8188CUS", sc->ntxchains, sc->nrxchains);
388
389 URTWN_UNLOCK(sc);
390
391 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211);
392 if (ifp == NULL) {
393 device_printf(sc->sc_dev, "can not if_alloc()\n");
394 goto detach;
395 }
396 ic = ifp->if_l2com;
397
398 ifp->if_softc = sc;
399 if_initname(ifp, "urtwn", device_get_unit(sc->sc_dev));
400 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
401 ifp->if_init = urtwn_init;
402 ifp->if_ioctl = urtwn_ioctl;
403 ifp->if_start = urtwn_start;
404 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
405 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
406 IFQ_SET_READY(&ifp->if_snd);
407
408 ic->ic_ifp = ifp;
409 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
410 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
411
412 /* set device capabilities */
413 ic->ic_caps =
414 IEEE80211_C_STA /* station mode */
415 | IEEE80211_C_MONITOR /* monitor mode */
416 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
417 | IEEE80211_C_SHSLOT /* short slot time supported */
418 | IEEE80211_C_BGSCAN /* capable of bg scanning */
419 | IEEE80211_C_WPA /* 802.11i */
420 ;
421
422 ic->ic_cryptocaps =
423 IEEE80211_CRYPTO_WEP |
424 IEEE80211_CRYPTO_AES_CCM |
425 IEEE80211_CRYPTO_TKIPMIC |
426 IEEE80211_CRYPTO_TKIP;
427
428 bands = 0;
429 setbit(&bands, IEEE80211_MODE_11B);
430 setbit(&bands, IEEE80211_MODE_11G);
431 ieee80211_init_channels(ic, NULL, &bands);
432
433 ieee80211_ifattach(ic, sc->sc_bssid);
434 ic->ic_raw_xmit = urtwn_raw_xmit;
435 ic->ic_scan_start = urtwn_scan_start;
436 ic->ic_scan_end = urtwn_scan_end;
437 ic->ic_set_channel = urtwn_set_channel;
438
439 ic->ic_vap_create = urtwn_vap_create;
440 ic->ic_vap_delete = urtwn_vap_delete;
441 ic->ic_update_mcast = urtwn_update_mcast;
442
443 ieee80211_radiotap_attach(ic, &sc->sc_txtap.wt_ihdr,
444 sizeof(sc->sc_txtap), URTWN_TX_RADIOTAP_PRESENT,
445 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap),
446 URTWN_RX_RADIOTAP_PRESENT);
447
448 if (bootverbose)
449 ieee80211_announce(ic);
450
451 return (0);
452
453detach:
454 urtwn_detach(self);
455 return (ENXIO); /* failure */
456}
457
458static int
459urtwn_detach(device_t self)
460{
461 struct urtwn_softc *sc = device_get_softc(self);
462 struct ifnet *ifp = sc->sc_ifp;
463 struct ieee80211com *ic = ifp->if_l2com;
464
465 if (!device_is_attached(self))
466 return (0);
467
468 urtwn_stop(ifp, 1);
469
470 callout_drain(&sc->sc_watchdog_ch);
471
472 /* stop all USB transfers */
473 usbd_transfer_unsetup(sc->sc_xfer, URTWN_N_TRANSFER);
474 ieee80211_ifdetach(ic);
475
476 urtwn_free_tx_list(sc);
477 urtwn_free_rx_list(sc);
478
479 if_free(ifp);
480 mtx_destroy(&sc->sc_mtx);
481
482 return (0);
483}
484
485static void
486urtwn_free_tx_list(struct urtwn_softc *sc)
487{
488 urtwn_free_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT);
489}
490
491static void
492urtwn_free_rx_list(struct urtwn_softc *sc)
493{
494 urtwn_free_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT);
495}
496
497static void
498urtwn_free_list(struct urtwn_softc *sc, struct urtwn_data data[], int ndata)
499{
500 int i;
501
502 for (i = 0; i < ndata; i++) {
503 struct urtwn_data *dp = &data[i];
504
505 if (dp->buf != NULL) {
506 free(dp->buf, M_USBDEV);
507 dp->buf = NULL;
508 }
509 if (dp->ni != NULL) {
510 ieee80211_free_node(dp->ni);
511 dp->ni = NULL;
512 }
513 }
514}
515
516static usb_error_t
517urtwn_do_request(struct urtwn_softc *sc, struct usb_device_request *req,
518 void *data)
519{
520 usb_error_t err;
521 int ntries = 10;
522
523 URTWN_ASSERT_LOCKED(sc);
524
525 while (ntries--) {
526 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx,
527 req, data, 0, NULL, 250 /* ms */);
528 if (err == 0)
529 break;
530
531 DPRINTFN(1, "Control request failed, %s (retrying)\n",
532 usbd_errstr(err));
533 usb_pause_mtx(&sc->sc_mtx, hz / 100);
534 }
535 return (err);
536}
537
538static struct ieee80211vap *
539urtwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
540 enum ieee80211_opmode opmode, int flags,
541 const uint8_t bssid[IEEE80211_ADDR_LEN],
542 const uint8_t mac[IEEE80211_ADDR_LEN])
543{
544 struct urtwn_vap *uvp;
545 struct ieee80211vap *vap;
546
547 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */
548 return (NULL);
549
550 uvp = (struct urtwn_vap *) malloc(sizeof(struct urtwn_vap),
551 M_80211_VAP, M_NOWAIT | M_ZERO);
552 if (uvp == NULL)
553 return (NULL);
554 vap = &uvp->vap;
555 /* enable s/w bmiss handling for sta mode */
556 ieee80211_vap_setup(ic, vap, name, unit, opmode,
557 flags | IEEE80211_CLONE_NOBEACONS, bssid, mac);
558
559 /* override state transition machine */
560 uvp->newstate = vap->iv_newstate;
561 vap->iv_newstate = urtwn_newstate;
562
563 /* complete setup */
564 ieee80211_vap_attach(vap, ieee80211_media_change,
565 ieee80211_media_status);
566 ic->ic_opmode = opmode;
567 return (vap);
568}
569
570static void
571urtwn_vap_delete(struct ieee80211vap *vap)
572{
573 struct urtwn_vap *uvp = URTWN_VAP(vap);
574
575 ieee80211_vap_detach(vap);
576 free(uvp, M_80211_VAP);
577}
578
579static struct mbuf *
580urtwn_rx_frame(struct urtwn_softc *sc, uint8_t *buf, int pktlen, int *rssi_p)
581{
582 struct ifnet *ifp = sc->sc_ifp;
583 struct ieee80211com *ic = ifp->if_l2com;
584 struct ieee80211_frame *wh;
585 struct mbuf *m;
586 struct r92c_rx_stat *stat;
587 uint32_t rxdw0, rxdw3;
588 uint8_t rate;
589 int8_t rssi = 0;
590 int infosz;
591
592 /*
593 * don't pass packets to the ieee80211 framework if the driver isn't
594 * RUNNING.
595 */
596 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
597 return (NULL);
598
599 stat = (struct r92c_rx_stat *)buf;
600 rxdw0 = le32toh(stat->rxdw0);
601 rxdw3 = le32toh(stat->rxdw3);
602
603 if (rxdw0 & (R92C_RXDW0_CRCERR | R92C_RXDW0_ICVERR)) {
604 /*
605 * This should not happen since we setup our Rx filter
606 * to not receive these frames.
607 */
608 ifp->if_ierrors++;
609 return (NULL);
610 }
611
612 rate = MS(rxdw3, R92C_RXDW3_RATE);
613 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8;
614
615 /* Get RSSI from PHY status descriptor if present. */
616 if (infosz != 0 && (rxdw0 & R92C_RXDW0_PHYST)) {
617 rssi = urtwn_get_rssi(sc, rate, &stat[1]);
618 /* Update our average RSSI. */
619 urtwn_update_avgrssi(sc, rate, rssi);
620 /*
621 * Convert the RSSI to a range that will be accepted
622 * by net80211.
623 */
624 rssi = URTWN_RSSI(rssi);
625 }
626
627 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
628 if (m == NULL) {
629 device_printf(sc->sc_dev, "could not create RX mbuf\n");
630 return (NULL);
631 }
632
633 /* Finalize mbuf. */
634 m->m_pkthdr.rcvif = ifp;
635 wh = (struct ieee80211_frame *)((uint8_t *)&stat[1] + infosz);
636 memcpy(mtod(m, uint8_t *), wh, pktlen);
637 m->m_pkthdr.len = m->m_len = pktlen;
638
639 if (ieee80211_radiotap_active(ic)) {
640 struct urtwn_rx_radiotap_header *tap = &sc->sc_rxtap;
641
642 tap->wr_flags = 0;
643 /* Map HW rate index to 802.11 rate. */
644 if (!(rxdw3 & R92C_RXDW3_HT)) {
645 switch (rate) {
646 /* CCK. */
647 case 0: tap->wr_rate = 2; break;
648 case 1: tap->wr_rate = 4; break;
649 case 2: tap->wr_rate = 11; break;
650 case 3: tap->wr_rate = 22; break;
651 /* OFDM. */
652 case 4: tap->wr_rate = 12; break;
653 case 5: tap->wr_rate = 18; break;
654 case 6: tap->wr_rate = 24; break;
655 case 7: tap->wr_rate = 36; break;
656 case 8: tap->wr_rate = 48; break;
657 case 9: tap->wr_rate = 72; break;
658 case 10: tap->wr_rate = 96; break;
659 case 11: tap->wr_rate = 108; break;
660 }
661 } else if (rate >= 12) { /* MCS0~15. */
662 /* Bit 7 set means HT MCS instead of rate. */
663 tap->wr_rate = 0x80 | (rate - 12);
664 }
665 tap->wr_dbm_antsignal = rssi;
666 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq);
667 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags);
668 }
669
670 *rssi_p = rssi;
671
672 return (m);
673}
674
675static struct mbuf *
676urtwn_rxeof(struct usb_xfer *xfer, struct urtwn_data *data, int *rssi,
677 int8_t *nf)
678{
679 struct urtwn_softc *sc = data->sc;
680 struct ifnet *ifp = sc->sc_ifp;
681 struct r92c_rx_stat *stat;
682 struct mbuf *m, *m0 = NULL, *prevm = NULL;
683 uint32_t rxdw0;
684 uint8_t *buf;
685 int len, totlen, pktlen, infosz, npkts;
686
687 usbd_xfer_status(xfer, &len, NULL, NULL, NULL);
688
689 if (len < sizeof(*stat)) {
690 ifp->if_ierrors++;
691 return (NULL);
692 }
693
694 buf = data->buf;
695 /* Get the number of encapsulated frames. */
696 stat = (struct r92c_rx_stat *)buf;
697 npkts = MS(le32toh(stat->rxdw2), R92C_RXDW2_PKTCNT);
698 DPRINTFN(6, "Rx %d frames in one chunk\n", npkts);
699
700 /* Process all of them. */
701 while (npkts-- > 0) {
702 if (len < sizeof(*stat))
703 break;
704 stat = (struct r92c_rx_stat *)buf;
705 rxdw0 = le32toh(stat->rxdw0);
706
707 pktlen = MS(rxdw0, R92C_RXDW0_PKTLEN);
708 if (pktlen == 0)
709 break;
710
711 infosz = MS(rxdw0, R92C_RXDW0_INFOSZ) * 8;
712
713 /* Make sure everything fits in xfer. */
714 totlen = sizeof(*stat) + infosz + pktlen;
715 if (totlen > len)
716 break;
717
718 m = urtwn_rx_frame(sc, buf, pktlen, rssi);
719 if (m0 == NULL)
720 m0 = m;
721 if (prevm == NULL)
722 prevm = m;
723 else {
724 prevm->m_next = m;
725 prevm = m;
726 }
727
728 /* Next chunk is 128-byte aligned. */
729 totlen = (totlen + 127) & ~127;
730 buf += totlen;
731 len -= totlen;
732 }
733
734 return (m0);
735}
736
737static void
738urtwn_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error)
739{
740 struct urtwn_softc *sc = usbd_xfer_softc(xfer);
741 struct ifnet *ifp = sc->sc_ifp;
742 struct ieee80211com *ic = ifp->if_l2com;
743 struct ieee80211_frame *wh;
744 struct ieee80211_node *ni;
745 struct mbuf *m = NULL, *next;
746 struct urtwn_data *data;
747 int8_t nf;
748 int rssi = 1;
749
750 URTWN_ASSERT_LOCKED(sc);
751
752 switch (USB_GET_STATE(xfer)) {
753 case USB_ST_TRANSFERRED:
754 data = STAILQ_FIRST(&sc->sc_rx_active);
755 if (data == NULL)
756 goto tr_setup;
757 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next);
758 m = urtwn_rxeof(xfer, data, &rssi, &nf);
759 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next);
760 /* FALLTHROUGH */
761 case USB_ST_SETUP:
762tr_setup:
763 data = STAILQ_FIRST(&sc->sc_rx_inactive);
764 if (data == NULL) {
765 KASSERT(m == NULL, ("mbuf isn't NULL"));
766 return;
767 }
768 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next);
769 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next);
770 usbd_xfer_set_frame_data(xfer, 0, data->buf,
771 usbd_xfer_max_len(xfer));
772 usbd_transfer_submit(xfer);
773
774 /*
775 * To avoid LOR we should unlock our private mutex here to call
776 * ieee80211_input() because here is at the end of a USB
777 * callback and safe to unlock.
778 */
779 URTWN_UNLOCK(sc);
780 while (m != NULL) {
781 next = m->m_next;
782 m->m_next = NULL;
783 wh = mtod(m, struct ieee80211_frame *);
784 ni = ieee80211_find_rxnode(ic,
785 (struct ieee80211_frame_min *)wh);
786 nf = URTWN_NOISE_FLOOR;
787 if (ni != NULL) {
788 (void)ieee80211_input(ni, m, rssi, nf);
789 ieee80211_free_node(ni);
790 } else
791 (void)ieee80211_input_all(ic, m, rssi, nf);
792 m = next;
793 }
794 URTWN_LOCK(sc);
795 break;
796 default:
797 /* needs it to the inactive queue due to a error. */
798 data = STAILQ_FIRST(&sc->sc_rx_active);
799 if (data != NULL) {
800 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next);
801 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next);
802 }
803 if (error != USB_ERR_CANCELLED) {
804 usbd_xfer_set_stall(xfer);
805 ifp->if_ierrors++;
806 goto tr_setup;
807 }
808 break;
809 }
810}
811
812static void
813urtwn_txeof(struct usb_xfer *xfer, struct urtwn_data *data)
814{
815 struct urtwn_softc *sc = usbd_xfer_softc(xfer);
816 struct ifnet *ifp = sc->sc_ifp;
817 struct mbuf *m;
818
819 URTWN_ASSERT_LOCKED(sc);
820
821 /*
822 * Do any tx complete callback. Note this must be done before releasing
823 * the node reference.
824 */
825 if (data->m) {
826 m = data->m;
827 if (m->m_flags & M_TXCB) {
828 /* XXX status? */
829 ieee80211_process_callback(data->ni, m, 0);
830 }
831 m_freem(m);
832 data->m = NULL;
833 }
834 if (data->ni) {
835 ieee80211_free_node(data->ni);
836 data->ni = NULL;
837 }
838 sc->sc_txtimer = 0;
839 ifp->if_opackets++;
840 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
841}
842
843static void
844urtwn_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error)
845{
846 struct urtwn_softc *sc = usbd_xfer_softc(xfer);
847 struct ifnet *ifp = sc->sc_ifp;
848 struct urtwn_data *data;
849
850 URTWN_ASSERT_LOCKED(sc);
851
852 switch (USB_GET_STATE(xfer)){
853 case USB_ST_TRANSFERRED:
854 data = STAILQ_FIRST(&sc->sc_tx_active);
855 if (data == NULL)
856 goto tr_setup;
857 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next);
858 urtwn_txeof(xfer, data);
859 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next);
860 /* FALLTHROUGH */
861 case USB_ST_SETUP:
862tr_setup:
863 data = STAILQ_FIRST(&sc->sc_tx_pending);
864 if (data == NULL) {
865 DPRINTF("%s: empty pending queue\n", __func__);
866 return;
867 }
868 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next);
869 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next);
870
871 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen);
872 usbd_transfer_submit(xfer);
873
874 URTWN_UNLOCK(sc);
875 urtwn_start(ifp);
876 URTWN_LOCK(sc);
877 break;
878 default:
879 data = STAILQ_FIRST(&sc->sc_tx_active);
880 if (data == NULL)
881 goto tr_setup;
882 if (data->ni != NULL) {
883 ieee80211_free_node(data->ni);
884 data->ni = NULL;
885 ifp->if_oerrors++;
886 }
887 if (error != USB_ERR_CANCELLED) {
888 usbd_xfer_set_stall(xfer);
889 goto tr_setup;
890 }
891 break;
892 }
893}
894
895static struct urtwn_data *
896_urtwn_getbuf(struct urtwn_softc *sc)
897{
898 struct urtwn_data *bf;
899
900 bf = STAILQ_FIRST(&sc->sc_tx_inactive);
901 if (bf != NULL)
902 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next);
903 else
904 bf = NULL;
905 if (bf == NULL)
906 DPRINTF("%s: %s\n", __func__, "out of xmit buffers");
907 return (bf);
908}
909
910static struct urtwn_data *
911urtwn_getbuf(struct urtwn_softc *sc)
912{
913 struct urtwn_data *bf;
914
915 URTWN_ASSERT_LOCKED(sc);
916
917 bf = _urtwn_getbuf(sc);
918 if (bf == NULL) {
919 struct ifnet *ifp = sc->sc_ifp;
920 DPRINTF("%s: stop queue\n", __func__);
921 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
922 }
923 return (bf);
924}
925
926static int
927urtwn_write_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf,
928 int len)
929{
930 usb_device_request_t req;
931
932 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
933 req.bRequest = R92C_REQ_REGS;
934 USETW(req.wValue, addr);
935 USETW(req.wIndex, 0);
936 USETW(req.wLength, len);
937 return (urtwn_do_request(sc, &req, buf));
938}
939
940static void
941urtwn_write_1(struct urtwn_softc *sc, uint16_t addr, uint8_t val)
942{
943 urtwn_write_region_1(sc, addr, &val, 1);
944}
945
946
947static void
948urtwn_write_2(struct urtwn_softc *sc, uint16_t addr, uint16_t val)
949{
950 val = htole16(val);
951 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 2);
952}
953
954static void
955urtwn_write_4(struct urtwn_softc *sc, uint16_t addr, uint32_t val)
956{
957 val = htole32(val);
958 urtwn_write_region_1(sc, addr, (uint8_t *)&val, 4);
959}
960
961static int
962urtwn_read_region_1(struct urtwn_softc *sc, uint16_t addr, uint8_t *buf,
963 int len)
964{
965 usb_device_request_t req;
966
967 req.bmRequestType = UT_READ_VENDOR_DEVICE;
968 req.bRequest = R92C_REQ_REGS;
969 USETW(req.wValue, addr);
970 USETW(req.wIndex, 0);
971 USETW(req.wLength, len);
972 return (urtwn_do_request(sc, &req, buf));
973}
974
975static uint8_t
976urtwn_read_1(struct urtwn_softc *sc, uint16_t addr)
977{
978 uint8_t val;
979
980 if (urtwn_read_region_1(sc, addr, &val, 1) != 0)
981 return (0xff);
982 return (val);
983}
984
985static uint16_t
986urtwn_read_2(struct urtwn_softc *sc, uint16_t addr)
987{
988 uint16_t val;
989
990 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 2) != 0)
991 return (0xffff);
992 return (le16toh(val));
993}
994
995static uint32_t
996urtwn_read_4(struct urtwn_softc *sc, uint16_t addr)
997{
998 uint32_t val;
999
1000 if (urtwn_read_region_1(sc, addr, (uint8_t *)&val, 4) != 0)
1001 return (0xffffffff);
1002 return (le32toh(val));
1003}
1004
1005static int
1006urtwn_fw_cmd(struct urtwn_softc *sc, uint8_t id, const void *buf, int len)
1007{
1008 struct r92c_fw_cmd cmd;
1009 int ntries;
1010
1011 /* Wait for current FW box to be empty. */
1012 for (ntries = 0; ntries < 100; ntries++) {
1013 if (!(urtwn_read_1(sc, R92C_HMETFR) & (1 << sc->fwcur)))
1014 break;
1015 DELAY(1);
1016 }
1017 if (ntries == 100) {
1018 device_printf(sc->sc_dev,
1019 "could not send firmware command\n");
1020 return (ETIMEDOUT);
1021 }
1022 memset(&cmd, 0, sizeof(cmd));
1023 cmd.id = id;
1024 if (len > 3)
1025 cmd.id |= R92C_CMD_FLAG_EXT;
1026 KASSERT(len <= sizeof(cmd.msg), ("urtwn_fw_cmd\n"));
1027 memcpy(cmd.msg, buf, len);
1028
1029 /* Write the first word last since that will trigger the FW. */
1030 urtwn_write_region_1(sc, R92C_HMEBOX_EXT(sc->fwcur),
1031 (uint8_t *)&cmd + 4, 2);
1032 urtwn_write_region_1(sc, R92C_HMEBOX(sc->fwcur),
1033 (uint8_t *)&cmd + 0, 4);
1034
1035 sc->fwcur = (sc->fwcur + 1) % R92C_H2C_NBOX;
1036 return (0);
1037}
1038
1039static void
1040urtwn_rf_write(struct urtwn_softc *sc, int chain, uint8_t addr, uint32_t val)
1041{
1042 urtwn_bb_write(sc, R92C_LSSI_PARAM(chain),
1043 SM(R92C_LSSI_PARAM_ADDR, addr) |
1044 SM(R92C_LSSI_PARAM_DATA, val));
1045}
1046
1047static uint32_t
1048urtwn_rf_read(struct urtwn_softc *sc, int chain, uint8_t addr)
1049{
1050 uint32_t reg[R92C_MAX_CHAINS], val;
1051
1052 reg[0] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(0));
1053 if (chain != 0)
1054 reg[chain] = urtwn_bb_read(sc, R92C_HSSI_PARAM2(chain));
1055
1056 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0),
1057 reg[0] & ~R92C_HSSI_PARAM2_READ_EDGE);
1058 DELAY(1000);
1059
1060 urtwn_bb_write(sc, R92C_HSSI_PARAM2(chain),
1061 RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) |
1062 R92C_HSSI_PARAM2_READ_EDGE);
1063 DELAY(1000);
1064
1065 urtwn_bb_write(sc, R92C_HSSI_PARAM2(0),
1066 reg[0] | R92C_HSSI_PARAM2_READ_EDGE);
1067 DELAY(1000);
1068
1069 if (urtwn_bb_read(sc, R92C_HSSI_PARAM1(chain)) & R92C_HSSI_PARAM1_PI)
1070 val = urtwn_bb_read(sc, R92C_HSPI_READBACK(chain));
1071 else
1072 val = urtwn_bb_read(sc, R92C_LSSI_READBACK(chain));
1073 return (MS(val, R92C_LSSI_READBACK_DATA));
1074}
1075
1076static int
1077urtwn_llt_write(struct urtwn_softc *sc, uint32_t addr, uint32_t data)
1078{
1079 int ntries;
1080
1081 urtwn_write_4(sc, R92C_LLT_INIT,
1082 SM(R92C_LLT_INIT_OP, R92C_LLT_INIT_OP_WRITE) |
1083 SM(R92C_LLT_INIT_ADDR, addr) |
1084 SM(R92C_LLT_INIT_DATA, data));
1085 /* Wait for write operation to complete. */
1086 for (ntries = 0; ntries < 20; ntries++) {
1087 if (MS(urtwn_read_4(sc, R92C_LLT_INIT), R92C_LLT_INIT_OP) ==
1088 R92C_LLT_INIT_OP_NO_ACTIVE)
1089 return (0);
1090 DELAY(5);
1091 }
1092 return (ETIMEDOUT);
1093}
1094
1095static uint8_t
1096urtwn_efuse_read_1(struct urtwn_softc *sc, uint16_t addr)
1097{
1098 uint32_t reg;
1099 int ntries;
1100
1101 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL);
1102 reg = RW(reg, R92C_EFUSE_CTRL_ADDR, addr);
1103 reg &= ~R92C_EFUSE_CTRL_VALID;
1104 urtwn_write_4(sc, R92C_EFUSE_CTRL, reg);
1105 /* Wait for read operation to complete. */
1106 for (ntries = 0; ntries < 100; ntries++) {
1107 reg = urtwn_read_4(sc, R92C_EFUSE_CTRL);
1108 if (reg & R92C_EFUSE_CTRL_VALID)
1109 return (MS(reg, R92C_EFUSE_CTRL_DATA));
1110 DELAY(5);
1111 }
1112 device_printf(sc->sc_dev,
1113 "could not read efuse byte at address 0x%x\n", addr);
1114 return (0xff);
1115}
1116
1117static void
1118urtwn_efuse_read(struct urtwn_softc *sc)
1119{
1120 uint8_t *rom = (uint8_t *)&sc->rom;
1121 uint16_t addr = 0;
1122 uint32_t reg;
1123 uint8_t off, msk;
1124 int i;
1125
1126 reg = urtwn_read_2(sc, R92C_SYS_ISO_CTRL);
1127 if (!(reg & R92C_SYS_ISO_CTRL_PWC_EV12V)) {
1128 urtwn_write_2(sc, R92C_SYS_ISO_CTRL,
1129 reg | R92C_SYS_ISO_CTRL_PWC_EV12V);
1130 }
1131 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN);
1132 if (!(reg & R92C_SYS_FUNC_EN_ELDR)) {
1133 urtwn_write_2(sc, R92C_SYS_FUNC_EN,
1134 reg | R92C_SYS_FUNC_EN_ELDR);
1135 }
1136 reg = urtwn_read_2(sc, R92C_SYS_CLKR);
1137 if ((reg & (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) !=
1138 (R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M)) {
1139 urtwn_write_2(sc, R92C_SYS_CLKR,
1140 reg | R92C_SYS_CLKR_LOADER_EN | R92C_SYS_CLKR_ANA8M);
1141 }
1142 memset(&sc->rom, 0xff, sizeof(sc->rom));
1143 while (addr < 512) {
1144 reg = urtwn_efuse_read_1(sc, addr);
1145 if (reg == 0xff)
1146 break;
1147 addr++;
1148 off = reg >> 4;
1149 msk = reg & 0xf;
1150 for (i = 0; i < 4; i++) {
1151 if (msk & (1 << i))
1152 continue;
1153 rom[off * 8 + i * 2 + 0] =
1154 urtwn_efuse_read_1(sc, addr);
1155 addr++;
1156 rom[off * 8 + i * 2 + 1] =
1157 urtwn_efuse_read_1(sc, addr);
1158 addr++;
1159 }
1160 }
1161#ifdef URTWN_DEBUG
1162 if (urtwn_debug >= 2) {
1163 /* Dump ROM content. */
1164 printf("\n");
1165 for (i = 0; i < sizeof(sc->rom); i++)
1166 printf("%02x:", rom[i]);
1167 printf("\n");
1168 }
1169#endif
1170}
1171
1172static int
1173urtwn_read_chipid(struct urtwn_softc *sc)
1174{
1175 uint32_t reg;
1176
1177 reg = urtwn_read_4(sc, R92C_SYS_CFG);
1178 if (reg & R92C_SYS_CFG_TRP_VAUX_EN)
1179 return (EIO);
1180
1181 if (reg & R92C_SYS_CFG_TYPE_92C) {
1182 sc->chip |= URTWN_CHIP_92C;
1183 /* Check if it is a castrated 8192C. */
1184 if (MS(urtwn_read_4(sc, R92C_HPON_FSM),
1185 R92C_HPON_FSM_CHIP_BONDING_ID) ==
1186 R92C_HPON_FSM_CHIP_BONDING_ID_92C_1T2R)
1187 sc->chip |= URTWN_CHIP_92C_1T2R;
1188 }
1189 if (reg & R92C_SYS_CFG_VENDOR_UMC) {
1190 sc->chip |= URTWN_CHIP_UMC;
1191 if (MS(reg, R92C_SYS_CFG_CHIP_VER_RTL) == 0)
1192 sc->chip |= URTWN_CHIP_UMC_A_CUT;
1193 }
1194 return (0);
1195}
1196
1197static void
1198urtwn_read_rom(struct urtwn_softc *sc)
1199{
1200 struct r92c_rom *rom = &sc->rom;
1201
1202 /* Read full ROM image. */
1203 urtwn_efuse_read(sc);
1204
1205 /* XXX Weird but this is what the vendor driver does. */
1206 sc->pa_setting = urtwn_efuse_read_1(sc, 0x1fa);
1207 DPRINTF("PA setting=0x%x\n", sc->pa_setting);
1208
1209 sc->board_type = MS(rom->rf_opt1, R92C_ROM_RF1_BOARD_TYPE);
1210
1211 sc->regulatory = MS(rom->rf_opt1, R92C_ROM_RF1_REGULATORY);
1212 DPRINTF("regulatory type=%d\n", sc->regulatory);
1213
1214 IEEE80211_ADDR_COPY(sc->sc_bssid, rom->macaddr);
1215}
1216
1217/*
1218 * Initialize rate adaptation in firmware.
1219 */
1220static int
1221urtwn_ra_init(struct urtwn_softc *sc)
1222{
1223 static const uint8_t map[] =
1224 { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 };
1225 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
1226 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
1227 struct ieee80211_node *ni;
1228 struct ieee80211_rateset *rs;
1229 struct r92c_fw_cmd_macid_cfg cmd;
1230 uint32_t rates, basicrates;
1231 uint8_t mode;
1232 int maxrate, maxbasicrate, error, i, j;
1233
1234 ni = ieee80211_ref_node(vap->iv_bss);
1235 rs = &ni->ni_rates;
1236
1237 /* Get normal and basic rates mask. */
1238 rates = basicrates = 0;
1239 maxrate = maxbasicrate = 0;
1240 for (i = 0; i < rs->rs_nrates; i++) {
1241 /* Convert 802.11 rate to HW rate index. */
1242 for (j = 0; j < nitems(map); j++)
1243 if ((rs->rs_rates[i] & IEEE80211_RATE_VAL) == map[j])
1244 break;
1245 if (j == nitems(map)) /* Unknown rate, skip. */
1246 continue;
1247 rates |= 1 << j;
1248 if (j > maxrate)
1249 maxrate = j;
1250 if (rs->rs_rates[i] & IEEE80211_RATE_BASIC) {
1251 basicrates |= 1 << j;
1252 if (j > maxbasicrate)
1253 maxbasicrate = j;
1254 }
1255 }
1256 if (ic->ic_curmode == IEEE80211_MODE_11B)
1257 mode = R92C_RAID_11B;
1258 else
1259 mode = R92C_RAID_11BG;
1260 DPRINTF("mode=0x%x rates=0x%08x, basicrates=0x%08x\n",
1261 mode, rates, basicrates);
1262
1263 /* Set rates mask for group addressed frames. */
1264 cmd.macid = URTWN_MACID_BC | URTWN_MACID_VALID;
1265 cmd.mask = htole32(mode << 28 | basicrates);
1266 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd));
1267 if (error != 0) {
1268 ieee80211_free_node(ni);
1269 device_printf(sc->sc_dev,
1270 "could not add broadcast station\n");
1271 return (error);
1272 }
1273 /* Set initial MRR rate. */
1274 DPRINTF("maxbasicrate=%d\n", maxbasicrate);
1275 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BC),
1276 maxbasicrate);
1277
1278 /* Set rates mask for unicast frames. */
1279 cmd.macid = URTWN_MACID_BSS | URTWN_MACID_VALID;
1280 cmd.mask = htole32(mode << 28 | rates);
1281 error = urtwn_fw_cmd(sc, R92C_CMD_MACID_CONFIG, &cmd, sizeof(cmd));
1282 if (error != 0) {
1283 ieee80211_free_node(ni);
1284 device_printf(sc->sc_dev, "could not add BSS station\n");
1285 return (error);
1286 }
1287 /* Set initial MRR rate. */
1288 DPRINTF("maxrate=%d\n", maxrate);
1289 urtwn_write_1(sc, R92C_INIDATA_RATE_SEL(URTWN_MACID_BSS),
1290 maxrate);
1291
1292 /* Indicate highest supported rate. */
1293 ni->ni_txrate = rs->rs_rates[rs->rs_nrates - 1];
1294 ieee80211_free_node(ni);
1295
1296 return (0);
1297}
1298
1299void
1300urtwn_tsf_sync_enable(struct urtwn_softc *sc)
1301{
1302 struct ifnet *ifp = sc->sc_ifp;
1303 struct ieee80211com *ic = ifp->if_l2com;
1304 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
1305 struct ieee80211_node *ni = vap->iv_bss;
1306
1307 uint64_t tsf;
1308
1309 /* Enable TSF synchronization. */
1310 urtwn_write_1(sc, R92C_BCN_CTRL,
1311 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_DIS_TSF_UDT0);
1312
1313 urtwn_write_1(sc, R92C_BCN_CTRL,
1314 urtwn_read_1(sc, R92C_BCN_CTRL) & ~R92C_BCN_CTRL_EN_BCN);
1315
1316 /* Set initial TSF. */
1317 memcpy(&tsf, ni->ni_tstamp.data, 8);
1318 tsf = le64toh(tsf);
1319 tsf = tsf - (tsf % (vap->iv_bss->ni_intval * IEEE80211_DUR_TU));
1320 tsf -= IEEE80211_DUR_TU;
1321 urtwn_write_4(sc, R92C_TSFTR + 0, tsf);
1322 urtwn_write_4(sc, R92C_TSFTR + 4, tsf >> 32);
1323
1324 urtwn_write_1(sc, R92C_BCN_CTRL,
1325 urtwn_read_1(sc, R92C_BCN_CTRL) | R92C_BCN_CTRL_EN_BCN);
1326}
1327
1328static void
1329urtwn_set_led(struct urtwn_softc *sc, int led, int on)
1330{
1331 uint8_t reg;
1332
1333 if (led == URTWN_LED_LINK) {
1334 reg = urtwn_read_1(sc, R92C_LEDCFG0) & 0x70;
1335 if (!on)
1336 reg |= R92C_LEDCFG0_DIS;
1337 urtwn_write_1(sc, R92C_LEDCFG0, reg);
1338 sc->ledlink = on; /* Save LED state. */
1339 }
1340}
1341
1342static int
1343urtwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
1344{
1345 struct urtwn_vap *uvp = URTWN_VAP(vap);
1346 struct ieee80211com *ic = vap->iv_ic;
1347 struct urtwn_softc *sc = ic->ic_ifp->if_softc;
1348 struct ieee80211_node *ni;
1349 enum ieee80211_state ostate;
1350 uint32_t reg;
1351
1352 ostate = vap->iv_state;
1353 DPRINTF("%s -> %s\n", ieee80211_state_name[ostate],
1354 ieee80211_state_name[nstate]);
1355
1356 IEEE80211_UNLOCK(ic);
1357 URTWN_LOCK(sc);
1358 callout_stop(&sc->sc_watchdog_ch);
1359
1360 if (ostate == IEEE80211_S_RUN) {
1361 /* Turn link LED off. */
1362 urtwn_set_led(sc, URTWN_LED_LINK, 0);
1363
1364 /* Set media status to 'No Link'. */
1365 reg = urtwn_read_4(sc, R92C_CR);
1366 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_NOLINK);
1367 urtwn_write_4(sc, R92C_CR, reg);
1368
1369 /* Stop Rx of data frames. */
1370 urtwn_write_2(sc, R92C_RXFLTMAP2, 0);
1371
1372 /* Rest TSF. */
1373 urtwn_write_1(sc, R92C_DUAL_TSF_RST, 0x03);
1374
1375 /* Disable TSF synchronization. */
1376 urtwn_write_1(sc, R92C_BCN_CTRL,
1377 urtwn_read_1(sc, R92C_BCN_CTRL) |
1378 R92C_BCN_CTRL_DIS_TSF_UDT0);
1379
1380 /* Reset EDCA parameters. */
1381 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002f3217);
1382 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005e4317);
1383 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x00105320);
1384 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a444);
1385 }
1386
1387 switch (nstate) {
1388 case IEEE80211_S_INIT:
1389 /* Turn link LED off. */
1390 urtwn_set_led(sc, URTWN_LED_LINK, 0);
1391 break;
1392 case IEEE80211_S_SCAN:
1393 if (ostate != IEEE80211_S_SCAN) {
1394 /* Allow Rx from any BSSID. */
1395 urtwn_write_4(sc, R92C_RCR,
1396 urtwn_read_4(sc, R92C_RCR) &
1397 ~(R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN));
1398
1399 /* Set gain for scanning. */
1400 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0));
1401 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20);
1402 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg);
1403
1404 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));
1405 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x20);
1406 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg);
1407 }
1408
1409 /* Make link LED blink during scan. */
1410 urtwn_set_led(sc, URTWN_LED_LINK, !sc->ledlink);
1411
1412 /* Pause AC Tx queues. */
1413 urtwn_write_1(sc, R92C_TXPAUSE,
1414 urtwn_read_1(sc, R92C_TXPAUSE) | 0x0f);
1415
1416 urtwn_set_chan(sc, ic->ic_curchan, NULL);
1417 break;
1418 case IEEE80211_S_AUTH:
1419 /* Set initial gain under link. */
1420 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(0));
1421 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32);
1422 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(0), reg);
1423
1424 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCCORE1(1));
1425 reg = RW(reg, R92C_OFDM0_AGCCORE1_GAIN, 0x32);
1426 urtwn_bb_write(sc, R92C_OFDM0_AGCCORE1(1), reg);
1427
1428 urtwn_set_chan(sc, ic->ic_curchan, NULL);
1429 break;
1430 case IEEE80211_S_RUN:
1431 if (vap->iv_opmode == IEEE80211_M_MONITOR) {
1432 /* Enable Rx of data frames. */
1433 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff);
1434
1435 /* Turn link LED on. */
1436 urtwn_set_led(sc, URTWN_LED_LINK, 1);
1437 break;
1438 }
1439
1440 ni = ieee80211_ref_node(vap->iv_bss);
1441 /* Set media status to 'Associated'. */
1442 reg = urtwn_read_4(sc, R92C_CR);
1443 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA);
1444 urtwn_write_4(sc, R92C_CR, reg);
1445
1446 /* Set BSSID. */
1447 urtwn_write_4(sc, R92C_BSSID + 0, LE_READ_4(&ni->ni_bssid[0]));
1448 urtwn_write_4(sc, R92C_BSSID + 4, LE_READ_2(&ni->ni_bssid[4]));
1449
1450 if (ic->ic_curmode == IEEE80211_MODE_11B)
1451 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 0);
1452 else /* 802.11b/g */
1453 urtwn_write_1(sc, R92C_INIRTS_RATE_SEL, 3);
1454
1455 /* Enable Rx of data frames. */
1456 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff);
1457
1458 /* Flush all AC queues. */
1459 urtwn_write_1(sc, R92C_TXPAUSE, 0);
1460
1461 /* Set beacon interval. */
1462 urtwn_write_2(sc, R92C_BCN_INTERVAL, ni->ni_intval);
1463
1464 /* Allow Rx from our BSSID only. */
1465 urtwn_write_4(sc, R92C_RCR,
1466 urtwn_read_4(sc, R92C_RCR) |
1467 R92C_RCR_CBSSID_DATA | R92C_RCR_CBSSID_BCN);
1468
1469 /* Enable TSF synchronization. */
1470 urtwn_tsf_sync_enable(sc);
1471
1472 urtwn_write_1(sc, R92C_SIFS_CCK + 1, 10);
1473 urtwn_write_1(sc, R92C_SIFS_OFDM + 1, 10);
1474 urtwn_write_1(sc, R92C_SPEC_SIFS + 1, 10);
1475 urtwn_write_1(sc, R92C_MAC_SPEC_SIFS + 1, 10);
1476 urtwn_write_1(sc, R92C_R2T_SIFS + 1, 10);
1477 urtwn_write_1(sc, R92C_T2T_SIFS + 1, 10);
1478
1479 /* Intialize rate adaptation. */
1480 urtwn_ra_init(sc);
1481 /* Turn link LED on. */
1482 urtwn_set_led(sc, URTWN_LED_LINK, 1);
1483
1484 sc->avg_pwdb = -1; /* Reset average RSSI. */
1485 /* Reset temperature calibration state machine. */
1486 sc->thcal_state = 0;
1487 sc->thcal_lctemp = 0;
1488 ieee80211_free_node(ni);
1489 break;
1490 default:
1491 break;
1492 }
1493 URTWN_UNLOCK(sc);
1494 IEEE80211_LOCK(ic);
1495 return(uvp->newstate(vap, nstate, arg));
1496}
1497
1498static void
1499urtwn_watchdog(void *arg)
1500{
1501 struct urtwn_softc *sc = arg;
1502 struct ifnet *ifp = sc->sc_ifp;
1503
1504 if (sc->sc_txtimer > 0) {
1505 if (--sc->sc_txtimer == 0) {
1506 device_printf(sc->sc_dev, "device timeout\n");
1507 ifp->if_oerrors++;
1508 return;
1509 }
1510 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc);
1511 }
1512}
1513
1514static void
1515urtwn_update_avgrssi(struct urtwn_softc *sc, int rate, int8_t rssi)
1516{
1517 int pwdb;
1518
1519 /* Convert antenna signal to percentage. */
1520 if (rssi <= -100 || rssi >= 20)
1521 pwdb = 0;
1522 else if (rssi >= 0)
1523 pwdb = 100;
1524 else
1525 pwdb = 100 + rssi;
1526 if (rate <= 3) {
1527 /* CCK gain is smaller than OFDM/MCS gain. */
1528 pwdb += 6;
1529 if (pwdb > 100)
1530 pwdb = 100;
1531 if (pwdb <= 14)
1532 pwdb -= 4;
1533 else if (pwdb <= 26)
1534 pwdb -= 8;
1535 else if (pwdb <= 34)
1536 pwdb -= 6;
1537 else if (pwdb <= 42)
1538 pwdb -= 2;
1539 }
1540 if (sc->avg_pwdb == -1) /* Init. */
1541 sc->avg_pwdb = pwdb;
1542 else if (sc->avg_pwdb < pwdb)
1543 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20) + 1;
1544 else
1545 sc->avg_pwdb = ((sc->avg_pwdb * 19 + pwdb) / 20);
1546 DPRINTFN(4, "PWDB=%d EMA=%d\n", pwdb, sc->avg_pwdb);
1547}
1548
1549static int8_t
1550urtwn_get_rssi(struct urtwn_softc *sc, int rate, void *physt)
1551{
1552 static const int8_t cckoff[] = { 16, -12, -26, -46 };
1553 struct r92c_rx_phystat *phy;
1554 struct r92c_rx_cck *cck;
1555 uint8_t rpt;
1556 int8_t rssi;
1557
1558 if (rate <= 3) {
1559 cck = (struct r92c_rx_cck *)physt;
1560 if (sc->sc_flags & URTWN_FLAG_CCK_HIPWR) {
1561 rpt = (cck->agc_rpt >> 5) & 0x3;
1562 rssi = (cck->agc_rpt & 0x1f) << 1;
1563 } else {
1564 rpt = (cck->agc_rpt >> 6) & 0x3;
1565 rssi = cck->agc_rpt & 0x3e;
1566 }
1567 rssi = cckoff[rpt] - rssi;
1568 } else { /* OFDM/HT. */
1569 phy = (struct r92c_rx_phystat *)physt;
1570 rssi = ((le32toh(phy->phydw1) >> 1) & 0x7f) - 110;
1571 }
1572 return (rssi);
1573}
1574
1575static int
1576urtwn_tx_start(struct urtwn_softc *sc, struct ieee80211_node *ni,
1577 struct mbuf *m0, struct urtwn_data *data)
1578{
1579 struct ifnet *ifp = sc->sc_ifp;
1580 struct ieee80211_frame *wh;
1581 struct ieee80211_key *k;
1582 struct ieee80211com *ic = ifp->if_l2com;
1583 struct ieee80211vap *vap = ni->ni_vap;
1584 struct usb_xfer *xfer;
1585 struct r92c_tx_desc *txd;
1586 uint8_t raid, type;
1587 uint16_t sum;
1588 int i, hasqos, xferlen;
1589 struct usb_xfer *urtwn_pipes[4] = {
1590 sc->sc_xfer[URTWN_BULK_TX_BE],
1591 sc->sc_xfer[URTWN_BULK_TX_BK],
1592 sc->sc_xfer[URTWN_BULK_TX_VI],
1593 sc->sc_xfer[URTWN_BULK_TX_VO]
1594 };
1595
1596 URTWN_ASSERT_LOCKED(sc);
1597
1598 /*
1599 * Software crypto.
1600 */
1601 wh = mtod(m0, struct ieee80211_frame *);
1602 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
1603 k = ieee80211_crypto_encap(ni, m0);
1604 if (k == NULL) {
1605 device_printf(sc->sc_dev,
1606 "ieee80211_crypto_encap returns NULL.\n");
1607 /* XXX we don't expect the fragmented frames */
1608 m_freem(m0);
1609 return (ENOBUFS);
1610 }
1611
1612 /* in case packet header moved, reset pointer */
1613 wh = mtod(m0, struct ieee80211_frame *);
1614 }
1615
1616 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) {
1617 case IEEE80211_FC0_TYPE_CTL:
1618 case IEEE80211_FC0_TYPE_MGT:
1619 xfer = sc->sc_xfer[URTWN_BULK_TX_VO];
1620 break;
1621 default:
1622 KASSERT(M_WME_GETAC(m0) < 4,
1623 ("unsupported WME pipe %d", M_WME_GETAC(m0)));
1624 xfer = urtwn_pipes[M_WME_GETAC(m0)];
1625 break;
1626 }
1627
1628 hasqos = 0;
1629
1630 /* Fill Tx descriptor. */
1631 txd = (struct r92c_tx_desc *)data->buf;
1632 memset(txd, 0, sizeof(*txd));
1633
1634 txd->txdw0 |= htole32(
1635 SM(R92C_TXDW0_PKTLEN, m0->m_pkthdr.len) |
1636 SM(R92C_TXDW0_OFFSET, sizeof(*txd)) |
1637 R92C_TXDW0_OWN | R92C_TXDW0_FSG | R92C_TXDW0_LSG);
1638 if (IEEE80211_IS_MULTICAST(wh->i_addr1))
1639 txd->txdw0 |= htole32(R92C_TXDW0_BMCAST);
1640
1641 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
1642 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) &&
1643 type == IEEE80211_FC0_TYPE_DATA) {
1644 if (ic->ic_curmode == IEEE80211_MODE_11B)
1645 raid = R92C_RAID_11B;
1646 else
1647 raid = R92C_RAID_11BG;
1648 txd->txdw1 |= htole32(
1649 SM(R92C_TXDW1_MACID, URTWN_MACID_BSS) |
1650 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_BE) |
1651 SM(R92C_TXDW1_RAID, raid) |
1652 R92C_TXDW1_AGGBK);
1653
1654 if (ic->ic_flags & IEEE80211_F_USEPROT) {
1655 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) {
1656 txd->txdw4 |= htole32(R92C_TXDW4_CTS2SELF |
1657 R92C_TXDW4_HWRTSEN);
1658 } else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) {
1659 txd->txdw4 |= htole32(R92C_TXDW4_RTSEN |
1660 R92C_TXDW4_HWRTSEN);
1661 }
1662 }
1663 /* Send RTS at OFDM24. */
1664 txd->txdw4 |= htole32(SM(R92C_TXDW4_RTSRATE, 8));
1665 txd->txdw5 |= htole32(0x0001ff00);
1666 /* Send data at OFDM54. */
1667 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 11));
1668 } else {
1669 txd->txdw1 |= htole32(
1670 SM(R92C_TXDW1_MACID, 0) |
1671 SM(R92C_TXDW1_QSEL, R92C_TXDW1_QSEL_MGNT) |
1672 SM(R92C_TXDW1_RAID, R92C_RAID_11B));
1673
1674 /* Force CCK1. */
1675 txd->txdw4 |= htole32(R92C_TXDW4_DRVRATE);
1676 txd->txdw5 |= htole32(SM(R92C_TXDW5_DATARATE, 0));
1677 }
1678 /* Set sequence number (already little endian). */
1679 txd->txdseq |= *(uint16_t *)wh->i_seq;
1680
1681 if (!hasqos) {
1682 /* Use HW sequence numbering for non-QoS frames. */
1683 txd->txdw4 |= htole32(R92C_TXDW4_HWSEQ);
1684 txd->txdseq |= htole16(0x8000);
1685 } else
1686 txd->txdw4 |= htole32(R92C_TXDW4_QOS);
1687
1688 /* Compute Tx descriptor checksum. */
1689 sum = 0;
1690 for (i = 0; i < sizeof(*txd) / 2; i++)
1691 sum ^= ((uint16_t *)txd)[i];
1692 txd->txdsum = sum; /* NB: already little endian. */
1693
1694 if (ieee80211_radiotap_active_vap(vap)) {
1695 struct urtwn_tx_radiotap_header *tap = &sc->sc_txtap;
1696
1697 tap->wt_flags = 0;
1698 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq);
1699 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags);
1700 ieee80211_radiotap_tx(vap, m0);
1701 }
1702
1703 xferlen = sizeof(*txd) + m0->m_pkthdr.len;
1704 m_copydata(m0, 0, m0->m_pkthdr.len, (caddr_t)&txd[1]);
1705
1706 data->buflen = xferlen;
1707 data->ni = ni;
1708 data->m = m0;
1709
1710 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next);
1711 usbd_transfer_start(xfer);
1712 return (0);
1713}
1714
1715static void
1716urtwn_start(struct ifnet *ifp)
1717{
1718 struct urtwn_softc *sc = ifp->if_softc;
1719 struct ieee80211_node *ni;
1720 struct mbuf *m;
1721 struct urtwn_data *bf;
1722
1723 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1724 return;
1725
1726 URTWN_LOCK(sc);
1727 for (;;) {
1728 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
1729 if (m == NULL)
1730 break;
1731 bf = urtwn_getbuf(sc);
1732 if (bf == NULL) {
1733 IFQ_DRV_PREPEND(&ifp->if_snd, m);
1734 break;
1735 }
1736 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
1737 m->m_pkthdr.rcvif = NULL;
1738
1739 if (urtwn_tx_start(sc, ni, m, bf) != 0) {
1740 ifp->if_oerrors++;
1741 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next);
1742 ieee80211_free_node(ni);
1743 break;
1744 }
1745
1746 sc->sc_txtimer = 5;
1747 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc);
1748 }
1749 URTWN_UNLOCK(sc);
1750}
1751
1752static int
1753urtwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1754{
1755 struct ieee80211com *ic = ifp->if_l2com;
1756 struct ifreq *ifr = (struct ifreq *) data;
1757 int error = 0, startall = 0;
1758
1759 switch (cmd) {
1760 case SIOCSIFFLAGS:
1761 if (ifp->if_flags & IFF_UP) {
1762 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1763 urtwn_init(ifp->if_softc);
1764 startall = 1;
1765 }
1766 } else {
1767 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1768 urtwn_stop(ifp, 1);
1769 }
1770 if (startall)
1771 ieee80211_start_all(ic);
1772 break;
1773 case SIOCGIFMEDIA:
1774 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd);
1775 break;
1776 case SIOCGIFADDR:
1777 error = ether_ioctl(ifp, cmd, data);
1778 break;
1779 default:
1780 error = EINVAL;
1781 break;
1782 }
1783 return (error);
1784}
1785
1786static int
1787urtwn_alloc_list(struct urtwn_softc *sc, struct urtwn_data data[],
1788 int ndata, int maxsz)
1789{
1790 int i, error;
1791
1792 for (i = 0; i < ndata; i++) {
1793 struct urtwn_data *dp = &data[i];
1794 dp->sc = sc;
1795 dp->m = NULL;
1796 dp->buf = malloc(maxsz, M_USBDEV, M_NOWAIT);
1797 if (dp->buf == NULL) {
1798 device_printf(sc->sc_dev,
1799 "could not allocate buffer\n");
1800 error = ENOMEM;
1801 goto fail;
1802 }
1803 dp->ni = NULL;
1804 }
1805
1806 return (0);
1807fail:
1808 urtwn_free_list(sc, data, ndata);
1809 return (error);
1810}
1811
1812static int
1813urtwn_alloc_rx_list(struct urtwn_softc *sc)
1814{
1815 int error, i;
1816
1817 error = urtwn_alloc_list(sc, sc->sc_rx, URTWN_RX_LIST_COUNT,
1818 URTWN_RXBUFSZ);
1819 if (error != 0)
1820 return (error);
1821
1822 STAILQ_INIT(&sc->sc_rx_active);
1823 STAILQ_INIT(&sc->sc_rx_inactive);
1824
1825 for (i = 0; i < URTWN_RX_LIST_COUNT; i++)
1826 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next);
1827
1828 return (0);
1829}
1830
1831static int
1832urtwn_alloc_tx_list(struct urtwn_softc *sc)
1833{
1834 int error, i;
1835
1836 error = urtwn_alloc_list(sc, sc->sc_tx, URTWN_TX_LIST_COUNT,
1837 URTWN_TXBUFSZ);
1838 if (error != 0)
1839 return (error);
1840
1841 STAILQ_INIT(&sc->sc_tx_active);
1842 STAILQ_INIT(&sc->sc_tx_inactive);
1843 STAILQ_INIT(&sc->sc_tx_pending);
1844
1845 for (i = 0; i < URTWN_TX_LIST_COUNT; i++)
1846 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], next);
1847
1848 return (0);
1849}
1850
1851static int
1852urtwn_power_on(struct urtwn_softc *sc)
1853{
1854 uint32_t reg;
1855 int ntries;
1856
1857 /* Wait for autoload done bit. */
1858 for (ntries = 0; ntries < 1000; ntries++) {
1859 if (urtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN)
1860 break;
1861 DELAY(5);
1862 }
1863 if (ntries == 1000) {
1864 device_printf(sc->sc_dev,
1865 "timeout waiting for chip autoload\n");
1866 return (ETIMEDOUT);
1867 }
1868
1869 /* Unlock ISO/CLK/Power control register. */
1870 urtwn_write_1(sc, R92C_RSV_CTRL, 0);
1871 /* Move SPS into PWM mode. */
1872 urtwn_write_1(sc, R92C_SPS0_CTRL, 0x2b);
1873 DELAY(100);
1874
1875 reg = urtwn_read_1(sc, R92C_LDOV12D_CTRL);
1876 if (!(reg & R92C_LDOV12D_CTRL_LDV12_EN)) {
1877 urtwn_write_1(sc, R92C_LDOV12D_CTRL,
1878 reg | R92C_LDOV12D_CTRL_LDV12_EN);
1879 DELAY(100);
1880 urtwn_write_1(sc, R92C_SYS_ISO_CTRL,
1881 urtwn_read_1(sc, R92C_SYS_ISO_CTRL) &
1882 ~R92C_SYS_ISO_CTRL_MD2PP);
1883 }
1884
1885 /* Auto enable WLAN. */
1886 urtwn_write_2(sc, R92C_APS_FSMCO,
1887 urtwn_read_2(sc, R92C_APS_FSMCO) | R92C_APS_FSMCO_APFM_ONMAC);
1888 for (ntries = 0; ntries < 1000; ntries++) {
1889 if (urtwn_read_2(sc, R92C_APS_FSMCO) &
1890 R92C_APS_FSMCO_APFM_ONMAC)
1891 break;
1892 DELAY(5);
1893 }
1894 if (ntries == 1000) {
1895 device_printf(sc->sc_dev,
1896 "timeout waiting for MAC auto ON\n");
1897 return (ETIMEDOUT);
1898 }
1899
1900 /* Enable radio, GPIO and LED functions. */
1901 urtwn_write_2(sc, R92C_APS_FSMCO,
1902 R92C_APS_FSMCO_AFSM_HSUS |
1903 R92C_APS_FSMCO_PDN_EN |
1904 R92C_APS_FSMCO_PFM_ALDN);
1905 /* Release RF digital isolation. */
1906 urtwn_write_2(sc, R92C_SYS_ISO_CTRL,
1907 urtwn_read_2(sc, R92C_SYS_ISO_CTRL) & ~R92C_SYS_ISO_CTRL_DIOR);
1908
1909 /* Initialize MAC. */
1910 urtwn_write_1(sc, R92C_APSD_CTRL,
1911 urtwn_read_1(sc, R92C_APSD_CTRL) & ~R92C_APSD_CTRL_OFF);
1912 for (ntries = 0; ntries < 200; ntries++) {
1913 if (!(urtwn_read_1(sc, R92C_APSD_CTRL) &
1914 R92C_APSD_CTRL_OFF_STATUS))
1915 break;
1916 DELAY(5);
1917 }
1918 if (ntries == 200) {
1919 device_printf(sc->sc_dev,
1920 "timeout waiting for MAC initialization\n");
1921 return (ETIMEDOUT);
1922 }
1923
1924 /* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
1925 reg = urtwn_read_2(sc, R92C_CR);
1926 reg |= R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
1927 R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN | R92C_CR_PROTOCOL_EN |
1928 R92C_CR_SCHEDULE_EN | R92C_CR_MACTXEN | R92C_CR_MACRXEN |
1929 R92C_CR_ENSEC;
1930 urtwn_write_2(sc, R92C_CR, reg);
1931
1932 urtwn_write_1(sc, 0xfe10, 0x19);
1933 return (0);
1934}
1935
1936static int
1937urtwn_llt_init(struct urtwn_softc *sc)
1938{
1939 int i, error;
1940
1941 /* Reserve pages [0; R92C_TX_PAGE_COUNT]. */
1942 for (i = 0; i < R92C_TX_PAGE_COUNT; i++) {
1943 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0)
1944 return (error);
1945 }
1946 /* NB: 0xff indicates end-of-list. */
1947 if ((error = urtwn_llt_write(sc, i, 0xff)) != 0)
1948 return (error);
1949 /*
1950 * Use pages [R92C_TX_PAGE_COUNT + 1; R92C_TXPKTBUF_COUNT - 1]
1951 * as ring buffer.
1952 */
1953 for (++i; i < R92C_TXPKTBUF_COUNT - 1; i++) {
1954 if ((error = urtwn_llt_write(sc, i, i + 1)) != 0)
1955 return (error);
1956 }
1957 /* Make the last page point to the beginning of the ring buffer. */
1958 error = urtwn_llt_write(sc, i, R92C_TX_PAGE_COUNT + 1);
1959 return (error);
1960}
1961
1962static void
1963urtwn_fw_reset(struct urtwn_softc *sc)
1964{
1965 uint16_t reg;
1966 int ntries;
1967
1968 /* Tell 8051 to reset itself. */
1969 urtwn_write_1(sc, R92C_HMETFR + 3, 0x20);
1970
1971 /* Wait until 8051 resets by itself. */
1972 for (ntries = 0; ntries < 100; ntries++) {
1973 reg = urtwn_read_2(sc, R92C_SYS_FUNC_EN);
1974 if (!(reg & R92C_SYS_FUNC_EN_CPUEN))
1975 return;
1976 DELAY(50);
1977 }
1978 /* Force 8051 reset. */
1979 urtwn_write_2(sc, R92C_SYS_FUNC_EN, reg & ~R92C_SYS_FUNC_EN_CPUEN);
1980}
1981
1982static int
1983urtwn_fw_loadpage(struct urtwn_softc *sc, int page, const uint8_t *buf, int len)
1984{
1985 uint32_t reg;
1986 int off, mlen, error = 0;
1987
1988 reg = urtwn_read_4(sc, R92C_MCUFWDL);
1989 reg = RW(reg, R92C_MCUFWDL_PAGE, page);
1990 urtwn_write_4(sc, R92C_MCUFWDL, reg);
1991
1992 off = R92C_FW_START_ADDR;
1993 while (len > 0) {
1994 if (len > 196)
1995 mlen = 196;
1996 else if (len > 4)
1997 mlen = 4;
1998 else
1999 mlen = 1;
2000 /* XXX fix this deconst */
2001 error = urtwn_write_region_1(sc, off,
2002 __DECONST(uint8_t *, buf), mlen);
2003 if (error != 0)
2004 break;
2005 off += mlen;
2006 buf += mlen;
2007 len -= mlen;
2008 }
2009 return (error);
2010}
2011
2012static int
2013urtwn_load_firmware(struct urtwn_softc *sc)
2014{
2015 const struct firmware *fw;
2016 const struct r92c_fw_hdr *hdr;
2017 const char *imagename;
2018 const u_char *ptr;
2019 size_t len;
2020 uint32_t reg;
2021 int mlen, ntries, page, error;
2022
2023 /* Read firmware image from the filesystem. */
2024 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) ==
2025 URTWN_CHIP_UMC_A_CUT)
2026 imagename = "urtwn-rtl8192cfwU";
2027 else
2028 imagename = "urtwn-rtl8192cfwT";
2029
2030 fw = firmware_get(imagename);
2031 if (fw == NULL) {
2032 device_printf(sc->sc_dev,
2033 "failed loadfirmware of file %s\n", imagename);
2034 return (ENOENT);
2035 }
2036
2037 len = fw->datasize;
2038
2039 if (len < sizeof(*hdr)) {
2040 device_printf(sc->sc_dev, "firmware too short\n");
2041 error = EINVAL;
2042 goto fail;
2043 }
2044 ptr = fw->data;
2045 hdr = (const struct r92c_fw_hdr *)ptr;
2046 /* Check if there is a valid FW header and skip it. */
2047 if ((le16toh(hdr->signature) >> 4) == 0x88c ||
2048 (le16toh(hdr->signature) >> 4) == 0x92c) {
2049 DPRINTF("FW V%d.%d %02d-%02d %02d:%02d\n",
2050 le16toh(hdr->version), le16toh(hdr->subversion),
2051 hdr->month, hdr->date, hdr->hour, hdr->minute);
2052 ptr += sizeof(*hdr);
2053 len -= sizeof(*hdr);
2054 }
2055
2056 if (urtwn_read_1(sc, R92C_MCUFWDL) & 0x80) {
2057 urtwn_fw_reset(sc);
2058 urtwn_write_1(sc, R92C_MCUFWDL, 0);
2059 }
2060 urtwn_write_2(sc, R92C_SYS_FUNC_EN,
2061 urtwn_read_2(sc, R92C_SYS_FUNC_EN) |
2062 R92C_SYS_FUNC_EN_CPUEN);
2063 urtwn_write_1(sc, R92C_MCUFWDL,
2064 urtwn_read_1(sc, R92C_MCUFWDL) | R92C_MCUFWDL_EN);
2065 urtwn_write_1(sc, R92C_MCUFWDL + 2,
2066 urtwn_read_1(sc, R92C_MCUFWDL + 2) & ~0x08);
2067
2068 for (page = 0; len > 0; page++) {
2069 mlen = min(len, R92C_FW_PAGE_SIZE);
2070 error = urtwn_fw_loadpage(sc, page, ptr, mlen);
2071 if (error != 0) {
2072 device_printf(sc->sc_dev,
2073 "could not load firmware page\n");
2074 goto fail;
2075 }
2076 ptr += mlen;
2077 len -= mlen;
2078 }
2079 urtwn_write_1(sc, R92C_MCUFWDL,
2080 urtwn_read_1(sc, R92C_MCUFWDL) & ~R92C_MCUFWDL_EN);
2081 urtwn_write_1(sc, R92C_MCUFWDL + 1, 0);
2082
2083 /* Wait for checksum report. */
2084 for (ntries = 0; ntries < 1000; ntries++) {
2085 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_CHKSUM_RPT)
2086 break;
2087 DELAY(5);
2088 }
2089 if (ntries == 1000) {
2090 device_printf(sc->sc_dev,
2091 "timeout waiting for checksum report\n");
2092 error = ETIMEDOUT;
2093 goto fail;
2094 }
2095
2096 reg = urtwn_read_4(sc, R92C_MCUFWDL);
2097 reg = (reg & ~R92C_MCUFWDL_WINTINI_RDY) | R92C_MCUFWDL_RDY;
2098 urtwn_write_4(sc, R92C_MCUFWDL, reg);
2099 /* Wait for firmware readiness. */
2100 for (ntries = 0; ntries < 1000; ntries++) {
2101 if (urtwn_read_4(sc, R92C_MCUFWDL) & R92C_MCUFWDL_WINTINI_RDY)
2102 break;
2103 DELAY(5);
2104 }
2105 if (ntries == 1000) {
2106 device_printf(sc->sc_dev,
2107 "timeout waiting for firmware readiness\n");
2108 error = ETIMEDOUT;
2109 goto fail;
2110 }
2111fail:
2112 firmware_put(fw, FIRMWARE_UNLOAD);
2113 return (error);
2114}
2115
2116static int
2117urtwn_dma_init(struct urtwn_softc *sc)
2118{
2119 int hashq, hasnq, haslq, nqueues, nqpages, nrempages;
2120 uint32_t reg;
2121 int error;
2122
2123 /* Initialize LLT table. */
2124 error = urtwn_llt_init(sc);
2125 if (error != 0)
2126 return (error);
2127
2128 /* Get Tx queues to USB endpoints mapping. */
2129 hashq = hasnq = haslq = 0;
2130 reg = urtwn_read_2(sc, R92C_USB_EP + 1);
2131 DPRINTFN(2, "USB endpoints mapping 0x%x\n", reg);
2132 if (MS(reg, R92C_USB_EP_HQ) != 0)
2133 hashq = 1;
2134 if (MS(reg, R92C_USB_EP_NQ) != 0)
2135 hasnq = 1;
2136 if (MS(reg, R92C_USB_EP_LQ) != 0)
2137 haslq = 1;
2138 nqueues = hashq + hasnq + haslq;
2139 if (nqueues == 0)
2140 return (EIO);
2141 /* Get the number of pages for each queue. */
2142 nqpages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) / nqueues;
2143 /* The remaining pages are assigned to the high priority queue. */
2144 nrempages = (R92C_TX_PAGE_COUNT - R92C_PUBQ_NPAGES) % nqueues;
2145
2146 /* Set number of pages for normal priority queue. */
2147 urtwn_write_1(sc, R92C_RQPN_NPQ, hasnq ? nqpages : 0);
2148 urtwn_write_4(sc, R92C_RQPN,
2149 /* Set number of pages for public queue. */
2150 SM(R92C_RQPN_PUBQ, R92C_PUBQ_NPAGES) |
2151 /* Set number of pages for high priority queue. */
2152 SM(R92C_RQPN_HPQ, hashq ? nqpages + nrempages : 0) |
2153 /* Set number of pages for low priority queue. */
2154 SM(R92C_RQPN_LPQ, haslq ? nqpages : 0) |
2155 /* Load values. */
2156 R92C_RQPN_LD);
2157
2158 urtwn_write_1(sc, R92C_TXPKTBUF_BCNQ_BDNY, R92C_TX_PAGE_BOUNDARY);
2159 urtwn_write_1(sc, R92C_TXPKTBUF_MGQ_BDNY, R92C_TX_PAGE_BOUNDARY);
2160 urtwn_write_1(sc, R92C_TXPKTBUF_WMAC_LBK_BF_HD, R92C_TX_PAGE_BOUNDARY);
2161 urtwn_write_1(sc, R92C_TRXFF_BNDY, R92C_TX_PAGE_BOUNDARY);
2162 urtwn_write_1(sc, R92C_TDECTRL + 1, R92C_TX_PAGE_BOUNDARY);
2163
2164 /* Set queue to USB pipe mapping. */
2165 reg = urtwn_read_2(sc, R92C_TRXDMA_CTRL);
2166 reg &= ~R92C_TRXDMA_CTRL_QMAP_M;
2167 if (nqueues == 1) {
2168 if (hashq)
2169 reg |= R92C_TRXDMA_CTRL_QMAP_HQ;
2170 else if (hasnq)
2171 reg |= R92C_TRXDMA_CTRL_QMAP_NQ;
2172 else
2173 reg |= R92C_TRXDMA_CTRL_QMAP_LQ;
2174 } else if (nqueues == 2) {
2175 /* All 2-endpoints configs have a high priority queue. */
2176 if (!hashq)
2177 return (EIO);
2178 if (hasnq)
2179 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_NQ;
2180 else
2181 reg |= R92C_TRXDMA_CTRL_QMAP_HQ_LQ;
2182 } else
2183 reg |= R92C_TRXDMA_CTRL_QMAP_3EP;
2184 urtwn_write_2(sc, R92C_TRXDMA_CTRL, reg);
2185
2186 /* Set Tx/Rx transfer page boundary. */
2187 urtwn_write_2(sc, R92C_TRXFF_BNDY + 2, 0x27ff);
2188
2189 /* Set Tx/Rx transfer page size. */
2190 urtwn_write_1(sc, R92C_PBP,
2191 SM(R92C_PBP_PSRX, R92C_PBP_128) |
2192 SM(R92C_PBP_PSTX, R92C_PBP_128));
2193 return (0);
2194}
2195
2196static void
2197urtwn_mac_init(struct urtwn_softc *sc)
2198{
2199 int i;
2200
2201 /* Write MAC initialization values. */
2202 for (i = 0; i < nitems(rtl8192cu_mac); i++)
2203 urtwn_write_1(sc, rtl8192cu_mac[i].reg, rtl8192cu_mac[i].val);
2204}
2205
2206static void
2207urtwn_bb_init(struct urtwn_softc *sc)
2208{
2209 const struct urtwn_bb_prog *prog;
2210 uint32_t reg;
2211 int i;
2212
2213 /* Enable BB and RF. */
2214 urtwn_write_2(sc, R92C_SYS_FUNC_EN,
2215 urtwn_read_2(sc, R92C_SYS_FUNC_EN) |
2216 R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST |
2217 R92C_SYS_FUNC_EN_DIO_RF);
2218
2219 urtwn_write_2(sc, R92C_AFE_PLL_CTRL, 0xdb83);
2220
2221 urtwn_write_1(sc, R92C_RF_CTRL,
2222 R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB);
2223 urtwn_write_1(sc, R92C_SYS_FUNC_EN,
2224 R92C_SYS_FUNC_EN_USBA | R92C_SYS_FUNC_EN_USBD |
2225 R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB);
2226
2227 urtwn_write_1(sc, R92C_LDOHCI12_CTRL, 0x0f);
2228 urtwn_write_1(sc, 0x15, 0xe9);
2229 urtwn_write_1(sc, R92C_AFE_XTAL_CTRL + 1, 0x80);
2230
2231 /* Select BB programming based on board type. */
2232 if (!(sc->chip & URTWN_CHIP_92C)) {
2233 if (sc->board_type == R92C_BOARD_TYPE_MINICARD)
2234 prog = &rtl8188ce_bb_prog;
2235 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA)
2236 prog = &rtl8188ru_bb_prog;
2237 else
2238 prog = &rtl8188cu_bb_prog;
2239 } else {
2240 if (sc->board_type == R92C_BOARD_TYPE_MINICARD)
2241 prog = &rtl8192ce_bb_prog;
2242 else
2243 prog = &rtl8192cu_bb_prog;
2244 }
2245 /* Write BB initialization values. */
2246 for (i = 0; i < prog->count; i++) {
2247 urtwn_bb_write(sc, prog->regs[i], prog->vals[i]);
2248 DELAY(1);
2249 }
2250
2251 if (sc->chip & URTWN_CHIP_92C_1T2R) {
2252 /* 8192C 1T only configuration. */
2253 reg = urtwn_bb_read(sc, R92C_FPGA0_TXINFO);
2254 reg = (reg & ~0x00000003) | 0x2;
2255 urtwn_bb_write(sc, R92C_FPGA0_TXINFO, reg);
2256
2257 reg = urtwn_bb_read(sc, R92C_FPGA1_TXINFO);
2258 reg = (reg & ~0x00300033) | 0x00200022;
2259 urtwn_bb_write(sc, R92C_FPGA1_TXINFO, reg);
2260
2261 reg = urtwn_bb_read(sc, R92C_CCK0_AFESETTING);
2262 reg = (reg & ~0xff000000) | 0x45 << 24;
2263 urtwn_bb_write(sc, R92C_CCK0_AFESETTING, reg);
2264
2265 reg = urtwn_bb_read(sc, R92C_OFDM0_TRXPATHENA);
2266 reg = (reg & ~0x000000ff) | 0x23;
2267 urtwn_bb_write(sc, R92C_OFDM0_TRXPATHENA, reg);
2268
2269 reg = urtwn_bb_read(sc, R92C_OFDM0_AGCPARAM1);
2270 reg = (reg & ~0x00000030) | 1 << 4;
2271 urtwn_bb_write(sc, R92C_OFDM0_AGCPARAM1, reg);
2272
2273 reg = urtwn_bb_read(sc, 0xe74);
2274 reg = (reg & ~0x0c000000) | 2 << 26;
2275 urtwn_bb_write(sc, 0xe74, reg);
2276 reg = urtwn_bb_read(sc, 0xe78);
2277 reg = (reg & ~0x0c000000) | 2 << 26;
2278 urtwn_bb_write(sc, 0xe78, reg);
2279 reg = urtwn_bb_read(sc, 0xe7c);
2280 reg = (reg & ~0x0c000000) | 2 << 26;
2281 urtwn_bb_write(sc, 0xe7c, reg);
2282 reg = urtwn_bb_read(sc, 0xe80);
2283 reg = (reg & ~0x0c000000) | 2 << 26;
2284 urtwn_bb_write(sc, 0xe80, reg);
2285 reg = urtwn_bb_read(sc, 0xe88);
2286 reg = (reg & ~0x0c000000) | 2 << 26;
2287 urtwn_bb_write(sc, 0xe88, reg);
2288 }
2289
2290 /* Write AGC values. */
2291 for (i = 0; i < prog->agccount; i++) {
2292 urtwn_bb_write(sc, R92C_OFDM0_AGCRSSITABLE,
2293 prog->agcvals[i]);
2294 DELAY(1);
2295 }
2296
2297 if (urtwn_bb_read(sc, R92C_HSSI_PARAM2(0)) &
2298 R92C_HSSI_PARAM2_CCK_HIPWR)
2299 sc->sc_flags |= URTWN_FLAG_CCK_HIPWR;
2300}
2301
2302void
2303urtwn_rf_init(struct urtwn_softc *sc)
2304{
2305 const struct urtwn_rf_prog *prog;
2306 uint32_t reg, type;
2307 int i, j, idx, off;
2308
2309 /* Select RF programming based on board type. */
2310 if (!(sc->chip & URTWN_CHIP_92C)) {
2311 if (sc->board_type == R92C_BOARD_TYPE_MINICARD)
2312 prog = rtl8188ce_rf_prog;
2313 else if (sc->board_type == R92C_BOARD_TYPE_HIGHPA)
2314 prog = rtl8188ru_rf_prog;
2315 else
2316 prog = rtl8188cu_rf_prog;
2317 } else
2318 prog = rtl8192ce_rf_prog;
2319
2320 for (i = 0; i < sc->nrxchains; i++) {
2321 /* Save RF_ENV control type. */
2322 idx = i / 2;
2323 off = (i % 2) * 16;
2324 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));
2325 type = (reg >> off) & 0x10;
2326
2327 /* Set RF_ENV enable. */
2328 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i));
2329 reg |= 0x100000;
2330 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg);
2331 DELAY(1);
2332 /* Set RF_ENV output high. */
2333 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(i));
2334 reg |= 0x10;
2335 urtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(i), reg);
2336 DELAY(1);
2337 /* Set address and data lengths of RF registers. */
2338 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i));
2339 reg &= ~R92C_HSSI_PARAM2_ADDR_LENGTH;
2340 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg);
2341 DELAY(1);
2342 reg = urtwn_bb_read(sc, R92C_HSSI_PARAM2(i));
2343 reg &= ~R92C_HSSI_PARAM2_DATA_LENGTH;
2344 urtwn_bb_write(sc, R92C_HSSI_PARAM2(i), reg);
2345 DELAY(1);
2346
2347 /* Write RF initialization values for this chain. */
2348 for (j = 0; j < prog[i].count; j++) {
2349 if (prog[i].regs[j] >= 0xf9 &&
2350 prog[i].regs[j] <= 0xfe) {
2351 /*
2352 * These are fake RF registers offsets that
2353 * indicate a delay is required.
2354 */
2355 usb_pause_mtx(&sc->sc_mtx, 50);
2356 continue;
2357 }
2358 urtwn_rf_write(sc, i, prog[i].regs[j],
2359 prog[i].vals[j]);
2360 DELAY(1);
2361 }
2362
2363 /* Restore RF_ENV control type. */
2364 reg = urtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));
2365 reg &= ~(0x10 << off) | (type << off);
2366 urtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg);
2367
2368 /* Cache RF register CHNLBW. */
2369 sc->rf_chnlbw[i] = urtwn_rf_read(sc, i, R92C_RF_CHNLBW);
2370 }
2371
2372 if ((sc->chip & (URTWN_CHIP_UMC_A_CUT | URTWN_CHIP_92C)) ==
2373 URTWN_CHIP_UMC_A_CUT) {
2374 urtwn_rf_write(sc, 0, R92C_RF_RX_G1, 0x30255);
2375 urtwn_rf_write(sc, 0, R92C_RF_RX_G2, 0x50a00);
2376 }
2377}
2378
2379static void
2380urtwn_cam_init(struct urtwn_softc *sc)
2381{
2382 /* Invalidate all CAM entries. */
2383 urtwn_write_4(sc, R92C_CAMCMD,
2384 R92C_CAMCMD_POLLING | R92C_CAMCMD_CLR);
2385}
2386
2387static void
2388urtwn_pa_bias_init(struct urtwn_softc *sc)
2389{
2390 uint8_t reg;
2391 int i;
2392
2393 for (i = 0; i < sc->nrxchains; i++) {
2394 if (sc->pa_setting & (1 << i))
2395 continue;
2396 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x0f406);
2397 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x4f406);
2398 urtwn_rf_write(sc, i, R92C_RF_IPA, 0x8f406);
2399 urtwn_rf_write(sc, i, R92C_RF_IPA, 0xcf406);
2400 }
2401 if (!(sc->pa_setting & 0x10)) {
2402 reg = urtwn_read_1(sc, 0x16);
2403 reg = (reg & ~0xf0) | 0x90;
2404 urtwn_write_1(sc, 0x16, reg);
2405 }
2406}
2407
2408static void
2409urtwn_rxfilter_init(struct urtwn_softc *sc)
2410{
2411 /* Initialize Rx filter. */
2412 /* TODO: use better filter for monitor mode. */
2413 urtwn_write_4(sc, R92C_RCR,
2414 R92C_RCR_AAP | R92C_RCR_APM | R92C_RCR_AM | R92C_RCR_AB |
2415 R92C_RCR_APP_ICV | R92C_RCR_AMF | R92C_RCR_HTC_LOC_CTRL |
2416 R92C_RCR_APP_MIC | R92C_RCR_APP_PHYSTS);
2417 /* Accept all multicast frames. */
2418 urtwn_write_4(sc, R92C_MAR + 0, 0xffffffff);
2419 urtwn_write_4(sc, R92C_MAR + 4, 0xffffffff);
2420 /* Accept all management frames. */
2421 urtwn_write_2(sc, R92C_RXFLTMAP0, 0xffff);
2422 /* Reject all control frames. */
2423 urtwn_write_2(sc, R92C_RXFLTMAP1, 0x0000);
2424 /* Accept all data frames. */
2425 urtwn_write_2(sc, R92C_RXFLTMAP2, 0xffff);
2426}
2427
2428static void
2429urtwn_edca_init(struct urtwn_softc *sc)
2430{
2431 urtwn_write_2(sc, R92C_SPEC_SIFS, 0x100a);
2432 urtwn_write_2(sc, R92C_MAC_SPEC_SIFS, 0x100a);
2433 urtwn_write_2(sc, R92C_SIFS_CCK, 0x100a);
2434 urtwn_write_2(sc, R92C_SIFS_OFDM, 0x100a);
2435 urtwn_write_4(sc, R92C_EDCA_BE_PARAM, 0x005ea42b);
2436 urtwn_write_4(sc, R92C_EDCA_BK_PARAM, 0x0000a44f);
2437 urtwn_write_4(sc, R92C_EDCA_VI_PARAM, 0x005ea324);
2438 urtwn_write_4(sc, R92C_EDCA_VO_PARAM, 0x002fa226);
2439}
2440
2441void
2442urtwn_write_txpower(struct urtwn_softc *sc, int chain,
2443 uint16_t power[URTWN_RIDX_COUNT])
2444{
2445 uint32_t reg;
2446
2447 /* Write per-CCK rate Tx power. */
2448 if (chain == 0) {
2449 reg = urtwn_bb_read(sc, R92C_TXAGC_A_CCK1_MCS32);
2450 reg = RW(reg, R92C_TXAGC_A_CCK1, power[0]);
2451 urtwn_bb_write(sc, R92C_TXAGC_A_CCK1_MCS32, reg);
2452 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
2453 reg = RW(reg, R92C_TXAGC_A_CCK2, power[1]);
2454 reg = RW(reg, R92C_TXAGC_A_CCK55, power[2]);
2455 reg = RW(reg, R92C_TXAGC_A_CCK11, power[3]);
2456 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);
2457 } else {
2458 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK1_55_MCS32);
2459 reg = RW(reg, R92C_TXAGC_B_CCK1, power[0]);
2460 reg = RW(reg, R92C_TXAGC_B_CCK2, power[1]);
2461 reg = RW(reg, R92C_TXAGC_B_CCK55, power[2]);
2462 urtwn_bb_write(sc, R92C_TXAGC_B_CCK1_55_MCS32, reg);
2463 reg = urtwn_bb_read(sc, R92C_TXAGC_B_CCK11_A_CCK2_11);
2464 reg = RW(reg, R92C_TXAGC_B_CCK11, power[3]);
2465 urtwn_bb_write(sc, R92C_TXAGC_B_CCK11_A_CCK2_11, reg);
2466 }
2467 /* Write per-OFDM rate Tx power. */
2468 urtwn_bb_write(sc, R92C_TXAGC_RATE18_06(chain),
2469 SM(R92C_TXAGC_RATE06, power[ 4]) |
2470 SM(R92C_TXAGC_RATE09, power[ 5]) |
2471 SM(R92C_TXAGC_RATE12, power[ 6]) |
2472 SM(R92C_TXAGC_RATE18, power[ 7]));
2473 urtwn_bb_write(sc, R92C_TXAGC_RATE54_24(chain),
2474 SM(R92C_TXAGC_RATE24, power[ 8]) |
2475 SM(R92C_TXAGC_RATE36, power[ 9]) |
2476 SM(R92C_TXAGC_RATE48, power[10]) |
2477 SM(R92C_TXAGC_RATE54, power[11]));
2478 /* Write per-MCS Tx power. */
2479 urtwn_bb_write(sc, R92C_TXAGC_MCS03_MCS00(chain),
2480 SM(R92C_TXAGC_MCS00, power[12]) |
2481 SM(R92C_TXAGC_MCS01, power[13]) |
2482 SM(R92C_TXAGC_MCS02, power[14]) |
2483 SM(R92C_TXAGC_MCS03, power[15]));
2484 urtwn_bb_write(sc, R92C_TXAGC_MCS07_MCS04(chain),
2485 SM(R92C_TXAGC_MCS04, power[16]) |
2486 SM(R92C_TXAGC_MCS05, power[17]) |
2487 SM(R92C_TXAGC_MCS06, power[18]) |
2488 SM(R92C_TXAGC_MCS07, power[19]));
2489 urtwn_bb_write(sc, R92C_TXAGC_MCS11_MCS08(chain),
2490 SM(R92C_TXAGC_MCS08, power[20]) |
2491 SM(R92C_TXAGC_MCS08, power[21]) |
2492 SM(R92C_TXAGC_MCS10, power[22]) |
2493 SM(R92C_TXAGC_MCS11, power[23]));
2494 urtwn_bb_write(sc, R92C_TXAGC_MCS15_MCS12(chain),
2495 SM(R92C_TXAGC_MCS12, power[24]) |
2496 SM(R92C_TXAGC_MCS13, power[25]) |
2497 SM(R92C_TXAGC_MCS14, power[26]) |
2498 SM(R92C_TXAGC_MCS15, power[27]));
2499}
2500
2501void
2502urtwn_get_txpower(struct urtwn_softc *sc, int chain,
2503 struct ieee80211_channel *c, struct ieee80211_channel *extc,
2504 uint16_t power[URTWN_RIDX_COUNT])
2505{
2506 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
2507 struct r92c_rom *rom = &sc->rom;
2508 uint16_t cckpow, ofdmpow, htpow, diff, max;
2509 const struct urtwn_txpwr *base;
2510 int ridx, chan, group;
2511
2512 /* Determine channel group. */
2513 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */
2514 if (chan <= 3)
2515 group = 0;
2516 else if (chan <= 9)
2517 group = 1;
2518 else
2519 group = 2;
2520
2521 /* Get original Tx power based on board type and RF chain. */
2522 if (!(sc->chip & URTWN_CHIP_92C)) {
2523 if (sc->board_type == R92C_BOARD_TYPE_HIGHPA)
2524 base = &rtl8188ru_txagc[chain];
2525 else
2526 base = &rtl8192cu_txagc[chain];
2527 } else
2528 base = &rtl8192cu_txagc[chain];
2529
2530 memset(power, 0, URTWN_RIDX_COUNT * sizeof(power[0]));
2531 if (sc->regulatory == 0) {
2532 for (ridx = 0; ridx <= 3; ridx++)
2533 power[ridx] = base->pwr[0][ridx];
2534 }
2535 for (ridx = 4; ridx < URTWN_RIDX_COUNT; ridx++) {
2536 if (sc->regulatory == 3) {
2537 power[ridx] = base->pwr[0][ridx];
2538 /* Apply vendor limits. */
2539 if (extc != NULL)
2540 max = rom->ht40_max_pwr[group];
2541 else
2542 max = rom->ht20_max_pwr[group];
2543 max = (max >> (chain * 4)) & 0xf;
2544 if (power[ridx] > max)
2545 power[ridx] = max;
2546 } else if (sc->regulatory == 1) {
2547 if (extc == NULL)
2548 power[ridx] = base->pwr[group][ridx];
2549 } else if (sc->regulatory != 2)
2550 power[ridx] = base->pwr[0][ridx];
2551 }
2552
2553 /* Compute per-CCK rate Tx power. */
2554 cckpow = rom->cck_tx_pwr[chain][group];
2555 for (ridx = 0; ridx <= 3; ridx++) {
2556 power[ridx] += cckpow;
2557 if (power[ridx] > R92C_MAX_TX_PWR)
2558 power[ridx] = R92C_MAX_TX_PWR;
2559 }
2560
2561 htpow = rom->ht40_1s_tx_pwr[chain][group];
2562 if (sc->ntxchains > 1) {
2563 /* Apply reduction for 2 spatial streams. */
2564 diff = rom->ht40_2s_tx_pwr_diff[group];
2565 diff = (diff >> (chain * 4)) & 0xf;
2566 htpow = (htpow > diff) ? htpow - diff : 0;
2567 }
2568
2569 /* Compute per-OFDM rate Tx power. */
2570 diff = rom->ofdm_tx_pwr_diff[group];
2571 diff = (diff >> (chain * 4)) & 0xf;
2572 ofdmpow = htpow + diff; /* HT->OFDM correction. */
2573 for (ridx = 4; ridx <= 11; ridx++) {
2574 power[ridx] += ofdmpow;
2575 if (power[ridx] > R92C_MAX_TX_PWR)
2576 power[ridx] = R92C_MAX_TX_PWR;
2577 }
2578
2579 /* Compute per-MCS Tx power. */
2580 if (extc == NULL) {
2581 diff = rom->ht20_tx_pwr_diff[group];
2582 diff = (diff >> (chain * 4)) & 0xf;
2583 htpow += diff; /* HT40->HT20 correction. */
2584 }
2585 for (ridx = 12; ridx <= 27; ridx++) {
2586 power[ridx] += htpow;
2587 if (power[ridx] > R92C_MAX_TX_PWR)
2588 power[ridx] = R92C_MAX_TX_PWR;
2589 }
2590#ifdef URTWN_DEBUG
2591 if (urtwn_debug >= 4) {
2592 /* Dump per-rate Tx power values. */
2593 printf("Tx power for chain %d:\n", chain);
2594 for (ridx = 0; ridx < URTWN_RIDX_COUNT; ridx++)
2595 printf("Rate %d = %u\n", ridx, power[ridx]);
2596 }
2597#endif
2598}
2599
2600void
2601urtwn_set_txpower(struct urtwn_softc *sc, struct ieee80211_channel *c,
2602 struct ieee80211_channel *extc)
2603{
2604 uint16_t power[URTWN_RIDX_COUNT];
2605 int i;
2606
2607 for (i = 0; i < sc->ntxchains; i++) {
2608 /* Compute per-rate Tx power values. */
2609 urtwn_get_txpower(sc, i, c, extc, power);
2610 /* Write per-rate Tx power values to hardware. */
2611 urtwn_write_txpower(sc, i, power);
2612 }
2613}
2614
2615static void
2616urtwn_scan_start(struct ieee80211com *ic)
2617{
2618 /* XXX do nothing? */
2619}
2620
2621static void
2622urtwn_scan_end(struct ieee80211com *ic)
2623{
2624 /* XXX do nothing? */
2625}
2626
2627static void
2628urtwn_set_channel(struct ieee80211com *ic)
2629{
2630 struct urtwn_softc *sc = ic->ic_ifp->if_softc;
2631
2632 URTWN_LOCK(sc);
2633 urtwn_set_chan(sc, ic->ic_curchan, NULL);
2634 URTWN_UNLOCK(sc);
2635}
2636
2637static void
2638urtwn_update_mcast(struct ifnet *ifp)
2639{
2640 /* XXX do nothing? */
2641}
2642
2643static void
2644urtwn_set_chan(struct urtwn_softc *sc, struct ieee80211_channel *c,
2645 struct ieee80211_channel *extc)
2646{
2647 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
2648 uint32_t reg;
2649 u_int chan;
2650 int i;
2651
2652 chan = ieee80211_chan2ieee(ic, c); /* XXX center freq! */
2653 if (chan == 0 || chan == IEEE80211_CHAN_ANY) {
2654 device_printf(sc->sc_dev,
2655 "%s: invalid channel %x\n", __func__, chan);
2656 return;
2657 }
2658
2659 /* Set Tx power for this new channel. */
2660 urtwn_set_txpower(sc, c, extc);
2661
2662 for (i = 0; i < sc->nrxchains; i++) {
2663 urtwn_rf_write(sc, i, R92C_RF_CHNLBW,
2664 RW(sc->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan));
2665 }
2666#ifndef IEEE80211_NO_HT
2667 if (extc != NULL) {
2668 /* Is secondary channel below or above primary? */
2669 int prichlo = c->ic_freq < extc->ic_freq;
2670
2671 urtwn_write_1(sc, R92C_BWOPMODE,
2672 urtwn_read_1(sc, R92C_BWOPMODE) & ~R92C_BWOPMODE_20MHZ);
2673
2674 reg = urtwn_read_1(sc, R92C_RRSR + 2);
2675 reg = (reg & ~0x6f) | (prichlo ? 1 : 2) << 5;
2676 urtwn_write_1(sc, R92C_RRSR + 2, reg);
2677
2678 urtwn_bb_write(sc, R92C_FPGA0_RFMOD,
2679 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) | R92C_RFMOD_40MHZ);
2680 urtwn_bb_write(sc, R92C_FPGA1_RFMOD,
2681 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) | R92C_RFMOD_40MHZ);
2682
2683 /* Set CCK side band. */
2684 reg = urtwn_bb_read(sc, R92C_CCK0_SYSTEM);
2685 reg = (reg & ~0x00000010) | (prichlo ? 0 : 1) << 4;
2686 urtwn_bb_write(sc, R92C_CCK0_SYSTEM, reg);
2687
2688 reg = urtwn_bb_read(sc, R92C_OFDM1_LSTF);
2689 reg = (reg & ~0x00000c00) | (prichlo ? 1 : 2) << 10;
2690 urtwn_bb_write(sc, R92C_OFDM1_LSTF, reg);
2691
2692 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2,
2693 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) &
2694 ~R92C_FPGA0_ANAPARAM2_CBW20);
2695
2696 reg = urtwn_bb_read(sc, 0x818);
2697 reg = (reg & ~0x0c000000) | (prichlo ? 2 : 1) << 26;
2698 urtwn_bb_write(sc, 0x818, reg);
2699
2700 /* Select 40MHz bandwidth. */
2701 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW,
2702 (sc->rf_chnlbw[0] & ~0xfff) | chan);
2703 } else
2704#endif
2705 {
2706 urtwn_write_1(sc, R92C_BWOPMODE,
2707 urtwn_read_1(sc, R92C_BWOPMODE) | R92C_BWOPMODE_20MHZ);
2708
2709 urtwn_bb_write(sc, R92C_FPGA0_RFMOD,
2710 urtwn_bb_read(sc, R92C_FPGA0_RFMOD) & ~R92C_RFMOD_40MHZ);
2711 urtwn_bb_write(sc, R92C_FPGA1_RFMOD,
2712 urtwn_bb_read(sc, R92C_FPGA1_RFMOD) & ~R92C_RFMOD_40MHZ);
2713
2714 urtwn_bb_write(sc, R92C_FPGA0_ANAPARAM2,
2715 urtwn_bb_read(sc, R92C_FPGA0_ANAPARAM2) |
2716 R92C_FPGA0_ANAPARAM2_CBW20);
2717
2718 /* Select 20MHz bandwidth. */
2719 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW,
2720 (sc->rf_chnlbw[0] & ~0xfff) | R92C_RF_CHNLBW_BW20 | chan);
2721 }
2722}
2723
2724static void
2725urtwn_iq_calib(struct urtwn_softc *sc)
2726{
2727 /* TODO */
2728}
2729
2730static void
2731urtwn_lc_calib(struct urtwn_softc *sc)
2732{
2733 uint32_t rf_ac[2];
2734 uint8_t txmode;
2735 int i;
2736
2737 txmode = urtwn_read_1(sc, R92C_OFDM1_LSTF + 3);
2738 if ((txmode & 0x70) != 0) {
2739 /* Disable all continuous Tx. */
2740 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode & ~0x70);
2741
2742 /* Set RF mode to standby mode. */
2743 for (i = 0; i < sc->nrxchains; i++) {
2744 rf_ac[i] = urtwn_rf_read(sc, i, R92C_RF_AC);
2745 urtwn_rf_write(sc, i, R92C_RF_AC,
2746 RW(rf_ac[i], R92C_RF_AC_MODE,
2747 R92C_RF_AC_MODE_STANDBY));
2748 }
2749 } else {
2750 /* Block all Tx queues. */
2751 urtwn_write_1(sc, R92C_TXPAUSE, 0xff);
2752 }
2753 /* Start calibration. */
2754 urtwn_rf_write(sc, 0, R92C_RF_CHNLBW,
2755 urtwn_rf_read(sc, 0, R92C_RF_CHNLBW) | R92C_RF_CHNLBW_LCSTART);
2756
2757 /* Give calibration the time to complete. */
2758 usb_pause_mtx(&sc->sc_mtx, 100);
2759
2760 /* Restore configuration. */
2761 if ((txmode & 0x70) != 0) {
2762 /* Restore Tx mode. */
2763 urtwn_write_1(sc, R92C_OFDM1_LSTF + 3, txmode);
2764 /* Restore RF mode. */
2765 for (i = 0; i < sc->nrxchains; i++)
2766 urtwn_rf_write(sc, i, R92C_RF_AC, rf_ac[i]);
2767 } else {
2768 /* Unblock all Tx queues. */
2769 urtwn_write_1(sc, R92C_TXPAUSE, 0x00);
2770 }
2771}
2772
2773static void
2774urtwn_init_locked(void *arg)
2775{
2776 struct urtwn_softc *sc = arg;
2777 struct ifnet *ifp = sc->sc_ifp;
2778 uint32_t reg;
2779 int error;
2780
2781 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2782 urtwn_stop_locked(ifp, 0);
2783
2784 /* Init firmware commands ring. */
2785 sc->fwcur = 0;
2786
2787 /* Allocate Tx/Rx buffers. */
2788 error = urtwn_alloc_rx_list(sc);
2789 if (error != 0)
2790 goto fail;
2791
2792 error = urtwn_alloc_tx_list(sc);
2793 if (error != 0)
2794 goto fail;
2795
2796 /* Power on adapter. */
2797 error = urtwn_power_on(sc);
2798 if (error != 0)
2799 goto fail;
2800
2801 /* Initialize DMA. */
2802 error = urtwn_dma_init(sc);
2803 if (error != 0)
2804 goto fail;
2805
2806 /* Set info size in Rx descriptors (in 64-bit words). */
2807 urtwn_write_1(sc, R92C_RX_DRVINFO_SZ, 4);
2808
2809 /* Init interrupts. */
2810 urtwn_write_4(sc, R92C_HISR, 0xffffffff);
2811 urtwn_write_4(sc, R92C_HIMR, 0xffffffff);
2812
2813 /* Set MAC address. */
2814 urtwn_write_region_1(sc, R92C_MACID, IF_LLADDR(ifp),
2815 IEEE80211_ADDR_LEN);
2816
2817 /* Set initial network type. */
2818 reg = urtwn_read_4(sc, R92C_CR);
2819 reg = RW(reg, R92C_CR_NETTYPE, R92C_CR_NETTYPE_INFRA);
2820 urtwn_write_4(sc, R92C_CR, reg);
2821
2822 urtwn_rxfilter_init(sc);
2823
2824 reg = urtwn_read_4(sc, R92C_RRSR);
2825 reg = RW(reg, R92C_RRSR_RATE_BITMAP, R92C_RRSR_RATE_CCK_ONLY_1M);
2826 urtwn_write_4(sc, R92C_RRSR, reg);
2827
2828 /* Set short/long retry limits. */
2829 urtwn_write_2(sc, R92C_RL,
2830 SM(R92C_RL_SRL, 0x30) | SM(R92C_RL_LRL, 0x30));
2831
2832 /* Initialize EDCA parameters. */
2833 urtwn_edca_init(sc);
2834
2835 /* Setup rate fallback. */
2836 urtwn_write_4(sc, R92C_DARFRC + 0, 0x00000000);
2837 urtwn_write_4(sc, R92C_DARFRC + 4, 0x10080404);
2838 urtwn_write_4(sc, R92C_RARFRC + 0, 0x04030201);
2839 urtwn_write_4(sc, R92C_RARFRC + 4, 0x08070605);
2840
2841 urtwn_write_1(sc, R92C_FWHW_TXQ_CTRL,
2842 urtwn_read_1(sc, R92C_FWHW_TXQ_CTRL) |
2843 R92C_FWHW_TXQ_CTRL_AMPDU_RTY_NEW);
2844 /* Set ACK timeout. */
2845 urtwn_write_1(sc, R92C_ACKTO, 0x40);
2846
2847 /* Setup USB aggregation. */
2848 reg = urtwn_read_4(sc, R92C_TDECTRL);
2849 reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, 6);
2850 urtwn_write_4(sc, R92C_TDECTRL, reg);
2851 urtwn_write_1(sc, R92C_TRXDMA_CTRL,
2852 urtwn_read_1(sc, R92C_TRXDMA_CTRL) |
2853 R92C_TRXDMA_CTRL_RXDMA_AGG_EN);
2854 urtwn_write_1(sc, R92C_USB_SPECIAL_OPTION,
2855 urtwn_read_1(sc, R92C_USB_SPECIAL_OPTION) |
2856 R92C_USB_SPECIAL_OPTION_AGG_EN);
2857 urtwn_write_1(sc, R92C_RXDMA_AGG_PG_TH, 48);
2858 urtwn_write_1(sc, R92C_USB_DMA_AGG_TO, 4);
2859 urtwn_write_1(sc, R92C_USB_AGG_TH, 8);
2860 urtwn_write_1(sc, R92C_USB_AGG_TO, 6);
2861
2862 /* Initialize beacon parameters. */
2863 urtwn_write_2(sc, R92C_TBTT_PROHIBIT, 0x6404);
2864 urtwn_write_1(sc, R92C_DRVERLYINT, 0x05);
2865 urtwn_write_1(sc, R92C_BCNDMATIM, 0x02);
2866 urtwn_write_2(sc, R92C_BCNTCFG, 0x660f);
2867
2868 /* Setup AMPDU aggregation. */
2869 urtwn_write_4(sc, R92C_AGGLEN_LMT, 0x99997631); /* MCS7~0 */
2870 urtwn_write_1(sc, R92C_AGGR_BREAK_TIME, 0x16);
2871 urtwn_write_2(sc, 0x4ca, 0x0708);
2872
2873 urtwn_write_1(sc, R92C_BCN_MAX_ERR, 0xff);
2874 urtwn_write_1(sc, R92C_BCN_CTRL, R92C_BCN_CTRL_DIS_TSF_UDT0);
2875
2876 /* Load 8051 microcode. */
2877 error = urtwn_load_firmware(sc);
2878 if (error != 0)
2879 goto fail;
2880
2881 /* Initialize MAC/BB/RF blocks. */
2882 urtwn_mac_init(sc);
2883 urtwn_bb_init(sc);
2884 urtwn_rf_init(sc);
2885
2886 /* Turn CCK and OFDM blocks on. */
2887 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD);
2888 reg |= R92C_RFMOD_CCK_EN;
2889 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg);
2890 reg = urtwn_bb_read(sc, R92C_FPGA0_RFMOD);
2891 reg |= R92C_RFMOD_OFDM_EN;
2892 urtwn_bb_write(sc, R92C_FPGA0_RFMOD, reg);
2893
2894 /* Clear per-station keys table. */
2895 urtwn_cam_init(sc);
2896
2897 /* Enable hardware sequence numbering. */
2898 urtwn_write_1(sc, R92C_HWSEQ_CTRL, 0xff);
2899
2900 /* Perform LO and IQ calibrations. */
2901 urtwn_iq_calib(sc);
2902 /* Perform LC calibration. */
2903 urtwn_lc_calib(sc);
2904
2905 /* Fix USB interference issue. */
2906 urtwn_write_1(sc, 0xfe40, 0xe0);
2907 urtwn_write_1(sc, 0xfe41, 0x8d);
2908 urtwn_write_1(sc, 0xfe42, 0x80);
2909
2910 urtwn_pa_bias_init(sc);
2911
2912 /* Initialize GPIO setting. */
2913 urtwn_write_1(sc, R92C_GPIO_MUXCFG,
2914 urtwn_read_1(sc, R92C_GPIO_MUXCFG) & ~R92C_GPIO_MUXCFG_ENBT);
2915
2916 /* Fix for lower temperature. */
2917 urtwn_write_1(sc, 0x15, 0xe9);
2918
2919 usbd_transfer_start(sc->sc_xfer[URTWN_BULK_RX]);
2920
2921 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2922 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2923
2924 callout_reset(&sc->sc_watchdog_ch, hz, urtwn_watchdog, sc);
2925fail:
2926 return;
2927}
2928
2929static void
2930urtwn_init(void *arg)
2931{
2932 struct urtwn_softc *sc = arg;
2933
2934 URTWN_LOCK(sc);
2935 urtwn_init_locked(arg);
2936 URTWN_UNLOCK(sc);
2937}
2938
2939static void
2940urtwn_stop_locked(struct ifnet *ifp, int disable)
2941{
2942 struct urtwn_softc *sc = ifp->if_softc;
2943
2944 (void)disable;
2945 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2946
2947 callout_stop(&sc->sc_watchdog_ch);
2948 urtwn_abort_xfers(sc);
2949}
2950
2951static void
2952urtwn_stop(struct ifnet *ifp, int disable)
2953{
2954 struct urtwn_softc *sc = ifp->if_softc;
2955
2956 URTWN_LOCK(sc);
2957 urtwn_stop_locked(ifp, disable);
2958 URTWN_UNLOCK(sc);
2959}
2960
2961static void
2962urtwn_abort_xfers(struct urtwn_softc *sc)
2963{
2964 int i;
2965
2966 URTWN_ASSERT_LOCKED(sc);
2967
2968 /* abort any pending transfers */
2969 for (i = 0; i < URTWN_N_TRANSFER; i++)
2970 usbd_transfer_stop(sc->sc_xfer[i]);
2971}
2972
2973static int
2974urtwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
2975 const struct ieee80211_bpf_params *params)
2976{
2977 struct ieee80211com *ic = ni->ni_ic;
2978 struct ifnet *ifp = ic->ic_ifp;
2979 struct urtwn_softc *sc = ifp->if_softc;
2980 struct urtwn_data *bf;
2981
2982 /* prevent management frames from being sent if we're not ready */
2983 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
2984 m_freem(m);
2985 ieee80211_free_node(ni);
2986 return (ENETDOWN);
2987 }
2988 URTWN_LOCK(sc);
2989 bf = urtwn_getbuf(sc);
2990 if (bf == NULL) {
2991 ieee80211_free_node(ni);
2992 m_freem(m);
2993 URTWN_UNLOCK(sc);
2994 return (ENOBUFS);
2995 }
2996
2997 ifp->if_opackets++;
2998 if (urtwn_tx_start(sc, ni, m, bf) != 0) {
2999 ieee80211_free_node(ni);
3000 ifp->if_oerrors++;
3001 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next);
3002 URTWN_UNLOCK(sc);
3003 return (EIO);
3004 }
3005 URTWN_UNLOCK(sc);
3006
3007 sc->sc_txtimer = 5;
3008 return (0);
3009}
3010
3011static device_method_t urtwn_methods[] = {
3012 /* Device interface */
3013 DEVMETHOD(device_probe, urtwn_match),
3014 DEVMETHOD(device_attach, urtwn_attach),
3015 DEVMETHOD(device_detach, urtwn_detach),
3016
3017 { 0, 0 }
3018};
3019
3020static driver_t urtwn_driver = {
3021 "urtwn",
3022 urtwn_methods,
3023 sizeof(struct urtwn_softc)
3024};
3025
3026static devclass_t urtwn_devclass;
3027
3028DRIVER_MODULE(urtwn, uhub, urtwn_driver, urtwn_devclass, NULL, NULL);
3029MODULE_DEPEND(urtwn, usb, 1, 1, 1);
3030MODULE_DEPEND(urtwn, wlan, 1, 1, 1);
3031MODULE_DEPEND(urtwn, firmware, 1, 1, 1);
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