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uhci.c (184610) uhci.c (184824)
1/*-
2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved.
3 * Copyright (c) 1998 The NetBSD Foundation, Inc. All rights reserved.
4 * Copyright (c) 1998 Lennart Augustsson. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 12 unchanged lines hidden (view full) ---

21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved.
3 * Copyright (c) 1998 The NetBSD Foundation, Inc. All rights reserved.
4 * Copyright (c) 1998 Lennart Augustsson. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 12 unchanged lines hidden (view full) ---

21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
29__FBSDID("$FreeBSD: head/sys/dev/usb2/controller/uhci2.c 184610 2008-11-04 02:31:03Z alfred $");
29__FBSDID("$FreeBSD: head/sys/dev/usb2/controller/uhci2.c 184824 2008-11-10 20:54:31Z thompsa $");
30
31/*
32 * USB Universal Host Controller driver.
33 * Handles e.g. PIIX3 and PIIX4.
34 *
35 * UHCI spec: http://developer.intel.com/design/USB/UHCI11D.htm
36 * USB spec: http://www.usb.org/developers/docs/usbspec.zip
37 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf

--- 222 unchanged lines hidden (view full) ---

260}
261
262void
263uhci_reset(uhci_softc_t *sc)
264{
265 struct usb2_page_search buf_res;
266 uint16_t n;
267
30
31/*
32 * USB Universal Host Controller driver.
33 * Handles e.g. PIIX3 and PIIX4.
34 *
35 * UHCI spec: http://developer.intel.com/design/USB/UHCI11D.htm
36 * USB spec: http://www.usb.org/developers/docs/usbspec.zip
37 * PIIXn spec: ftp://download.intel.com/design/intarch/datashts/29055002.pdf

--- 222 unchanged lines hidden (view full) ---

260}
261
262void
263uhci_reset(uhci_softc_t *sc)
264{
265 struct usb2_page_search buf_res;
266 uint16_t n;
267
268 mtx_assert(&sc->sc_bus.mtx, MA_OWNED);
268 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
269
270 DPRINTF("resetting the HC\n");
271
272 /* disable interrupts */
273
274 UWRITE2(sc, UHCI_INTR, 0);
275
276 /* global reset */
277
278 UHCICMD(sc, UHCI_CMD_GRESET);
279
280 /* wait */
281
269
270 DPRINTF("resetting the HC\n");
271
272 /* disable interrupts */
273
274 UWRITE2(sc, UHCI_INTR, 0);
275
276 /* global reset */
277
278 UHCICMD(sc, UHCI_CMD_GRESET);
279
280 /* wait */
281
282 usb2_pause_mtx(&sc->sc_bus.mtx,
282 usb2_pause_mtx(&sc->sc_bus.bus_mtx,
283 USB_BUS_RESET_DELAY);
284
285 /* terminate all transfers */
286
287 UHCICMD(sc, UHCI_CMD_HCRESET);
288
289 /* the reset bit goes low when the controller is done */
290
291 n = UHCI_RESET_TIMEOUT;
292 while (n--) {
293 /* wait one millisecond */
294
283 USB_BUS_RESET_DELAY);
284
285 /* terminate all transfers */
286
287 UHCICMD(sc, UHCI_CMD_HCRESET);
288
289 /* the reset bit goes low when the controller is done */
290
291 n = UHCI_RESET_TIMEOUT;
292 while (n--) {
293 /* wait one millisecond */
294
295 usb2_pause_mtx(&sc->sc_bus.mtx, 1);
295 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 1);
296
297 if (!(UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET)) {
298 goto done_1;
299 }
300 }
301
302 device_printf(sc->sc_bus.bdev,
303 "controller did not reset\n");
304
305done_1:
306
307 n = 10;
308 while (n--) {
309 /* wait one millisecond */
310
296
297 if (!(UREAD2(sc, UHCI_CMD) & UHCI_CMD_HCRESET)) {
298 goto done_1;
299 }
300 }
301
302 device_printf(sc->sc_bus.bdev,
303 "controller did not reset\n");
304
305done_1:
306
307 n = 10;
308 while (n--) {
309 /* wait one millisecond */
310
311 usb2_pause_mtx(&sc->sc_bus.mtx, 1);
311 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 1);
312
313 /* check if HC is stopped */
314 if (UREAD2(sc, UHCI_STS) & UHCI_STS_HCH) {
315 goto done_2;
316 }
317 }
318
319 device_printf(sc->sc_bus.bdev,

--- 7 unchanged lines hidden (view full) ---

327 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum);
328 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof);
329 return;
330}
331
332static void
333uhci_start(uhci_softc_t *sc)
334{
312
313 /* check if HC is stopped */
314 if (UREAD2(sc, UHCI_STS) & UHCI_STS_HCH) {
315 goto done_2;
316 }
317 }
318
319 device_printf(sc->sc_bus.bdev,

--- 7 unchanged lines hidden (view full) ---

327 UWRITE2(sc, UHCI_FRNUM, sc->sc_saved_frnum);
328 UWRITE1(sc, UHCI_SOF, sc->sc_saved_sof);
329 return;
330}
331
332static void
333uhci_start(uhci_softc_t *sc)
334{
335 mtx_assert(&sc->sc_bus.mtx, MA_OWNED);
335 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
336
337 DPRINTFN(2, "enabling\n");
338
339 /* enable interrupts */
340
341 UWRITE2(sc, UHCI_INTR,
342 (UHCI_INTR_TOCRCIE |
343 UHCI_INTR_RIE |

--- 6 unchanged lines hidden (view full) ---

350
351 UHCICMD(sc, (UHCI_CMD_MAXP | UHCI_CMD_RS));
352
353 uint8_t n = 10;
354
355 while (n--) {
356 /* wait one millisecond */
357
336
337 DPRINTFN(2, "enabling\n");
338
339 /* enable interrupts */
340
341 UWRITE2(sc, UHCI_INTR,
342 (UHCI_INTR_TOCRCIE |
343 UHCI_INTR_RIE |

--- 6 unchanged lines hidden (view full) ---

350
351 UHCICMD(sc, (UHCI_CMD_MAXP | UHCI_CMD_RS));
352
353 uint8_t n = 10;
354
355 while (n--) {
356 /* wait one millisecond */
357
358 usb2_pause_mtx(&sc->sc_bus.mtx, 1);
358 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 1);
359
360 /* check that controller has started */
361
362 if (!(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH)) {
363 goto done;
364 }
365 }
366

--- 44 unchanged lines hidden (view full) ---

411
412usb2_error_t
413uhci_init(uhci_softc_t *sc)
414{
415 uint16_t bit;
416 uint16_t x;
417 uint16_t y;
418
359
360 /* check that controller has started */
361
362 if (!(UREAD2(sc, UHCI_STS) & UHCI_STS_HCH)) {
363 goto done;
364 }
365 }
366

--- 44 unchanged lines hidden (view full) ---

411
412usb2_error_t
413uhci_init(uhci_softc_t *sc)
414{
415 uint16_t bit;
416 uint16_t x;
417 uint16_t y;
418
419 mtx_lock(&sc->sc_bus.mtx);
419 USB_BUS_LOCK(&sc->sc_bus);
420
421 DPRINTF("start\n");
422
423#if USB_DEBUG
424 if (uhcidebug > 2) {
425 uhci_dumpregs(sc);
426 }
427#endif

--- 180 unchanged lines hidden (view full) ---

608 sc->sc_bus.methods = &uhci_bus_methods;
609
610 /* reset the controller */
611 uhci_reset(sc);
612
613 /* start the controller */
614 uhci_start(sc);
615
420
421 DPRINTF("start\n");
422
423#if USB_DEBUG
424 if (uhcidebug > 2) {
425 uhci_dumpregs(sc);
426 }
427#endif

--- 180 unchanged lines hidden (view full) ---

608 sc->sc_bus.methods = &uhci_bus_methods;
609
610 /* reset the controller */
611 uhci_reset(sc);
612
613 /* start the controller */
614 uhci_start(sc);
615
616 mtx_unlock(&sc->sc_bus.mtx);
616 USB_BUS_UNLOCK(&sc->sc_bus);
617
618 /* catch lost interrupts */
619 uhci_do_poll(&sc->sc_bus);
620
621 return (0);
622}
623
624/* NOTE: suspend/resume is called from
625 * interrupt context and cannot sleep!
626 */
627
628void
629uhci_suspend(uhci_softc_t *sc)
630{
617
618 /* catch lost interrupts */
619 uhci_do_poll(&sc->sc_bus);
620
621 return (0);
622}
623
624/* NOTE: suspend/resume is called from
625 * interrupt context and cannot sleep!
626 */
627
628void
629uhci_suspend(uhci_softc_t *sc)
630{
631 mtx_lock(&sc->sc_bus.mtx);
631 USB_BUS_LOCK(&sc->sc_bus);
632
633#if USB_DEBUG
634 if (uhcidebug > 2) {
635 uhci_dumpregs(sc);
636 }
637#endif
638 /* save some state if BIOS doesn't */
639
640 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM);
641 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF);
642
643 /* stop the controller */
644
645 uhci_reset(sc);
646
647 /* enter global suspend */
648
649 UHCICMD(sc, UHCI_CMD_EGSM);
650
632
633#if USB_DEBUG
634 if (uhcidebug > 2) {
635 uhci_dumpregs(sc);
636 }
637#endif
638 /* save some state if BIOS doesn't */
639
640 sc->sc_saved_frnum = UREAD2(sc, UHCI_FRNUM);
641 sc->sc_saved_sof = UREAD1(sc, UHCI_SOF);
642
643 /* stop the controller */
644
645 uhci_reset(sc);
646
647 /* enter global suspend */
648
649 UHCICMD(sc, UHCI_CMD_EGSM);
650
651 usb2_pause_mtx(&sc->sc_bus.mtx, USB_RESUME_WAIT);
651 usb2_pause_mtx(&sc->sc_bus.bus_mtx, USB_RESUME_WAIT);
652
652
653 mtx_unlock(&sc->sc_bus.mtx);
653 USB_BUS_UNLOCK(&sc->sc_bus);
654 return;
655}
656
657void
658uhci_resume(uhci_softc_t *sc)
659{
654 return;
655}
656
657void
658uhci_resume(uhci_softc_t *sc)
659{
660 mtx_lock(&sc->sc_bus.mtx);
660 USB_BUS_LOCK(&sc->sc_bus);
661
662 /* reset the controller */
663
664 uhci_reset(sc);
665
666 /* force global resume */
667
668 UHCICMD(sc, UHCI_CMD_FGR);
669
661
662 /* reset the controller */
663
664 uhci_reset(sc);
665
666 /* force global resume */
667
668 UHCICMD(sc, UHCI_CMD_FGR);
669
670 usb2_pause_mtx(&sc->sc_bus.mtx,
670 usb2_pause_mtx(&sc->sc_bus.bus_mtx,
671 USB_RESUME_DELAY);
672
673 /* and start traffic again */
674
675 uhci_start(sc);
676
677#if USB_DEBUG
678 if (uhcidebug > 2) {
679 uhci_dumpregs(sc);
680 }
681#endif
682
671 USB_RESUME_DELAY);
672
673 /* and start traffic again */
674
675 uhci_start(sc);
676
677#if USB_DEBUG
678 if (uhcidebug > 2) {
679 uhci_dumpregs(sc);
680 }
681#endif
682
683 mtx_unlock(&sc->sc_bus.mtx);
683 USB_BUS_UNLOCK(&sc->sc_bus);
684
685 /* catch lost interrupts */
686 uhci_do_poll(&sc->sc_bus);
687
688 return;
689}
690
691#if USB_DEBUG

--- 751 unchanged lines hidden (view full) ---

1443 * hence the interrupt handler will be setup before "sc->sc_bus.bdev"
1444 * is present !
1445 *------------------------------------------------------------------------*/
1446void
1447uhci_interrupt(uhci_softc_t *sc)
1448{
1449 uint32_t status;
1450
684
685 /* catch lost interrupts */
686 uhci_do_poll(&sc->sc_bus);
687
688 return;
689}
690
691#if USB_DEBUG

--- 751 unchanged lines hidden (view full) ---

1443 * hence the interrupt handler will be setup before "sc->sc_bus.bdev"
1444 * is present !
1445 *------------------------------------------------------------------------*/
1446void
1447uhci_interrupt(uhci_softc_t *sc)
1448{
1449 uint32_t status;
1450
1451 mtx_lock(&sc->sc_bus.mtx);
1451 USB_BUS_LOCK(&sc->sc_bus);
1452
1453 DPRINTFN(16, "real interrupt\n");
1454
1455#if USB_DEBUG
1456 if (uhcidebug > 15) {
1457 uhci_dumpregs(sc);
1458 }
1459#endif

--- 41 unchanged lines hidden (view full) ---

1501 }
1502 /* acknowledge interrupts */
1503 UWRITE2(sc, UHCI_STS, status);
1504
1505 /* poll all the USB transfers */
1506 uhci_interrupt_poll(sc);
1507
1508done:
1452
1453 DPRINTFN(16, "real interrupt\n");
1454
1455#if USB_DEBUG
1456 if (uhcidebug > 15) {
1457 uhci_dumpregs(sc);
1458 }
1459#endif

--- 41 unchanged lines hidden (view full) ---

1501 }
1502 /* acknowledge interrupts */
1503 UWRITE2(sc, UHCI_STS, status);
1504
1505 /* poll all the USB transfers */
1506 uhci_interrupt_poll(sc);
1507
1508done:
1509 mtx_unlock(&sc->sc_bus.mtx);
1509 USB_BUS_UNLOCK(&sc->sc_bus);
1510 return;
1511}
1512
1513/*
1514 * called when a request does not complete
1515 */
1516static void
1517uhci_timeout(void *arg)
1518{
1519 struct usb2_xfer *xfer = arg;
1520 uhci_softc_t *sc = xfer->usb2_sc;
1521
1522 DPRINTF("xfer=%p\n", xfer);
1523
1510 return;
1511}
1512
1513/*
1514 * called when a request does not complete
1515 */
1516static void
1517uhci_timeout(void *arg)
1518{
1519 struct usb2_xfer *xfer = arg;
1520 uhci_softc_t *sc = xfer->usb2_sc;
1521
1522 DPRINTF("xfer=%p\n", xfer);
1523
1524 mtx_assert(&sc->sc_bus.mtx, MA_OWNED);
1524 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1525
1526 /* transfer is transferred */
1527 uhci_device_done(xfer, USB_ERR_TIMEOUT);
1528
1525
1526 /* transfer is transferred */
1527 uhci_device_done(xfer, USB_ERR_TIMEOUT);
1528
1529 mtx_unlock(&sc->sc_bus.mtx);
1529 USB_BUS_UNLOCK(&sc->sc_bus);
1530
1531 return;
1532}
1533
1534static void
1535uhci_do_poll(struct usb2_bus *bus)
1536{
1537 struct uhci_softc *sc = UHCI_BUS2SC(bus);
1538
1530
1531 return;
1532}
1533
1534static void
1535uhci_do_poll(struct usb2_bus *bus)
1536{
1537 struct uhci_softc *sc = UHCI_BUS2SC(bus);
1538
1539 mtx_lock(&sc->sc_bus.mtx);
1539 USB_BUS_LOCK(&sc->sc_bus);
1540 uhci_interrupt_poll(sc);
1541 uhci_root_ctrl_poll(sc);
1540 uhci_interrupt_poll(sc);
1541 uhci_root_ctrl_poll(sc);
1542 mtx_unlock(&sc->sc_bus.mtx);
1542 USB_BUS_UNLOCK(&sc->sc_bus);
1543 return;
1544}
1545
1546static void
1547uhci_setup_standard_chain_sub(struct uhci_std_temp *temp)
1548{
1549 uhci_td_t *td;
1550 uhci_td_t *td_next;

--- 301 unchanged lines hidden (view full) ---

1852
1853static void
1854uhci_device_done(struct usb2_xfer *xfer, usb2_error_t error)
1855{
1856 struct usb2_pipe_methods *methods = xfer->pipe->methods;
1857 uhci_softc_t *sc = xfer->usb2_sc;
1858 uhci_qh_t *qh;
1859
1543 return;
1544}
1545
1546static void
1547uhci_setup_standard_chain_sub(struct uhci_std_temp *temp)
1548{
1549 uhci_td_t *td;
1550 uhci_td_t *td_next;

--- 301 unchanged lines hidden (view full) ---

1852
1853static void
1854uhci_device_done(struct usb2_xfer *xfer, usb2_error_t error)
1855{
1856 struct usb2_pipe_methods *methods = xfer->pipe->methods;
1857 uhci_softc_t *sc = xfer->usb2_sc;
1858 uhci_qh_t *qh;
1859
1860 mtx_assert(&sc->sc_bus.mtx, MA_OWNED);
1860 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1861
1862 DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n",
1863 xfer, xfer->pipe, error);
1864
1865 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1866 if (qh) {
1867 usb2_pc_cpu_invalidate(qh->page_cache);
1868

--- 563 unchanged lines hidden (view full) ---

2432
2433 x = URWMASK(UREAD2(sc, port));
2434 UWRITE2(sc, port, x | UHCI_PORTSC_PR);
2435
2436 if (use_polling) {
2437 /* polling */
2438 DELAY(USB_PORT_ROOT_RESET_DELAY * 1000);
2439 } else {
1861
1862 DPRINTFN(2, "xfer=%p, pipe=%p, error=%d\n",
1863 xfer, xfer->pipe, error);
1864
1865 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1866 if (qh) {
1867 usb2_pc_cpu_invalidate(qh->page_cache);
1868

--- 563 unchanged lines hidden (view full) ---

2432
2433 x = URWMASK(UREAD2(sc, port));
2434 UWRITE2(sc, port, x | UHCI_PORTSC_PR);
2435
2436 if (use_polling) {
2437 /* polling */
2438 DELAY(USB_PORT_ROOT_RESET_DELAY * 1000);
2439 } else {
2440 usb2_pause_mtx(&sc->sc_bus.mtx,
2440 usb2_pause_mtx(&sc->sc_bus.bus_mtx,
2441 USB_PORT_ROOT_RESET_DELAY);
2442 }
2443
2444 DPRINTFN(4, "uhci port %d reset, status0 = 0x%04x\n",
2445 index, UREAD2(sc, port));
2446
2447 x = URWMASK(UREAD2(sc, port));
2448 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR);
2449
2450 if (use_polling) {
2451 /* polling */
2452 DELAY(1000);
2453 } else {
2441 USB_PORT_ROOT_RESET_DELAY);
2442 }
2443
2444 DPRINTFN(4, "uhci port %d reset, status0 = 0x%04x\n",
2445 index, UREAD2(sc, port));
2446
2447 x = URWMASK(UREAD2(sc, port));
2448 UWRITE2(sc, port, x & ~UHCI_PORTSC_PR);
2449
2450 if (use_polling) {
2451 /* polling */
2452 DELAY(1000);
2453 } else {
2454 usb2_pause_mtx(&sc->sc_bus.mtx, 1);
2454 usb2_pause_mtx(&sc->sc_bus.bus_mtx, 1);
2455 }
2456
2457 DPRINTFN(4, "uhci port %d reset, status1 = 0x%04x\n",
2458 index, UREAD2(sc, port));
2459
2460 x = URWMASK(UREAD2(sc, port));
2461 UWRITE2(sc, port, x | UHCI_PORTSC_PE);
2462
2463 for (lim = 0; lim < 12; lim++) {
2464
2465 if (use_polling) {
2466 /* polling */
2467 DELAY(USB_PORT_RESET_DELAY * 1000);
2468 } else {
2455 }
2456
2457 DPRINTFN(4, "uhci port %d reset, status1 = 0x%04x\n",
2458 index, UREAD2(sc, port));
2459
2460 x = URWMASK(UREAD2(sc, port));
2461 UWRITE2(sc, port, x | UHCI_PORTSC_PE);
2462
2463 for (lim = 0; lim < 12; lim++) {
2464
2465 if (use_polling) {
2466 /* polling */
2467 DELAY(USB_PORT_RESET_DELAY * 1000);
2468 } else {
2469 usb2_pause_mtx(&sc->sc_bus.mtx,
2469 usb2_pause_mtx(&sc->sc_bus.bus_mtx,
2470 USB_PORT_RESET_DELAY);
2471 }
2472
2473 x = UREAD2(sc, port);
2474
2475 DPRINTFN(4, "uhci port %d iteration %u, status = 0x%04x\n",
2476 index, lim, x);
2477

--- 77 unchanged lines hidden (view full) ---

2555 uint16_t x;
2556 uint16_t port;
2557 uint16_t value;
2558 uint16_t index;
2559 uint16_t status;
2560 uint16_t change;
2561 uint8_t use_polling;
2562
2470 USB_PORT_RESET_DELAY);
2471 }
2472
2473 x = UREAD2(sc, port);
2474
2475 DPRINTFN(4, "uhci port %d iteration %u, status = 0x%04x\n",
2476 index, lim, x);
2477

--- 77 unchanged lines hidden (view full) ---

2555 uint16_t x;
2556 uint16_t port;
2557 uint16_t value;
2558 uint16_t index;
2559 uint16_t status;
2560 uint16_t change;
2561 uint8_t use_polling;
2562
2563 mtx_assert(&sc->sc_bus.mtx, MA_OWNED);
2563 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2564
2565 if (std->state != USB_SW_TR_SETUP) {
2566 if (std->state == USB_SW_TR_PRE_CALLBACK) {
2567 /* transfer transferred */
2568 uhci_device_done(xfer, std->err);
2569 }
2570 goto done;
2571 }
2572 /* buffer reset */
2573 std->ptr = sc->sc_hub_desc.temp;
2574 std->len = 0;
2575
2576 value = UGETW(std->req.wValue);
2577 index = UGETW(std->req.wIndex);
2578
2564
2565 if (std->state != USB_SW_TR_SETUP) {
2566 if (std->state == USB_SW_TR_PRE_CALLBACK) {
2567 /* transfer transferred */
2568 uhci_device_done(xfer, std->err);
2569 }
2570 goto done;
2571 }
2572 /* buffer reset */
2573 std->ptr = sc->sc_hub_desc.temp;
2574 std->len = 0;
2575
2576 value = UGETW(std->req.wValue);
2577 index = UGETW(std->req.wIndex);
2578
2579 use_polling = mtx_owned(xfer->priv_mtx) ? 1 : 0;
2579 use_polling = mtx_owned(xfer->xfer_mtx) ? 1 : 0;
2580
2581 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
2582 "wValue=0x%04x wIndex=0x%04x\n",
2583 std->req.bmRequestType, std->req.bRequest,
2584 UGETW(std->req.wLength), value, index);
2585
2586#define C(x,y) ((x) | ((y) << 8))
2587 switch (C(std->req.bRequest, std->req.bmRequestType)) {

--- 320 unchanged lines hidden (view full) ---

2908}
2909
2910static void
2911uhci_root_intr_done(struct usb2_xfer *xfer,
2912 struct usb2_sw_transfer *std)
2913{
2914 uhci_softc_t *sc = xfer->usb2_sc;
2915
2580
2581 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
2582 "wValue=0x%04x wIndex=0x%04x\n",
2583 std->req.bmRequestType, std->req.bRequest,
2584 UGETW(std->req.wLength), value, index);
2585
2586#define C(x,y) ((x) | ((y) << 8))
2587 switch (C(std->req.bRequest, std->req.bmRequestType)) {

--- 320 unchanged lines hidden (view full) ---

2908}
2909
2910static void
2911uhci_root_intr_done(struct usb2_xfer *xfer,
2912 struct usb2_sw_transfer *std)
2913{
2914 uhci_softc_t *sc = xfer->usb2_sc;
2915
2916 mtx_assert(&sc->sc_bus.mtx, MA_OWNED);
2916 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2917
2918 if (std->state != USB_SW_TR_PRE_DATA) {
2919 if (std->state == USB_SW_TR_PRE_CALLBACK) {
2920 /* transfer is transferred */
2921 uhci_device_done(xfer, std->err);
2922 }
2923 goto done;
2924 }

--- 11 unchanged lines hidden (view full) ---

2936static void
2937uhci_root_intr_check(void *arg)
2938{
2939 struct usb2_xfer *xfer = arg;
2940 uhci_softc_t *sc = xfer->usb2_sc;
2941
2942 DPRINTFN(21, "\n");
2943
2917
2918 if (std->state != USB_SW_TR_PRE_DATA) {
2919 if (std->state == USB_SW_TR_PRE_CALLBACK) {
2920 /* transfer is transferred */
2921 uhci_device_done(xfer, std->err);
2922 }
2923 goto done;
2924 }

--- 11 unchanged lines hidden (view full) ---

2936static void
2937uhci_root_intr_check(void *arg)
2938{
2939 struct usb2_xfer *xfer = arg;
2940 uhci_softc_t *sc = xfer->usb2_sc;
2941
2942 DPRINTFN(21, "\n");
2943
2944 mtx_assert(&sc->sc_bus.mtx, MA_OWNED);
2944 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2945
2946 sc->sc_hub_idata[0] = 0;
2947
2948 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC | UHCI_PORTSC_OCIC)) {
2949 sc->sc_hub_idata[0] |= 1 << 1;
2950 }
2951 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC | UHCI_PORTSC_OCIC)) {
2952 sc->sc_hub_idata[0] |= 1 << 2;
2953 }
2954 if ((sc->sc_hub_idata[0] == 0) || !(UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) {
2955 /*
2956 * no change or controller not running, try again in a while
2957 */
2958 uhci_root_intr_start(xfer);
2959 } else {
2960 usb2_sw_transfer(&sc->sc_root_intr,
2961 &uhci_root_intr_done);
2962 }
2945
2946 sc->sc_hub_idata[0] = 0;
2947
2948 if (UREAD2(sc, UHCI_PORTSC1) & (UHCI_PORTSC_CSC | UHCI_PORTSC_OCIC)) {
2949 sc->sc_hub_idata[0] |= 1 << 1;
2950 }
2951 if (UREAD2(sc, UHCI_PORTSC2) & (UHCI_PORTSC_CSC | UHCI_PORTSC_OCIC)) {
2952 sc->sc_hub_idata[0] |= 1 << 2;
2953 }
2954 if ((sc->sc_hub_idata[0] == 0) || !(UREAD2(sc, UHCI_CMD) & UHCI_CMD_RS)) {
2955 /*
2956 * no change or controller not running, try again in a while
2957 */
2958 uhci_root_intr_start(xfer);
2959 } else {
2960 usb2_sw_transfer(&sc->sc_root_intr,
2961 &uhci_root_intr_done);
2962 }
2963 mtx_unlock(&sc->sc_bus.mtx);
2963 USB_BUS_UNLOCK(&sc->sc_bus);
2964 return;
2965}
2966
2967struct usb2_pipe_methods uhci_root_intr_methods =
2968{
2969 .open = uhci_root_intr_open,
2970 .close = uhci_root_intr_close,
2971 .enter = uhci_root_intr_enter,

--- 285 unchanged lines hidden --- 		2964 return;
2965}
2966
2967struct usb2_pipe_methods uhci_root_intr_methods =
2968{
2969 .open = uhci_root_intr_open,
2970 .close = uhci_root_intr_close,
2971 .enter = uhci_root_intr_enter,

--- 285 unchanged lines hidden ---