| ohci.h (196219) | ohci.h (198151) |
|---|---|
| 1/* $FreeBSD: head/sys/dev/usb/controller/ohci.h 196219 2009-08-14 20:03:53Z jhb $ */ | 1/* $FreeBSD: head/sys/dev/usb/controller/ohci.h 198151 2009-10-15 20:07:08Z thompsa $ */ |
| 2/*- 3 * Copyright (c) 1998 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Lennart Augustsson (lennart@augustsson.net) at 8 * Carlstedt Research & Technology. 9 * --- 26 unchanged lines hidden (view full) --- 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39#ifndef _OHCI_H_ 40#define _OHCI_H_ 41 42#define OHCI_MAX_DEVICES MIN(USB_MAX_DEVICES, 128) 43 | 2/*- 3 * Copyright (c) 1998 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Lennart Augustsson (lennart@augustsson.net) at 8 * Carlstedt Research & Technology. 9 * --- 26 unchanged lines hidden (view full) --- 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39#ifndef _OHCI_H_ 40#define _OHCI_H_ 41 42#define OHCI_MAX_DEVICES MIN(USB_MAX_DEVICES, 128) 43 |
| 44/* PCI config registers */ 45#define PCI_CBMEM 0x10 /* configuration base memory */ 46#define PCI_INTERFACE_OHCI 0x10 47 48/* OHCI registers */ 49#define OHCI_REVISION 0x00 /* OHCI revision */ 50#define OHCI_REV_LO(rev) ((rev) & 0xf) 51#define OHCI_REV_HI(rev) (((rev)>>4) & 0xf) 52#define OHCI_REV_LEGACY(rev) ((rev) & 0x100) 53#define OHCI_CONTROL 0x04 54#define OHCI_CBSR_MASK 0x00000003 /* Control/Bulk Service Ratio */ 55#define OHCI_RATIO_1_1 0x00000000 56#define OHCI_RATIO_1_2 0x00000001 57#define OHCI_RATIO_1_3 0x00000002 58#define OHCI_RATIO_1_4 0x00000003 59#define OHCI_PLE 0x00000004 /* Periodic List Enable */ 60#define OHCI_IE 0x00000008 /* Isochronous Enable */ 61#define OHCI_CLE 0x00000010 /* Control List Enable */ 62#define OHCI_BLE 0x00000020 /* Bulk List Enable */ 63#define OHCI_HCFS_MASK 0x000000c0 /* HostControllerFunctionalStat 64 * e */ 65#define OHCI_HCFS_RESET 0x00000000 66#define OHCI_HCFS_RESUME 0x00000040 67#define OHCI_HCFS_OPERATIONAL 0x00000080 68#define OHCI_HCFS_SUSPEND 0x000000c0 69#define OHCI_IR 0x00000100 /* Interrupt Routing */ 70#define OHCI_RWC 0x00000200 /* Remote Wakeup Connected */ 71#define OHCI_RWE 0x00000400 /* Remote Wakeup Enabled */ 72#define OHCI_COMMAND_STATUS 0x08 73#define OHCI_HCR 0x00000001 /* Host Controller Reset */ 74#define OHCI_CLF 0x00000002 /* Control List Filled */ 75#define OHCI_BLF 0x00000004 /* Bulk List Filled */ 76#define OHCI_OCR 0x00000008 /* Ownership Change Request */ 77#define OHCI_SOC_MASK 0x00030000 /* Scheduling Overrun Count */ 78#define OHCI_INTERRUPT_STATUS 0x0c 79#define OHCI_SO 0x00000001 /* Scheduling Overrun */ 80#define OHCI_WDH 0x00000002 /* Writeback Done Head */ 81#define OHCI_SF 0x00000004 /* Start of Frame */ 82#define OHCI_RD 0x00000008 /* Resume Detected */ 83#define OHCI_UE 0x00000010 /* Unrecoverable Error */ 84#define OHCI_FNO 0x00000020 /* Frame Number Overflow */ 85#define OHCI_RHSC 0x00000040 /* Root Hub Status Change */ 86#define OHCI_OC 0x40000000 /* Ownership Change */ 87#define OHCI_MIE 0x80000000 /* Master Interrupt Enable */ 88#define OHCI_INTERRUPT_ENABLE 0x10 89#define OHCI_INTERRUPT_DISABLE 0x14 90#define OHCI_HCCA 0x18 91#define OHCI_PERIOD_CURRENT_ED 0x1c 92#define OHCI_CONTROL_HEAD_ED 0x20 93#define OHCI_CONTROL_CURRENT_ED 0x24 94#define OHCI_BULK_HEAD_ED 0x28 95#define OHCI_BULK_CURRENT_ED 0x2c 96#define OHCI_DONE_HEAD 0x30 97#define OHCI_FM_INTERVAL 0x34 98#define OHCI_GET_IVAL(s) ((s) & 0x3fff) 99#define OHCI_GET_FSMPS(s) (((s) >> 16) & 0x7fff) 100#define OHCI_FIT 0x80000000 101#define OHCI_FM_REMAINING 0x38 102#define OHCI_FM_NUMBER 0x3c 103#define OHCI_PERIODIC_START 0x40 104#define OHCI_LS_THRESHOLD 0x44 105#define OHCI_RH_DESCRIPTOR_A 0x48 106#define OHCI_GET_NDP(s) ((s) & 0xff) 107#define OHCI_PSM 0x0100 /* Power Switching Mode */ 108#define OHCI_NPS 0x0200 /* No Power Switching */ 109#define OHCI_DT 0x0400 /* Device Type */ 110#define OHCI_OCPM 0x0800 /* Overcurrent Protection Mode */ 111#define OHCI_NOCP 0x1000 /* No Overcurrent Protection */ 112#define OHCI_GET_POTPGT(s) ((s) >> 24) 113#define OHCI_RH_DESCRIPTOR_B 0x4c 114#define OHCI_RH_STATUS 0x50 115#define OHCI_LPS 0x00000001 /* Local Power Status */ 116#define OHCI_OCI 0x00000002 /* OverCurrent Indicator */ 117#define OHCI_DRWE 0x00008000 /* Device Remote Wakeup Enable */ 118#define OHCI_LPSC 0x00010000 /* Local Power Status Change */ 119#define OHCI_CCIC 0x00020000 /* OverCurrent Indicator 120 * Change */ 121#define OHCI_CRWE 0x80000000 /* Clear Remote Wakeup Enable */ 122#define OHCI_RH_PORT_STATUS(n) (0x50 + ((n)*4)) /* 1 based indexing */ 123 124#define OHCI_LES (OHCI_PLE | OHCI_IE | OHCI_CLE | OHCI_BLE) 125#define OHCI_ALL_INTRS (OHCI_SO | OHCI_WDH | OHCI_SF | \ 126 OHCI_RD | OHCI_UE | OHCI_FNO | \ 127 OHCI_RHSC | OHCI_OC) 128#define OHCI_NORMAL_INTRS (OHCI_WDH | OHCI_RD | OHCI_UE | OHCI_RHSC) 129 130#define OHCI_FSMPS(i) (((i-210)*6/7) << 16) 131#define OHCI_PERIODIC(i) ((i)*9/10) 132 | |
| 133#define OHCI_NO_INTRS 32 134#define OHCI_HCCA_SIZE 256 135 136/* Structures alignment (bytes) */ 137#define OHCI_HCCA_ALIGN 256 138#define OHCI_ED_ALIGN 16 139#define OHCI_TD_ALIGN 16 140#define OHCI_ITD_ALIGN 32 --- 223 unchanged lines hidden --- | 44#define OHCI_NO_INTRS 32 45#define OHCI_HCCA_SIZE 256 46 47/* Structures alignment (bytes) */ 48#define OHCI_HCCA_ALIGN 256 49#define OHCI_ED_ALIGN 16 50#define OHCI_TD_ALIGN 16 51#define OHCI_ITD_ALIGN 32 --- 223 unchanged lines hidden --- |