| ehci.h (196219) | ehci.h (198151) |
|---|---|
| 1/* $FreeBSD: head/sys/dev/usb/controller/ehci.h 196219 2009-08-14 20:03:53Z jhb $ */ | 1/* $FreeBSD: head/sys/dev/usb/controller/ehci.h 198151 2009-10-15 20:07:08Z thompsa $ */ |
| 2/*- 3 * Copyright (c) 2001 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Lennart Augustsson (lennart@augustsson.net). 8 * 9 * Redistribution and use in source and binary forms, with or without --- 25 unchanged lines hidden (view full) --- 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38#ifndef _EHCI_H_ 39#define _EHCI_H_ 40 41#define EHCI_MAX_DEVICES MIN(USB_MAX_DEVICES, 128) 42 | 2/*- 3 * Copyright (c) 2001 The NetBSD Foundation, Inc. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by Lennart Augustsson (lennart@augustsson.net). 8 * 9 * Redistribution and use in source and binary forms, with or without --- 25 unchanged lines hidden (view full) --- 35 * POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38#ifndef _EHCI_H_ 39#define _EHCI_H_ 40 41#define EHCI_MAX_DEVICES MIN(USB_MAX_DEVICES, 128) 42 |
| 43/* PCI config registers */ 44#define PCI_CBMEM 0x10 /* configuration base MEM */ 45#define PCI_INTERFACE_EHCI 0x20 46#define PCI_USBREV 0x60 /* RO USB protocol revision */ 47#define PCI_USB_REV_MASK 0xff 48#define PCI_USB_REV_PRE_1_0 0x00 49#define PCI_USB_REV_1_0 0x10 50#define PCI_USB_REV_1_1 0x11 51#define PCI_USB_REV_2_0 0x20 52#define PCI_EHCI_FLADJ 0x61 /* RW Frame len adj, SOF=59488+6*fladj */ 53#define PCI_EHCI_PORTWAKECAP 0x62 /* RW Port wake caps (opt) */ 54 55/* EHCI Extended Capabilities */ 56#define EHCI_EC_LEGSUP 0x01 57#define EHCI_EECP_NEXT(x) (((x) >> 8) & 0xff) 58#define EHCI_EECP_ID(x) ((x) & 0xff) 59 60/* Legacy support extended capability */ 61#define EHCI_LEGSUP_BIOS_SEM 0x02 62#define EHCI_LEGSUP_OS_SEM 0x03 63#define EHCI_LEGSUP_USBLEGCTLSTS 0x04 64 65/* EHCI capability registers */ 66#define EHCI_CAPLENGTH 0x00 /* RO Capability register length field */ 67/* reserved 0x01 */ 68#define EHCI_HCIVERSION 0x02 /* RO Interface version number */ 69#define EHCI_HCSPARAMS 0x04 /* RO Structural parameters */ 70#define EHCI_HCS_DEBUGPORT(x) (((x) >> 20) & 0xf) 71#define EHCI_HCS_P_INDICATOR(x) ((x) & 0x10000) 72#define EHCI_HCS_N_CC(x) (((x) >> 12) & 0xf) /* # of companion ctlrs */ 73#define EHCI_HCS_N_PCC(x) (((x) >> 8) & 0xf) /* # of ports per comp. */ 74#define EHCI_HCS_PPC(x) ((x) & 0x10) /* port power control */ 75#define EHCI_HCS_N_PORTS(x) ((x) & 0xf) /* # of ports */ 76#define EHCI_HCCPARAMS 0x08 /* RO Capability parameters */ 77#define EHCI_HCC_EECP(x) (((x) >> 8) & 0xff) /* extended ports caps */ 78#define EHCI_HCC_IST(x) (((x) >> 4) & 0xf) /* isoc sched threshold */ 79#define EHCI_HCC_ASPC(x) ((x) & 0x4) /* async sched park cap */ 80#define EHCI_HCC_PFLF(x) ((x) & 0x2) /* prog frame list flag */ 81#define EHCI_HCC_64BIT(x) ((x) & 0x1) /* 64 bit address cap */ 82#define EHCI_HCSP_PORTROUTE 0x0c /* RO Companion port route description */ 83 84/* EHCI operational registers. Offset given by EHCI_CAPLENGTH register */ 85#define EHCI_USBCMD 0x00 /* RO, RW, WO Command register */ 86#define EHCI_CMD_ITC_M 0x00ff0000 /* RW interrupt threshold ctrl */ 87#define EHCI_CMD_ITC_1 0x00010000 88#define EHCI_CMD_ITC_2 0x00020000 89#define EHCI_CMD_ITC_4 0x00040000 90#define EHCI_CMD_ITC_8 0x00080000 91#define EHCI_CMD_ITC_16 0x00100000 92#define EHCI_CMD_ITC_32 0x00200000 93#define EHCI_CMD_ITC_64 0x00400000 94#define EHCI_CMD_ASPME 0x00000800 /* RW/RO async park enable */ 95#define EHCI_CMD_ASPMC 0x00000300 /* RW/RO async park count */ 96#define EHCI_CMD_LHCR 0x00000080 /* RW light host ctrl reset */ 97#define EHCI_CMD_IAAD 0x00000040 /* RW intr on async adv door 98 * bell */ 99#define EHCI_CMD_ASE 0x00000020 /* RW async sched enable */ 100#define EHCI_CMD_PSE 0x00000010 /* RW periodic sched enable */ 101#define EHCI_CMD_FLS_M 0x0000000c /* RW/RO frame list size */ 102#define EHCI_CMD_FLS(x) (((x) >> 2) & 3) /* RW/RO frame list size */ 103#define EHCI_CMD_HCRESET 0x00000002 /* RW reset */ 104#define EHCI_CMD_RS 0x00000001 /* RW run/stop */ 105#define EHCI_USBSTS 0x04 /* RO, RW, RWC Status register */ 106#define EHCI_STS_ASS 0x00008000 /* RO async sched status */ 107#define EHCI_STS_PSS 0x00004000 /* RO periodic sched status */ 108#define EHCI_STS_REC 0x00002000 /* RO reclamation */ 109#define EHCI_STS_HCH 0x00001000 /* RO host controller halted */ 110#define EHCI_STS_IAA 0x00000020 /* RWC interrupt on async adv */ 111#define EHCI_STS_HSE 0x00000010 /* RWC host system error */ 112#define EHCI_STS_FLR 0x00000008 /* RWC frame list rollover */ 113#define EHCI_STS_PCD 0x00000004 /* RWC port change detect */ 114#define EHCI_STS_ERRINT 0x00000002 /* RWC error interrupt */ 115#define EHCI_STS_INT 0x00000001 /* RWC interrupt */ 116#define EHCI_STS_INTRS(x) ((x) & 0x3f) 117 | |
| 118/* | 43/* |
| 119 * NOTE: the doorbell interrupt is enabled, but the doorbell is never 120 * used! SiS chipsets require this. 121 */ 122#define EHCI_NORMAL_INTRS (EHCI_STS_IAA | EHCI_STS_HSE | \ 123 EHCI_STS_PCD | EHCI_STS_ERRINT | EHCI_STS_INT) 124 125#define EHCI_USBINTR 0x08 /* RW Interrupt register */ 126#define EHCI_INTR_IAAE 0x00000020 /* interrupt on async advance 127 * ena */ 128#define EHCI_INTR_HSEE 0x00000010 /* host system error ena */ 129#define EHCI_INTR_FLRE 0x00000008 /* frame list rollover ena */ 130#define EHCI_INTR_PCIE 0x00000004 /* port change ena */ 131#define EHCI_INTR_UEIE 0x00000002 /* USB error intr ena */ 132#define EHCI_INTR_UIE 0x00000001 /* USB intr ena */ 133 134#define EHCI_FRINDEX 0x0c /* RW Frame Index register */ 135 136#define EHCI_CTRLDSSEGMENT 0x10 /* RW Control Data Structure Segment */ 137 138#define EHCI_PERIODICLISTBASE 0x14 /* RW Periodic List Base */ 139#define EHCI_ASYNCLISTADDR 0x18 /* RW Async List Base */ 140 141#define EHCI_CONFIGFLAG 0x40 /* RW Configure Flag register */ 142#define EHCI_CONF_CF 0x00000001 /* RW configure flag */ 143 144#define EHCI_PORTSC(n) (0x40+(4*(n))) /* RO, RW, RWC Port Status reg */ 145#define EHCI_PS_WKOC_E 0x00400000 /* RW wake on over current ena */ 146#define EHCI_PS_WKDSCNNT_E 0x00200000 /* RW wake on disconnect ena */ 147#define EHCI_PS_WKCNNT_E 0x00100000 /* RW wake on connect ena */ 148#define EHCI_PS_PTC 0x000f0000 /* RW port test control */ 149#define EHCI_PS_PIC 0x0000c000 /* RW port indicator control */ 150#define EHCI_PS_PO 0x00002000 /* RW port owner */ 151#define EHCI_PS_PP 0x00001000 /* RW,RO port power */ 152#define EHCI_PS_LS 0x00000c00 /* RO line status */ 153#define EHCI_PS_IS_LOWSPEED(x) (((x) & EHCI_PS_LS) == 0x00000400) 154#define EHCI_PS_PR 0x00000100 /* RW port reset */ 155#define EHCI_PS_SUSP 0x00000080 /* RW suspend */ 156#define EHCI_PS_FPR 0x00000040 /* RW force port resume */ 157#define EHCI_PS_OCC 0x00000020 /* RWC over current change */ 158#define EHCI_PS_OCA 0x00000010 /* RO over current active */ 159#define EHCI_PS_PEC 0x00000008 /* RWC port enable change */ 160#define EHCI_PS_PE 0x00000004 /* RW port enable */ 161#define EHCI_PS_CSC 0x00000002 /* RWC connect status change */ 162#define EHCI_PS_CS 0x00000001 /* RO connect status */ 163#define EHCI_PS_CLEAR (EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC) 164 165#define EHCI_USBMODE 0x68 /* RW USB Device mode register */ 166#define EHCI_UM_CM 0x00000003 /* R/WO Controller Mode */ 167#define EHCI_UM_CM_IDLE 0x0 /* Idle */ 168#define EHCI_UM_CM_HOST 0x3 /* Host Controller */ 169#define EHCI_UM_ES 0x00000004 /* R/WO Endian Select */ 170#define EHCI_UM_ES_LE 0x0 /* Little-endian byte alignment */ 171#define EHCI_UM_ES_BE 0x4 /* Big-endian byte alignment */ 172#define EHCI_UM_SDIS 0x00000010 /* R/WO Stream Disable Mode */ 173 174#define EHCI_PORT_RESET_COMPLETE 2 /* ms */ 175 176/* | |
| 177 * Alignment NOTE: structures must be aligned so that the hardware can index 178 * without performing addition. 179 */ 180#define EHCI_FRAMELIST_ALIGN 0x1000 /* bytes */ 181#define EHCI_FRAMELIST_COUNT 1024 /* units */ 182#define EHCI_VIRTUAL_FRAMELIST_COUNT 128 /* units */ 183 184#if ((8*EHCI_VIRTUAL_FRAMELIST_COUNT) < USB_MAX_HS_ISOC_FRAMES_PER_XFER) --- 403 unchanged lines hidden --- | 44 * Alignment NOTE: structures must be aligned so that the hardware can index 45 * without performing addition. 46 */ 47#define EHCI_FRAMELIST_ALIGN 0x1000 /* bytes */ 48#define EHCI_FRAMELIST_COUNT 1024 /* units */ 49#define EHCI_VIRTUAL_FRAMELIST_COUNT 128 /* units */ 50 51#if ((8*EHCI_VIRTUAL_FRAMELIST_COUNT) < USB_MAX_HS_ISOC_FRAMES_PER_XFER) --- 403 unchanged lines hidden --- |