1/*
2 * Copyright (c) 1997, 1998, 1999
3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * $FreeBSD: head/sys/dev/ti/if_ti.c 95673 2002-04-28 20:34:20Z phk $
33 */
34
35/*
36 * Alteon Networks Tigon PCI gigabit ethernet driver for FreeBSD.
37 * Manuals, sample driver and firmware source kits are available
38 * from http://www.alteon.com/support/openkits.
39 *
40 * Written by Bill Paul <wpaul@ctr.columbia.edu>
41 * Electrical Engineering Department
42 * Columbia University, New York City
43 */
44
45/*
46 * The Alteon Networks Tigon chip contains an embedded R4000 CPU,
47 * gigabit MAC, dual DMA channels and a PCI interface unit. NICs
48 * using the Tigon may have anywhere from 512K to 2MB of SRAM. The
49 * Tigon supports hardware IP, TCP and UCP checksumming, multicast
50 * filtering and jumbo (9014 byte) frames. The hardware is largely
51 * controlled by firmware, which must be loaded into the NIC during
52 * initialization.
53 *
54 * The Tigon 2 contains 2 R4000 CPUs and requires a newer firmware
55 * revision, which supports new features such as extended commands,
56 * extended jumbo receive ring desciptors and a mini receive ring.
57 *
58 * Alteon Networks is to be commended for releasing such a vast amount
59 * of development material for the Tigon NIC without requiring an NDA
60 * (although they really should have done it a long time ago). With
61 * any luck, the other vendors will finally wise up and follow Alteon's
62 * stellar example.
63 *
64 * The firmware for the Tigon 1 and 2 NICs is compiled directly into
65 * this driver by #including it as a C header file. This bloats the
66 * driver somewhat, but it's the easiest method considering that the
67 * driver code and firmware code need to be kept in sync. The source
68 * for the firmware is not provided with the FreeBSD distribution since
69 * compiling it requires a GNU toolchain targeted for mips-sgi-irix5.3.
70 *
71 * The following people deserve special thanks:
72 * - Terry Murphy of 3Com, for providing a 3c985 Tigon 1 board
73 * for testing
74 * - Raymond Lee of Netgear, for providing a pair of Netgear
75 * GA620 Tigon 2 boards for testing
76 * - Ulf Zimmermann, for bringing the GA260 to my attention and
77 * convincing me to write this driver.
78 * - Andrew Gallatin for providing FreeBSD/Alpha support.
79 */
80
81#include <sys/param.h>
82#include <sys/systm.h>
83#include <sys/sockio.h>
84#include <sys/mbuf.h>
85#include <sys/malloc.h>
86#include <sys/kernel.h>
87#include <sys/socket.h>
88#include <sys/queue.h>
89
90#include <net/if.h>
91#include <net/if_arp.h>
92#include <net/ethernet.h>
93#include <net/if_dl.h>
94#include <net/if_media.h>
95#include <net/if_types.h>
96#include <net/if_vlan_var.h>
97
98#include <net/bpf.h>
99
100#include <netinet/in_systm.h>
101#include <netinet/in.h>
102#include <netinet/ip.h>
103
104#include <vm/vm.h> /* for vtophys */
105#include <vm/pmap.h> /* for vtophys */
106#include <machine/bus_memio.h>
107#include <machine/bus.h>
108#include <machine/resource.h>
109#include <sys/bus.h>
110#include <sys/rman.h>
111
112#include <pci/pcireg.h>
113#include <pci/pcivar.h>
114
115#include <pci/if_tireg.h>
116#include <pci/ti_fw.h>
117#include <pci/ti_fw2.h>
118
119#define TI_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS)
120
121#if !defined(lint)
122static const char rcsid[] =
123 "$FreeBSD: head/sys/dev/ti/if_ti.c 95673 2002-04-28 20:34:20Z phk $";
124#endif
125
126/*
127 * Various supported device vendors/types and their names.
128 */
129
130static struct ti_type ti_devs[] = {
131 { ALT_VENDORID, ALT_DEVICEID_ACENIC,
132 "Alteon AceNIC 1000baseSX Gigabit Ethernet" },
133 { ALT_VENDORID, ALT_DEVICEID_ACENIC_COPPER,
134 "Alteon AceNIC 1000baseT Gigabit Ethernet" },
135 { TC_VENDORID, TC_DEVICEID_3C985,
136 "3Com 3c985-SX Gigabit Ethernet" },
137 { NG_VENDORID, NG_DEVICEID_GA620,
138 "Netgear GA620 1000baseSX Gigabit Ethernet" },
139 { NG_VENDORID, NG_DEVICEID_GA620T,
140 "Netgear GA620 1000baseT Gigabit Ethernet" },
141 { SGI_VENDORID, SGI_DEVICEID_TIGON,
142 "Silicon Graphics Gigabit Ethernet" },
143 { DEC_VENDORID, DEC_DEVICEID_FARALLON_PN9000SX,
144 "Farallon PN9000SX Gigabit Ethernet" },
145 { 0, 0, NULL }
146};
147
148static int ti_probe (device_t);
149static int ti_attach (device_t);
150static int ti_detach (device_t);
151static void ti_txeof (struct ti_softc *);
152static void ti_rxeof (struct ti_softc *);
153
154static void ti_stats_update (struct ti_softc *);
155static int ti_encap (struct ti_softc *, struct mbuf *, u_int32_t *);
156
157static void ti_intr (void *);
158static void ti_start (struct ifnet *);
159static int ti_ioctl (struct ifnet *, u_long, caddr_t);
160static void ti_init (void *);
161static void ti_init2 (struct ti_softc *);
162static void ti_stop (struct ti_softc *);
163static void ti_watchdog (struct ifnet *);
164static void ti_shutdown (device_t);
165static int ti_ifmedia_upd (struct ifnet *);
166static void ti_ifmedia_sts (struct ifnet *, struct ifmediareq *);
167
168static u_int32_t ti_eeprom_putbyte (struct ti_softc *, int);
169static u_int8_t ti_eeprom_getbyte (struct ti_softc *, int, u_int8_t *);
170static int ti_read_eeprom (struct ti_softc *, caddr_t, int, int);
171
172static void ti_add_mcast (struct ti_softc *, struct ether_addr *);
173static void ti_del_mcast (struct ti_softc *, struct ether_addr *);
174static void ti_setmulti (struct ti_softc *);
175
176static void ti_mem (struct ti_softc *, u_int32_t,
177 u_int32_t, caddr_t);
178static void ti_loadfw (struct ti_softc *);
179static void ti_cmd (struct ti_softc *, struct ti_cmd_desc *);
180static void ti_cmd_ext (struct ti_softc *, struct ti_cmd_desc *,
181 caddr_t, int);
182static void ti_handle_events (struct ti_softc *);
183static int ti_alloc_jumbo_mem (struct ti_softc *);
184static void *ti_jalloc (struct ti_softc *);
185static void ti_jfree (caddr_t, void *);
186static int ti_newbuf_std (struct ti_softc *, int, struct mbuf *);
187static int ti_newbuf_mini (struct ti_softc *, int, struct mbuf *);
188static int ti_newbuf_jumbo (struct ti_softc *, int, struct mbuf *);
189static int ti_init_rx_ring_std (struct ti_softc *);
190static void ti_free_rx_ring_std (struct ti_softc *);
191static int ti_init_rx_ring_jumbo (struct ti_softc *);
192static void ti_free_rx_ring_jumbo (struct ti_softc *);
193static int ti_init_rx_ring_mini (struct ti_softc *);
194static void ti_free_rx_ring_mini (struct ti_softc *);
195static void ti_free_tx_ring (struct ti_softc *);
196static int ti_init_tx_ring (struct ti_softc *);
197
198static int ti_64bitslot_war (struct ti_softc *);
199static int ti_chipinit (struct ti_softc *);
200static int ti_gibinit (struct ti_softc *);
201
202static device_method_t ti_methods[] = {
203 /* Device interface */
204 DEVMETHOD(device_probe, ti_probe),
205 DEVMETHOD(device_attach, ti_attach),
206 DEVMETHOD(device_detach, ti_detach),
207 DEVMETHOD(device_shutdown, ti_shutdown),
208 { 0, 0 }
209};
210
211static driver_t ti_driver = {
212 "ti",
213 ti_methods,
214 sizeof(struct ti_softc)
215};
216
217static devclass_t ti_devclass;
218
219DRIVER_MODULE(if_ti, pci, ti_driver, ti_devclass, 0, 0);
220
221/*
222 * Send an instruction or address to the EEPROM, check for ACK.
223 */
224static u_int32_t ti_eeprom_putbyte(sc, byte)
225 struct ti_softc *sc;
226 int byte;
227{
228 register int i, ack = 0;
229
230 /*
231 * Make sure we're in TX mode.
232 */
233 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
234
235 /*
236 * Feed in each bit and stobe the clock.
237 */
238 for (i = 0x80; i; i >>= 1) {
239 if (byte & i) {
240 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
241 } else {
242 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_DOUT);
243 }
244 DELAY(1);
245 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
246 DELAY(1);
247 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
248 }
249
250 /*
251 * Turn off TX mode.
252 */
253 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
254
255 /*
256 * Check for ack.
257 */
258 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
259 ack = CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN;
260 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
261
262 return(ack);
263}
264
265/*
266 * Read a byte of data stored in the EEPROM at address 'addr.'
267 * We have to send two address bytes since the EEPROM can hold
268 * more than 256 bytes of data.
269 */
270static u_int8_t ti_eeprom_getbyte(sc, addr, dest)
271 struct ti_softc *sc;
272 int addr;
273 u_int8_t *dest;
274{
275 register int i;
276 u_int8_t byte = 0;
277
278 EEPROM_START;
279
280 /*
281 * Send write control code to EEPROM.
282 */
283 if (ti_eeprom_putbyte(sc, EEPROM_CTL_WRITE)) {
284 printf("ti%d: failed to send write command, status: %x\n",
285 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
286 return(1);
287 }
288
289 /*
290 * Send first byte of address of byte we want to read.
291 */
292 if (ti_eeprom_putbyte(sc, (addr >> 8) & 0xFF)) {
293 printf("ti%d: failed to send address, status: %x\n",
294 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
295 return(1);
296 }
297 /*
298 * Send second byte address of byte we want to read.
299 */
300 if (ti_eeprom_putbyte(sc, addr & 0xFF)) {
301 printf("ti%d: failed to send address, status: %x\n",
302 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
303 return(1);
304 }
305
306 EEPROM_STOP;
307 EEPROM_START;
308 /*
309 * Send read control code to EEPROM.
310 */
311 if (ti_eeprom_putbyte(sc, EEPROM_CTL_READ)) {
312 printf("ti%d: failed to send read command, status: %x\n",
313 sc->ti_unit, CSR_READ_4(sc, TI_MISC_LOCAL_CTL));
314 return(1);
315 }
316
317 /*
318 * Start reading bits from EEPROM.
319 */
320 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_TXEN);
321 for (i = 0x80; i; i >>= 1) {
322 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
323 DELAY(1);
324 if (CSR_READ_4(sc, TI_MISC_LOCAL_CTL) & TI_MLC_EE_DIN)
325 byte |= i;
326 TI_CLRBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_EE_CLK);
327 DELAY(1);
328 }
329
330 EEPROM_STOP;
331
332 /*
333 * No ACK generated for read, so just return byte.
334 */
335
336 *dest = byte;
337
338 return(0);
339}
340
341/*
342 * Read a sequence of bytes from the EEPROM.
343 */
344static int ti_read_eeprom(sc, dest, off, cnt)
345 struct ti_softc *sc;
346 caddr_t dest;
347 int off;
348 int cnt;
349{
350 int err = 0, i;
351 u_int8_t byte = 0;
352
353 for (i = 0; i < cnt; i++) {
354 err = ti_eeprom_getbyte(sc, off + i, &byte);
355 if (err)
356 break;
357 *(dest + i) = byte;
358 }
359
360 return(err ? 1 : 0);
361}
362
363/*
364 * NIC memory access function. Can be used to either clear a section
365 * of NIC local memory or (if buf is non-NULL) copy data into it.
366 */
367static void ti_mem(sc, addr, len, buf)
368 struct ti_softc *sc;
369 u_int32_t addr, len;
370 caddr_t buf;
371{
372 int segptr, segsize, cnt;
373 caddr_t ti_winbase, ptr;
374
375 segptr = addr;
376 cnt = len;
377 ti_winbase = (caddr_t)(sc->ti_vhandle + TI_WINDOW);
378 ptr = buf;
379
380 while(cnt) {
381 if (cnt < TI_WINLEN)
382 segsize = cnt;
383 else
384 segsize = TI_WINLEN - (segptr % TI_WINLEN);
385 CSR_WRITE_4(sc, TI_WINBASE, (segptr & ~(TI_WINLEN - 1)));
386 if (buf == NULL)
387 bzero((char *)ti_winbase + (segptr &
388 (TI_WINLEN - 1)), segsize);
389 else {
390 bcopy((char *)ptr, (char *)ti_winbase +
391 (segptr & (TI_WINLEN - 1)), segsize);
392 ptr += segsize;
393 }
394 segptr += segsize;
395 cnt -= segsize;
396 }
397
398 return;
399}
400
401/*
402 * Load firmware image into the NIC. Check that the firmware revision
403 * is acceptable and see if we want the firmware for the Tigon 1 or
404 * Tigon 2.
405 */
406static void ti_loadfw(sc)
407 struct ti_softc *sc;
408{
409 switch(sc->ti_hwrev) {
410 case TI_HWREV_TIGON:
411 if (tigonFwReleaseMajor != TI_FIRMWARE_MAJOR ||
412 tigonFwReleaseMinor != TI_FIRMWARE_MINOR ||
413 tigonFwReleaseFix != TI_FIRMWARE_FIX) {
414 printf("ti%d: firmware revision mismatch; want "
415 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit,
416 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
417 TI_FIRMWARE_FIX, tigonFwReleaseMajor,
418 tigonFwReleaseMinor, tigonFwReleaseFix);
419 return;
420 }
421 ti_mem(sc, tigonFwTextAddr, tigonFwTextLen,
422 (caddr_t)tigonFwText);
423 ti_mem(sc, tigonFwDataAddr, tigonFwDataLen,
424 (caddr_t)tigonFwData);
425 ti_mem(sc, tigonFwRodataAddr, tigonFwRodataLen,
426 (caddr_t)tigonFwRodata);
427 ti_mem(sc, tigonFwBssAddr, tigonFwBssLen, NULL);
428 ti_mem(sc, tigonFwSbssAddr, tigonFwSbssLen, NULL);
429 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigonFwStartAddr);
430 break;
431 case TI_HWREV_TIGON_II:
432 if (tigon2FwReleaseMajor != TI_FIRMWARE_MAJOR ||
433 tigon2FwReleaseMinor != TI_FIRMWARE_MINOR ||
434 tigon2FwReleaseFix != TI_FIRMWARE_FIX) {
435 printf("ti%d: firmware revision mismatch; want "
436 "%d.%d.%d, got %d.%d.%d\n", sc->ti_unit,
437 TI_FIRMWARE_MAJOR, TI_FIRMWARE_MINOR,
438 TI_FIRMWARE_FIX, tigon2FwReleaseMajor,
439 tigon2FwReleaseMinor, tigon2FwReleaseFix);
440 return;
441 }
442 ti_mem(sc, tigon2FwTextAddr, tigon2FwTextLen,
443 (caddr_t)tigon2FwText);
444 ti_mem(sc, tigon2FwDataAddr, tigon2FwDataLen,
445 (caddr_t)tigon2FwData);
446 ti_mem(sc, tigon2FwRodataAddr, tigon2FwRodataLen,
447 (caddr_t)tigon2FwRodata);
448 ti_mem(sc, tigon2FwBssAddr, tigon2FwBssLen, NULL);
449 ti_mem(sc, tigon2FwSbssAddr, tigon2FwSbssLen, NULL);
450 CSR_WRITE_4(sc, TI_CPU_PROGRAM_COUNTER, tigon2FwStartAddr);
451 break;
452 default:
453 printf("ti%d: can't load firmware: unknown hardware rev\n",
454 sc->ti_unit);
455 break;
456 }
457
458 return;
459}
460
461/*
462 * Send the NIC a command via the command ring.
463 */
464static void ti_cmd(sc, cmd)
465 struct ti_softc *sc;
466 struct ti_cmd_desc *cmd;
467{
468 u_int32_t index;
469
470 if (sc->ti_rdata->ti_cmd_ring == NULL)
471 return;
472
473 index = sc->ti_cmd_saved_prodidx;
474 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
475 TI_INC(index, TI_CMD_RING_CNT);
476 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
477 sc->ti_cmd_saved_prodidx = index;
478
479 return;
480}
481
482/*
483 * Send the NIC an extended command. The 'len' parameter specifies the
484 * number of command slots to include after the initial command.
485 */
486static void ti_cmd_ext(sc, cmd, arg, len)
487 struct ti_softc *sc;
488 struct ti_cmd_desc *cmd;
489 caddr_t arg;
490 int len;
491{
492 u_int32_t index;
493 register int i;
494
495 if (sc->ti_rdata->ti_cmd_ring == NULL)
496 return;
497
498 index = sc->ti_cmd_saved_prodidx;
499 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4), *(u_int32_t *)(cmd));
500 TI_INC(index, TI_CMD_RING_CNT);
501 for (i = 0; i < len; i++) {
502 CSR_WRITE_4(sc, TI_GCR_CMDRING + (index * 4),
503 *(u_int32_t *)(&arg[i * 4]));
504 TI_INC(index, TI_CMD_RING_CNT);
505 }
506 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, index);
507 sc->ti_cmd_saved_prodidx = index;
508
509 return;
510}
511
512/*
513 * Handle events that have triggered interrupts.
514 */
515static void ti_handle_events(sc)
516 struct ti_softc *sc;
517{
518 struct ti_event_desc *e;
519
520 if (sc->ti_rdata->ti_event_ring == NULL)
521 return;
522
523 while (sc->ti_ev_saved_considx != sc->ti_ev_prodidx.ti_idx) {
524 e = &sc->ti_rdata->ti_event_ring[sc->ti_ev_saved_considx];
525 switch(e->ti_event) {
526 case TI_EV_LINKSTAT_CHANGED:
527 sc->ti_linkstat = e->ti_code;
528 if (e->ti_code == TI_EV_CODE_LINK_UP)
529 printf("ti%d: 10/100 link up\n", sc->ti_unit);
530 else if (e->ti_code == TI_EV_CODE_GIG_LINK_UP)
531 printf("ti%d: gigabit link up\n", sc->ti_unit);
532 else if (e->ti_code == TI_EV_CODE_LINK_DOWN)
533 printf("ti%d: link down\n", sc->ti_unit);
534 break;
535 case TI_EV_ERROR:
536 if (e->ti_code == TI_EV_CODE_ERR_INVAL_CMD)
537 printf("ti%d: invalid command\n", sc->ti_unit);
538 else if (e->ti_code == TI_EV_CODE_ERR_UNIMP_CMD)
539 printf("ti%d: unknown command\n", sc->ti_unit);
540 else if (e->ti_code == TI_EV_CODE_ERR_BADCFG)
541 printf("ti%d: bad config data\n", sc->ti_unit);
542 break;
543 case TI_EV_FIRMWARE_UP:
544 ti_init2(sc);
545 break;
546 case TI_EV_STATS_UPDATED:
547 ti_stats_update(sc);
548 break;
549 case TI_EV_RESET_JUMBO_RING:
550 case TI_EV_MCAST_UPDATED:
551 /* Who cares. */
552 break;
553 default:
554 printf("ti%d: unknown event: %d\n",
555 sc->ti_unit, e->ti_event);
556 break;
557 }
558 /* Advance the consumer index. */
559 TI_INC(sc->ti_ev_saved_considx, TI_EVENT_RING_CNT);
560 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, sc->ti_ev_saved_considx);
561 }
562
563 return;
564}
565
566/*
567 * Memory management for the jumbo receive ring is a pain in the
568 * butt. We need to allocate at least 9018 bytes of space per frame,
569 * _and_ it has to be contiguous (unless you use the extended
570 * jumbo descriptor format). Using malloc() all the time won't
571 * work: malloc() allocates memory in powers of two, which means we
572 * would end up wasting a considerable amount of space by allocating
573 * 9K chunks. We don't have a jumbo mbuf cluster pool. Thus, we have
574 * to do our own memory management.
575 *
576 * The driver needs to allocate a contiguous chunk of memory at boot
577 * time. We then chop this up ourselves into 9K pieces and use them
578 * as external mbuf storage.
579 *
580 * One issue here is how much memory to allocate. The jumbo ring has
581 * 256 slots in it, but at 9K per slot than can consume over 2MB of
582 * RAM. This is a bit much, especially considering we also need
583 * RAM for the standard ring and mini ring (on the Tigon 2). To
584 * save space, we only actually allocate enough memory for 64 slots
585 * by default, which works out to between 500 and 600K. This can
586 * be tuned by changing a #define in if_tireg.h.
587 */
588
589static int ti_alloc_jumbo_mem(sc)
590 struct ti_softc *sc;
591{
592 caddr_t ptr;
593 register int i;
594 struct ti_jpool_entry *entry;
595
596 /* Grab a big chunk o' storage. */
597 sc->ti_cdata.ti_jumbo_buf = contigmalloc(TI_JMEM, M_DEVBUF,
598 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
599
600 if (sc->ti_cdata.ti_jumbo_buf == NULL) {
601 printf("ti%d: no memory for jumbo buffers!\n", sc->ti_unit);
602 return(ENOBUFS);
603 }
604
605 SLIST_INIT(&sc->ti_jfree_listhead);
606 SLIST_INIT(&sc->ti_jinuse_listhead);
607
608 /*
609 * Now divide it up into 9K pieces and save the addresses
610 * in an array.
611 */
612 ptr = sc->ti_cdata.ti_jumbo_buf;
613 for (i = 0; i < TI_JSLOTS; i++) {
614 sc->ti_cdata.ti_jslots[i] = ptr;
615 ptr += TI_JLEN;
616 entry = malloc(sizeof(struct ti_jpool_entry),
617 M_DEVBUF, M_NOWAIT);
618 if (entry == NULL) {
619 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM,
620 M_DEVBUF);
621 sc->ti_cdata.ti_jumbo_buf = NULL;
622 printf("ti%d: no memory for jumbo "
623 "buffer queue!\n", sc->ti_unit);
624 return(ENOBUFS);
625 }
626 entry->slot = i;
627 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
628 }
629
630 return(0);
631}
632
633/*
634 * Allocate a jumbo buffer.
635 */
636static void *ti_jalloc(sc)
637 struct ti_softc *sc;
638{
639 struct ti_jpool_entry *entry;
640
641 entry = SLIST_FIRST(&sc->ti_jfree_listhead);
642
643 if (entry == NULL) {
644 printf("ti%d: no free jumbo buffers\n", sc->ti_unit);
645 return(NULL);
646 }
647
648 SLIST_REMOVE_HEAD(&sc->ti_jfree_listhead, jpool_entries);
649 SLIST_INSERT_HEAD(&sc->ti_jinuse_listhead, entry, jpool_entries);
650 return(sc->ti_cdata.ti_jslots[entry->slot]);
651}
652
653/*
654 * Release a jumbo buffer.
655 */
656static void ti_jfree(buf, args)
657 caddr_t buf;
658 void *args;
659{
660 struct ti_softc *sc;
661 int i;
662 struct ti_jpool_entry *entry;
663
664 /* Extract the softc struct pointer. */
665 sc = (struct ti_softc *)args;
666
667 if (sc == NULL)
668 panic("ti_jfree: didn't get softc pointer!");
669
670 /* calculate the slot this buffer belongs to */
671 i = ((vm_offset_t)buf
672 - (vm_offset_t)sc->ti_cdata.ti_jumbo_buf) / TI_JLEN;
673
674 if ((i < 0) || (i >= TI_JSLOTS))
675 panic("ti_jfree: asked to free buffer that we don't manage!");
676
677 entry = SLIST_FIRST(&sc->ti_jinuse_listhead);
678 if (entry == NULL)
679 panic("ti_jfree: buffer not in use!");
680 entry->slot = i;
681 SLIST_REMOVE_HEAD(&sc->ti_jinuse_listhead, jpool_entries);
682 SLIST_INSERT_HEAD(&sc->ti_jfree_listhead, entry, jpool_entries);
683
684 return;
685}
686
687
688/*
689 * Intialize a standard receive ring descriptor.
690 */
691static int ti_newbuf_std(sc, i, m)
692 struct ti_softc *sc;
693 int i;
694 struct mbuf *m;
695{
696 struct mbuf *m_new = NULL;
697 struct ti_rx_desc *r;
698
699 if (m == NULL) {
700 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
701 if (m_new == NULL)
702 return(ENOBUFS);
703
704 MCLGET(m_new, M_DONTWAIT);
705 if (!(m_new->m_flags & M_EXT)) {
706 m_freem(m_new);
707 return(ENOBUFS);
708 }
709 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
710 } else {
711 m_new = m;
712 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
713 m_new->m_data = m_new->m_ext.ext_buf;
714 }
715
716 m_adj(m_new, ETHER_ALIGN);
717 sc->ti_cdata.ti_rx_std_chain[i] = m_new;
718 r = &sc->ti_rdata->ti_rx_std_ring[i];
719 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
720 r->ti_type = TI_BDTYPE_RECV_BD;
721 r->ti_flags = 0;
722 if (sc->arpcom.ac_if.if_hwassist)
723 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
724 r->ti_len = m_new->m_len;
725 r->ti_idx = i;
726
727 return(0);
728}
729
730/*
731 * Intialize a mini receive ring descriptor. This only applies to
732 * the Tigon 2.
733 */
734static int ti_newbuf_mini(sc, i, m)
735 struct ti_softc *sc;
736 int i;
737 struct mbuf *m;
738{
739 struct mbuf *m_new = NULL;
740 struct ti_rx_desc *r;
741
742 if (m == NULL) {
743 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
744 if (m_new == NULL) {
745 return(ENOBUFS);
746 }
747 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
748 } else {
749 m_new = m;
750 m_new->m_data = m_new->m_pktdat;
751 m_new->m_len = m_new->m_pkthdr.len = MHLEN;
752 }
753
754 m_adj(m_new, ETHER_ALIGN);
755 r = &sc->ti_rdata->ti_rx_mini_ring[i];
756 sc->ti_cdata.ti_rx_mini_chain[i] = m_new;
757 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
758 r->ti_type = TI_BDTYPE_RECV_BD;
759 r->ti_flags = TI_BDFLAG_MINI_RING;
760 if (sc->arpcom.ac_if.if_hwassist)
761 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
762 r->ti_len = m_new->m_len;
763 r->ti_idx = i;
764
765 return(0);
766}
767
768/*
769 * Initialize a jumbo receive ring descriptor. This allocates
770 * a jumbo buffer from the pool managed internally by the driver.
771 */
772static int ti_newbuf_jumbo(sc, i, m)
773 struct ti_softc *sc;
774 int i;
775 struct mbuf *m;
776{
777 struct mbuf *m_new = NULL;
778 struct ti_rx_desc *r;
779
780 if (m == NULL) {
781 caddr_t *buf = NULL;
782
783 /* Allocate the mbuf. */
784 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
785 if (m_new == NULL) {
786 return(ENOBUFS);
787 }
788
789 /* Allocate the jumbo buffer */
790 buf = ti_jalloc(sc);
791 if (buf == NULL) {
792 m_freem(m_new);
793 printf("ti%d: jumbo allocation failed "
794 "-- packet dropped!\n", sc->ti_unit);
795 return(ENOBUFS);
796 }
797
798 /* Attach the buffer to the mbuf. */
799 m_new->m_data = (void *) buf;
800 m_new->m_len = m_new->m_pkthdr.len = TI_JUMBO_FRAMELEN;
801 MEXTADD(m_new, buf, TI_JUMBO_FRAMELEN, ti_jfree,
802 (struct ti_softc *)sc, 0, EXT_NET_DRV);
803 } else {
804 m_new = m;
805 m_new->m_data = m_new->m_ext.ext_buf;
806 m_new->m_ext.ext_size = TI_JUMBO_FRAMELEN;
807 }
808
809 m_adj(m_new, ETHER_ALIGN);
810 /* Set up the descriptor. */
811 r = &sc->ti_rdata->ti_rx_jumbo_ring[i];
812 sc->ti_cdata.ti_rx_jumbo_chain[i] = m_new;
813 TI_HOSTADDR(r->ti_addr) = vtophys(mtod(m_new, caddr_t));
814 r->ti_type = TI_BDTYPE_RECV_JUMBO_BD;
815 r->ti_flags = TI_BDFLAG_JUMBO_RING;
816 if (sc->arpcom.ac_if.if_hwassist)
817 r->ti_flags |= TI_BDFLAG_TCP_UDP_CKSUM | TI_BDFLAG_IP_CKSUM;
818 r->ti_len = m_new->m_len;
819 r->ti_idx = i;
820
821 return(0);
822}
823
824/*
825 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
826 * that's 1MB or memory, which is a lot. For now, we fill only the first
827 * 256 ring entries and hope that our CPU is fast enough to keep up with
828 * the NIC.
829 */
830static int ti_init_rx_ring_std(sc)
831 struct ti_softc *sc;
832{
833 register int i;
834 struct ti_cmd_desc cmd;
835
836 for (i = 0; i < TI_SSLOTS; i++) {
837 if (ti_newbuf_std(sc, i, NULL) == ENOBUFS)
838 return(ENOBUFS);
839 };
840
841 TI_UPDATE_STDPROD(sc, i - 1);
842 sc->ti_std = i - 1;
843
844 return(0);
845}
846
847static void ti_free_rx_ring_std(sc)
848 struct ti_softc *sc;
849{
850 register int i;
851
852 for (i = 0; i < TI_STD_RX_RING_CNT; i++) {
853 if (sc->ti_cdata.ti_rx_std_chain[i] != NULL) {
854 m_freem(sc->ti_cdata.ti_rx_std_chain[i]);
855 sc->ti_cdata.ti_rx_std_chain[i] = NULL;
856 }
857 bzero((char *)&sc->ti_rdata->ti_rx_std_ring[i],
858 sizeof(struct ti_rx_desc));
859 }
860
861 return;
862}
863
864static int ti_init_rx_ring_jumbo(sc)
865 struct ti_softc *sc;
866{
867 register int i;
868 struct ti_cmd_desc cmd;
869
870 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
871 if (ti_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
872 return(ENOBUFS);
873 };
874
875 TI_UPDATE_JUMBOPROD(sc, i - 1);
876 sc->ti_jumbo = i - 1;
877
878 return(0);
879}
880
881static void ti_free_rx_ring_jumbo(sc)
882 struct ti_softc *sc;
883{
884 register int i;
885
886 for (i = 0; i < TI_JUMBO_RX_RING_CNT; i++) {
887 if (sc->ti_cdata.ti_rx_jumbo_chain[i] != NULL) {
888 m_freem(sc->ti_cdata.ti_rx_jumbo_chain[i]);
889 sc->ti_cdata.ti_rx_jumbo_chain[i] = NULL;
890 }
891 bzero((char *)&sc->ti_rdata->ti_rx_jumbo_ring[i],
892 sizeof(struct ti_rx_desc));
893 }
894
895 return;
896}
897
898static int ti_init_rx_ring_mini(sc)
899 struct ti_softc *sc;
900{
901 register int i;
902
903 for (i = 0; i < TI_MSLOTS; i++) {
904 if (ti_newbuf_mini(sc, i, NULL) == ENOBUFS)
905 return(ENOBUFS);
906 };
907
908 TI_UPDATE_MINIPROD(sc, i - 1);
909 sc->ti_mini = i - 1;
910
911 return(0);
912}
913
914static void ti_free_rx_ring_mini(sc)
915 struct ti_softc *sc;
916{
917 register int i;
918
919 for (i = 0; i < TI_MINI_RX_RING_CNT; i++) {
920 if (sc->ti_cdata.ti_rx_mini_chain[i] != NULL) {
921 m_freem(sc->ti_cdata.ti_rx_mini_chain[i]);
922 sc->ti_cdata.ti_rx_mini_chain[i] = NULL;
923 }
924 bzero((char *)&sc->ti_rdata->ti_rx_mini_ring[i],
925 sizeof(struct ti_rx_desc));
926 }
927
928 return;
929}
930
931static void ti_free_tx_ring(sc)
932 struct ti_softc *sc;
933{
934 register int i;
935
936 if (sc->ti_rdata->ti_tx_ring == NULL)
937 return;
938
939 for (i = 0; i < TI_TX_RING_CNT; i++) {
940 if (sc->ti_cdata.ti_tx_chain[i] != NULL) {
941 m_freem(sc->ti_cdata.ti_tx_chain[i]);
942 sc->ti_cdata.ti_tx_chain[i] = NULL;
943 }
944 bzero((char *)&sc->ti_rdata->ti_tx_ring[i],
945 sizeof(struct ti_tx_desc));
946 }
947
948 return;
949}
950
951static int ti_init_tx_ring(sc)
952 struct ti_softc *sc;
953{
954 sc->ti_txcnt = 0;
955 sc->ti_tx_saved_considx = 0;
956 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, 0);
957 return(0);
958}
959
960/*
961 * The Tigon 2 firmware has a new way to add/delete multicast addresses,
962 * but we have to support the old way too so that Tigon 1 cards will
963 * work.
964 */
965void ti_add_mcast(sc, addr)
966 struct ti_softc *sc;
967 struct ether_addr *addr;
968{
969 struct ti_cmd_desc cmd;
970 u_int16_t *m;
971 u_int32_t ext[2] = {0, 0};
972
973 m = (u_int16_t *)&addr->octet[0];
974
975 switch(sc->ti_hwrev) {
976 case TI_HWREV_TIGON:
977 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
978 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
979 TI_DO_CMD(TI_CMD_ADD_MCAST_ADDR, 0, 0);
980 break;
981 case TI_HWREV_TIGON_II:
982 ext[0] = htons(m[0]);
983 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
984 TI_DO_CMD_EXT(TI_CMD_EXT_ADD_MCAST, 0, 0, (caddr_t)&ext, 2);
985 break;
986 default:
987 printf("ti%d: unknown hwrev\n", sc->ti_unit);
988 break;
989 }
990
991 return;
992}
993
994void ti_del_mcast(sc, addr)
995 struct ti_softc *sc;
996 struct ether_addr *addr;
997{
998 struct ti_cmd_desc cmd;
999 u_int16_t *m;
1000 u_int32_t ext[2] = {0, 0};
1001
1002 m = (u_int16_t *)&addr->octet[0];
1003
1004 switch(sc->ti_hwrev) {
1005 case TI_HWREV_TIGON:
1006 CSR_WRITE_4(sc, TI_GCR_MAR0, htons(m[0]));
1007 CSR_WRITE_4(sc, TI_GCR_MAR1, (htons(m[1]) << 16) | htons(m[2]));
1008 TI_DO_CMD(TI_CMD_DEL_MCAST_ADDR, 0, 0);
1009 break;
1010 case TI_HWREV_TIGON_II:
1011 ext[0] = htons(m[0]);
1012 ext[1] = (htons(m[1]) << 16) | htons(m[2]);
1013 TI_DO_CMD_EXT(TI_CMD_EXT_DEL_MCAST, 0, 0, (caddr_t)&ext, 2);
1014 break;
1015 default:
1016 printf("ti%d: unknown hwrev\n", sc->ti_unit);
1017 break;
1018 }
1019
1020 return;
1021}
1022
1023/*
1024 * Configure the Tigon's multicast address filter.
1025 *
1026 * The actual multicast table management is a bit of a pain, thanks to
1027 * slight brain damage on the part of both Alteon and us. With our
1028 * multicast code, we are only alerted when the multicast address table
1029 * changes and at that point we only have the current list of addresses:
1030 * we only know the current state, not the previous state, so we don't
1031 * actually know what addresses were removed or added. The firmware has
1032 * state, but we can't get our grubby mits on it, and there is no 'delete
1033 * all multicast addresses' command. Hence, we have to maintain our own
1034 * state so we know what addresses have been programmed into the NIC at
1035 * any given time.
1036 */
1037static void ti_setmulti(sc)
1038 struct ti_softc *sc;
1039{
1040 struct ifnet *ifp;
1041 struct ifmultiaddr *ifma;
1042 struct ti_cmd_desc cmd;
1043 struct ti_mc_entry *mc;
1044 u_int32_t intrs;
1045
1046 ifp = &sc->arpcom.ac_if;
1047
1048 if (ifp->if_flags & IFF_ALLMULTI) {
1049 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_ENB, 0);
1050 return;
1051 } else {
1052 TI_DO_CMD(TI_CMD_SET_ALLMULTI, TI_CMD_CODE_ALLMULTI_DIS, 0);
1053 }
1054
1055 /* Disable interrupts. */
1056 intrs = CSR_READ_4(sc, TI_MB_HOSTINTR);
1057 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1058
1059 /* First, zot all the existing filters. */
1060 while (SLIST_FIRST(&sc->ti_mc_listhead) != NULL) {
1061 mc = SLIST_FIRST(&sc->ti_mc_listhead);
1062 ti_del_mcast(sc, &mc->mc_addr);
1063 SLIST_REMOVE_HEAD(&sc->ti_mc_listhead, mc_entries);
1064 free(mc, M_DEVBUF);
1065 }
1066
1067 /* Now program new ones. */
1068 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1069 if (ifma->ifma_addr->sa_family != AF_LINK)
1070 continue;
1071 mc = malloc(sizeof(struct ti_mc_entry), M_DEVBUF, M_NOWAIT);
1072 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1073 (char *)&mc->mc_addr, ETHER_ADDR_LEN);
1074 SLIST_INSERT_HEAD(&sc->ti_mc_listhead, mc, mc_entries);
1075 ti_add_mcast(sc, &mc->mc_addr);
1076 }
1077
1078 /* Re-enable interrupts. */
1079 CSR_WRITE_4(sc, TI_MB_HOSTINTR, intrs);
1080
1081 return;
1082}
1083
1084/*
1085 * Check to see if the BIOS has configured us for a 64 bit slot when
1086 * we aren't actually in one. If we detect this condition, we can work
1087 * around it on the Tigon 2 by setting a bit in the PCI state register,
1088 * but for the Tigon 1 we must give up and abort the interface attach.
1089 */
1090static int ti_64bitslot_war(sc)
1091 struct ti_softc *sc;
1092{
1093 if (!(CSR_READ_4(sc, TI_PCI_STATE) & TI_PCISTATE_32BIT_BUS)) {
1094 CSR_WRITE_4(sc, 0x600, 0);
1095 CSR_WRITE_4(sc, 0x604, 0);
1096 CSR_WRITE_4(sc, 0x600, 0x5555AAAA);
1097 if (CSR_READ_4(sc, 0x604) == 0x5555AAAA) {
1098 if (sc->ti_hwrev == TI_HWREV_TIGON)
1099 return(EINVAL);
1100 else {
1101 TI_SETBIT(sc, TI_PCI_STATE,
1102 TI_PCISTATE_32BIT_BUS);
1103 return(0);
1104 }
1105 }
1106 }
1107
1108 return(0);
1109}
1110
1111/*
1112 * Do endian, PCI and DMA initialization. Also check the on-board ROM
1113 * self-test results.
1114 */
1115static int ti_chipinit(sc)
1116 struct ti_softc *sc;
1117{
1118 u_int32_t cacheline;
1119 u_int32_t pci_writemax = 0;
1120
1121 /* Initialize link to down state. */
1122 sc->ti_linkstat = TI_EV_CODE_LINK_DOWN;
1123
1124 if (sc->arpcom.ac_if.if_capenable & IFCAP_HWCSUM)
1125 sc->arpcom.ac_if.if_hwassist = TI_CSUM_FEATURES;
1126 else
1127 sc->arpcom.ac_if.if_hwassist = 0;
1128
1129 /* Set endianness before we access any non-PCI registers. */
1130#if BYTE_ORDER == BIG_ENDIAN
1131 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1132 TI_MHC_BIGENDIAN_INIT | (TI_MHC_BIGENDIAN_INIT << 24));
1133#else
1134 CSR_WRITE_4(sc, TI_MISC_HOST_CTL,
1135 TI_MHC_LITTLEENDIAN_INIT | (TI_MHC_LITTLEENDIAN_INIT << 24));
1136#endif
1137
1138 /* Check the ROM failed bit to see if self-tests passed. */
1139 if (CSR_READ_4(sc, TI_CPU_STATE) & TI_CPUSTATE_ROMFAIL) {
1140 printf("ti%d: board self-diagnostics failed!\n", sc->ti_unit);
1141 return(ENODEV);
1142 }
1143
1144 /* Halt the CPU. */
1145 TI_SETBIT(sc, TI_CPU_STATE, TI_CPUSTATE_HALT);
1146
1147 /* Figure out the hardware revision. */
1148 switch(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_CHIP_REV_MASK) {
1149 case TI_REV_TIGON_I:
1150 sc->ti_hwrev = TI_HWREV_TIGON;
1151 break;
1152 case TI_REV_TIGON_II:
1153 sc->ti_hwrev = TI_HWREV_TIGON_II;
1154 break;
1155 default:
1156 printf("ti%d: unsupported chip revision\n", sc->ti_unit);
1157 return(ENODEV);
1158 }
1159
1160 /* Do special setup for Tigon 2. */
1161 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1162 TI_SETBIT(sc, TI_CPU_CTL_B, TI_CPUSTATE_HALT);
1163 TI_SETBIT(sc, TI_MISC_LOCAL_CTL, TI_MLC_SRAM_BANK_512K);
1164 TI_SETBIT(sc, TI_MISC_CONF, TI_MCR_SRAM_SYNCHRONOUS);
1165 }
1166
1167 /* Set up the PCI state register. */
1168 CSR_WRITE_4(sc, TI_PCI_STATE, TI_PCI_READ_CMD|TI_PCI_WRITE_CMD);
1169 if (sc->ti_hwrev == TI_HWREV_TIGON_II) {
1170 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_USE_MEM_RD_MULT);
1171 }
1172
1173 /* Clear the read/write max DMA parameters. */
1174 TI_CLRBIT(sc, TI_PCI_STATE, (TI_PCISTATE_WRITE_MAXDMA|
1175 TI_PCISTATE_READ_MAXDMA));
1176
1177 /* Get cache line size. */
1178 cacheline = CSR_READ_4(sc, TI_PCI_BIST) & 0xFF;
1179
1180 /*
1181 * If the system has set enabled the PCI memory write
1182 * and invalidate command in the command register, set
1183 * the write max parameter accordingly. This is necessary
1184 * to use MWI with the Tigon 2.
1185 */
1186 if (CSR_READ_4(sc, TI_PCI_CMDSTAT) & PCIM_CMD_MWIEN) {
1187 switch(cacheline) {
1188 case 1:
1189 case 4:
1190 case 8:
1191 case 16:
1192 case 32:
1193 case 64:
1194 break;
1195 default:
1196 /* Disable PCI memory write and invalidate. */
1197 if (bootverbose)
1198 printf("ti%d: cache line size %d not "
1199 "supported; disabling PCI MWI\n",
1200 sc->ti_unit, cacheline);
1201 CSR_WRITE_4(sc, TI_PCI_CMDSTAT, CSR_READ_4(sc,
1202 TI_PCI_CMDSTAT) & ~PCIM_CMD_MWIEN);
1203 break;
1204 }
1205 }
1206
1207#ifdef __brokenalpha__
1208 /*
1209 * From the Alteon sample driver:
1210 * Must insure that we do not cross an 8K (bytes) boundary
1211 * for DMA reads. Our highest limit is 1K bytes. This is a
1212 * restriction on some ALPHA platforms with early revision
1213 * 21174 PCI chipsets, such as the AlphaPC 164lx
1214 */
1215 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax|TI_PCI_READMAX_1024);
1216#else
1217 TI_SETBIT(sc, TI_PCI_STATE, pci_writemax);
1218#endif
1219
1220 /* This sets the min dma param all the way up (0xff). */
1221 TI_SETBIT(sc, TI_PCI_STATE, TI_PCISTATE_MINDMA);
1222
1223 /* Configure DMA variables. */
1224#if BYTE_ORDER == BIG_ENDIAN
1225 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_BD |
1226 TI_OPMODE_BYTESWAP_DATA | TI_OPMODE_WORDSWAP_BD |
1227 TI_OPMODE_WARN_ENB | TI_OPMODE_FATAL_ENB |
1228 TI_OPMODE_DONT_FRAG_JUMBO);
1229#else
1230 CSR_WRITE_4(sc, TI_GCR_OPMODE, TI_OPMODE_BYTESWAP_DATA|
1231 TI_OPMODE_WORDSWAP_BD|TI_OPMODE_DONT_FRAG_JUMBO|
1232 TI_OPMODE_WARN_ENB|TI_OPMODE_FATAL_ENB);
1233#endif
1234
1235 /*
1236 * Only allow 1 DMA channel to be active at a time.
1237 * I don't think this is a good idea, but without it
1238 * the firmware racks up lots of nicDmaReadRingFull
1239 * errors. This is not compatible with hardware checksums.
1240 */
1241 if (sc->arpcom.ac_if.if_hwassist == 0)
1242 TI_SETBIT(sc, TI_GCR_OPMODE, TI_OPMODE_1_DMA_ACTIVE);
1243
1244 /* Recommended settings from Tigon manual. */
1245 CSR_WRITE_4(sc, TI_GCR_DMA_WRITECFG, TI_DMA_STATE_THRESH_8W);
1246 CSR_WRITE_4(sc, TI_GCR_DMA_READCFG, TI_DMA_STATE_THRESH_8W);
1247
1248 if (ti_64bitslot_war(sc)) {
1249 printf("ti%d: bios thinks we're in a 64 bit slot, "
1250 "but we aren't", sc->ti_unit);
1251 return(EINVAL);
1252 }
1253
1254 return(0);
1255}
1256
1257/*
1258 * Initialize the general information block and firmware, and
1259 * start the CPU(s) running.
1260 */
1261static int ti_gibinit(sc)
1262 struct ti_softc *sc;
1263{
1264 struct ti_rcb *rcb;
1265 int i;
1266 struct ifnet *ifp;
1267
1268 ifp = &sc->arpcom.ac_if;
1269
1270 /* Disable interrupts for now. */
1271 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1272
1273 /* Tell the chip where to find the general information block. */
1274 CSR_WRITE_4(sc, TI_GCR_GENINFO_HI, 0);
1275 CSR_WRITE_4(sc, TI_GCR_GENINFO_LO, vtophys(&sc->ti_rdata->ti_info));
1276
1277 /* Load the firmware into SRAM. */
1278 ti_loadfw(sc);
1279
1280 /* Set up the contents of the general info and ring control blocks. */
1281
1282 /* Set up the event ring and producer pointer. */
1283 rcb = &sc->ti_rdata->ti_info.ti_ev_rcb;
1284
1285 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_event_ring);
1286 rcb->ti_flags = 0;
1287 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_ev_prodidx_ptr) =
1288 vtophys(&sc->ti_ev_prodidx);
1289 sc->ti_ev_prodidx.ti_idx = 0;
1290 CSR_WRITE_4(sc, TI_GCR_EVENTCONS_IDX, 0);
1291 sc->ti_ev_saved_considx = 0;
1292
1293 /* Set up the command ring and producer mailbox. */
1294 rcb = &sc->ti_rdata->ti_info.ti_cmd_rcb;
1295
1296 sc->ti_rdata->ti_cmd_ring =
1297 (struct ti_cmd_desc *)(sc->ti_vhandle + TI_GCR_CMDRING);
1298 TI_HOSTADDR(rcb->ti_hostaddr) = TI_GCR_NIC_ADDR(TI_GCR_CMDRING);
1299 rcb->ti_flags = 0;
1300 rcb->ti_max_len = 0;
1301 for (i = 0; i < TI_CMD_RING_CNT; i++) {
1302 CSR_WRITE_4(sc, TI_GCR_CMDRING + (i * 4), 0);
1303 }
1304 CSR_WRITE_4(sc, TI_GCR_CMDCONS_IDX, 0);
1305 CSR_WRITE_4(sc, TI_MB_CMDPROD_IDX, 0);
1306 sc->ti_cmd_saved_prodidx = 0;
1307
1308 /*
1309 * Assign the address of the stats refresh buffer.
1310 * We re-use the current stats buffer for this to
1311 * conserve memory.
1312 */
1313 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_refresh_stats_ptr) =
1314 vtophys(&sc->ti_rdata->ti_info.ti_stats);
1315
1316 /* Set up the standard receive ring. */
1317 rcb = &sc->ti_rdata->ti_info.ti_std_rx_rcb;
1318 TI_HOSTADDR(rcb->ti_hostaddr) = vtophys(&sc->ti_rdata->ti_rx_std_ring);
1319 rcb->ti_max_len = TI_FRAMELEN;
1320 rcb->ti_flags = 0;
1321 if (sc->arpcom.ac_if.if_hwassist)
1322 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1323 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1324 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1325
1326 /* Set up the jumbo receive ring. */
1327 rcb = &sc->ti_rdata->ti_info.ti_jumbo_rx_rcb;
1328 TI_HOSTADDR(rcb->ti_hostaddr) =
1329 vtophys(&sc->ti_rdata->ti_rx_jumbo_ring);
1330 rcb->ti_max_len = TI_JUMBO_FRAMELEN;
1331 rcb->ti_flags = 0;
1332 if (sc->arpcom.ac_if.if_hwassist)
1333 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1334 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1335 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1336
1337 /*
1338 * Set up the mini ring. Only activated on the
1339 * Tigon 2 but the slot in the config block is
1340 * still there on the Tigon 1.
1341 */
1342 rcb = &sc->ti_rdata->ti_info.ti_mini_rx_rcb;
1343 TI_HOSTADDR(rcb->ti_hostaddr) =
1344 vtophys(&sc->ti_rdata->ti_rx_mini_ring);
1345 rcb->ti_max_len = MHLEN - ETHER_ALIGN;
1346 if (sc->ti_hwrev == TI_HWREV_TIGON)
1347 rcb->ti_flags = TI_RCB_FLAG_RING_DISABLED;
1348 else
1349 rcb->ti_flags = 0;
1350 if (sc->arpcom.ac_if.if_hwassist)
1351 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1352 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1353 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1354
1355 /*
1356 * Set up the receive return ring.
1357 */
1358 rcb = &sc->ti_rdata->ti_info.ti_return_rcb;
1359 TI_HOSTADDR(rcb->ti_hostaddr) =
1360 vtophys(&sc->ti_rdata->ti_rx_return_ring);
1361 rcb->ti_flags = 0;
1362 rcb->ti_max_len = TI_RETURN_RING_CNT;
1363 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_return_prodidx_ptr) =
1364 vtophys(&sc->ti_return_prodidx);
1365
1366 /*
1367 * Set up the tx ring. Note: for the Tigon 2, we have the option
1368 * of putting the transmit ring in the host's address space and
1369 * letting the chip DMA it instead of leaving the ring in the NIC's
1370 * memory and accessing it through the shared memory region. We
1371 * do this for the Tigon 2, but it doesn't work on the Tigon 1,
1372 * so we have to revert to the shared memory scheme if we detect
1373 * a Tigon 1 chip.
1374 */
1375 CSR_WRITE_4(sc, TI_WINBASE, TI_TX_RING_BASE);
1376 if (sc->ti_hwrev == TI_HWREV_TIGON) {
1377 sc->ti_rdata->ti_tx_ring_nic =
1378 (struct ti_tx_desc *)(sc->ti_vhandle + TI_WINDOW);
1379 }
1380 bzero((char *)sc->ti_rdata->ti_tx_ring,
1381 TI_TX_RING_CNT * sizeof(struct ti_tx_desc));
1382 rcb = &sc->ti_rdata->ti_info.ti_tx_rcb;
1383 if (sc->ti_hwrev == TI_HWREV_TIGON)
1384 rcb->ti_flags = 0;
1385 else
1386 rcb->ti_flags = TI_RCB_FLAG_HOST_RING;
1387 rcb->ti_flags |= TI_RCB_FLAG_VLAN_ASSIST;
1388 if (sc->arpcom.ac_if.if_hwassist)
1389 rcb->ti_flags |= TI_RCB_FLAG_TCP_UDP_CKSUM |
1390 TI_RCB_FLAG_IP_CKSUM | TI_RCB_FLAG_NO_PHDR_CKSUM;
1391 rcb->ti_max_len = TI_TX_RING_CNT;
1392 if (sc->ti_hwrev == TI_HWREV_TIGON)
1393 TI_HOSTADDR(rcb->ti_hostaddr) = TI_TX_RING_BASE;
1394 else
1395 TI_HOSTADDR(rcb->ti_hostaddr) =
1396 vtophys(&sc->ti_rdata->ti_tx_ring);
1397 TI_HOSTADDR(sc->ti_rdata->ti_info.ti_tx_considx_ptr) =
1398 vtophys(&sc->ti_tx_considx);
1399
1400 /* Set up tuneables */
1401 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
1402 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS,
1403 (sc->ti_rx_coal_ticks / 10));
1404 else
1405 CSR_WRITE_4(sc, TI_GCR_RX_COAL_TICKS, sc->ti_rx_coal_ticks);
1406 CSR_WRITE_4(sc, TI_GCR_TX_COAL_TICKS, sc->ti_tx_coal_ticks);
1407 CSR_WRITE_4(sc, TI_GCR_STAT_TICKS, sc->ti_stat_ticks);
1408 CSR_WRITE_4(sc, TI_GCR_RX_MAX_COAL_BD, sc->ti_rx_max_coal_bds);
1409 CSR_WRITE_4(sc, TI_GCR_TX_MAX_COAL_BD, sc->ti_tx_max_coal_bds);
1410 CSR_WRITE_4(sc, TI_GCR_TX_BUFFER_RATIO, sc->ti_tx_buf_ratio);
1411
1412 /* Turn interrupts on. */
1413 CSR_WRITE_4(sc, TI_GCR_MASK_INTRS, 0);
1414 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
1415
1416 /* Start CPU. */
1417 TI_CLRBIT(sc, TI_CPU_STATE, (TI_CPUSTATE_HALT|TI_CPUSTATE_STEP));
1418
1419 return(0);
1420}
1421
1422/*
1423 * Probe for a Tigon chip. Check the PCI vendor and device IDs
1424 * against our list and return its name if we find a match.
1425 */
1426static int ti_probe(dev)
1427 device_t dev;
1428{
1429 struct ti_type *t;
1430
1431 t = ti_devs;
1432
1433 while(t->ti_name != NULL) {
1434 if ((pci_get_vendor(dev) == t->ti_vid) &&
1435 (pci_get_device(dev) == t->ti_did)) {
1436 device_set_desc(dev, t->ti_name);
1437 return(0);
1438 }
1439 t++;
1440 }
1441
1442 return(ENXIO);
1443}
1444
1445static int ti_attach(dev)
1446 device_t dev;
1447{
1448 u_int32_t command;
1449 struct ifnet *ifp;
1450 struct ti_softc *sc;
1451 int unit, error = 0, rid;
1452
1453 sc = device_get_softc(dev);
1454 unit = device_get_unit(dev);
1455 bzero(sc, sizeof(struct ti_softc));
1456
1457 mtx_init(&sc->ti_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1458 MTX_DEF | MTX_RECURSE);
1459 TI_LOCK(sc);
1460 sc->arpcom.ac_if.if_capabilities = IFCAP_HWCSUM;
1461 sc->arpcom.ac_if.if_capenable = sc->arpcom.ac_if.if_capabilities;
1462
1463 /*
1464 * Map control/status registers.
1465 */
1466 pci_enable_busmaster(dev);
1467 pci_enable_io(dev, SYS_RES_MEMORY);
1468 command = pci_read_config(dev, PCIR_COMMAND, 4);
1469
1470 if (!(command & PCIM_CMD_MEMEN)) {
1471 printf("ti%d: failed to enable memory mapping!\n", unit);
1472 error = ENXIO;
1473 goto fail;
1474 }
1475
1476 rid = TI_PCI_LOMEM;
1477 sc->ti_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1478 0, ~0, 1, RF_ACTIVE|PCI_RF_DENSE);
1479
1480 if (sc->ti_res == NULL) {
1481 printf ("ti%d: couldn't map memory\n", unit);
1482 error = ENXIO;
1483 goto fail;
1484 }
1485
1486 sc->ti_btag = rman_get_bustag(sc->ti_res);
1487 sc->ti_bhandle = rman_get_bushandle(sc->ti_res);
1488 sc->ti_vhandle = (vm_offset_t)rman_get_virtual(sc->ti_res);
1489
1490 /* Allocate interrupt */
1491 rid = 0;
1492
1493 sc->ti_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
1494 RF_SHAREABLE | RF_ACTIVE);
1495
1496 if (sc->ti_irq == NULL) {
1497 printf("ti%d: couldn't map interrupt\n", unit);
1498 error = ENXIO;
1499 goto fail;
1500 }
1501
1502 error = bus_setup_intr(dev, sc->ti_irq, INTR_TYPE_NET,
1503 ti_intr, sc, &sc->ti_intrhand);
1504
1505 if (error) {
1506 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1507 bus_release_resource(dev, SYS_RES_MEMORY,
1508 TI_PCI_LOMEM, sc->ti_res);
1509 printf("ti%d: couldn't set up irq\n", unit);
1510 goto fail;
1511 }
1512
1513 sc->ti_unit = unit;
1514
1515 if (ti_chipinit(sc)) {
1516 printf("ti%d: chip initialization failed\n", sc->ti_unit);
1517 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1518 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1519 bus_release_resource(dev, SYS_RES_MEMORY,
1520 TI_PCI_LOMEM, sc->ti_res);
1521 error = ENXIO;
1522 goto fail;
1523 }
1524
1525 /* Zero out the NIC's on-board SRAM. */
1526 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL);
1527
1528 /* Init again -- zeroing memory may have clobbered some registers. */
1529 if (ti_chipinit(sc)) {
1530 printf("ti%d: chip initialization failed\n", sc->ti_unit);
1531 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1532 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1533 bus_release_resource(dev, SYS_RES_MEMORY,
1534 TI_PCI_LOMEM, sc->ti_res);
1535 error = ENXIO;
1536 goto fail;
1537 }
1538
1539 /*
1540 * Get station address from the EEPROM. Note: the manual states
1541 * that the MAC address is at offset 0x8c, however the data is
1542 * stored as two longwords (since that's how it's loaded into
1543 * the NIC). This means the MAC address is actually preceded
1544 * by two zero bytes. We need to skip over those.
1545 */
1546 if (ti_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
1547 TI_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
1548 printf("ti%d: failed to read station address\n", unit);
1549 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1550 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1551 bus_release_resource(dev, SYS_RES_MEMORY,
1552 TI_PCI_LOMEM, sc->ti_res);
1553 error = ENXIO;
1554 goto fail;
1555 }
1556
1557 /*
1558 * A Tigon chip was detected. Inform the world.
1559 */
1560 printf("ti%d: Ethernet address: %6D\n", unit,
1561 sc->arpcom.ac_enaddr, ":");
1562
1563 /* Allocate the general information block and ring buffers. */
1564 sc->ti_rdata = contigmalloc(sizeof(struct ti_ring_data), M_DEVBUF,
1565 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
1566
1567 if (sc->ti_rdata == NULL) {
1568 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1569 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1570 bus_release_resource(dev, SYS_RES_MEMORY,
1571 TI_PCI_LOMEM, sc->ti_res);
1572 error = ENXIO;
1573 printf("ti%d: no memory for list buffers!\n", sc->ti_unit);
1574 goto fail;
1575 }
1576
1577 bzero(sc->ti_rdata, sizeof(struct ti_ring_data));
1578
1579 /* Try to allocate memory for jumbo buffers. */
1580 if (ti_alloc_jumbo_mem(sc)) {
1581 printf("ti%d: jumbo buffer allocation failed\n", sc->ti_unit);
1582 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1583 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1584 bus_release_resource(dev, SYS_RES_MEMORY,
1585 TI_PCI_LOMEM, sc->ti_res);
1586 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data),
1587 M_DEVBUF);
1588 error = ENXIO;
1589 goto fail;
1590 }
1591
1592 /*
1593 * We really need a better way to tell a 1000baseTX card
1594 * from a 1000baseSX one, since in theory there could be
1595 * OEMed 1000baseTX cards from lame vendors who aren't
1596 * clever enough to change the PCI ID. For the moment
1597 * though, the AceNIC is the only copper card available.
1598 */
1599 if (pci_get_vendor(dev) == ALT_VENDORID &&
1600 pci_get_device(dev) == ALT_DEVICEID_ACENIC_COPPER)
1601 sc->ti_copper = 1;
1602 /* Ok, it's not the only copper card available. */
1603 if (pci_get_vendor(dev) == NG_VENDORID &&
1604 pci_get_device(dev) == NG_DEVICEID_GA620T)
1605 sc->ti_copper = 1;
1606
1607 /* Set default tuneable values. */
1608 sc->ti_stat_ticks = 2 * TI_TICKS_PER_SEC;
1609 sc->ti_rx_coal_ticks = TI_TICKS_PER_SEC / 5000;
1610 sc->ti_tx_coal_ticks = TI_TICKS_PER_SEC / 500;
1611 sc->ti_rx_max_coal_bds = 64;
1612 sc->ti_tx_max_coal_bds = 128;
1613 sc->ti_tx_buf_ratio = 21;
1614
1615 /* Set up ifnet structure */
1616 ifp = &sc->arpcom.ac_if;
1617 ifp->if_softc = sc;
1618 ifp->if_unit = sc->ti_unit;
1619 ifp->if_name = "ti";
1620 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1621 ifp->if_ioctl = ti_ioctl;
1622 ifp->if_output = ether_output;
1623 ifp->if_start = ti_start;
1624 ifp->if_watchdog = ti_watchdog;
1625 ifp->if_init = ti_init;
1626 ifp->if_mtu = ETHERMTU;
1627 ifp->if_snd.ifq_maxlen = TI_TX_RING_CNT - 1;
1628
1629 /* Set up ifmedia support. */
1630 ifmedia_init(&sc->ifmedia, IFM_IMASK, ti_ifmedia_upd, ti_ifmedia_sts);
1631 if (sc->ti_copper) {
1632 /*
1633 * Copper cards allow manual 10/100 mode selection,
1634 * but not manual 1000baseTX mode selection. Why?
1635 * Becuase currently there's no way to specify the
1636 * master/slave setting through the firmware interface,
1637 * so Alteon decided to just bag it and handle it
1638 * via autonegotiation.
1639 */
1640 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1641 ifmedia_add(&sc->ifmedia,
1642 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1643 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_TX, 0, NULL);
1644 ifmedia_add(&sc->ifmedia,
1645 IFM_ETHER|IFM_100_TX|IFM_FDX, 0, NULL);
1646 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_T, 0, NULL);
1647 ifmedia_add(&sc->ifmedia,
1648 IFM_ETHER|IFM_1000_T|IFM_FDX, 0, NULL);
1649 } else {
1650 /* Fiber cards don't support 10/100 modes. */
1651 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1652 ifmedia_add(&sc->ifmedia,
1653 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1654 }
1655 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1656 ifmedia_set(&sc->ifmedia, IFM_ETHER|IFM_AUTO);
1657
1658 /*
1659 * Call MI attach routine.
1660 */
1661 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
1662 TI_UNLOCK(sc);
1663 return(0);
1664
1665fail:
1666 TI_UNLOCK(sc);
1667 mtx_destroy(&sc->ti_mtx);
1668 return(error);
1669}
1670
1671static int ti_detach(dev)
1672 device_t dev;
1673{
1674 struct ti_softc *sc;
1675 struct ifnet *ifp;
1676
1677
1678 sc = device_get_softc(dev);
1679 TI_LOCK(sc);
1680 ifp = &sc->arpcom.ac_if;
1681
1682 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
1683 ti_stop(sc);
1684
1685 bus_teardown_intr(dev, sc->ti_irq, sc->ti_intrhand);
1686 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ti_irq);
1687 bus_release_resource(dev, SYS_RES_MEMORY, TI_PCI_LOMEM, sc->ti_res);
1688
1689 contigfree(sc->ti_cdata.ti_jumbo_buf, TI_JMEM, M_DEVBUF);
1690 contigfree(sc->ti_rdata, sizeof(struct ti_ring_data), M_DEVBUF);
1691 ifmedia_removeall(&sc->ifmedia);
1692
1693 TI_UNLOCK(sc);
1694 mtx_destroy(&sc->ti_mtx);
1695
1696 return(0);
1697}
1698
1699/*
1700 * Frame reception handling. This is called if there's a frame
1701 * on the receive return list.
1702 *
1703 * Note: we have to be able to handle three possibilities here:
1704 * 1) the frame is from the mini receive ring (can only happen)
1705 * on Tigon 2 boards)
1706 * 2) the frame is from the jumbo recieve ring
1707 * 3) the frame is from the standard receive ring
1708 */
1709
1710static void ti_rxeof(sc)
1711 struct ti_softc *sc;
1712{
1713 struct ifnet *ifp;
1714 struct ti_cmd_desc cmd;
1715
1716 ifp = &sc->arpcom.ac_if;
1717
1718 while(sc->ti_rx_saved_considx != sc->ti_return_prodidx.ti_idx) {
1719 struct ti_rx_desc *cur_rx;
1720 u_int32_t rxidx;
1721 struct ether_header *eh;
1722 struct mbuf *m = NULL;
1723 u_int16_t vlan_tag = 0;
1724 int have_tag = 0;
1725
1726 cur_rx =
1727 &sc->ti_rdata->ti_rx_return_ring[sc->ti_rx_saved_considx];
1728 rxidx = cur_rx->ti_idx;
1729 TI_INC(sc->ti_rx_saved_considx, TI_RETURN_RING_CNT);
1730
1731 if (cur_rx->ti_flags & TI_BDFLAG_VLAN_TAG) {
1732 have_tag = 1;
1733 vlan_tag = cur_rx->ti_vlan_tag & 0xfff;
1734 }
1735
1736 if (cur_rx->ti_flags & TI_BDFLAG_JUMBO_RING) {
1737 TI_INC(sc->ti_jumbo, TI_JUMBO_RX_RING_CNT);
1738 m = sc->ti_cdata.ti_rx_jumbo_chain[rxidx];
1739 sc->ti_cdata.ti_rx_jumbo_chain[rxidx] = NULL;
1740 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1741 ifp->if_ierrors++;
1742 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
1743 continue;
1744 }
1745 if (ti_newbuf_jumbo(sc, sc->ti_jumbo, NULL) == ENOBUFS) {
1746 ifp->if_ierrors++;
1747 ti_newbuf_jumbo(sc, sc->ti_jumbo, m);
1748 continue;
1749 }
1750 } else if (cur_rx->ti_flags & TI_BDFLAG_MINI_RING) {
1751 TI_INC(sc->ti_mini, TI_MINI_RX_RING_CNT);
1752 m = sc->ti_cdata.ti_rx_mini_chain[rxidx];
1753 sc->ti_cdata.ti_rx_mini_chain[rxidx] = NULL;
1754 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1755 ifp->if_ierrors++;
1756 ti_newbuf_mini(sc, sc->ti_mini, m);
1757 continue;
1758 }
1759 if (ti_newbuf_mini(sc, sc->ti_mini, NULL) == ENOBUFS) {
1760 ifp->if_ierrors++;
1761 ti_newbuf_mini(sc, sc->ti_mini, m);
1762 continue;
1763 }
1764 } else {
1765 TI_INC(sc->ti_std, TI_STD_RX_RING_CNT);
1766 m = sc->ti_cdata.ti_rx_std_chain[rxidx];
1767 sc->ti_cdata.ti_rx_std_chain[rxidx] = NULL;
1768 if (cur_rx->ti_flags & TI_BDFLAG_ERROR) {
1769 ifp->if_ierrors++;
1770 ti_newbuf_std(sc, sc->ti_std, m);
1771 continue;
1772 }
1773 if (ti_newbuf_std(sc, sc->ti_std, NULL) == ENOBUFS) {
1774 ifp->if_ierrors++;
1775 ti_newbuf_std(sc, sc->ti_std, m);
1776 continue;
1777 }
1778 }
1779
1780 m->m_pkthdr.len = m->m_len = cur_rx->ti_len;
1781 ifp->if_ipackets++;
1782 eh = mtod(m, struct ether_header *);
1783 m->m_pkthdr.rcvif = ifp;
1784
1785 /* Remove header from mbuf and pass it on. */
1786 m_adj(m, sizeof(struct ether_header));
1787
1788 if (ifp->if_hwassist) {
1789 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
1790 CSUM_DATA_VALID;
1791 if ((cur_rx->ti_ip_cksum ^ 0xffff) == 0)
1792 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1793 m->m_pkthdr.csum_data = cur_rx->ti_tcp_udp_cksum;
1794 }
1795
1796 /*
1797 * If we received a packet with a vlan tag, pass it
1798 * to vlan_input() instead of ether_input().
1799 */
1800 if (have_tag) {
1801 VLAN_INPUT_TAG(eh, m, vlan_tag);
1802 have_tag = vlan_tag = 0;
1803 continue;
1804 }
1805 ether_input(ifp, eh, m);
1806 }
1807
1808 /* Only necessary on the Tigon 1. */
1809 if (sc->ti_hwrev == TI_HWREV_TIGON)
1810 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX,
1811 sc->ti_rx_saved_considx);
1812
1813 TI_UPDATE_STDPROD(sc, sc->ti_std);
1814 TI_UPDATE_MINIPROD(sc, sc->ti_mini);
1815 TI_UPDATE_JUMBOPROD(sc, sc->ti_jumbo);
1816
1817 return;
1818}
1819
1820static void ti_txeof(sc)
1821 struct ti_softc *sc;
1822{
1823 struct ti_tx_desc *cur_tx = NULL;
1824 struct ifnet *ifp;
1825
1826 ifp = &sc->arpcom.ac_if;
1827
1828 /*
1829 * Go through our tx ring and free mbufs for those
1830 * frames that have been sent.
1831 */
1832 while (sc->ti_tx_saved_considx != sc->ti_tx_considx.ti_idx) {
1833 u_int32_t idx = 0;
1834
1835 idx = sc->ti_tx_saved_considx;
1836 if (sc->ti_hwrev == TI_HWREV_TIGON) {
1837 if (idx > 383)
1838 CSR_WRITE_4(sc, TI_WINBASE,
1839 TI_TX_RING_BASE + 6144);
1840 else if (idx > 255)
1841 CSR_WRITE_4(sc, TI_WINBASE,
1842 TI_TX_RING_BASE + 4096);
1843 else if (idx > 127)
1844 CSR_WRITE_4(sc, TI_WINBASE,
1845 TI_TX_RING_BASE + 2048);
1846 else
1847 CSR_WRITE_4(sc, TI_WINBASE,
1848 TI_TX_RING_BASE);
1849 cur_tx = &sc->ti_rdata->ti_tx_ring_nic[idx % 128];
1850 } else
1851 cur_tx = &sc->ti_rdata->ti_tx_ring[idx];
1852 if (cur_tx->ti_flags & TI_BDFLAG_END)
1853 ifp->if_opackets++;
1854 if (sc->ti_cdata.ti_tx_chain[idx] != NULL) {
1855 m_freem(sc->ti_cdata.ti_tx_chain[idx]);
1856 sc->ti_cdata.ti_tx_chain[idx] = NULL;
1857 }
1858 sc->ti_txcnt--;
1859 TI_INC(sc->ti_tx_saved_considx, TI_TX_RING_CNT);
1860 ifp->if_timer = 0;
1861 }
1862
1863 if (cur_tx != NULL)
1864 ifp->if_flags &= ~IFF_OACTIVE;
1865
1866 return;
1867}
1868
1869static void ti_intr(xsc)
1870 void *xsc;
1871{
1872 struct ti_softc *sc;
1873 struct ifnet *ifp;
1874
1875 sc = xsc;
1876 TI_LOCK(sc);
1877 ifp = &sc->arpcom.ac_if;
1878
1879#ifdef notdef
1880 /* Avoid this for now -- checking this register is expensive. */
1881 /* Make sure this is really our interrupt. */
1882 if (!(CSR_READ_4(sc, TI_MISC_HOST_CTL) & TI_MHC_INTSTATE)) {
1883 TI_UNLOCK(sc);
1884 return;
1885 }
1886#endif
1887
1888 /* Ack interrupt and stop others from occuring. */
1889 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
1890
1891 if (ifp->if_flags & IFF_RUNNING) {
1892 /* Check RX return ring producer/consumer */
1893 ti_rxeof(sc);
1894
1895 /* Check TX ring producer/consumer */
1896 ti_txeof(sc);
1897 }
1898
1899 ti_handle_events(sc);
1900
1901 /* Re-enable interrupts. */
1902 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
1903
1904 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL)
1905 ti_start(ifp);
1906
1907 TI_UNLOCK(sc);
1908
1909 return;
1910}
1911
1912static void ti_stats_update(sc)
1913 struct ti_softc *sc;
1914{
1915 struct ifnet *ifp;
1916
1917 ifp = &sc->arpcom.ac_if;
1918
1919 ifp->if_collisions +=
1920 (sc->ti_rdata->ti_info.ti_stats.dot3StatsSingleCollisionFrames +
1921 sc->ti_rdata->ti_info.ti_stats.dot3StatsMultipleCollisionFrames +
1922 sc->ti_rdata->ti_info.ti_stats.dot3StatsExcessiveCollisions +
1923 sc->ti_rdata->ti_info.ti_stats.dot3StatsLateCollisions) -
1924 ifp->if_collisions;
1925
1926 return;
1927}
1928
1929/*
1930 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
1931 * pointers to descriptors.
1932 */
1933static int ti_encap(sc, m_head, txidx)
1934 struct ti_softc *sc;
1935 struct mbuf *m_head;
1936 u_int32_t *txidx;
1937{
1938 struct ti_tx_desc *f = NULL;
1939 struct mbuf *m;
1940 u_int32_t frag, cur, cnt = 0;
1941 u_int16_t csum_flags = 0;
1942 struct ifvlan *ifv = NULL;
1943
1944 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
1945 m_head->m_pkthdr.rcvif != NULL &&
1946 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
1947 ifv = m_head->m_pkthdr.rcvif->if_softc;
1948
1949 m = m_head;
1950 cur = frag = *txidx;
1951
1952 if (m_head->m_pkthdr.csum_flags) {
1953 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
1954 csum_flags |= TI_BDFLAG_IP_CKSUM;
1955 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
1956 csum_flags |= TI_BDFLAG_TCP_UDP_CKSUM;
1957 if (m_head->m_flags & M_LASTFRAG)
1958 csum_flags |= TI_BDFLAG_IP_FRAG_END;
1959 else if (m_head->m_flags & M_FRAG)
1960 csum_flags |= TI_BDFLAG_IP_FRAG;
1961 }
1962 /*
1963 * Start packing the mbufs in this chain into
1964 * the fragment pointers. Stop when we run out
1965 * of fragments or hit the end of the mbuf chain.
1966 */
1967 for (m = m_head; m != NULL; m = m->m_next) {
1968 if (m->m_len != 0) {
1969 if (sc->ti_hwrev == TI_HWREV_TIGON) {
1970 if (frag > 383)
1971 CSR_WRITE_4(sc, TI_WINBASE,
1972 TI_TX_RING_BASE + 6144);
1973 else if (frag > 255)
1974 CSR_WRITE_4(sc, TI_WINBASE,
1975 TI_TX_RING_BASE + 4096);
1976 else if (frag > 127)
1977 CSR_WRITE_4(sc, TI_WINBASE,
1978 TI_TX_RING_BASE + 2048);
1979 else
1980 CSR_WRITE_4(sc, TI_WINBASE,
1981 TI_TX_RING_BASE);
1982 f = &sc->ti_rdata->ti_tx_ring_nic[frag % 128];
1983 } else
1984 f = &sc->ti_rdata->ti_tx_ring[frag];
1985 if (sc->ti_cdata.ti_tx_chain[frag] != NULL)
1986 break;
1987 TI_HOSTADDR(f->ti_addr) = vtophys(mtod(m, vm_offset_t));
1988 f->ti_len = m->m_len;
1989 f->ti_flags = csum_flags;
1990
1991 if (ifv != NULL) {
1992 f->ti_flags |= TI_BDFLAG_VLAN_TAG;
1993 f->ti_vlan_tag = ifv->ifv_tag & 0xfff;
1994 } else {
1995 f->ti_vlan_tag = 0;
1996 }
1997
1998 /*
1999 * Sanity check: avoid coming within 16 descriptors
2000 * of the end of the ring.
2001 */
2002 if ((TI_TX_RING_CNT - (sc->ti_txcnt + cnt)) < 16)
2003 return(ENOBUFS);
2004 cur = frag;
2005 TI_INC(frag, TI_TX_RING_CNT);
2006 cnt++;
2007 }
2008 }
2009
2010 if (m != NULL)
2011 return(ENOBUFS);
2012
2013 if (frag == sc->ti_tx_saved_considx)
2014 return(ENOBUFS);
2015
2016 if (sc->ti_hwrev == TI_HWREV_TIGON)
2017 sc->ti_rdata->ti_tx_ring_nic[cur % 128].ti_flags |=
2018 TI_BDFLAG_END;
2019 else
2020 sc->ti_rdata->ti_tx_ring[cur].ti_flags |= TI_BDFLAG_END;
2021 sc->ti_cdata.ti_tx_chain[cur] = m_head;
2022 sc->ti_txcnt += cnt;
2023
2024 *txidx = frag;
2025
2026 return(0);
2027}
2028
2029/*
2030 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2031 * to the mbuf data regions directly in the transmit descriptors.
2032 */
2033static void ti_start(ifp)
2034 struct ifnet *ifp;
2035{
2036 struct ti_softc *sc;
2037 struct mbuf *m_head = NULL;
2038 u_int32_t prodidx = 0;
2039
2040 sc = ifp->if_softc;
2041 TI_LOCK(sc);
2042
2043 prodidx = CSR_READ_4(sc, TI_MB_SENDPROD_IDX);
2044
2045 while(sc->ti_cdata.ti_tx_chain[prodidx] == NULL) {
2046 IF_DEQUEUE(&ifp->if_snd, m_head);
2047 if (m_head == NULL)
2048 break;
2049
2050 /*
2051 * XXX
2052 * safety overkill. If this is a fragmented packet chain
2053 * with delayed TCP/UDP checksums, then only encapsulate
2054 * it if we have enough descriptors to handle the entire
2055 * chain at once.
2056 * (paranoia -- may not actually be needed)
2057 */
2058 if (m_head->m_flags & M_FIRSTFRAG &&
2059 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
2060 if ((TI_TX_RING_CNT - sc->ti_txcnt) <
2061 m_head->m_pkthdr.csum_data + 16) {
2062 IF_PREPEND(&ifp->if_snd, m_head);
2063 ifp->if_flags |= IFF_OACTIVE;
2064 break;
2065 }
2066 }
2067
2068 /*
2069 * Pack the data into the transmit ring. If we
2070 * don't have room, set the OACTIVE flag and wait
2071 * for the NIC to drain the ring.
2072 */
2073 if (ti_encap(sc, m_head, &prodidx)) {
2074 IF_PREPEND(&ifp->if_snd, m_head);
2075 ifp->if_flags |= IFF_OACTIVE;
2076 break;
2077 }
2078
2079 /*
2080 * If there's a BPF listener, bounce a copy of this frame
2081 * to him.
2082 */
2083 if (ifp->if_bpf)
2084 bpf_mtap(ifp, m_head);
2085 }
2086
2087 /* Transmit */
2088 CSR_WRITE_4(sc, TI_MB_SENDPROD_IDX, prodidx);
2089
2090 /*
2091 * Set a timeout in case the chip goes out to lunch.
2092 */
2093 ifp->if_timer = 5;
2094 TI_UNLOCK(sc);
2095
2096 return;
2097}
2098
2099static void ti_init(xsc)
2100 void *xsc;
2101{
2102 struct ti_softc *sc = xsc;
2103
2104 /* Cancel pending I/O and flush buffers. */
2105 ti_stop(sc);
2106
2107 TI_LOCK(sc);
2108 /* Init the gen info block, ring control blocks and firmware. */
2109 if (ti_gibinit(sc)) {
2110 printf("ti%d: initialization failure\n", sc->ti_unit);
2111 TI_UNLOCK(sc);
2112 return;
2113 }
2114
2115 TI_UNLOCK(sc);
2116
2117 return;
2118}
2119
2120static void ti_init2(sc)
2121 struct ti_softc *sc;
2122{
2123 struct ti_cmd_desc cmd;
2124 struct ifnet *ifp;
2125 u_int16_t *m;
2126 struct ifmedia *ifm;
2127 int tmp;
2128
2129 ifp = &sc->arpcom.ac_if;
2130
2131 /* Specify MTU and interface index. */
2132 CSR_WRITE_4(sc, TI_GCR_IFINDEX, ifp->if_unit);
2133 CSR_WRITE_4(sc, TI_GCR_IFMTU, ifp->if_mtu +
2134 ETHER_HDR_LEN + ETHER_CRC_LEN);
2135 TI_DO_CMD(TI_CMD_UPDATE_GENCOM, 0, 0);
2136
2137 /* Load our MAC address. */
2138 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0];
2139 CSR_WRITE_4(sc, TI_GCR_PAR0, htons(m[0]));
2140 CSR_WRITE_4(sc, TI_GCR_PAR1, (htons(m[1]) << 16) | htons(m[2]));
2141 TI_DO_CMD(TI_CMD_SET_MAC_ADDR, 0, 0);
2142
2143 /* Enable or disable promiscuous mode as needed. */
2144 if (ifp->if_flags & IFF_PROMISC) {
2145 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_ENB, 0);
2146 } else {
2147 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE, TI_CMD_CODE_PROMISC_DIS, 0);
2148 }
2149
2150 /* Program multicast filter. */
2151 ti_setmulti(sc);
2152
2153 /*
2154 * If this is a Tigon 1, we should tell the
2155 * firmware to use software packet filtering.
2156 */
2157 if (sc->ti_hwrev == TI_HWREV_TIGON) {
2158 TI_DO_CMD(TI_CMD_FDR_FILTERING, TI_CMD_CODE_FILT_ENB, 0);
2159 }
2160
2161 /* Init RX ring. */
2162 ti_init_rx_ring_std(sc);
2163
2164 /* Init jumbo RX ring. */
2165 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2166 ti_init_rx_ring_jumbo(sc);
2167
2168 /*
2169 * If this is a Tigon 2, we can also configure the
2170 * mini ring.
2171 */
2172 if (sc->ti_hwrev == TI_HWREV_TIGON_II)
2173 ti_init_rx_ring_mini(sc);
2174
2175 CSR_WRITE_4(sc, TI_GCR_RXRETURNCONS_IDX, 0);
2176 sc->ti_rx_saved_considx = 0;
2177
2178 /* Init TX ring. */
2179 ti_init_tx_ring(sc);
2180
2181 /* Tell firmware we're alive. */
2182 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_UP, 0);
2183
2184 /* Enable host interrupts. */
2185 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 0);
2186
2187 ifp->if_flags |= IFF_RUNNING;
2188 ifp->if_flags &= ~IFF_OACTIVE;
2189
2190 /*
2191 * Make sure to set media properly. We have to do this
2192 * here since we have to issue commands in order to set
2193 * the link negotiation and we can't issue commands until
2194 * the firmware is running.
2195 */
2196 ifm = &sc->ifmedia;
2197 tmp = ifm->ifm_media;
2198 ifm->ifm_media = ifm->ifm_cur->ifm_media;
2199 ti_ifmedia_upd(ifp);
2200 ifm->ifm_media = tmp;
2201
2202 return;
2203}
2204
2205/*
2206 * Set media options.
2207 */
2208static int ti_ifmedia_upd(ifp)
2209 struct ifnet *ifp;
2210{
2211 struct ti_softc *sc;
2212 struct ifmedia *ifm;
2213 struct ti_cmd_desc cmd;
2214
2215 sc = ifp->if_softc;
2216 ifm = &sc->ifmedia;
2217
2218 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2219 return(EINVAL);
2220
2221 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2222 case IFM_AUTO:
2223 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
2224 TI_GLNK_FULL_DUPLEX|TI_GLNK_RX_FLOWCTL_Y|
2225 TI_GLNK_AUTONEGENB|TI_GLNK_ENB);
2226 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_100MB|TI_LNK_10MB|
2227 TI_LNK_FULL_DUPLEX|TI_LNK_HALF_DUPLEX|
2228 TI_LNK_AUTONEGENB|TI_LNK_ENB);
2229 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2230 TI_CMD_CODE_NEGOTIATE_BOTH, 0);
2231 break;
2232 case IFM_1000_SX:
2233 case IFM_1000_T:
2234 CSR_WRITE_4(sc, TI_GCR_GLINK, TI_GLNK_PREF|TI_GLNK_1000MB|
2235 TI_GLNK_RX_FLOWCTL_Y|TI_GLNK_ENB);
2236 CSR_WRITE_4(sc, TI_GCR_LINK, 0);
2237 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2238 TI_SETBIT(sc, TI_GCR_GLINK, TI_GLNK_FULL_DUPLEX);
2239 }
2240 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2241 TI_CMD_CODE_NEGOTIATE_GIGABIT, 0);
2242 break;
2243 case IFM_100_FX:
2244 case IFM_10_FL:
2245 case IFM_100_TX:
2246 case IFM_10_T:
2247 CSR_WRITE_4(sc, TI_GCR_GLINK, 0);
2248 CSR_WRITE_4(sc, TI_GCR_LINK, TI_LNK_ENB|TI_LNK_PREF);
2249 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_100_FX ||
2250 IFM_SUBTYPE(ifm->ifm_media) == IFM_100_TX) {
2251 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_100MB);
2252 } else {
2253 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_10MB);
2254 }
2255 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2256 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_FULL_DUPLEX);
2257 } else {
2258 TI_SETBIT(sc, TI_GCR_LINK, TI_LNK_HALF_DUPLEX);
2259 }
2260 TI_DO_CMD(TI_CMD_LINK_NEGOTIATION,
2261 TI_CMD_CODE_NEGOTIATE_10_100, 0);
2262 break;
2263 }
2264
2265 return(0);
2266}
2267
2268/*
2269 * Report current media status.
2270 */
2271static void ti_ifmedia_sts(ifp, ifmr)
2272 struct ifnet *ifp;
2273 struct ifmediareq *ifmr;
2274{
2275 struct ti_softc *sc;
2276 u_int32_t media = 0;
2277
2278 sc = ifp->if_softc;
2279
2280 ifmr->ifm_status = IFM_AVALID;
2281 ifmr->ifm_active = IFM_ETHER;
2282
2283 if (sc->ti_linkstat == TI_EV_CODE_LINK_DOWN)
2284 return;
2285
2286 ifmr->ifm_status |= IFM_ACTIVE;
2287
2288 if (sc->ti_linkstat == TI_EV_CODE_GIG_LINK_UP) {
2289 media = CSR_READ_4(sc, TI_GCR_GLINK_STAT);
2290 if (sc->ti_copper)
2291 ifmr->ifm_active |= IFM_1000_T;
2292 else
2293 ifmr->ifm_active |= IFM_1000_SX;
2294 if (media & TI_GLNK_FULL_DUPLEX)
2295 ifmr->ifm_active |= IFM_FDX;
2296 else
2297 ifmr->ifm_active |= IFM_HDX;
2298 } else if (sc->ti_linkstat == TI_EV_CODE_LINK_UP) {
2299 media = CSR_READ_4(sc, TI_GCR_LINK_STAT);
2300 if (sc->ti_copper) {
2301 if (media & TI_LNK_100MB)
2302 ifmr->ifm_active |= IFM_100_TX;
2303 if (media & TI_LNK_10MB)
2304 ifmr->ifm_active |= IFM_10_T;
2305 } else {
2306 if (media & TI_LNK_100MB)
2307 ifmr->ifm_active |= IFM_100_FX;
2308 if (media & TI_LNK_10MB)
2309 ifmr->ifm_active |= IFM_10_FL;
2310 }
2311 if (media & TI_LNK_FULL_DUPLEX)
2312 ifmr->ifm_active |= IFM_FDX;
2313 if (media & TI_LNK_HALF_DUPLEX)
2314 ifmr->ifm_active |= IFM_HDX;
2315 }
2316
2317 return;
2318}
2319
2320static int ti_ioctl(ifp, command, data)
2321 struct ifnet *ifp;
2322 u_long command;
2323 caddr_t data;
2324{
2325 struct ti_softc *sc = ifp->if_softc;
2326 struct ifreq *ifr = (struct ifreq *) data;
2327 int mask, error = 0;
2328 struct ti_cmd_desc cmd;
2329
2330 TI_LOCK(sc);
2331
2332 switch(command) {
2333 case SIOCSIFADDR:
2334 case SIOCGIFADDR:
2335 error = ether_ioctl(ifp, command, data);
2336 break;
2337 case SIOCSIFMTU:
2338 if (ifr->ifr_mtu > TI_JUMBO_MTU)
2339 error = EINVAL;
2340 else {
2341 ifp->if_mtu = ifr->ifr_mtu;
2342 ti_init(sc);
2343 }
2344 break;
2345 case SIOCSIFFLAGS:
2346 if (ifp->if_flags & IFF_UP) {
2347 /*
2348 * If only the state of the PROMISC flag changed,
2349 * then just use the 'set promisc mode' command
2350 * instead of reinitializing the entire NIC. Doing
2351 * a full re-init means reloading the firmware and
2352 * waiting for it to start up, which may take a
2353 * second or two.
2354 */
2355 if (ifp->if_flags & IFF_RUNNING &&
2356 ifp->if_flags & IFF_PROMISC &&
2357 !(sc->ti_if_flags & IFF_PROMISC)) {
2358 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
2359 TI_CMD_CODE_PROMISC_ENB, 0);
2360 } else if (ifp->if_flags & IFF_RUNNING &&
2361 !(ifp->if_flags & IFF_PROMISC) &&
2362 sc->ti_if_flags & IFF_PROMISC) {
2363 TI_DO_CMD(TI_CMD_SET_PROMISC_MODE,
2364 TI_CMD_CODE_PROMISC_DIS, 0);
2365 } else
2366 ti_init(sc);
2367 } else {
2368 if (ifp->if_flags & IFF_RUNNING) {
2369 ti_stop(sc);
2370 }
2371 }
2372 sc->ti_if_flags = ifp->if_flags;
2373 error = 0;
2374 break;
2375 case SIOCADDMULTI:
2376 case SIOCDELMULTI:
2377 if (ifp->if_flags & IFF_RUNNING) {
2378 ti_setmulti(sc);
2379 error = 0;
2380 }
2381 break;
2382 case SIOCSIFMEDIA:
2383 case SIOCGIFMEDIA:
2384 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
2385 break;
2386 case SIOCSIFCAP:
2387 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2388 if (mask & IFCAP_HWCSUM) {
2389 if (IFCAP_HWCSUM & ifp->if_capenable)
2390 ifp->if_capenable &= ~IFCAP_HWCSUM;
2391 else
2392 ifp->if_capenable |= IFCAP_HWCSUM;
2393 if (ifp->if_flags & IFF_RUNNING)
2394 ti_init(sc);
2395 }
2396 error = 0;
2397 break;
2398 default:
2399 error = EINVAL;
2400 break;
2401 }
2402
2403 TI_UNLOCK(sc);
2404
2405 return(error);
2406}
2407
2408static void ti_watchdog(ifp)
2409 struct ifnet *ifp;
2410{
2411 struct ti_softc *sc;
2412
2413 sc = ifp->if_softc;
2414 TI_LOCK(sc);
2415
2416 printf("ti%d: watchdog timeout -- resetting\n", sc->ti_unit);
2417 ti_stop(sc);
2418 ti_init(sc);
2419
2420 ifp->if_oerrors++;
2421 TI_UNLOCK(sc);
2422
2423 return;
2424}
2425
2426/*
2427 * Stop the adapter and free any mbufs allocated to the
2428 * RX and TX lists.
2429 */
2430static void ti_stop(sc)
2431 struct ti_softc *sc;
2432{
2433 struct ifnet *ifp;
2434 struct ti_cmd_desc cmd;
2435
2436 TI_LOCK(sc);
2437
2438 ifp = &sc->arpcom.ac_if;
2439
2440 /* Disable host interrupts. */
2441 CSR_WRITE_4(sc, TI_MB_HOSTINTR, 1);
2442 /*
2443 * Tell firmware we're shutting down.
2444 */
2445 TI_DO_CMD(TI_CMD_HOST_STATE, TI_CMD_CODE_STACK_DOWN, 0);
2446
2447 /* Halt and reinitialize. */
2448 ti_chipinit(sc);
2449 ti_mem(sc, 0x2000, 0x100000 - 0x2000, NULL);
2450 ti_chipinit(sc);
2451
2452 /* Free the RX lists. */
2453 ti_free_rx_ring_std(sc);
2454
2455 /* Free jumbo RX list. */
2456 ti_free_rx_ring_jumbo(sc);
2457
2458 /* Free mini RX list. */
2459 ti_free_rx_ring_mini(sc);
2460
2461 /* Free TX buffers. */
2462 ti_free_tx_ring(sc);
2463
2464 sc->ti_ev_prodidx.ti_idx = 0;
2465 sc->ti_return_prodidx.ti_idx = 0;
2466 sc->ti_tx_considx.ti_idx = 0;
2467 sc->ti_tx_saved_considx = TI_TXCONS_UNSET;
2468
2469 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2470 TI_UNLOCK(sc);
2471
2472 return;
2473}
2474
2475/*
2476 * Stop all chip I/O so that the kernel's probe routines don't
2477 * get confused by errant DMAs when rebooting.
2478 */
2479static void ti_shutdown(dev)
2480 device_t dev;
2481{
2482 struct ti_softc *sc;
2483
2484 sc = device_get_softc(dev);
2485 TI_LOCK(sc);
2486 ti_chipinit(sc);
2487 TI_UNLOCK(sc);
2488
2489 return;
2490}