1/*
2 * Copyright (c) 2000 Orion Hodson <O.Hodson@cs.ucl.ac.uk>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * This driver exists largely as a result of other people's efforts.
27 * Much of register handling is based on NetBSD CMI8x38 audio driver
28 * by Takuya Shiozaki <AoiMoe@imou.to>. Chen-Li Tien
29 * <cltien@cmedia.com.tw> clarified points regarding the DMA related
30 * registers and the 8738 mixer devices. His Linux was driver a also
31 * useful reference point.
32 *
33 * TODO: MIDI
34 *
35 * SPDIF contributed by Gerhard Gonter <gonter@whisky.wu-wien.ac.at>.
36 *
37 * This card/code does not always manage to sample at 44100 - actual
38 * rate drifts slightly between recordings (usually 0-3%). No
39 * differences visible in register dumps between times that work and
40 * those that don't.
41 */
42
43#include <dev/sound/pcm/sound.h>
44#include <dev/sound/pci/cmireg.h>
45#include <dev/sound/isa/sb.h>
46
47#include <pci/pcireg.h>
48#include <pci/pcivar.h>
49
50#include <sys/sysctl.h>
51
52#include "mixer_if.h"
53
54SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/cmi.c 82180 2001-08-23 11:30:52Z cg $");
55
56/* Supported chip ID's */
57#define CMI8338A_PCI_ID 0x010013f6
58#define CMI8338B_PCI_ID 0x010113f6
59#define CMI8738_PCI_ID 0x011113f6
60#define CMI8738B_PCI_ID 0x011213f6
61
62/* Buffer size max is 64k for permitted DMA boundaries */
63#define CMI_BUFFER_SIZE 16384
64
65/* Interrupts per length of buffer */
66#define CMI_INTR_PER_BUFFER 2
67
68/* Clarify meaning of named defines in cmireg.h */
69#define CMPCI_REG_DMA0_MAX_SAMPLES CMPCI_REG_DMA0_BYTES
70#define CMPCI_REG_DMA0_INTR_SAMPLES CMPCI_REG_DMA0_SAMPLES
71#define CMPCI_REG_DMA1_MAX_SAMPLES CMPCI_REG_DMA1_BYTES
72#define CMPCI_REG_DMA1_INTR_SAMPLES CMPCI_REG_DMA1_SAMPLES
73
74/* Our indication of custom mixer control */
75#define CMPCI_NON_SB16_CONTROL 0xff
76
77/* Debugging macro's */
78#undef DEB
79#ifndef DEB
80#define DEB(x) /* x */
81#endif /* DEB */
82
83#ifndef DEBMIX
84#define DEBMIX(x) /* x */
85#endif /* DEBMIX */
86
87/* ------------------------------------------------------------------------- */
88/* Structures */
89
90struct sc_info;
91
92struct sc_chinfo {
93 struct sc_info *parent;
94 struct pcm_channel *channel;
95 struct snd_dbuf *buffer;
96 u_int32_t fmt, spd, phys_buf, bps;
97 u_int32_t dma_active:1, dma_was_active:1;
98 int dir;
99};
100
101struct sc_info {
102 device_t dev;
103
104 bus_space_tag_t st;
105 bus_space_handle_t sh;
106 bus_dma_tag_t parent_dmat;
107 struct resource *reg, *irq;
108 int regid, irqid;
109 void *ih;
110
111 struct sc_chinfo pch, rch;
112};
113
114/* Channel caps */
115
116static u_int32_t cmi_fmt[] = {
117 AFMT_U8,
118 AFMT_STEREO | AFMT_U8,
119 AFMT_S16_LE,
120 AFMT_STEREO | AFMT_S16_LE,
121 0
122};
123
124static struct pcmchan_caps cmi_caps = {5512, 48000, cmi_fmt, 0};
125
126/* ------------------------------------------------------------------------- */
127/* Register Utilities */
128
129static u_int32_t
130cmi_rd(struct sc_info *sc, int regno, int size)
131{
132 switch (size) {
133 case 1:
134 return bus_space_read_1(sc->st, sc->sh, regno);
135 case 2:
136 return bus_space_read_2(sc->st, sc->sh, regno);
137 case 4:
138 return bus_space_read_4(sc->st, sc->sh, regno);
139 default:
140 DEB(printf("cmi_rd: failed 0x%04x %d\n", regno, size));
141 return 0xFFFFFFFF;
142 }
143}
144
145static void
146cmi_wr(struct sc_info *sc, int regno, u_int32_t data, int size)
147{
148 switch (size) {
149 case 1:
150 bus_space_write_1(sc->st, sc->sh, regno, data);
151 break;
152 case 2:
153 bus_space_write_2(sc->st, sc->sh, regno, data);
154 break;
155 case 4:
156 bus_space_write_4(sc->st, sc->sh, regno, data);
157 break;
158 }
159}
160
161static void
162cmi_partial_wr4(struct sc_info *sc,
163 int reg, int shift, u_int32_t mask, u_int32_t val)
164{
165 u_int32_t r;
166
167 r = cmi_rd(sc, reg, 4);
168 r &= ~(mask << shift);
169 r |= val << shift;
170 cmi_wr(sc, reg, r, 4);
171}
172
173static void
174cmi_clr4(struct sc_info *sc, int reg, u_int32_t mask)
175{
176 u_int32_t r;
177
178 r = cmi_rd(sc, reg, 4);
179 r &= ~mask;
180 cmi_wr(sc, reg, r, 4);
181}
182
183static void
184cmi_set4(struct sc_info *sc, int reg, u_int32_t mask)
185{
186 u_int32_t r;
187
188 r = cmi_rd(sc, reg, 4);
189 r |= mask;
190 cmi_wr(sc, reg, r, 4);
191}
192
193/* ------------------------------------------------------------------------- */
194/* Rate Mapping */
195
196static int cmi_rates[] = {5512, 8000, 11025, 16000,
197 22050, 32000, 44100, 48000};
198#define NUM_CMI_RATES (sizeof(cmi_rates)/sizeof(cmi_rates[0]))
199
200/* cmpci_rate_to_regvalue returns sampling freq selector for FCR1
201 * register - reg order is 5k,11k,22k,44k,8k,16k,32k,48k */
202
203static u_int32_t
204cmpci_rate_to_regvalue(int rate)
205{
206 int i, r;
207
208 for(i = 0; i < NUM_CMI_RATES - 1; i++) {
209 if (rate < ((cmi_rates[i] + cmi_rates[i + 1]) / 2)) {
210 break;
211 }
212 }
213
214 DEB(printf("cmpci_rate_to_regvalue: %d -> %d\n", rate, cmi_rates[i]));
215
216 r = ((i >> 1) | (i << 2)) & 0x07;
217 return r;
218}
219
220static int
221cmpci_regvalue_to_rate(u_int32_t r)
222{
223 int i;
224
225 i = ((r << 1) | (r >> 2)) & 0x07;
226 DEB(printf("cmpci_regvalue_to_rate: %d -> %d\n", r, i));
227 return cmi_rates[i];
228}
229
230/* ------------------------------------------------------------------------- */
231/* ADC/DAC control - there are 2 dma channels on 8738, either can be
232 * playback or capture. We use ch0 for playback and ch1 for capture. */
233
234static void
235cmi_dma_prog(struct sc_info *sc, struct sc_chinfo *ch, u_int32_t base)
236{
237 u_int32_t s, i, sz, physbuf;
238
239 physbuf = vtophys(sndbuf_getbuf(ch->buffer));
240
241 cmi_wr(sc, base, physbuf, 4);
242 sz = (u_int32_t)sndbuf_getsize(ch->buffer);
243
244 s = sz / ch->bps - 1;
245 cmi_wr(sc, base + 4, s, 2);
246
247 i = sz / (ch->bps * CMI_INTR_PER_BUFFER) - 1;
248 cmi_wr(sc, base + 6, i, 2);
249}
250
251
252static void
253cmi_ch0_start(struct sc_info *sc, struct sc_chinfo *ch)
254{
255 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE);
256
257 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE);
258 cmi_set4(sc, CMPCI_REG_INTR_CTRL,
259 CMPCI_REG_CH0_INTR_ENABLE);
260
261 ch->dma_active = 1;
262}
263
264static u_int32_t
265cmi_ch0_stop(struct sc_info *sc, struct sc_chinfo *ch)
266{
267 u_int32_t r = ch->dma_active;
268
269 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE);
270 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE);
271 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET);
272 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET);
273 ch->dma_active = 0;
274 return r;
275}
276
277static void
278cmi_ch1_start(struct sc_info *sc, struct sc_chinfo *ch)
279{
280 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE);
281 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE);
282 /* Enable Interrupts */
283 cmi_set4(sc, CMPCI_REG_INTR_CTRL,
284 CMPCI_REG_CH1_INTR_ENABLE);
285 DEB(printf("cmi_ch1_start: dma prog\n"));
286 ch->dma_active = 1;
287}
288
289static u_int32_t
290cmi_ch1_stop(struct sc_info *sc, struct sc_chinfo *ch)
291{
292 u_int32_t r = ch->dma_active;
293
294 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE);
295 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE);
296 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET);
297 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET);
298 ch->dma_active = 0;
299 return r;
300}
301
302static void
303cmi_spdif_speed(struct sc_info *sc, int speed) {
304 u_int32_t fcr1, lcr, mcr;
305
306 if (speed >= 44100) {
307 fcr1 = CMPCI_REG_SPDIF0_ENABLE;
308 lcr = CMPCI_REG_XSPDIF_ENABLE;
309 mcr = (speed == 48000) ?
310 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K : 0;
311 } else {
312 fcr1 = mcr = lcr = 0;
313 }
314
315 cmi_partial_wr4(sc, CMPCI_REG_MISC, 0,
316 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K, mcr);
317 cmi_partial_wr4(sc, CMPCI_REG_FUNC_1, 0,
318 CMPCI_REG_SPDIF0_ENABLE, fcr1);
319 cmi_partial_wr4(sc, CMPCI_REG_LEGACY_CTRL, 0,
320 CMPCI_REG_XSPDIF_ENABLE, lcr);
321}
322
323/* ------------------------------------------------------------------------- */
324/* Channel Interface implementation */
325
326static void *
327cmichan_init(kobj_t obj, void *devinfo,
328 struct snd_dbuf *b, struct pcm_channel *c, int dir)
329{
330 struct sc_info *sc = devinfo;
331 struct sc_chinfo *ch = (dir == PCMDIR_PLAY) ? &sc->pch : &sc->rch;
332
333 ch->parent = sc;
334 ch->channel = c;
335 ch->bps = 1;
336 ch->fmt = AFMT_U8;
337 ch->spd = DSP_DEFAULT_SPEED;
338 ch->buffer = b;
339 ch->dma_active = 0;
340 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, CMI_BUFFER_SIZE) != 0) {
341 DEB(printf("cmichan_init failed\n"));
342 return NULL;
343 }
344
345 ch->dir = dir;
346 if (ch->dir == PCMDIR_PLAY) {
347 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE);
348 } else {
349 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE);
350 }
351
352 return ch;
353}
354
355static int
356cmichan_setformat(kobj_t obj, void *data, u_int32_t format)
357{
358 struct sc_chinfo *ch = data;
359 u_int32_t f;
360
361 if (format & AFMT_S16_LE) {
362 f = CMPCI_REG_FORMAT_16BIT;
363 ch->bps = 2;
364 } else {
365 f = CMPCI_REG_FORMAT_8BIT;
366 ch->bps = 1;
367 }
368
369 if (format & AFMT_STEREO) {
370 f |= CMPCI_REG_FORMAT_STEREO;
371 ch->bps *= 2;
372 } else {
373 f |= CMPCI_REG_FORMAT_MONO;
374 }
375
376 if (ch->dir == PCMDIR_PLAY) {
377 cmi_partial_wr4(ch->parent,
378 CMPCI_REG_CHANNEL_FORMAT,
379 CMPCI_REG_CH0_FORMAT_SHIFT,
380 CMPCI_REG_CH0_FORMAT_MASK,
381 f);
382 } else {
383 cmi_partial_wr4(ch->parent,
384 CMPCI_REG_CHANNEL_FORMAT,
385 CMPCI_REG_CH1_FORMAT_SHIFT,
386 CMPCI_REG_CH1_FORMAT_MASK,
387 f);
388 }
389 ch->fmt = format;
390
391 return 0;
392}
393
394static int
395cmichan_setspeed(kobj_t obj, void *data, u_int32_t speed)
396{
397 struct sc_chinfo *ch = data;
398 u_int32_t r, rsp;
399
400 r = cmpci_rate_to_regvalue(speed);
401 if (ch->dir == PCMDIR_PLAY) {
402 if (speed < 44100) /* disable if req before rate change */
403 cmi_spdif_speed(ch->parent, speed);
404 cmi_partial_wr4(ch->parent,
405 CMPCI_REG_FUNC_1,
406 CMPCI_REG_DAC_FS_SHIFT,
407 CMPCI_REG_DAC_FS_MASK,
408 r);
409 if (speed >= 44100) /* enable if req after rate change */
410 cmi_spdif_speed(ch->parent, speed);
411 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4);
412 rsp >>= CMPCI_REG_DAC_FS_SHIFT;
413 rsp &= CMPCI_REG_DAC_FS_MASK;
414 } else {
415 cmi_partial_wr4(ch->parent,
416 CMPCI_REG_FUNC_1,
417 CMPCI_REG_ADC_FS_SHIFT,
418 CMPCI_REG_ADC_FS_MASK,
419 r);
420 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4);
421 rsp >>= CMPCI_REG_ADC_FS_SHIFT;
422 rsp &= CMPCI_REG_ADC_FS_MASK;
423 }
424 ch->spd = cmpci_regvalue_to_rate(r);
425
426 DEB(printf("cmichan_setspeed (%s) %d -> %d (%d)\n",
427 (ch->dir == PCMDIR_PLAY) ? "play" : "rec",
428 speed, ch->spd, cmpci_regvalue_to_rate(rsp)));
429
430 return ch->spd;
431}
432
433static int
434cmichan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
435{
436 struct sc_chinfo *ch = data;
437
438 /* user has requested interrupts every blocksize bytes */
439 if (blocksize > CMI_BUFFER_SIZE / CMI_INTR_PER_BUFFER) {
440 blocksize = CMI_BUFFER_SIZE / CMI_INTR_PER_BUFFER;
441 }
442 sndbuf_resize(ch->buffer, CMI_INTR_PER_BUFFER, blocksize);
443
444 return sndbuf_getsize(ch->buffer);
445}
446
447static int
448cmichan_trigger(kobj_t obj, void *data, int go)
449{
450 struct sc_chinfo *ch = data;
451 struct sc_info *sc = ch->parent;
452
453 if (ch->dir == PCMDIR_PLAY) {
454 switch(go) {
455 case PCMTRIG_START:
456 cmi_ch0_start(sc, ch);
457 break;
458 case PCMTRIG_ABORT:
459 cmi_ch0_stop(sc, ch);
460 break;
461 }
462 } else {
463 switch(go) {
464 case PCMTRIG_START:
465 cmi_ch1_start(sc, ch);
466 break;
467 case PCMTRIG_ABORT:
468 cmi_ch1_stop(sc, ch);
469 break;
470 }
471 }
472 return 0;
473}
474
475static int
476cmichan_getptr(kobj_t obj, void *data)
477{
478 struct sc_chinfo *ch = data;
479 struct sc_info *sc = ch->parent;
480 u_int32_t physptr, bufptr, sz;
481
482 if (ch->dir == PCMDIR_PLAY) {
483 physptr = cmi_rd(sc, CMPCI_REG_DMA0_BASE, 4);
484 } else {
485 physptr = cmi_rd(sc, CMPCI_REG_DMA1_BASE, 4);
486 }
487
488 sz = sndbuf_getsize(ch->buffer);
489 bufptr = (physptr - ch->phys_buf + sz - ch->bps) % sz;
490
491 return bufptr;
492}
493
494static void
495cmi_intr(void *data)
496{
497 struct sc_info *sc = data;
498 u_int32_t intrstat;
499
500 intrstat = cmi_rd(sc, CMPCI_REG_INTR_STATUS, 4);
501 if ((intrstat & CMPCI_REG_ANY_INTR) == 0) {
502 return;
503 }
504
505 /* Disable interrupts */
506 if (intrstat & CMPCI_REG_CH0_INTR) {
507 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE);
508 }
509
510 if (intrstat & CMPCI_REG_CH1_INTR) {
511 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE);
512 }
513
514 /* Signal interrupts to channel */
515 if (intrstat & CMPCI_REG_CH0_INTR) {
516 chn_intr(sc->pch.channel);
517 }
518
519 if (intrstat & CMPCI_REG_CH1_INTR) {
520 chn_intr(sc->rch.channel);
521 }
522
523 /* Enable interrupts */
524 if (intrstat & CMPCI_REG_CH0_INTR) {
525 cmi_set4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE);
526 }
527
528 if (intrstat & CMPCI_REG_CH1_INTR) {
529 cmi_set4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE);
530 }
531
532 return;
533}
534
535static struct pcmchan_caps *
536cmichan_getcaps(kobj_t obj, void *data)
537{
538 return &cmi_caps;
539}
540
541static kobj_method_t cmichan_methods[] = {
542 KOBJMETHOD(channel_init, cmichan_init),
543 KOBJMETHOD(channel_setformat, cmichan_setformat),
544 KOBJMETHOD(channel_setspeed, cmichan_setspeed),
545 KOBJMETHOD(channel_setblocksize, cmichan_setblocksize),
546 KOBJMETHOD(channel_trigger, cmichan_trigger),
547 KOBJMETHOD(channel_getptr, cmichan_getptr),
548 KOBJMETHOD(channel_getcaps, cmichan_getcaps),
549 { 0, 0 }
550};
551CHANNEL_DECLARE(cmichan);
552
553/* ------------------------------------------------------------------------- */
554/* Mixer - sb16 with kinks */
555
556static void
557cmimix_wr(struct sc_info *sc, u_int8_t port, u_int8_t val)
558{
559 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1);
560 cmi_wr(sc, CMPCI_REG_SBDATA, val, 1);
561}
562
563static u_int8_t
564cmimix_rd(struct sc_info *sc, u_int8_t port)
565{
566 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1);
567 return (u_int8_t)cmi_rd(sc, CMPCI_REG_SBDATA, 1);
568}
569
570struct sb16props {
571 u_int8_t rreg; /* right reg chan register */
572 u_int8_t stereo:1; /* (no explanation needed, honest) */
573 u_int8_t rec:1; /* recording source */
574 u_int8_t bits:3; /* num bits to represent maximum gain rep */
575 u_int8_t oselect; /* output select mask */
576 u_int8_t iselect; /* right input select mask */
577} static const cmt[SOUND_MIXER_NRDEVICES] = {
578 [SOUND_MIXER_SYNTH] = {CMPCI_SB16_MIXER_FM_R, 1, 1, 5,
579 CMPCI_SB16_SW_FM, CMPCI_SB16_MIXER_FM_SRC_R},
580 [SOUND_MIXER_CD] = {CMPCI_SB16_MIXER_CDDA_R, 1, 1, 5,
581 CMPCI_SB16_SW_CD, CMPCI_SB16_MIXER_CD_SRC_R},
582 [SOUND_MIXER_LINE] = {CMPCI_SB16_MIXER_LINE_R, 1, 1, 5,
583 CMPCI_SB16_SW_LINE, CMPCI_SB16_MIXER_LINE_SRC_R},
584 [SOUND_MIXER_MIC] = {CMPCI_SB16_MIXER_MIC, 0, 1, 5,
585 CMPCI_SB16_SW_MIC, CMPCI_SB16_MIXER_MIC_SRC},
586 [SOUND_MIXER_SPEAKER] = {CMPCI_SB16_MIXER_SPEAKER, 0, 0, 2, 0, 0},
587 [SOUND_MIXER_PCM] = {CMPCI_SB16_MIXER_VOICE_R, 1, 0, 5, 0, 0},
588 [SOUND_MIXER_VOLUME] = {CMPCI_SB16_MIXER_MASTER_R, 1, 0, 5, 0, 0},
589 /* These controls are not implemented in CMI8738, but maybe at a
590 future date. They are not documented in C-Media documentation,
591 though appear in other drivers for future h/w (ALSA, Linux, NetBSD).
592 */
593 [SOUND_MIXER_IGAIN] = {CMPCI_SB16_MIXER_INGAIN_R, 1, 0, 2, 0, 0},
594 [SOUND_MIXER_OGAIN] = {CMPCI_SB16_MIXER_OUTGAIN_R, 1, 0, 2, 0, 0},
595 [SOUND_MIXER_BASS] = {CMPCI_SB16_MIXER_BASS_R, 1, 0, 4, 0, 0},
596 [SOUND_MIXER_TREBLE] = {CMPCI_SB16_MIXER_TREBLE_R, 1, 0, 4, 0, 0},
597 /* The mic pre-amp is implemented with non-SB16 compatible
598 registers. */
599 [SOUND_MIXER_MONITOR] = {CMPCI_NON_SB16_CONTROL, 0, 1, 4, 0},
600};
601
602#define MIXER_GAIN_REG_RTOL(r) (r - 1)
603
604static int
605cmimix_init(struct snd_mixer *m)
606{
607 struct sc_info *sc = mix_getdevinfo(m);
608 u_int32_t i,v;
609
610 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) {
611 if (cmt[i].bits) v |= 1 << i;
612 }
613 mix_setdevs(m, v);
614
615 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) {
616 if (cmt[i].rec) v |= 1 << i;
617 }
618 mix_setrecdevs(m, v);
619
620 cmimix_wr(sc, CMPCI_SB16_MIXER_RESET, 0);
621 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, 0);
622 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, 0);
623 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX,
624 CMPCI_SB16_SW_CD | CMPCI_SB16_SW_MIC | CMPCI_SB16_SW_LINE);
625 return 0;
626}
627
628static int
629cmimix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right)
630{
631 struct sc_info *sc = mix_getdevinfo(m);
632 u_int32_t r, l, max;
633 u_int8_t v;
634
635 max = (1 << cmt[dev].bits) - 1;
636
637 if (cmt[dev].rreg == CMPCI_NON_SB16_CONTROL) {
638 /* For time being this can only be one thing (mic in
639 * mic/aux reg) */
640 v = cmi_rd(sc, CMPCI_REG_AUX_MIC, 1) & 0xf0;
641 l = left * max / 100;
642 /* 3 bit gain with LSB MICGAIN off(1),on(1) -> 4 bit value */
643 v |= ((l << 1) | (~l >> 3)) & 0x0f;
644 cmi_wr(sc, CMPCI_REG_AUX_MIC, v, 1);
645 return 0;
646 }
647
648 l = (left * max / 100) << (8 - cmt[dev].bits);
649 if (cmt[dev].stereo) {
650 r = (right * max / 100) << (8 - cmt[dev].bits);
651 cmimix_wr(sc, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l);
652 cmimix_wr(sc, cmt[dev].rreg, r);
653 DEBMIX(printf("Mixer stereo write dev %d reg 0x%02x "\
654 "value 0x%02x:0x%02x\n",
655 dev, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l, r));
656 } else {
657 r = l;
658 cmimix_wr(sc, cmt[dev].rreg, l);
659 DEBMIX(printf("Mixer mono write dev %d reg 0x%02x " \
660 "value 0x%02x:0x%02x\n",
661 dev, cmt[dev].rreg, l, l));
662 }
663
664 /* Zero gain does not mute channel from output, but this does... */
665 v = cmimix_rd(sc, CMPCI_SB16_MIXER_OUTMIX);
666 if (l == 0 && r == 0) {
667 v &= ~cmt[dev].oselect;
668 } else {
669 v |= cmt[dev].oselect;
670 }
671 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX, v);
672
673 return 0;
674}
675
676static int
677cmimix_setrecsrc(struct snd_mixer *m, u_int32_t src)
678{
679 struct sc_info *sc = mix_getdevinfo(m);
680 u_int32_t i, ml, sl;
681
682 ml = sl = 0;
683 for(i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
684 if ((1<<i) & src) {
685 if (cmt[i].stereo) {
686 sl |= cmt[i].iselect;
687 } else {
688 ml |= cmt[i].iselect;
689 }
690 }
691 }
692 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, sl|ml);
693 DEBMIX(printf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n",
694 CMPCI_SB16_MIXER_ADCMIX_R, sl|ml));
695 ml = CMPCI_SB16_MIXER_SRC_R_TO_L(ml);
696 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, sl|ml);
697 DEBMIX(printf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n",
698 CMPCI_SB16_MIXER_ADCMIX_L, sl|ml));
699
700 return src;
701}
702
703static kobj_method_t cmi_mixer_methods[] = {
704 KOBJMETHOD(mixer_init, cmimix_init),
705 KOBJMETHOD(mixer_set, cmimix_set),
706 KOBJMETHOD(mixer_setrecsrc, cmimix_setrecsrc),
707 { 0, 0 }
708};
709MIXER_DECLARE(cmi_mixer);
710
711/* ------------------------------------------------------------------------- */
712/* Power and reset */
713
714static void
715cmi_power(struct sc_info *sc, int state)
716{
717 switch (state) {
718 case 0: /* full power */
719 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN);
720 break;
721 default:
722 /* power off */
723 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN);
724 break;
725 }
726}
727
728static int
729cmi_init(struct sc_info *sc)
730{
731 /* Effect reset */
732 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET);
733 DELAY(100);
734 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET);
735
736 /* Disable interrupts and channels */
737 cmi_clr4(sc, CMPCI_REG_FUNC_0,
738 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE);
739 cmi_clr4(sc, CMPCI_REG_INTR_CTRL,
740 CMPCI_REG_CH0_INTR_ENABLE | CMPCI_REG_CH1_INTR_ENABLE);
741
742 /* Configure DMA channels, ch0 = play, ch1 = capture */
743 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_DIR);
744 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_DIR);
745
746 /* Attempt to enable 4 Channel output */
747 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_N4SPK3D);
748
749 /* Disable SPDIF1 - not compatible with config */
750 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF1_ENABLE);
751 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF_LOOP);
752
753 return 0;
754}
755
756static void
757cmi_uninit(struct sc_info *sc)
758{
759 /* Disable interrupts and channels */
760 cmi_clr4(sc, CMPCI_REG_INTR_CTRL,
761 CMPCI_REG_CH0_INTR_ENABLE |
762 CMPCI_REG_CH1_INTR_ENABLE |
763 CMPCI_REG_TDMA_INTR_ENABLE);
764 cmi_clr4(sc, CMPCI_REG_FUNC_0,
765 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE);
766}
767
768/* ------------------------------------------------------------------------- */
769/* Bus and device registration */
770static int
771cmi_probe(device_t dev)
772{
773 switch(pci_get_devid(dev)) {
774 case CMI8338A_PCI_ID:
775 device_set_desc(dev, "CMedia CMI8338A");
776 return 0;
777 case CMI8338B_PCI_ID:
778 device_set_desc(dev, "CMedia CMI8338B");
779 return 0;
780 case CMI8738_PCI_ID:
781 device_set_desc(dev, "CMedia CMI8738");
782 return 0;
783 case CMI8738B_PCI_ID:
784 device_set_desc(dev, "CMedia CMI8738B");
785 return 0;
786 default:
787 return ENXIO;
788 }
789}
790
791static int
792cmi_attach(device_t dev)
793{
794 struct snddev_info *d;
795 struct sc_info *sc;
796 u_int32_t data;
797 char status[SND_STATUSLEN];
798
799 d = device_get_softc(dev);
800 sc = malloc(sizeof(struct sc_info), M_DEVBUF, M_NOWAIT | M_ZERO);
801 if (sc == NULL) {
802 device_printf(dev, "cannot allocate softc\n");
803 return ENXIO;
804 }
805
806 data = pci_read_config(dev, PCIR_COMMAND, 2);
807 data |= (PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN);
808 pci_write_config(dev, PCIR_COMMAND, data, 2);
809 data = pci_read_config(dev, PCIR_COMMAND, 2);
810
811 sc->regid = PCIR_MAPS;
812 sc->reg = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->regid,
813 0, BUS_SPACE_UNRESTRICTED, 1, RF_ACTIVE);
814 if (!sc->reg) {
815 device_printf(dev, "cmi_attach: Cannot allocate bus resource\n");
816 goto bad;
817 }
818 sc->st = rman_get_bustag(sc->reg);
819 sc->sh = rman_get_bushandle(sc->reg);
820
821 sc->irqid = 0;
822 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irqid,
823 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
824 if (!sc->irq ||
825 snd_setup_intr(dev, sc->irq, 0, cmi_intr, sc, &sc->ih)){
826 device_printf(dev, "cmi_attach: Unable to map interrupt\n");
827 goto bad;
828 }
829
830 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0,
831 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
832 /*highaddr*/BUS_SPACE_MAXADDR,
833 /*filter*/NULL, /*filterarg*/NULL,
834 /*maxsize*/CMI_BUFFER_SIZE, /*nsegments*/1,
835 /*maxsegz*/0x3ffff, /*flags*/0,
836 &sc->parent_dmat) != 0) {
837 device_printf(dev, "cmi_attach: Unable to create dma tag\n");
838 goto bad;
839 }
840
841 cmi_power(sc, 0);
842 if (cmi_init(sc))
843 goto bad;
844
845 if (mixer_init(dev, &cmi_mixer_class, sc))
846 goto bad;
847
848 if (pcm_register(dev, sc, 1, 1))
849 goto bad;
850
851 pcm_addchan(dev, PCMDIR_PLAY, &cmichan_class, sc);
852 pcm_addchan(dev, PCMDIR_REC, &cmichan_class, sc);
853
854 snprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld",
855 rman_get_start(sc->reg), rman_get_start(sc->irq));
856 pcm_setstatus(dev, status);
857
858 DEB(printf("cmi_attach: succeeded\n"));
859 return 0;
860
861 bad:
862 if (sc->parent_dmat)
863 bus_dma_tag_destroy(sc->parent_dmat);
864 if (sc->ih)
865 bus_teardown_intr(dev, sc->irq, sc->ih);
866 if (sc->irq)
867 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
868 if (sc->reg)
869 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg);
870 if (sc)
871 free(sc, M_DEVBUF);
872
873 return ENXIO;
874}
875
876static int
877cmi_detach(device_t dev)
878{
879 struct sc_info *sc;
880 int r;
881
882 r = pcm_unregister(dev);
883 if (r) return r;
884
885 sc = pcm_getdevinfo(dev);
886 cmi_uninit(sc);
887 cmi_power(sc, 3);
888
889 bus_dma_tag_destroy(sc->parent_dmat);
890 bus_teardown_intr(dev, sc->irq, sc->ih);
891 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
892 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg);
893 free(sc, M_DEVBUF);
894
895 return 0;
896}
897
898static int
899cmi_suspend(device_t dev)
900{
901 struct sc_info *sc = pcm_getdevinfo(dev);
902
903 sc->pch.dma_was_active = cmi_ch0_stop(sc, &sc->pch);
904 sc->rch.dma_was_active = cmi_ch1_stop(sc, &sc->rch);
905 cmi_power(sc, 3);
906 return 0;
907}
908
909static int
910cmi_resume(device_t dev)
911{
912 struct sc_info *sc = pcm_getdevinfo(dev);
913
914 cmi_power(sc, 0);
915 if (cmi_init(sc) != 0) {
916 device_printf(dev, "unable to reinitialize the card\n");
917 return ENXIO;
918 }
919
920 if (mixer_reinit(dev) == -1) {
921 device_printf(dev, "unable to reinitialize the mixer\n");
922 return ENXIO;
923 }
924
925 if (sc->pch.dma_was_active) {
926 cmichan_setspeed(NULL, &sc->pch, sc->pch.spd);
927 cmichan_setformat(NULL, &sc->pch, sc->pch.fmt);
928 cmi_ch0_start(sc, &sc->pch);
929 }
930
931 if (sc->rch.dma_was_active) {
932 cmichan_setspeed(NULL, &sc->rch, sc->rch.spd);
933 cmichan_setformat(NULL, &sc->rch, sc->rch.fmt);
934 cmi_ch1_start(sc, &sc->rch);
935 }
936 return 0;
937}
938
939static device_method_t cmi_methods[] = {
940 DEVMETHOD(device_probe, cmi_probe),
941 DEVMETHOD(device_attach, cmi_attach),
942 DEVMETHOD(device_detach, cmi_detach),
943 DEVMETHOD(device_resume, cmi_resume),
944 DEVMETHOD(device_suspend, cmi_suspend),
945 { 0, 0 }
946};
947
948static driver_t cmi_driver = {
949 "pcm",
950 cmi_methods,
951 PCM_SOFTC_SIZE
952};
953
954DRIVER_MODULE(snd_cmipci, pci, cmi_driver, pcm_devclass, 0, 0);
955MODULE_DEPEND(snd_cmipci, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER);
956MODULE_VERSION(snd_cmipci, 1);
2 * Copyright (c) 2000 Orion Hodson <O.Hodson@cs.ucl.ac.uk>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * This driver exists largely as a result of other people's efforts.
27 * Much of register handling is based on NetBSD CMI8x38 audio driver
28 * by Takuya Shiozaki <AoiMoe@imou.to>. Chen-Li Tien
29 * <cltien@cmedia.com.tw> clarified points regarding the DMA related
30 * registers and the 8738 mixer devices. His Linux was driver a also
31 * useful reference point.
32 *
33 * TODO: MIDI
34 *
35 * SPDIF contributed by Gerhard Gonter <gonter@whisky.wu-wien.ac.at>.
36 *
37 * This card/code does not always manage to sample at 44100 - actual
38 * rate drifts slightly between recordings (usually 0-3%). No
39 * differences visible in register dumps between times that work and
40 * those that don't.
41 */
42
43#include <dev/sound/pcm/sound.h>
44#include <dev/sound/pci/cmireg.h>
45#include <dev/sound/isa/sb.h>
46
47#include <pci/pcireg.h>
48#include <pci/pcivar.h>
49
50#include <sys/sysctl.h>
51
52#include "mixer_if.h"
53
54SND_DECLARE_FILE("$FreeBSD: head/sys/dev/sound/pci/cmi.c 82180 2001-08-23 11:30:52Z cg $");
55
56/* Supported chip ID's */
57#define CMI8338A_PCI_ID 0x010013f6
58#define CMI8338B_PCI_ID 0x010113f6
59#define CMI8738_PCI_ID 0x011113f6
60#define CMI8738B_PCI_ID 0x011213f6
61
62/* Buffer size max is 64k for permitted DMA boundaries */
63#define CMI_BUFFER_SIZE 16384
64
65/* Interrupts per length of buffer */
66#define CMI_INTR_PER_BUFFER 2
67
68/* Clarify meaning of named defines in cmireg.h */
69#define CMPCI_REG_DMA0_MAX_SAMPLES CMPCI_REG_DMA0_BYTES
70#define CMPCI_REG_DMA0_INTR_SAMPLES CMPCI_REG_DMA0_SAMPLES
71#define CMPCI_REG_DMA1_MAX_SAMPLES CMPCI_REG_DMA1_BYTES
72#define CMPCI_REG_DMA1_INTR_SAMPLES CMPCI_REG_DMA1_SAMPLES
73
74/* Our indication of custom mixer control */
75#define CMPCI_NON_SB16_CONTROL 0xff
76
77/* Debugging macro's */
78#undef DEB
79#ifndef DEB
80#define DEB(x) /* x */
81#endif /* DEB */
82
83#ifndef DEBMIX
84#define DEBMIX(x) /* x */
85#endif /* DEBMIX */
86
87/* ------------------------------------------------------------------------- */
88/* Structures */
89
90struct sc_info;
91
92struct sc_chinfo {
93 struct sc_info *parent;
94 struct pcm_channel *channel;
95 struct snd_dbuf *buffer;
96 u_int32_t fmt, spd, phys_buf, bps;
97 u_int32_t dma_active:1, dma_was_active:1;
98 int dir;
99};
100
101struct sc_info {
102 device_t dev;
103
104 bus_space_tag_t st;
105 bus_space_handle_t sh;
106 bus_dma_tag_t parent_dmat;
107 struct resource *reg, *irq;
108 int regid, irqid;
109 void *ih;
110
111 struct sc_chinfo pch, rch;
112};
113
114/* Channel caps */
115
116static u_int32_t cmi_fmt[] = {
117 AFMT_U8,
118 AFMT_STEREO | AFMT_U8,
119 AFMT_S16_LE,
120 AFMT_STEREO | AFMT_S16_LE,
121 0
122};
123
124static struct pcmchan_caps cmi_caps = {5512, 48000, cmi_fmt, 0};
125
126/* ------------------------------------------------------------------------- */
127/* Register Utilities */
128
129static u_int32_t
130cmi_rd(struct sc_info *sc, int regno, int size)
131{
132 switch (size) {
133 case 1:
134 return bus_space_read_1(sc->st, sc->sh, regno);
135 case 2:
136 return bus_space_read_2(sc->st, sc->sh, regno);
137 case 4:
138 return bus_space_read_4(sc->st, sc->sh, regno);
139 default:
140 DEB(printf("cmi_rd: failed 0x%04x %d\n", regno, size));
141 return 0xFFFFFFFF;
142 }
143}
144
145static void
146cmi_wr(struct sc_info *sc, int regno, u_int32_t data, int size)
147{
148 switch (size) {
149 case 1:
150 bus_space_write_1(sc->st, sc->sh, regno, data);
151 break;
152 case 2:
153 bus_space_write_2(sc->st, sc->sh, regno, data);
154 break;
155 case 4:
156 bus_space_write_4(sc->st, sc->sh, regno, data);
157 break;
158 }
159}
160
161static void
162cmi_partial_wr4(struct sc_info *sc,
163 int reg, int shift, u_int32_t mask, u_int32_t val)
164{
165 u_int32_t r;
166
167 r = cmi_rd(sc, reg, 4);
168 r &= ~(mask << shift);
169 r |= val << shift;
170 cmi_wr(sc, reg, r, 4);
171}
172
173static void
174cmi_clr4(struct sc_info *sc, int reg, u_int32_t mask)
175{
176 u_int32_t r;
177
178 r = cmi_rd(sc, reg, 4);
179 r &= ~mask;
180 cmi_wr(sc, reg, r, 4);
181}
182
183static void
184cmi_set4(struct sc_info *sc, int reg, u_int32_t mask)
185{
186 u_int32_t r;
187
188 r = cmi_rd(sc, reg, 4);
189 r |= mask;
190 cmi_wr(sc, reg, r, 4);
191}
192
193/* ------------------------------------------------------------------------- */
194/* Rate Mapping */
195
196static int cmi_rates[] = {5512, 8000, 11025, 16000,
197 22050, 32000, 44100, 48000};
198#define NUM_CMI_RATES (sizeof(cmi_rates)/sizeof(cmi_rates[0]))
199
200/* cmpci_rate_to_regvalue returns sampling freq selector for FCR1
201 * register - reg order is 5k,11k,22k,44k,8k,16k,32k,48k */
202
203static u_int32_t
204cmpci_rate_to_regvalue(int rate)
205{
206 int i, r;
207
208 for(i = 0; i < NUM_CMI_RATES - 1; i++) {
209 if (rate < ((cmi_rates[i] + cmi_rates[i + 1]) / 2)) {
210 break;
211 }
212 }
213
214 DEB(printf("cmpci_rate_to_regvalue: %d -> %d\n", rate, cmi_rates[i]));
215
216 r = ((i >> 1) | (i << 2)) & 0x07;
217 return r;
218}
219
220static int
221cmpci_regvalue_to_rate(u_int32_t r)
222{
223 int i;
224
225 i = ((r << 1) | (r >> 2)) & 0x07;
226 DEB(printf("cmpci_regvalue_to_rate: %d -> %d\n", r, i));
227 return cmi_rates[i];
228}
229
230/* ------------------------------------------------------------------------- */
231/* ADC/DAC control - there are 2 dma channels on 8738, either can be
232 * playback or capture. We use ch0 for playback and ch1 for capture. */
233
234static void
235cmi_dma_prog(struct sc_info *sc, struct sc_chinfo *ch, u_int32_t base)
236{
237 u_int32_t s, i, sz, physbuf;
238
239 physbuf = vtophys(sndbuf_getbuf(ch->buffer));
240
241 cmi_wr(sc, base, physbuf, 4);
242 sz = (u_int32_t)sndbuf_getsize(ch->buffer);
243
244 s = sz / ch->bps - 1;
245 cmi_wr(sc, base + 4, s, 2);
246
247 i = sz / (ch->bps * CMI_INTR_PER_BUFFER) - 1;
248 cmi_wr(sc, base + 6, i, 2);
249}
250
251
252static void
253cmi_ch0_start(struct sc_info *sc, struct sc_chinfo *ch)
254{
255 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE);
256
257 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE);
258 cmi_set4(sc, CMPCI_REG_INTR_CTRL,
259 CMPCI_REG_CH0_INTR_ENABLE);
260
261 ch->dma_active = 1;
262}
263
264static u_int32_t
265cmi_ch0_stop(struct sc_info *sc, struct sc_chinfo *ch)
266{
267 u_int32_t r = ch->dma_active;
268
269 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE);
270 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_ENABLE);
271 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET);
272 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_RESET);
273 ch->dma_active = 0;
274 return r;
275}
276
277static void
278cmi_ch1_start(struct sc_info *sc, struct sc_chinfo *ch)
279{
280 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE);
281 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE);
282 /* Enable Interrupts */
283 cmi_set4(sc, CMPCI_REG_INTR_CTRL,
284 CMPCI_REG_CH1_INTR_ENABLE);
285 DEB(printf("cmi_ch1_start: dma prog\n"));
286 ch->dma_active = 1;
287}
288
289static u_int32_t
290cmi_ch1_stop(struct sc_info *sc, struct sc_chinfo *ch)
291{
292 u_int32_t r = ch->dma_active;
293
294 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE);
295 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_ENABLE);
296 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET);
297 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_RESET);
298 ch->dma_active = 0;
299 return r;
300}
301
302static void
303cmi_spdif_speed(struct sc_info *sc, int speed) {
304 u_int32_t fcr1, lcr, mcr;
305
306 if (speed >= 44100) {
307 fcr1 = CMPCI_REG_SPDIF0_ENABLE;
308 lcr = CMPCI_REG_XSPDIF_ENABLE;
309 mcr = (speed == 48000) ?
310 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K : 0;
311 } else {
312 fcr1 = mcr = lcr = 0;
313 }
314
315 cmi_partial_wr4(sc, CMPCI_REG_MISC, 0,
316 CMPCI_REG_W_SPDIF_48L | CMPCI_REG_SPDIF_48K, mcr);
317 cmi_partial_wr4(sc, CMPCI_REG_FUNC_1, 0,
318 CMPCI_REG_SPDIF0_ENABLE, fcr1);
319 cmi_partial_wr4(sc, CMPCI_REG_LEGACY_CTRL, 0,
320 CMPCI_REG_XSPDIF_ENABLE, lcr);
321}
322
323/* ------------------------------------------------------------------------- */
324/* Channel Interface implementation */
325
326static void *
327cmichan_init(kobj_t obj, void *devinfo,
328 struct snd_dbuf *b, struct pcm_channel *c, int dir)
329{
330 struct sc_info *sc = devinfo;
331 struct sc_chinfo *ch = (dir == PCMDIR_PLAY) ? &sc->pch : &sc->rch;
332
333 ch->parent = sc;
334 ch->channel = c;
335 ch->bps = 1;
336 ch->fmt = AFMT_U8;
337 ch->spd = DSP_DEFAULT_SPEED;
338 ch->buffer = b;
339 ch->dma_active = 0;
340 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, CMI_BUFFER_SIZE) != 0) {
341 DEB(printf("cmichan_init failed\n"));
342 return NULL;
343 }
344
345 ch->dir = dir;
346 if (ch->dir == PCMDIR_PLAY) {
347 cmi_dma_prog(sc, ch, CMPCI_REG_DMA0_BASE);
348 } else {
349 cmi_dma_prog(sc, ch, CMPCI_REG_DMA1_BASE);
350 }
351
352 return ch;
353}
354
355static int
356cmichan_setformat(kobj_t obj, void *data, u_int32_t format)
357{
358 struct sc_chinfo *ch = data;
359 u_int32_t f;
360
361 if (format & AFMT_S16_LE) {
362 f = CMPCI_REG_FORMAT_16BIT;
363 ch->bps = 2;
364 } else {
365 f = CMPCI_REG_FORMAT_8BIT;
366 ch->bps = 1;
367 }
368
369 if (format & AFMT_STEREO) {
370 f |= CMPCI_REG_FORMAT_STEREO;
371 ch->bps *= 2;
372 } else {
373 f |= CMPCI_REG_FORMAT_MONO;
374 }
375
376 if (ch->dir == PCMDIR_PLAY) {
377 cmi_partial_wr4(ch->parent,
378 CMPCI_REG_CHANNEL_FORMAT,
379 CMPCI_REG_CH0_FORMAT_SHIFT,
380 CMPCI_REG_CH0_FORMAT_MASK,
381 f);
382 } else {
383 cmi_partial_wr4(ch->parent,
384 CMPCI_REG_CHANNEL_FORMAT,
385 CMPCI_REG_CH1_FORMAT_SHIFT,
386 CMPCI_REG_CH1_FORMAT_MASK,
387 f);
388 }
389 ch->fmt = format;
390
391 return 0;
392}
393
394static int
395cmichan_setspeed(kobj_t obj, void *data, u_int32_t speed)
396{
397 struct sc_chinfo *ch = data;
398 u_int32_t r, rsp;
399
400 r = cmpci_rate_to_regvalue(speed);
401 if (ch->dir == PCMDIR_PLAY) {
402 if (speed < 44100) /* disable if req before rate change */
403 cmi_spdif_speed(ch->parent, speed);
404 cmi_partial_wr4(ch->parent,
405 CMPCI_REG_FUNC_1,
406 CMPCI_REG_DAC_FS_SHIFT,
407 CMPCI_REG_DAC_FS_MASK,
408 r);
409 if (speed >= 44100) /* enable if req after rate change */
410 cmi_spdif_speed(ch->parent, speed);
411 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4);
412 rsp >>= CMPCI_REG_DAC_FS_SHIFT;
413 rsp &= CMPCI_REG_DAC_FS_MASK;
414 } else {
415 cmi_partial_wr4(ch->parent,
416 CMPCI_REG_FUNC_1,
417 CMPCI_REG_ADC_FS_SHIFT,
418 CMPCI_REG_ADC_FS_MASK,
419 r);
420 rsp = cmi_rd(ch->parent, CMPCI_REG_FUNC_1, 4);
421 rsp >>= CMPCI_REG_ADC_FS_SHIFT;
422 rsp &= CMPCI_REG_ADC_FS_MASK;
423 }
424 ch->spd = cmpci_regvalue_to_rate(r);
425
426 DEB(printf("cmichan_setspeed (%s) %d -> %d (%d)\n",
427 (ch->dir == PCMDIR_PLAY) ? "play" : "rec",
428 speed, ch->spd, cmpci_regvalue_to_rate(rsp)));
429
430 return ch->spd;
431}
432
433static int
434cmichan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
435{
436 struct sc_chinfo *ch = data;
437
438 /* user has requested interrupts every blocksize bytes */
439 if (blocksize > CMI_BUFFER_SIZE / CMI_INTR_PER_BUFFER) {
440 blocksize = CMI_BUFFER_SIZE / CMI_INTR_PER_BUFFER;
441 }
442 sndbuf_resize(ch->buffer, CMI_INTR_PER_BUFFER, blocksize);
443
444 return sndbuf_getsize(ch->buffer);
445}
446
447static int
448cmichan_trigger(kobj_t obj, void *data, int go)
449{
450 struct sc_chinfo *ch = data;
451 struct sc_info *sc = ch->parent;
452
453 if (ch->dir == PCMDIR_PLAY) {
454 switch(go) {
455 case PCMTRIG_START:
456 cmi_ch0_start(sc, ch);
457 break;
458 case PCMTRIG_ABORT:
459 cmi_ch0_stop(sc, ch);
460 break;
461 }
462 } else {
463 switch(go) {
464 case PCMTRIG_START:
465 cmi_ch1_start(sc, ch);
466 break;
467 case PCMTRIG_ABORT:
468 cmi_ch1_stop(sc, ch);
469 break;
470 }
471 }
472 return 0;
473}
474
475static int
476cmichan_getptr(kobj_t obj, void *data)
477{
478 struct sc_chinfo *ch = data;
479 struct sc_info *sc = ch->parent;
480 u_int32_t physptr, bufptr, sz;
481
482 if (ch->dir == PCMDIR_PLAY) {
483 physptr = cmi_rd(sc, CMPCI_REG_DMA0_BASE, 4);
484 } else {
485 physptr = cmi_rd(sc, CMPCI_REG_DMA1_BASE, 4);
486 }
487
488 sz = sndbuf_getsize(ch->buffer);
489 bufptr = (physptr - ch->phys_buf + sz - ch->bps) % sz;
490
491 return bufptr;
492}
493
494static void
495cmi_intr(void *data)
496{
497 struct sc_info *sc = data;
498 u_int32_t intrstat;
499
500 intrstat = cmi_rd(sc, CMPCI_REG_INTR_STATUS, 4);
501 if ((intrstat & CMPCI_REG_ANY_INTR) == 0) {
502 return;
503 }
504
505 /* Disable interrupts */
506 if (intrstat & CMPCI_REG_CH0_INTR) {
507 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE);
508 }
509
510 if (intrstat & CMPCI_REG_CH1_INTR) {
511 cmi_clr4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE);
512 }
513
514 /* Signal interrupts to channel */
515 if (intrstat & CMPCI_REG_CH0_INTR) {
516 chn_intr(sc->pch.channel);
517 }
518
519 if (intrstat & CMPCI_REG_CH1_INTR) {
520 chn_intr(sc->rch.channel);
521 }
522
523 /* Enable interrupts */
524 if (intrstat & CMPCI_REG_CH0_INTR) {
525 cmi_set4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH0_INTR_ENABLE);
526 }
527
528 if (intrstat & CMPCI_REG_CH1_INTR) {
529 cmi_set4(sc, CMPCI_REG_INTR_CTRL, CMPCI_REG_CH1_INTR_ENABLE);
530 }
531
532 return;
533}
534
535static struct pcmchan_caps *
536cmichan_getcaps(kobj_t obj, void *data)
537{
538 return &cmi_caps;
539}
540
541static kobj_method_t cmichan_methods[] = {
542 KOBJMETHOD(channel_init, cmichan_init),
543 KOBJMETHOD(channel_setformat, cmichan_setformat),
544 KOBJMETHOD(channel_setspeed, cmichan_setspeed),
545 KOBJMETHOD(channel_setblocksize, cmichan_setblocksize),
546 KOBJMETHOD(channel_trigger, cmichan_trigger),
547 KOBJMETHOD(channel_getptr, cmichan_getptr),
548 KOBJMETHOD(channel_getcaps, cmichan_getcaps),
549 { 0, 0 }
550};
551CHANNEL_DECLARE(cmichan);
552
553/* ------------------------------------------------------------------------- */
554/* Mixer - sb16 with kinks */
555
556static void
557cmimix_wr(struct sc_info *sc, u_int8_t port, u_int8_t val)
558{
559 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1);
560 cmi_wr(sc, CMPCI_REG_SBDATA, val, 1);
561}
562
563static u_int8_t
564cmimix_rd(struct sc_info *sc, u_int8_t port)
565{
566 cmi_wr(sc, CMPCI_REG_SBADDR, port, 1);
567 return (u_int8_t)cmi_rd(sc, CMPCI_REG_SBDATA, 1);
568}
569
570struct sb16props {
571 u_int8_t rreg; /* right reg chan register */
572 u_int8_t stereo:1; /* (no explanation needed, honest) */
573 u_int8_t rec:1; /* recording source */
574 u_int8_t bits:3; /* num bits to represent maximum gain rep */
575 u_int8_t oselect; /* output select mask */
576 u_int8_t iselect; /* right input select mask */
577} static const cmt[SOUND_MIXER_NRDEVICES] = {
578 [SOUND_MIXER_SYNTH] = {CMPCI_SB16_MIXER_FM_R, 1, 1, 5,
579 CMPCI_SB16_SW_FM, CMPCI_SB16_MIXER_FM_SRC_R},
580 [SOUND_MIXER_CD] = {CMPCI_SB16_MIXER_CDDA_R, 1, 1, 5,
581 CMPCI_SB16_SW_CD, CMPCI_SB16_MIXER_CD_SRC_R},
582 [SOUND_MIXER_LINE] = {CMPCI_SB16_MIXER_LINE_R, 1, 1, 5,
583 CMPCI_SB16_SW_LINE, CMPCI_SB16_MIXER_LINE_SRC_R},
584 [SOUND_MIXER_MIC] = {CMPCI_SB16_MIXER_MIC, 0, 1, 5,
585 CMPCI_SB16_SW_MIC, CMPCI_SB16_MIXER_MIC_SRC},
586 [SOUND_MIXER_SPEAKER] = {CMPCI_SB16_MIXER_SPEAKER, 0, 0, 2, 0, 0},
587 [SOUND_MIXER_PCM] = {CMPCI_SB16_MIXER_VOICE_R, 1, 0, 5, 0, 0},
588 [SOUND_MIXER_VOLUME] = {CMPCI_SB16_MIXER_MASTER_R, 1, 0, 5, 0, 0},
589 /* These controls are not implemented in CMI8738, but maybe at a
590 future date. They are not documented in C-Media documentation,
591 though appear in other drivers for future h/w (ALSA, Linux, NetBSD).
592 */
593 [SOUND_MIXER_IGAIN] = {CMPCI_SB16_MIXER_INGAIN_R, 1, 0, 2, 0, 0},
594 [SOUND_MIXER_OGAIN] = {CMPCI_SB16_MIXER_OUTGAIN_R, 1, 0, 2, 0, 0},
595 [SOUND_MIXER_BASS] = {CMPCI_SB16_MIXER_BASS_R, 1, 0, 4, 0, 0},
596 [SOUND_MIXER_TREBLE] = {CMPCI_SB16_MIXER_TREBLE_R, 1, 0, 4, 0, 0},
597 /* The mic pre-amp is implemented with non-SB16 compatible
598 registers. */
599 [SOUND_MIXER_MONITOR] = {CMPCI_NON_SB16_CONTROL, 0, 1, 4, 0},
600};
601
602#define MIXER_GAIN_REG_RTOL(r) (r - 1)
603
604static int
605cmimix_init(struct snd_mixer *m)
606{
607 struct sc_info *sc = mix_getdevinfo(m);
608 u_int32_t i,v;
609
610 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) {
611 if (cmt[i].bits) v |= 1 << i;
612 }
613 mix_setdevs(m, v);
614
615 for(i = v = 0; i < SOUND_MIXER_NRDEVICES; i++) {
616 if (cmt[i].rec) v |= 1 << i;
617 }
618 mix_setrecdevs(m, v);
619
620 cmimix_wr(sc, CMPCI_SB16_MIXER_RESET, 0);
621 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, 0);
622 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, 0);
623 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX,
624 CMPCI_SB16_SW_CD | CMPCI_SB16_SW_MIC | CMPCI_SB16_SW_LINE);
625 return 0;
626}
627
628static int
629cmimix_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned right)
630{
631 struct sc_info *sc = mix_getdevinfo(m);
632 u_int32_t r, l, max;
633 u_int8_t v;
634
635 max = (1 << cmt[dev].bits) - 1;
636
637 if (cmt[dev].rreg == CMPCI_NON_SB16_CONTROL) {
638 /* For time being this can only be one thing (mic in
639 * mic/aux reg) */
640 v = cmi_rd(sc, CMPCI_REG_AUX_MIC, 1) & 0xf0;
641 l = left * max / 100;
642 /* 3 bit gain with LSB MICGAIN off(1),on(1) -> 4 bit value */
643 v |= ((l << 1) | (~l >> 3)) & 0x0f;
644 cmi_wr(sc, CMPCI_REG_AUX_MIC, v, 1);
645 return 0;
646 }
647
648 l = (left * max / 100) << (8 - cmt[dev].bits);
649 if (cmt[dev].stereo) {
650 r = (right * max / 100) << (8 - cmt[dev].bits);
651 cmimix_wr(sc, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l);
652 cmimix_wr(sc, cmt[dev].rreg, r);
653 DEBMIX(printf("Mixer stereo write dev %d reg 0x%02x "\
654 "value 0x%02x:0x%02x\n",
655 dev, MIXER_GAIN_REG_RTOL(cmt[dev].rreg), l, r));
656 } else {
657 r = l;
658 cmimix_wr(sc, cmt[dev].rreg, l);
659 DEBMIX(printf("Mixer mono write dev %d reg 0x%02x " \
660 "value 0x%02x:0x%02x\n",
661 dev, cmt[dev].rreg, l, l));
662 }
663
664 /* Zero gain does not mute channel from output, but this does... */
665 v = cmimix_rd(sc, CMPCI_SB16_MIXER_OUTMIX);
666 if (l == 0 && r == 0) {
667 v &= ~cmt[dev].oselect;
668 } else {
669 v |= cmt[dev].oselect;
670 }
671 cmimix_wr(sc, CMPCI_SB16_MIXER_OUTMIX, v);
672
673 return 0;
674}
675
676static int
677cmimix_setrecsrc(struct snd_mixer *m, u_int32_t src)
678{
679 struct sc_info *sc = mix_getdevinfo(m);
680 u_int32_t i, ml, sl;
681
682 ml = sl = 0;
683 for(i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
684 if ((1<<i) & src) {
685 if (cmt[i].stereo) {
686 sl |= cmt[i].iselect;
687 } else {
688 ml |= cmt[i].iselect;
689 }
690 }
691 }
692 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_R, sl|ml);
693 DEBMIX(printf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n",
694 CMPCI_SB16_MIXER_ADCMIX_R, sl|ml));
695 ml = CMPCI_SB16_MIXER_SRC_R_TO_L(ml);
696 cmimix_wr(sc, CMPCI_SB16_MIXER_ADCMIX_L, sl|ml);
697 DEBMIX(printf("cmimix_setrecsrc: reg 0x%02x val 0x%02x\n",
698 CMPCI_SB16_MIXER_ADCMIX_L, sl|ml));
699
700 return src;
701}
702
703static kobj_method_t cmi_mixer_methods[] = {
704 KOBJMETHOD(mixer_init, cmimix_init),
705 KOBJMETHOD(mixer_set, cmimix_set),
706 KOBJMETHOD(mixer_setrecsrc, cmimix_setrecsrc),
707 { 0, 0 }
708};
709MIXER_DECLARE(cmi_mixer);
710
711/* ------------------------------------------------------------------------- */
712/* Power and reset */
713
714static void
715cmi_power(struct sc_info *sc, int state)
716{
717 switch (state) {
718 case 0: /* full power */
719 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN);
720 break;
721 default:
722 /* power off */
723 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_POWER_DOWN);
724 break;
725 }
726}
727
728static int
729cmi_init(struct sc_info *sc)
730{
731 /* Effect reset */
732 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET);
733 DELAY(100);
734 cmi_clr4(sc, CMPCI_REG_MISC, CMPCI_REG_BUS_AND_DSP_RESET);
735
736 /* Disable interrupts and channels */
737 cmi_clr4(sc, CMPCI_REG_FUNC_0,
738 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE);
739 cmi_clr4(sc, CMPCI_REG_INTR_CTRL,
740 CMPCI_REG_CH0_INTR_ENABLE | CMPCI_REG_CH1_INTR_ENABLE);
741
742 /* Configure DMA channels, ch0 = play, ch1 = capture */
743 cmi_clr4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH0_DIR);
744 cmi_set4(sc, CMPCI_REG_FUNC_0, CMPCI_REG_CH1_DIR);
745
746 /* Attempt to enable 4 Channel output */
747 cmi_set4(sc, CMPCI_REG_MISC, CMPCI_REG_N4SPK3D);
748
749 /* Disable SPDIF1 - not compatible with config */
750 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF1_ENABLE);
751 cmi_clr4(sc, CMPCI_REG_FUNC_1, CMPCI_REG_SPDIF_LOOP);
752
753 return 0;
754}
755
756static void
757cmi_uninit(struct sc_info *sc)
758{
759 /* Disable interrupts and channels */
760 cmi_clr4(sc, CMPCI_REG_INTR_CTRL,
761 CMPCI_REG_CH0_INTR_ENABLE |
762 CMPCI_REG_CH1_INTR_ENABLE |
763 CMPCI_REG_TDMA_INTR_ENABLE);
764 cmi_clr4(sc, CMPCI_REG_FUNC_0,
765 CMPCI_REG_CH0_ENABLE | CMPCI_REG_CH1_ENABLE);
766}
767
768/* ------------------------------------------------------------------------- */
769/* Bus and device registration */
770static int
771cmi_probe(device_t dev)
772{
773 switch(pci_get_devid(dev)) {
774 case CMI8338A_PCI_ID:
775 device_set_desc(dev, "CMedia CMI8338A");
776 return 0;
777 case CMI8338B_PCI_ID:
778 device_set_desc(dev, "CMedia CMI8338B");
779 return 0;
780 case CMI8738_PCI_ID:
781 device_set_desc(dev, "CMedia CMI8738");
782 return 0;
783 case CMI8738B_PCI_ID:
784 device_set_desc(dev, "CMedia CMI8738B");
785 return 0;
786 default:
787 return ENXIO;
788 }
789}
790
791static int
792cmi_attach(device_t dev)
793{
794 struct snddev_info *d;
795 struct sc_info *sc;
796 u_int32_t data;
797 char status[SND_STATUSLEN];
798
799 d = device_get_softc(dev);
800 sc = malloc(sizeof(struct sc_info), M_DEVBUF, M_NOWAIT | M_ZERO);
801 if (sc == NULL) {
802 device_printf(dev, "cannot allocate softc\n");
803 return ENXIO;
804 }
805
806 data = pci_read_config(dev, PCIR_COMMAND, 2);
807 data |= (PCIM_CMD_PORTEN|PCIM_CMD_BUSMASTEREN);
808 pci_write_config(dev, PCIR_COMMAND, data, 2);
809 data = pci_read_config(dev, PCIR_COMMAND, 2);
810
811 sc->regid = PCIR_MAPS;
812 sc->reg = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->regid,
813 0, BUS_SPACE_UNRESTRICTED, 1, RF_ACTIVE);
814 if (!sc->reg) {
815 device_printf(dev, "cmi_attach: Cannot allocate bus resource\n");
816 goto bad;
817 }
818 sc->st = rman_get_bustag(sc->reg);
819 sc->sh = rman_get_bushandle(sc->reg);
820
821 sc->irqid = 0;
822 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irqid,
823 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
824 if (!sc->irq ||
825 snd_setup_intr(dev, sc->irq, 0, cmi_intr, sc, &sc->ih)){
826 device_printf(dev, "cmi_attach: Unable to map interrupt\n");
827 goto bad;
828 }
829
830 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0,
831 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
832 /*highaddr*/BUS_SPACE_MAXADDR,
833 /*filter*/NULL, /*filterarg*/NULL,
834 /*maxsize*/CMI_BUFFER_SIZE, /*nsegments*/1,
835 /*maxsegz*/0x3ffff, /*flags*/0,
836 &sc->parent_dmat) != 0) {
837 device_printf(dev, "cmi_attach: Unable to create dma tag\n");
838 goto bad;
839 }
840
841 cmi_power(sc, 0);
842 if (cmi_init(sc))
843 goto bad;
844
845 if (mixer_init(dev, &cmi_mixer_class, sc))
846 goto bad;
847
848 if (pcm_register(dev, sc, 1, 1))
849 goto bad;
850
851 pcm_addchan(dev, PCMDIR_PLAY, &cmichan_class, sc);
852 pcm_addchan(dev, PCMDIR_REC, &cmichan_class, sc);
853
854 snprintf(status, SND_STATUSLEN, "at io 0x%lx irq %ld",
855 rman_get_start(sc->reg), rman_get_start(sc->irq));
856 pcm_setstatus(dev, status);
857
858 DEB(printf("cmi_attach: succeeded\n"));
859 return 0;
860
861 bad:
862 if (sc->parent_dmat)
863 bus_dma_tag_destroy(sc->parent_dmat);
864 if (sc->ih)
865 bus_teardown_intr(dev, sc->irq, sc->ih);
866 if (sc->irq)
867 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
868 if (sc->reg)
869 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg);
870 if (sc)
871 free(sc, M_DEVBUF);
872
873 return ENXIO;
874}
875
876static int
877cmi_detach(device_t dev)
878{
879 struct sc_info *sc;
880 int r;
881
882 r = pcm_unregister(dev);
883 if (r) return r;
884
885 sc = pcm_getdevinfo(dev);
886 cmi_uninit(sc);
887 cmi_power(sc, 3);
888
889 bus_dma_tag_destroy(sc->parent_dmat);
890 bus_teardown_intr(dev, sc->irq, sc->ih);
891 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
892 bus_release_resource(dev, SYS_RES_IOPORT, sc->regid, sc->reg);
893 free(sc, M_DEVBUF);
894
895 return 0;
896}
897
898static int
899cmi_suspend(device_t dev)
900{
901 struct sc_info *sc = pcm_getdevinfo(dev);
902
903 sc->pch.dma_was_active = cmi_ch0_stop(sc, &sc->pch);
904 sc->rch.dma_was_active = cmi_ch1_stop(sc, &sc->rch);
905 cmi_power(sc, 3);
906 return 0;
907}
908
909static int
910cmi_resume(device_t dev)
911{
912 struct sc_info *sc = pcm_getdevinfo(dev);
913
914 cmi_power(sc, 0);
915 if (cmi_init(sc) != 0) {
916 device_printf(dev, "unable to reinitialize the card\n");
917 return ENXIO;
918 }
919
920 if (mixer_reinit(dev) == -1) {
921 device_printf(dev, "unable to reinitialize the mixer\n");
922 return ENXIO;
923 }
924
925 if (sc->pch.dma_was_active) {
926 cmichan_setspeed(NULL, &sc->pch, sc->pch.spd);
927 cmichan_setformat(NULL, &sc->pch, sc->pch.fmt);
928 cmi_ch0_start(sc, &sc->pch);
929 }
930
931 if (sc->rch.dma_was_active) {
932 cmichan_setspeed(NULL, &sc->rch, sc->rch.spd);
933 cmichan_setformat(NULL, &sc->rch, sc->rch.fmt);
934 cmi_ch1_start(sc, &sc->rch);
935 }
936 return 0;
937}
938
939static device_method_t cmi_methods[] = {
940 DEVMETHOD(device_probe, cmi_probe),
941 DEVMETHOD(device_attach, cmi_attach),
942 DEVMETHOD(device_detach, cmi_detach),
943 DEVMETHOD(device_resume, cmi_resume),
944 DEVMETHOD(device_suspend, cmi_suspend),
945 { 0, 0 }
946};
947
948static driver_t cmi_driver = {
949 "pcm",
950 cmi_methods,
951 PCM_SOFTC_SIZE
952};
953
954DRIVER_MODULE(snd_cmipci, pci, cmi_driver, pcm_devclass, 0, 0);
955MODULE_DEPEND(snd_cmipci, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER);
956MODULE_VERSION(snd_cmipci, 1);