1/* $FreeBSD: head/sys/dev/ral/rt2661.c 190526 2009-03-29 17:59:14Z sam $ */
2
3/*-
4 * Copyright (c) 2006
5 * Damien Bergamini <damien.bergamini@free.fr>
6 *
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20#include <sys/cdefs.h>
21__FBSDID("$FreeBSD: head/sys/dev/ral/rt2661.c 190526 2009-03-29 17:59:14Z sam $");
22
23/*-
24 * Ralink Technology RT2561, RT2561S and RT2661 chipset driver
25 * http://www.ralinktech.com/
26 */
27
28#include <sys/param.h>
29#include <sys/sysctl.h>
30#include <sys/sockio.h>
31#include <sys/mbuf.h>
32#include <sys/kernel.h>
33#include <sys/socket.h>
34#include <sys/systm.h>
35#include <sys/malloc.h>
36#include <sys/lock.h>
37#include <sys/mutex.h>
38#include <sys/module.h>
39#include <sys/bus.h>
40#include <sys/endian.h>
41#include <sys/firmware.h>
42
43#include <machine/bus.h>
44#include <machine/resource.h>
45#include <sys/rman.h>
46
47#include <net/bpf.h>
48#include <net/if.h>
49#include <net/if_arp.h>
50#include <net/ethernet.h>
51#include <net/if_dl.h>
52#include <net/if_media.h>
53#include <net/if_types.h>
54
55#include <net80211/ieee80211_var.h>
56#include <net80211/ieee80211_phy.h>
57#include <net80211/ieee80211_radiotap.h>
58#include <net80211/ieee80211_regdomain.h>
59#include <net80211/ieee80211_amrr.h>
60
61#include <netinet/in.h>
62#include <netinet/in_systm.h>
63#include <netinet/in_var.h>
64#include <netinet/ip.h>
65#include <netinet/if_ether.h>
66
67#include <dev/ral/rt2661reg.h>
68#include <dev/ral/rt2661var.h>
69
70#define RAL_DEBUG
71#ifdef RAL_DEBUG
72#define DPRINTF(sc, fmt, ...) do { \
73 if (sc->sc_debug > 0) \
74 printf(fmt, __VA_ARGS__); \
75} while (0)
76#define DPRINTFN(sc, n, fmt, ...) do { \
77 if (sc->sc_debug >= (n)) \
78 printf(fmt, __VA_ARGS__); \
79} while (0)
80#else
81#define DPRINTF(sc, fmt, ...)
82#define DPRINTFN(sc, n, fmt, ...)
83#endif
84
85static struct ieee80211vap *rt2661_vap_create(struct ieee80211com *,
86 const char name[IFNAMSIZ], int unit, int opmode,
87 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN],
88 const uint8_t mac[IEEE80211_ADDR_LEN]);
89static void rt2661_vap_delete(struct ieee80211vap *);
90static void rt2661_dma_map_addr(void *, bus_dma_segment_t *, int,
91 int);
92static int rt2661_alloc_tx_ring(struct rt2661_softc *,
93 struct rt2661_tx_ring *, int);
94static void rt2661_reset_tx_ring(struct rt2661_softc *,
95 struct rt2661_tx_ring *);
96static void rt2661_free_tx_ring(struct rt2661_softc *,
97 struct rt2661_tx_ring *);
98static int rt2661_alloc_rx_ring(struct rt2661_softc *,
99 struct rt2661_rx_ring *, int);
100static void rt2661_reset_rx_ring(struct rt2661_softc *,
101 struct rt2661_rx_ring *);
102static void rt2661_free_rx_ring(struct rt2661_softc *,
103 struct rt2661_rx_ring *);
104static struct ieee80211_node *rt2661_node_alloc(struct ieee80211vap *,
105 const uint8_t [IEEE80211_ADDR_LEN]);
106static void rt2661_newassoc(struct ieee80211_node *, int);
107static int rt2661_newstate(struct ieee80211vap *,
108 enum ieee80211_state, int);
109static uint16_t rt2661_eeprom_read(struct rt2661_softc *, uint8_t);
110static void rt2661_rx_intr(struct rt2661_softc *);
111static void rt2661_tx_intr(struct rt2661_softc *);
112static void rt2661_tx_dma_intr(struct rt2661_softc *,
113 struct rt2661_tx_ring *);
114static void rt2661_mcu_beacon_expire(struct rt2661_softc *);
115static void rt2661_mcu_wakeup(struct rt2661_softc *);
116static void rt2661_mcu_cmd_intr(struct rt2661_softc *);
117static void rt2661_scan_start(struct ieee80211com *);
118static void rt2661_scan_end(struct ieee80211com *);
119static void rt2661_set_channel(struct ieee80211com *);
120static void rt2661_setup_tx_desc(struct rt2661_softc *,
121 struct rt2661_tx_desc *, uint32_t, uint16_t, int,
122 int, const bus_dma_segment_t *, int, int);
123static int rt2661_tx_data(struct rt2661_softc *, struct mbuf *,
124 struct ieee80211_node *, int);
125static int rt2661_tx_mgt(struct rt2661_softc *, struct mbuf *,
126 struct ieee80211_node *);
127static void rt2661_start_locked(struct ifnet *);
128static void rt2661_start(struct ifnet *);
129static int rt2661_raw_xmit(struct ieee80211_node *, struct mbuf *,
130 const struct ieee80211_bpf_params *);
131static void rt2661_watchdog(void *);
132static int rt2661_ioctl(struct ifnet *, u_long, caddr_t);
133static void rt2661_bbp_write(struct rt2661_softc *, uint8_t,
134 uint8_t);
135static uint8_t rt2661_bbp_read(struct rt2661_softc *, uint8_t);
136static void rt2661_rf_write(struct rt2661_softc *, uint8_t,
137 uint32_t);
138static int rt2661_tx_cmd(struct rt2661_softc *, uint8_t,
139 uint16_t);
140static void rt2661_select_antenna(struct rt2661_softc *);
141static void rt2661_enable_mrr(struct rt2661_softc *);
142static void rt2661_set_txpreamble(struct rt2661_softc *);
143static void rt2661_set_basicrates(struct rt2661_softc *,
144 const struct ieee80211_rateset *);
145static void rt2661_select_band(struct rt2661_softc *,
146 struct ieee80211_channel *);
147static void rt2661_set_chan(struct rt2661_softc *,
148 struct ieee80211_channel *);
149static void rt2661_set_bssid(struct rt2661_softc *,
150 const uint8_t *);
151static void rt2661_set_macaddr(struct rt2661_softc *,
152 const uint8_t *);
153static void rt2661_update_promisc(struct ifnet *);
154static int rt2661_wme_update(struct ieee80211com *) __unused;
155static void rt2661_update_slot(struct ifnet *);
156static const char *rt2661_get_rf(int);
157static void rt2661_read_eeprom(struct rt2661_softc *,
158 uint8_t macaddr[IEEE80211_ADDR_LEN]);
159static int rt2661_bbp_init(struct rt2661_softc *);
160static void rt2661_init_locked(struct rt2661_softc *);
161static void rt2661_init(void *);
162static void rt2661_stop_locked(struct rt2661_softc *);
163static void rt2661_stop(void *);
164static int rt2661_load_microcode(struct rt2661_softc *);
165#ifdef notyet
166static void rt2661_rx_tune(struct rt2661_softc *);
167static void rt2661_radar_start(struct rt2661_softc *);
168static int rt2661_radar_stop(struct rt2661_softc *);
169#endif
170static int rt2661_prepare_beacon(struct rt2661_softc *,
171 struct ieee80211vap *);
172static void rt2661_enable_tsf_sync(struct rt2661_softc *);
173static int rt2661_get_rssi(struct rt2661_softc *, uint8_t);
174
175static const struct {
176 uint32_t reg;
177 uint32_t val;
178} rt2661_def_mac[] = {
179 RT2661_DEF_MAC
180};
181
182static const struct {
183 uint8_t reg;
184 uint8_t val;
185} rt2661_def_bbp[] = {
186 RT2661_DEF_BBP
187};
188
189static const struct rfprog {
190 uint8_t chan;
191 uint32_t r1, r2, r3, r4;
192} rt2661_rf5225_1[] = {
193 RT2661_RF5225_1
194}, rt2661_rf5225_2[] = {
195 RT2661_RF5225_2
196};
197
198int
199rt2661_attach(device_t dev, int id)
200{
201 struct rt2661_softc *sc = device_get_softc(dev);
202 struct ieee80211com *ic;
203 struct ifnet *ifp;
204 uint32_t val;
205 int error, ac, ntries;
206 uint8_t bands;
207 uint8_t macaddr[IEEE80211_ADDR_LEN];
208
209 sc->sc_id = id;
210 sc->sc_dev = dev;
211
212 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211);
213 if (ifp == NULL) {
214 device_printf(sc->sc_dev, "can not if_alloc()\n");
215 return ENOMEM;
216 }
217 ic = ifp->if_l2com;
218
219 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
220 MTX_DEF | MTX_RECURSE);
221
222 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0);
223
224 /* wait for NIC to initialize */
225 for (ntries = 0; ntries < 1000; ntries++) {
226 if ((val = RAL_READ(sc, RT2661_MAC_CSR0)) != 0)
227 break;
228 DELAY(1000);
229 }
230 if (ntries == 1000) {
231 device_printf(sc->sc_dev,
232 "timeout waiting for NIC to initialize\n");
233 error = EIO;
234 goto fail1;
235 }
236
237 /* retrieve RF rev. no and various other things from EEPROM */
238 rt2661_read_eeprom(sc, macaddr);
239
240 device_printf(dev, "MAC/BBP RT%X, RF %s\n", val,
241 rt2661_get_rf(sc->rf_rev));
242
243 /*
244 * Allocate Tx and Rx rings.
245 */
246 for (ac = 0; ac < 4; ac++) {
247 error = rt2661_alloc_tx_ring(sc, &sc->txq[ac],
248 RT2661_TX_RING_COUNT);
249 if (error != 0) {
250 device_printf(sc->sc_dev,
251 "could not allocate Tx ring %d\n", ac);
252 goto fail2;
253 }
254 }
255
256 error = rt2661_alloc_tx_ring(sc, &sc->mgtq, RT2661_MGT_RING_COUNT);
257 if (error != 0) {
258 device_printf(sc->sc_dev, "could not allocate Mgt ring\n");
259 goto fail2;
260 }
261
262 error = rt2661_alloc_rx_ring(sc, &sc->rxq, RT2661_RX_RING_COUNT);
263 if (error != 0) {
264 device_printf(sc->sc_dev, "could not allocate Rx ring\n");
265 goto fail3;
266 }
267
268 ifp->if_softc = sc;
269 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
270 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
271 ifp->if_init = rt2661_init;
272 ifp->if_ioctl = rt2661_ioctl;
273 ifp->if_start = rt2661_start;
274 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
275 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
276 IFQ_SET_READY(&ifp->if_snd);
277
278 ic->ic_ifp = ifp;
279 ic->ic_opmode = IEEE80211_M_STA;
280 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
281
282 /* set device capabilities */
283 ic->ic_caps =
284 IEEE80211_C_STA /* station mode */
285 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */
286 | IEEE80211_C_HOSTAP /* hostap mode */
287 | IEEE80211_C_MONITOR /* monitor mode */
288 | IEEE80211_C_AHDEMO /* adhoc demo mode */
289 | IEEE80211_C_WDS /* 4-address traffic works */
290 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
291 | IEEE80211_C_SHSLOT /* short slot time supported */
292 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */
293 | IEEE80211_C_BGSCAN /* capable of bg scanning */
294#ifdef notyet
295 | IEEE80211_C_TXFRAG /* handle tx frags */
296 | IEEE80211_C_WME /* 802.11e */
297#endif
298 ;
299
300 bands = 0;
301 setbit(&bands, IEEE80211_MODE_11B);
302 setbit(&bands, IEEE80211_MODE_11G);
303 if (sc->rf_rev == RT2661_RF_5225 || sc->rf_rev == RT2661_RF_5325)
304 setbit(&bands, IEEE80211_MODE_11A);
305 ieee80211_init_channels(ic, NULL, &bands);
306
307 ieee80211_ifattach(ic, macaddr);
308 ic->ic_newassoc = rt2661_newassoc;
309 ic->ic_node_alloc = rt2661_node_alloc;
310#if 0
311 ic->ic_wme.wme_update = rt2661_wme_update;
312#endif
313 ic->ic_scan_start = rt2661_scan_start;
314 ic->ic_scan_end = rt2661_scan_end;
315 ic->ic_set_channel = rt2661_set_channel;
316 ic->ic_updateslot = rt2661_update_slot;
317 ic->ic_update_promisc = rt2661_update_promisc;
318 ic->ic_raw_xmit = rt2661_raw_xmit;
319
320 ic->ic_vap_create = rt2661_vap_create;
321 ic->ic_vap_delete = rt2661_vap_delete;
322
323 sc->sc_rates = ieee80211_get_ratetable(ic->ic_curchan);
324
325 bpfattach(ifp, DLT_IEEE802_11_RADIO,
326 sizeof (struct ieee80211_frame) + sizeof (sc->sc_txtap));
327
328 sc->sc_rxtap_len = sizeof sc->sc_rxtap;
329 sc->sc_rxtap.wr_ihdr.it_len = htole16(sc->sc_rxtap_len);
330 sc->sc_rxtap.wr_ihdr.it_present = htole32(RT2661_RX_RADIOTAP_PRESENT);
331
332 sc->sc_txtap_len = sizeof sc->sc_txtap;
333 sc->sc_txtap.wt_ihdr.it_len = htole16(sc->sc_txtap_len);
334 sc->sc_txtap.wt_ihdr.it_present = htole32(RT2661_TX_RADIOTAP_PRESENT);
335
336#ifdef RAL_DEBUG
337 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
338 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
339 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "debug msgs");
340#endif
341 if (bootverbose)
342 ieee80211_announce(ic);
343
344 return 0;
345
346fail3: rt2661_free_tx_ring(sc, &sc->mgtq);
347fail2: while (--ac >= 0)
348 rt2661_free_tx_ring(sc, &sc->txq[ac]);
349fail1: mtx_destroy(&sc->sc_mtx);
350 if_free(ifp);
351 return error;
352}
353
354int
355rt2661_detach(void *xsc)
356{
357 struct rt2661_softc *sc = xsc;
358 struct ifnet *ifp = sc->sc_ifp;
359 struct ieee80211com *ic = ifp->if_l2com;
360
361 RAL_LOCK(sc);
362 rt2661_stop_locked(sc);
363 RAL_UNLOCK(sc);
364
365 bpfdetach(ifp);
366 ieee80211_ifdetach(ic);
367
368 rt2661_free_tx_ring(sc, &sc->txq[0]);
369 rt2661_free_tx_ring(sc, &sc->txq[1]);
370 rt2661_free_tx_ring(sc, &sc->txq[2]);
371 rt2661_free_tx_ring(sc, &sc->txq[3]);
372 rt2661_free_tx_ring(sc, &sc->mgtq);
373 rt2661_free_rx_ring(sc, &sc->rxq);
374
375 if_free(ifp);
376
377 mtx_destroy(&sc->sc_mtx);
378
379 return 0;
380}
381
382static struct ieee80211vap *
383rt2661_vap_create(struct ieee80211com *ic,
384 const char name[IFNAMSIZ], int unit, int opmode, int flags,
385 const uint8_t bssid[IEEE80211_ADDR_LEN],
386 const uint8_t mac[IEEE80211_ADDR_LEN])
387{
388 struct ifnet *ifp = ic->ic_ifp;
389 struct rt2661_vap *rvp;
390 struct ieee80211vap *vap;
391
392 switch (opmode) {
393 case IEEE80211_M_STA:
394 case IEEE80211_M_IBSS:
395 case IEEE80211_M_AHDEMO:
396 case IEEE80211_M_MONITOR:
397 case IEEE80211_M_HOSTAP:
398 if (!TAILQ_EMPTY(&ic->ic_vaps)) {
399 if_printf(ifp, "only 1 vap supported\n");
400 return NULL;
401 }
402 if (opmode == IEEE80211_M_STA)
403 flags |= IEEE80211_CLONE_NOBEACONS;
404 break;
405 case IEEE80211_M_WDS:
406 if (TAILQ_EMPTY(&ic->ic_vaps) ||
407 ic->ic_opmode != IEEE80211_M_HOSTAP) {
408 if_printf(ifp, "wds only supported in ap mode\n");
409 return NULL;
410 }
411 /*
412 * Silently remove any request for a unique
413 * bssid; WDS vap's always share the local
414 * mac address.
415 */
416 flags &= ~IEEE80211_CLONE_BSSID;
417 break;
418 default:
419 if_printf(ifp, "unknown opmode %d\n", opmode);
420 return NULL;
421 }
422 rvp = (struct rt2661_vap *) malloc(sizeof(struct rt2661_vap),
423 M_80211_VAP, M_NOWAIT | M_ZERO);
424 if (rvp == NULL)
425 return NULL;
426 vap = &rvp->ral_vap;
427 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid, mac);
428
429 /* override state transition machine */
430 rvp->ral_newstate = vap->iv_newstate;
431 vap->iv_newstate = rt2661_newstate;
432#if 0
433 vap->iv_update_beacon = rt2661_beacon_update;
434#endif
435
436 ieee80211_amrr_init(&rvp->amrr, vap,
437 IEEE80211_AMRR_MIN_SUCCESS_THRESHOLD,
438 IEEE80211_AMRR_MAX_SUCCESS_THRESHOLD,
439 500 /* ms */);
440
441 /* complete setup */
442 ieee80211_vap_attach(vap, ieee80211_media_change, ieee80211_media_status);
443 if (TAILQ_FIRST(&ic->ic_vaps) == vap)
444 ic->ic_opmode = opmode;
445 return vap;
446}
447
448static void
449rt2661_vap_delete(struct ieee80211vap *vap)
450{
451 struct rt2661_vap *rvp = RT2661_VAP(vap);
452
453 ieee80211_amrr_cleanup(&rvp->amrr);
454 ieee80211_vap_detach(vap);
455 free(rvp, M_80211_VAP);
456}
457
458void
459rt2661_shutdown(void *xsc)
460{
461 struct rt2661_softc *sc = xsc;
462
463 rt2661_stop(sc);
464}
465
466void
467rt2661_suspend(void *xsc)
468{
469 struct rt2661_softc *sc = xsc;
470
471 rt2661_stop(sc);
472}
473
474void
475rt2661_resume(void *xsc)
476{
477 struct rt2661_softc *sc = xsc;
478 struct ifnet *ifp = sc->sc_ifp;
479
480 if (ifp->if_flags & IFF_UP)
481 rt2661_init(sc);
482}
483
484static void
485rt2661_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
486{
487 if (error != 0)
488 return;
489
490 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
491
492 *(bus_addr_t *)arg = segs[0].ds_addr;
493}
494
495static int
496rt2661_alloc_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring,
497 int count)
498{
499 int i, error;
500
501 ring->count = count;
502 ring->queued = 0;
503 ring->cur = ring->next = ring->stat = 0;
504
505 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 4, 0,
506 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
507 count * RT2661_TX_DESC_SIZE, 1, count * RT2661_TX_DESC_SIZE,
508 0, NULL, NULL, &ring->desc_dmat);
509 if (error != 0) {
510 device_printf(sc->sc_dev, "could not create desc DMA tag\n");
511 goto fail;
512 }
513
514 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc,
515 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map);
516 if (error != 0) {
517 device_printf(sc->sc_dev, "could not allocate DMA memory\n");
518 goto fail;
519 }
520
521 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc,
522 count * RT2661_TX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr,
523 0);
524 if (error != 0) {
525 device_printf(sc->sc_dev, "could not load desc DMA map\n");
526 goto fail;
527 }
528
529 ring->data = malloc(count * sizeof (struct rt2661_tx_data), M_DEVBUF,
530 M_NOWAIT | M_ZERO);
531 if (ring->data == NULL) {
532 device_printf(sc->sc_dev, "could not allocate soft data\n");
533 error = ENOMEM;
534 goto fail;
535 }
536
537 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
538 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
539 RT2661_MAX_SCATTER, MCLBYTES, 0, NULL, NULL, &ring->data_dmat);
540 if (error != 0) {
541 device_printf(sc->sc_dev, "could not create data DMA tag\n");
542 goto fail;
543 }
544
545 for (i = 0; i < count; i++) {
546 error = bus_dmamap_create(ring->data_dmat, 0,
547 &ring->data[i].map);
548 if (error != 0) {
549 device_printf(sc->sc_dev, "could not create DMA map\n");
550 goto fail;
551 }
552 }
553
554 return 0;
555
556fail: rt2661_free_tx_ring(sc, ring);
557 return error;
558}
559
560static void
561rt2661_reset_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring)
562{
563 struct rt2661_tx_desc *desc;
564 struct rt2661_tx_data *data;
565 int i;
566
567 for (i = 0; i < ring->count; i++) {
568 desc = &ring->desc[i];
569 data = &ring->data[i];
570
571 if (data->m != NULL) {
572 bus_dmamap_sync(ring->data_dmat, data->map,
573 BUS_DMASYNC_POSTWRITE);
574 bus_dmamap_unload(ring->data_dmat, data->map);
575 m_freem(data->m);
576 data->m = NULL;
577 }
578
579 if (data->ni != NULL) {
580 ieee80211_free_node(data->ni);
581 data->ni = NULL;
582 }
583
584 desc->flags = 0;
585 }
586
587 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
588
589 ring->queued = 0;
590 ring->cur = ring->next = ring->stat = 0;
591}
592
593static void
594rt2661_free_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring)
595{
596 struct rt2661_tx_data *data;
597 int i;
598
599 if (ring->desc != NULL) {
600 bus_dmamap_sync(ring->desc_dmat, ring->desc_map,
601 BUS_DMASYNC_POSTWRITE);
602 bus_dmamap_unload(ring->desc_dmat, ring->desc_map);
603 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map);
604 }
605
606 if (ring->desc_dmat != NULL)
607 bus_dma_tag_destroy(ring->desc_dmat);
608
609 if (ring->data != NULL) {
610 for (i = 0; i < ring->count; i++) {
611 data = &ring->data[i];
612
613 if (data->m != NULL) {
614 bus_dmamap_sync(ring->data_dmat, data->map,
615 BUS_DMASYNC_POSTWRITE);
616 bus_dmamap_unload(ring->data_dmat, data->map);
617 m_freem(data->m);
618 }
619
620 if (data->ni != NULL)
621 ieee80211_free_node(data->ni);
622
623 if (data->map != NULL)
624 bus_dmamap_destroy(ring->data_dmat, data->map);
625 }
626
627 free(ring->data, M_DEVBUF);
628 }
629
630 if (ring->data_dmat != NULL)
631 bus_dma_tag_destroy(ring->data_dmat);
632}
633
634static int
635rt2661_alloc_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring,
636 int count)
637{
638 struct rt2661_rx_desc *desc;
639 struct rt2661_rx_data *data;
640 bus_addr_t physaddr;
641 int i, error;
642
643 ring->count = count;
644 ring->cur = ring->next = 0;
645
646 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 4, 0,
647 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
648 count * RT2661_RX_DESC_SIZE, 1, count * RT2661_RX_DESC_SIZE,
649 0, NULL, NULL, &ring->desc_dmat);
650 if (error != 0) {
651 device_printf(sc->sc_dev, "could not create desc DMA tag\n");
652 goto fail;
653 }
654
655 error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc,
656 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map);
657 if (error != 0) {
658 device_printf(sc->sc_dev, "could not allocate DMA memory\n");
659 goto fail;
660 }
661
662 error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc,
663 count * RT2661_RX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr,
664 0);
665 if (error != 0) {
666 device_printf(sc->sc_dev, "could not load desc DMA map\n");
667 goto fail;
668 }
669
670 ring->data = malloc(count * sizeof (struct rt2661_rx_data), M_DEVBUF,
671 M_NOWAIT | M_ZERO);
672 if (ring->data == NULL) {
673 device_printf(sc->sc_dev, "could not allocate soft data\n");
674 error = ENOMEM;
675 goto fail;
676 }
677
678 /*
679 * Pre-allocate Rx buffers and populate Rx ring.
680 */
681 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
682 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
683 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat);
684 if (error != 0) {
685 device_printf(sc->sc_dev, "could not create data DMA tag\n");
686 goto fail;
687 }
688
689 for (i = 0; i < count; i++) {
690 desc = &sc->rxq.desc[i];
691 data = &sc->rxq.data[i];
692
693 error = bus_dmamap_create(ring->data_dmat, 0, &data->map);
694 if (error != 0) {
695 device_printf(sc->sc_dev, "could not create DMA map\n");
696 goto fail;
697 }
698
699 data->m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
700 if (data->m == NULL) {
701 device_printf(sc->sc_dev,
702 "could not allocate rx mbuf\n");
703 error = ENOMEM;
704 goto fail;
705 }
706
707 error = bus_dmamap_load(ring->data_dmat, data->map,
708 mtod(data->m, void *), MCLBYTES, rt2661_dma_map_addr,
709 &physaddr, 0);
710 if (error != 0) {
711 device_printf(sc->sc_dev,
712 "could not load rx buf DMA map");
713 goto fail;
714 }
715
716 desc->flags = htole32(RT2661_RX_BUSY);
717 desc->physaddr = htole32(physaddr);
718 }
719
720 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
721
722 return 0;
723
724fail: rt2661_free_rx_ring(sc, ring);
725 return error;
726}
727
728static void
729rt2661_reset_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring)
730{
731 int i;
732
733 for (i = 0; i < ring->count; i++)
734 ring->desc[i].flags = htole32(RT2661_RX_BUSY);
735
736 bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE);
737
738 ring->cur = ring->next = 0;
739}
740
741static void
742rt2661_free_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring)
743{
744 struct rt2661_rx_data *data;
745 int i;
746
747 if (ring->desc != NULL) {
748 bus_dmamap_sync(ring->desc_dmat, ring->desc_map,
749 BUS_DMASYNC_POSTWRITE);
750 bus_dmamap_unload(ring->desc_dmat, ring->desc_map);
751 bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map);
752 }
753
754 if (ring->desc_dmat != NULL)
755 bus_dma_tag_destroy(ring->desc_dmat);
756
757 if (ring->data != NULL) {
758 for (i = 0; i < ring->count; i++) {
759 data = &ring->data[i];
760
761 if (data->m != NULL) {
762 bus_dmamap_sync(ring->data_dmat, data->map,
763 BUS_DMASYNC_POSTREAD);
764 bus_dmamap_unload(ring->data_dmat, data->map);
765 m_freem(data->m);
766 }
767
768 if (data->map != NULL)
769 bus_dmamap_destroy(ring->data_dmat, data->map);
770 }
771
772 free(ring->data, M_DEVBUF);
773 }
774
775 if (ring->data_dmat != NULL)
776 bus_dma_tag_destroy(ring->data_dmat);
777}
778
779static struct ieee80211_node *
780rt2661_node_alloc(struct ieee80211vap *vap,
781 const uint8_t mac[IEEE80211_ADDR_LEN])
782{
783 struct rt2661_node *rn;
784
785 rn = malloc(sizeof (struct rt2661_node), M_80211_NODE,
786 M_NOWAIT | M_ZERO);
787
788 return (rn != NULL) ? &rn->ni : NULL;
789}
790
791static void
792rt2661_newassoc(struct ieee80211_node *ni, int isnew)
793{
794 struct ieee80211vap *vap = ni->ni_vap;
795
796 ieee80211_amrr_node_init(&RT2661_VAP(vap)->amrr,
797 &RT2661_NODE(ni)->amrr, ni);
798}
799
800static int
801rt2661_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
802{
803 struct rt2661_vap *rvp = RT2661_VAP(vap);
804 struct ieee80211com *ic = vap->iv_ic;
805 struct rt2661_softc *sc = ic->ic_ifp->if_softc;
806 int error;
807
808 if (nstate == IEEE80211_S_INIT && vap->iv_state == IEEE80211_S_RUN) {
809 uint32_t tmp;
810
811 /* abort TSF synchronization */
812 tmp = RAL_READ(sc, RT2661_TXRX_CSR9);
813 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff);
814 }
815
816 error = rvp->ral_newstate(vap, nstate, arg);
817
818 if (error == 0 && nstate == IEEE80211_S_RUN) {
819 struct ieee80211_node *ni = vap->iv_bss;
820
821 if (vap->iv_opmode != IEEE80211_M_MONITOR) {
822 rt2661_enable_mrr(sc);
823 rt2661_set_txpreamble(sc);
824 rt2661_set_basicrates(sc, &ni->ni_rates);
825 rt2661_set_bssid(sc, ni->ni_bssid);
826 }
827
828 if (vap->iv_opmode == IEEE80211_M_HOSTAP ||
829 vap->iv_opmode == IEEE80211_M_IBSS) {
830 error = rt2661_prepare_beacon(sc, vap);
831 if (error != 0)
832 return error;
833 }
834 if (vap->iv_opmode != IEEE80211_M_MONITOR)
835 rt2661_enable_tsf_sync(sc);
836 }
837 return error;
838}
839
840/*
841 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or
842 * 93C66).
843 */
844static uint16_t
845rt2661_eeprom_read(struct rt2661_softc *sc, uint8_t addr)
846{
847 uint32_t tmp;
848 uint16_t val;
849 int n;
850
851 /* clock C once before the first command */
852 RT2661_EEPROM_CTL(sc, 0);
853
854 RT2661_EEPROM_CTL(sc, RT2661_S);
855 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C);
856 RT2661_EEPROM_CTL(sc, RT2661_S);
857
858 /* write start bit (1) */
859 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D);
860 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C);
861
862 /* write READ opcode (10) */
863 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D);
864 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C);
865 RT2661_EEPROM_CTL(sc, RT2661_S);
866 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C);
867
868 /* write address (A5-A0 or A7-A0) */
869 n = (RAL_READ(sc, RT2661_E2PROM_CSR) & RT2661_93C46) ? 5 : 7;
870 for (; n >= 0; n--) {
871 RT2661_EEPROM_CTL(sc, RT2661_S |
872 (((addr >> n) & 1) << RT2661_SHIFT_D));
873 RT2661_EEPROM_CTL(sc, RT2661_S |
874 (((addr >> n) & 1) << RT2661_SHIFT_D) | RT2661_C);
875 }
876
877 RT2661_EEPROM_CTL(sc, RT2661_S);
878
879 /* read data Q15-Q0 */
880 val = 0;
881 for (n = 15; n >= 0; n--) {
882 RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C);
883 tmp = RAL_READ(sc, RT2661_E2PROM_CSR);
884 val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n;
885 RT2661_EEPROM_CTL(sc, RT2661_S);
886 }
887
888 RT2661_EEPROM_CTL(sc, 0);
889
890 /* clear Chip Select and clock C */
891 RT2661_EEPROM_CTL(sc, RT2661_S);
892 RT2661_EEPROM_CTL(sc, 0);
893 RT2661_EEPROM_CTL(sc, RT2661_C);
894
895 return val;
896}
897
898static void
899rt2661_tx_intr(struct rt2661_softc *sc)
900{
901 struct ifnet *ifp = sc->sc_ifp;
902 struct rt2661_tx_ring *txq;
903 struct rt2661_tx_data *data;
904 struct rt2661_node *rn;
905 uint32_t val;
906 int qid, retrycnt;
907
908 for (;;) {
909 struct ieee80211_node *ni;
910 struct mbuf *m;
911
912 val = RAL_READ(sc, RT2661_STA_CSR4);
913 if (!(val & RT2661_TX_STAT_VALID))
914 break;
915
916 /* retrieve the queue in which this frame was sent */
917 qid = RT2661_TX_QID(val);
918 txq = (qid <= 3) ? &sc->txq[qid] : &sc->mgtq;
919
920 /* retrieve rate control algorithm context */
921 data = &txq->data[txq->stat];
922 m = data->m;
923 data->m = NULL;
924 ni = data->ni;
925 data->ni = NULL;
926
927 /* if no frame has been sent, ignore */
928 if (ni == NULL)
929 continue;
930
931 rn = RT2661_NODE(ni);
932
933 switch (RT2661_TX_RESULT(val)) {
934 case RT2661_TX_SUCCESS:
935 retrycnt = RT2661_TX_RETRYCNT(val);
936
937 DPRINTFN(sc, 10, "data frame sent successfully after "
938 "%d retries\n", retrycnt);
939 if (data->rix != IEEE80211_FIXED_RATE_NONE)
940 ieee80211_amrr_tx_complete(&rn->amrr,
941 IEEE80211_AMRR_SUCCESS, retrycnt);
942 ifp->if_opackets++;
943 break;
944
945 case RT2661_TX_RETRY_FAIL:
946 retrycnt = RT2661_TX_RETRYCNT(val);
947
948 DPRINTFN(sc, 9, "%s\n",
949 "sending data frame failed (too much retries)");
950 if (data->rix != IEEE80211_FIXED_RATE_NONE)
951 ieee80211_amrr_tx_complete(&rn->amrr,
952 IEEE80211_AMRR_FAILURE, retrycnt);
953 ifp->if_oerrors++;
954 break;
955
956 default:
957 /* other failure */
958 device_printf(sc->sc_dev,
959 "sending data frame failed 0x%08x\n", val);
960 ifp->if_oerrors++;
961 }
962
963 DPRINTFN(sc, 15, "tx done q=%d idx=%u\n", qid, txq->stat);
964
965 txq->queued--;
966 if (++txq->stat >= txq->count) /* faster than % count */
967 txq->stat = 0;
968
969 if (m->m_flags & M_TXCB)
970 ieee80211_process_callback(ni, m,
971 RT2661_TX_RESULT(val) != RT2661_TX_SUCCESS);
972 m_freem(m);
973 ieee80211_free_node(ni);
974 }
975
976 sc->sc_tx_timer = 0;
977 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
978
979 rt2661_start_locked(ifp);
980}
981
982static void
983rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *txq)
984{
985 struct rt2661_tx_desc *desc;
986 struct rt2661_tx_data *data;
987
988 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_POSTREAD);
989
990 for (;;) {
991 desc = &txq->desc[txq->next];
992 data = &txq->data[txq->next];
993
994 if ((le32toh(desc->flags) & RT2661_TX_BUSY) ||
995 !(le32toh(desc->flags) & RT2661_TX_VALID))
996 break;
997
998 bus_dmamap_sync(txq->data_dmat, data->map,
999 BUS_DMASYNC_POSTWRITE);
1000 bus_dmamap_unload(txq->data_dmat, data->map);
1001
1002 /* descriptor is no longer valid */
1003 desc->flags &= ~htole32(RT2661_TX_VALID);
1004
1005 DPRINTFN(sc, 15, "tx dma done q=%p idx=%u\n", txq, txq->next);
1006
1007 if (++txq->next >= txq->count) /* faster than % count */
1008 txq->next = 0;
1009 }
1010
1011 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE);
1012}
1013
1014static void
1015rt2661_rx_intr(struct rt2661_softc *sc)
1016{
1017 struct ifnet *ifp = sc->sc_ifp;
1018 struct ieee80211com *ic = ifp->if_l2com;
1019 struct rt2661_rx_desc *desc;
1020 struct rt2661_rx_data *data;
1021 bus_addr_t physaddr;
1022 struct ieee80211_frame *wh;
1023 struct ieee80211_node *ni;
1024 struct mbuf *mnew, *m;
1025 int error;
1026
1027 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map,
1028 BUS_DMASYNC_POSTREAD);
1029
1030 for (;;) {
1031 int rssi;
1032
1033 desc = &sc->rxq.desc[sc->rxq.cur];
1034 data = &sc->rxq.data[sc->rxq.cur];
1035
1036 if (le32toh(desc->flags) & RT2661_RX_BUSY)
1037 break;
1038
1039 if ((le32toh(desc->flags) & RT2661_RX_PHY_ERROR) ||
1040 (le32toh(desc->flags) & RT2661_RX_CRC_ERROR)) {
1041 /*
1042 * This should not happen since we did not request
1043 * to receive those frames when we filled TXRX_CSR0.
1044 */
1045 DPRINTFN(sc, 5, "PHY or CRC error flags 0x%08x\n",
1046 le32toh(desc->flags));
1047 ifp->if_ierrors++;
1048 goto skip;
1049 }
1050
1051 if ((le32toh(desc->flags) & RT2661_RX_CIPHER_MASK) != 0) {
1052 ifp->if_ierrors++;
1053 goto skip;
1054 }
1055
1056 /*
1057 * Try to allocate a new mbuf for this ring element and load it
1058 * before processing the current mbuf. If the ring element
1059 * cannot be loaded, drop the received packet and reuse the old
1060 * mbuf. In the unlikely case that the old mbuf can't be
1061 * reloaded either, explicitly panic.
1062 */
1063 mnew = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1064 if (mnew == NULL) {
1065 ifp->if_ierrors++;
1066 goto skip;
1067 }
1068
1069 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
1070 BUS_DMASYNC_POSTREAD);
1071 bus_dmamap_unload(sc->rxq.data_dmat, data->map);
1072
1073 error = bus_dmamap_load(sc->rxq.data_dmat, data->map,
1074 mtod(mnew, void *), MCLBYTES, rt2661_dma_map_addr,
1075 &physaddr, 0);
1076 if (error != 0) {
1077 m_freem(mnew);
1078
1079 /* try to reload the old mbuf */
1080 error = bus_dmamap_load(sc->rxq.data_dmat, data->map,
1081 mtod(data->m, void *), MCLBYTES,
1082 rt2661_dma_map_addr, &physaddr, 0);
1083 if (error != 0) {
1084 /* very unlikely that it will fail... */
1085 panic("%s: could not load old rx mbuf",
1086 device_get_name(sc->sc_dev));
1087 }
1088 ifp->if_ierrors++;
1089 goto skip;
1090 }
1091
1092 /*
1093 * New mbuf successfully loaded, update Rx ring and continue
1094 * processing.
1095 */
1096 m = data->m;
1097 data->m = mnew;
1098 desc->physaddr = htole32(physaddr);
1099
1100 /* finalize mbuf */
1101 m->m_pkthdr.rcvif = ifp;
1102 m->m_pkthdr.len = m->m_len =
1103 (le32toh(desc->flags) >> 16) & 0xfff;
1104
1105 rssi = rt2661_get_rssi(sc, desc->rssi);
1106
1107 if (bpf_peers_present(ifp->if_bpf)) {
1108 struct rt2661_rx_radiotap_header *tap = &sc->sc_rxtap;
1109 uint32_t tsf_lo, tsf_hi;
1110
1111 /* get timestamp (low and high 32 bits) */
1112 tsf_hi = RAL_READ(sc, RT2661_TXRX_CSR13);
1113 tsf_lo = RAL_READ(sc, RT2661_TXRX_CSR12);
1114
1115 tap->wr_tsf =
1116 htole64(((uint64_t)tsf_hi << 32) | tsf_lo);
1117 tap->wr_flags = 0;
1118 tap->wr_rate = ieee80211_plcp2rate(desc->rate,
1119 (desc->flags & htole32(RT2661_RX_OFDM)) ?
1120 IEEE80211_T_OFDM : IEEE80211_T_CCK);
1121 tap->wr_antsignal = rssi < 0 ? 0 : rssi;
1122
1123 bpf_mtap2(ifp->if_bpf, tap, sc->sc_rxtap_len, m);
1124 }
1125 sc->sc_flags |= RAL_INPUT_RUNNING;
1126 RAL_UNLOCK(sc);
1127 wh = mtod(m, struct ieee80211_frame *);
1128
1129 /* send the frame to the 802.11 layer */
1130 ni = ieee80211_find_rxnode(ic,
1131 (struct ieee80211_frame_min *)wh);
1132 if (ni != NULL) {
1133 /* Error happened during RSSI conversion. */
1134 if (rssi < 0)
1135 rssi = -30; /* XXX ignored by net80211 */
1136
1137 (void) ieee80211_input(ni, m, rssi,
1138 RT2661_NOISE_FLOOR, 0);
1139 ieee80211_free_node(ni);
1140 } else
1141 (void) ieee80211_input_all(ic, m, rssi,
1142 RT2661_NOISE_FLOOR, 0);
1143
1144 RAL_LOCK(sc);
1145 sc->sc_flags &= ~RAL_INPUT_RUNNING;
1146
1147skip: desc->flags |= htole32(RT2661_RX_BUSY);
1148
1149 DPRINTFN(sc, 15, "rx intr idx=%u\n", sc->rxq.cur);
1150
1151 sc->rxq.cur = (sc->rxq.cur + 1) % RT2661_RX_RING_COUNT;
1152 }
1153
1154 bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map,
1155 BUS_DMASYNC_PREWRITE);
1156}
1157
1158/* ARGSUSED */
1159static void
1160rt2661_mcu_beacon_expire(struct rt2661_softc *sc)
1161{
1162 /* do nothing */
1163}
1164
1165static void
1166rt2661_mcu_wakeup(struct rt2661_softc *sc)
1167{
1168 RAL_WRITE(sc, RT2661_MAC_CSR11, 5 << 16);
1169
1170 RAL_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7);
1171 RAL_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18);
1172 RAL_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20);
1173
1174 /* send wakeup command to MCU */
1175 rt2661_tx_cmd(sc, RT2661_MCU_CMD_WAKEUP, 0);
1176}
1177
1178static void
1179rt2661_mcu_cmd_intr(struct rt2661_softc *sc)
1180{
1181 RAL_READ(sc, RT2661_M2H_CMD_DONE_CSR);
1182 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff);
1183}
1184
1185void
1186rt2661_intr(void *arg)
1187{
1188 struct rt2661_softc *sc = arg;
1189 struct ifnet *ifp = sc->sc_ifp;
1190 uint32_t r1, r2;
1191
1192 RAL_LOCK(sc);
1193
1194 /* disable MAC and MCU interrupts */
1195 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f);
1196 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff);
1197
1198 /* don't re-enable interrupts if we're shutting down */
1199 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1200 RAL_UNLOCK(sc);
1201 return;
1202 }
1203
1204 r1 = RAL_READ(sc, RT2661_INT_SOURCE_CSR);
1205 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, r1);
1206
1207 r2 = RAL_READ(sc, RT2661_MCU_INT_SOURCE_CSR);
1208 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2);
1209
1210 if (r1 & RT2661_MGT_DONE)
1211 rt2661_tx_dma_intr(sc, &sc->mgtq);
1212
1213 if (r1 & RT2661_RX_DONE)
1214 rt2661_rx_intr(sc);
1215
1216 if (r1 & RT2661_TX0_DMA_DONE)
1217 rt2661_tx_dma_intr(sc, &sc->txq[0]);
1218
1219 if (r1 & RT2661_TX1_DMA_DONE)
1220 rt2661_tx_dma_intr(sc, &sc->txq[1]);
1221
1222 if (r1 & RT2661_TX2_DMA_DONE)
1223 rt2661_tx_dma_intr(sc, &sc->txq[2]);
1224
1225 if (r1 & RT2661_TX3_DMA_DONE)
1226 rt2661_tx_dma_intr(sc, &sc->txq[3]);
1227
1228 if (r1 & RT2661_TX_DONE)
1229 rt2661_tx_intr(sc);
1230
1231 if (r2 & RT2661_MCU_CMD_DONE)
1232 rt2661_mcu_cmd_intr(sc);
1233
1234 if (r2 & RT2661_MCU_BEACON_EXPIRE)
1235 rt2661_mcu_beacon_expire(sc);
1236
1237 if (r2 & RT2661_MCU_WAKEUP)
1238 rt2661_mcu_wakeup(sc);
1239
1240 /* re-enable MAC and MCU interrupts */
1241 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10);
1242 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0);
1243
1244 RAL_UNLOCK(sc);
1245}
1246
1247static uint8_t
1248rt2661_plcp_signal(int rate)
1249{
1250 switch (rate) {
1251 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */
1252 case 12: return 0xb;
1253 case 18: return 0xf;
1254 case 24: return 0xa;
1255 case 36: return 0xe;
1256 case 48: return 0x9;
1257 case 72: return 0xd;
1258 case 96: return 0x8;
1259 case 108: return 0xc;
1260
1261 /* CCK rates (NB: not IEEE std, device-specific) */
1262 case 2: return 0x0;
1263 case 4: return 0x1;
1264 case 11: return 0x2;
1265 case 22: return 0x3;
1266 }
1267 return 0xff; /* XXX unsupported/unknown rate */
1268}
1269
1270static void
1271rt2661_setup_tx_desc(struct rt2661_softc *sc, struct rt2661_tx_desc *desc,
1272 uint32_t flags, uint16_t xflags, int len, int rate,
1273 const bus_dma_segment_t *segs, int nsegs, int ac)
1274{
1275 struct ifnet *ifp = sc->sc_ifp;
1276 struct ieee80211com *ic = ifp->if_l2com;
1277 uint16_t plcp_length;
1278 int i, remainder;
1279
1280 desc->flags = htole32(flags);
1281 desc->flags |= htole32(len << 16);
1282 desc->flags |= htole32(RT2661_TX_BUSY | RT2661_TX_VALID);
1283
1284 desc->xflags = htole16(xflags);
1285 desc->xflags |= htole16(nsegs << 13);
1286
1287 desc->wme = htole16(
1288 RT2661_QID(ac) |
1289 RT2661_AIFSN(2) |
1290 RT2661_LOGCWMIN(4) |
1291 RT2661_LOGCWMAX(10));
1292
1293 /*
1294 * Remember in which queue this frame was sent. This field is driver
1295 * private data only. It will be made available by the NIC in STA_CSR4
1296 * on Tx interrupts.
1297 */
1298 desc->qid = ac;
1299
1300 /* setup PLCP fields */
1301 desc->plcp_signal = rt2661_plcp_signal(rate);
1302 desc->plcp_service = 4;
1303
1304 len += IEEE80211_CRC_LEN;
1305 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) {
1306 desc->flags |= htole32(RT2661_TX_OFDM);
1307
1308 plcp_length = len & 0xfff;
1309 desc->plcp_length_hi = plcp_length >> 6;
1310 desc->plcp_length_lo = plcp_length & 0x3f;
1311 } else {
1312 plcp_length = (16 * len + rate - 1) / rate;
1313 if (rate == 22) {
1314 remainder = (16 * len) % 22;
1315 if (remainder != 0 && remainder < 7)
1316 desc->plcp_service |= RT2661_PLCP_LENGEXT;
1317 }
1318 desc->plcp_length_hi = plcp_length >> 8;
1319 desc->plcp_length_lo = plcp_length & 0xff;
1320
1321 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE))
1322 desc->plcp_signal |= 0x08;
1323 }
1324
1325 /* RT2x61 supports scatter with up to 5 segments */
1326 for (i = 0; i < nsegs; i++) {
1327 desc->addr[i] = htole32(segs[i].ds_addr);
1328 desc->len [i] = htole16(segs[i].ds_len);
1329 }
1330}
1331
1332static int
1333rt2661_tx_mgt(struct rt2661_softc *sc, struct mbuf *m0,
1334 struct ieee80211_node *ni)
1335{
1336 struct ieee80211vap *vap = ni->ni_vap;
1337 struct ieee80211com *ic = ni->ni_ic;
1338 struct ifnet *ifp = sc->sc_ifp;
1339 struct rt2661_tx_desc *desc;
1340 struct rt2661_tx_data *data;
1341 struct ieee80211_frame *wh;
1342 struct ieee80211_key *k;
1343 bus_dma_segment_t segs[RT2661_MAX_SCATTER];
1344 uint16_t dur;
1345 uint32_t flags = 0; /* XXX HWSEQ */
1346 int nsegs, rate, error;
1347
1348 desc = &sc->mgtq.desc[sc->mgtq.cur];
1349 data = &sc->mgtq.data[sc->mgtq.cur];
1350
1351 rate = vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)].mgmtrate;
1352
1353 wh = mtod(m0, struct ieee80211_frame *);
1354
1355 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
1356 k = ieee80211_crypto_encap(ni, m0);
1357 if (k == NULL) {
1358 m_freem(m0);
1359 return ENOBUFS;
1360 }
1361 }
1362
1363 error = bus_dmamap_load_mbuf_sg(sc->mgtq.data_dmat, data->map, m0,
1364 segs, &nsegs, 0);
1365 if (error != 0) {
1366 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n",
1367 error);
1368 m_freem(m0);
1369 return error;
1370 }
1371
1372 if (bpf_peers_present(ifp->if_bpf)) {
1373 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap;
1374
1375 tap->wt_flags = 0;
1376 tap->wt_rate = rate;
1377
1378 bpf_mtap2(ifp->if_bpf, tap, sc->sc_txtap_len, m0);
1379 }
1380
1381 data->m = m0;
1382 data->ni = ni;
1383 /* management frames are not taken into account for amrr */
1384 data->rix = IEEE80211_FIXED_RATE_NONE;
1385
1386 wh = mtod(m0, struct ieee80211_frame *);
1387
1388 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1389 flags |= RT2661_TX_NEED_ACK;
1390
1391 dur = ieee80211_ack_duration(sc->sc_rates,
1392 rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE);
1393 *(uint16_t *)wh->i_dur = htole16(dur);
1394
1395 /* tell hardware to add timestamp in probe responses */
1396 if ((wh->i_fc[0] &
1397 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==
1398 (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP))
1399 flags |= RT2661_TX_TIMESTAMP;
1400 }
1401
1402 rt2661_setup_tx_desc(sc, desc, flags, 0 /* XXX HWSEQ */,
1403 m0->m_pkthdr.len, rate, segs, nsegs, RT2661_QID_MGT);
1404
1405 bus_dmamap_sync(sc->mgtq.data_dmat, data->map, BUS_DMASYNC_PREWRITE);
1406 bus_dmamap_sync(sc->mgtq.desc_dmat, sc->mgtq.desc_map,
1407 BUS_DMASYNC_PREWRITE);
1408
1409 DPRINTFN(sc, 10, "sending mgt frame len=%u idx=%u rate=%u\n",
1410 m0->m_pkthdr.len, sc->mgtq.cur, rate);
1411
1412 /* kick mgt */
1413 sc->mgtq.queued++;
1414 sc->mgtq.cur = (sc->mgtq.cur + 1) % RT2661_MGT_RING_COUNT;
1415 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT);
1416
1417 return 0;
1418}
1419
1420static int
1421rt2661_sendprot(struct rt2661_softc *sc, int ac,
1422 const struct mbuf *m, struct ieee80211_node *ni, int prot, int rate)
1423{
1424 struct ieee80211com *ic = ni->ni_ic;
1425 struct rt2661_tx_ring *txq = &sc->txq[ac];
1426 const struct ieee80211_frame *wh;
1427 struct rt2661_tx_desc *desc;
1428 struct rt2661_tx_data *data;
1429 struct mbuf *mprot;
1430 int protrate, ackrate, pktlen, flags, isshort, error;
1431 uint16_t dur;
1432 bus_dma_segment_t segs[RT2661_MAX_SCATTER];
1433 int nsegs;
1434
1435 KASSERT(prot == IEEE80211_PROT_RTSCTS || prot == IEEE80211_PROT_CTSONLY,
1436 ("protection %d", prot));
1437
1438 wh = mtod(m, const struct ieee80211_frame *);
1439 pktlen = m->m_pkthdr.len + IEEE80211_CRC_LEN;
1440
1441 protrate = ieee80211_ctl_rate(sc->sc_rates, rate);
1442 ackrate = ieee80211_ack_rate(sc->sc_rates, rate);
1443
1444 isshort = (ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0;
1445 dur = ieee80211_compute_duration(sc->sc_rates, pktlen, rate, isshort)
1446 + ieee80211_ack_duration(sc->sc_rates, rate, isshort);
1447 flags = RT2661_TX_MORE_FRAG;
1448 if (prot == IEEE80211_PROT_RTSCTS) {
1449 /* NB: CTS is the same size as an ACK */
1450 dur += ieee80211_ack_duration(sc->sc_rates, rate, isshort);
1451 flags |= RT2661_TX_NEED_ACK;
1452 mprot = ieee80211_alloc_rts(ic, wh->i_addr1, wh->i_addr2, dur);
1453 } else {
1454 mprot = ieee80211_alloc_cts(ic, ni->ni_vap->iv_myaddr, dur);
1455 }
1456 if (mprot == NULL) {
1457 /* XXX stat + msg */
1458 return ENOBUFS;
1459 }
1460
1461 data = &txq->data[txq->cur];
1462 desc = &txq->desc[txq->cur];
1463
1464 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, mprot, segs,
1465 &nsegs, 0);
1466 if (error != 0) {
1467 device_printf(sc->sc_dev,
1468 "could not map mbuf (error %d)\n", error);
1469 m_freem(mprot);
1470 return error;
1471 }
1472
1473 data->m = mprot;
1474 data->ni = ieee80211_ref_node(ni);
1475 /* ctl frames are not taken into account for amrr */
1476 data->rix = IEEE80211_FIXED_RATE_NONE;
1477
1478 rt2661_setup_tx_desc(sc, desc, flags, 0, mprot->m_pkthdr.len,
1479 protrate, segs, 1, ac);
1480
1481 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE);
1482 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE);
1483
1484 txq->queued++;
1485 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT;
1486
1487 return 0;
1488}
1489
1490static int
1491rt2661_tx_data(struct rt2661_softc *sc, struct mbuf *m0,
1492 struct ieee80211_node *ni, int ac)
1493{
1494 struct ieee80211vap *vap = ni->ni_vap;
1495 struct ifnet *ifp = sc->sc_ifp;
1496 struct ieee80211com *ic = ifp->if_l2com;
1497 struct rt2661_tx_ring *txq = &sc->txq[ac];
1498 struct rt2661_tx_desc *desc;
1499 struct rt2661_tx_data *data;
1500 struct ieee80211_frame *wh;
1501 const struct ieee80211_txparam *tp;
1502 struct ieee80211_key *k;
1503 const struct chanAccParams *cap;
1504 struct mbuf *mnew;
1505 bus_dma_segment_t segs[RT2661_MAX_SCATTER];
1506 uint16_t dur;
1507 uint32_t flags;
1508 int error, nsegs, rate, noack = 0;
1509
1510 wh = mtod(m0, struct ieee80211_frame *);
1511
1512 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)];
1513 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1514 rate = tp->mcastrate;
1515 } else if (m0->m_flags & M_EAPOL) {
1516 rate = tp->mgmtrate;
1517 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) {
1518 rate = tp->ucastrate;
1519 } else {
1520 (void) ieee80211_amrr_choose(ni, &RT2661_NODE(ni)->amrr);
1521 rate = ni->ni_txrate;
1522 }
1523 rate &= IEEE80211_RATE_VAL;
1524
1525 if (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS) {
1526 cap = &ic->ic_wme.wme_chanParams;
1527 noack = cap->cap_wmeParams[ac].wmep_noackPolicy;
1528 }
1529
1530 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
1531 k = ieee80211_crypto_encap(ni, m0);
1532 if (k == NULL) {
1533 m_freem(m0);
1534 return ENOBUFS;
1535 }
1536
1537 /* packet header may have moved, reset our local pointer */
1538 wh = mtod(m0, struct ieee80211_frame *);
1539 }
1540
1541 flags = 0;
1542 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1543 int prot = IEEE80211_PROT_NONE;
1544 if (m0->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold)
1545 prot = IEEE80211_PROT_RTSCTS;
1546 else if ((ic->ic_flags & IEEE80211_F_USEPROT) &&
1547 ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM)
1548 prot = ic->ic_protmode;
1549 if (prot != IEEE80211_PROT_NONE) {
1550 error = rt2661_sendprot(sc, ac, m0, ni, prot, rate);
1551 if (error) {
1552 m_freem(m0);
1553 return error;
1554 }
1555 flags |= RT2661_TX_LONG_RETRY | RT2661_TX_IFS;
1556 }
1557 }
1558
1559 data = &txq->data[txq->cur];
1560 desc = &txq->desc[txq->cur];
1561
1562 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0, segs,
1563 &nsegs, 0);
1564 if (error != 0 && error != EFBIG) {
1565 device_printf(sc->sc_dev, "could not map mbuf (error %d)\n",
1566 error);
1567 m_freem(m0);
1568 return error;
1569 }
1570 if (error != 0) {
1571 mnew = m_defrag(m0, M_DONTWAIT);
1572 if (mnew == NULL) {
1573 device_printf(sc->sc_dev,
1574 "could not defragment mbuf\n");
1575 m_freem(m0);
1576 return ENOBUFS;
1577 }
1578 m0 = mnew;
1579
1580 error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0,
1581 segs, &nsegs, 0);
1582 if (error != 0) {
1583 device_printf(sc->sc_dev,
1584 "could not map mbuf (error %d)\n", error);
1585 m_freem(m0);
1586 return error;
1587 }
1588
1589 /* packet header have moved, reset our local pointer */
1590 wh = mtod(m0, struct ieee80211_frame *);
1591 }
1592
1593 if (bpf_peers_present(ifp->if_bpf)) {
1594 struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap;
1595
1596 tap->wt_flags = 0;
1597 tap->wt_rate = rate;
1598 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq);
1599 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags);
1600
1601 bpf_mtap2(ifp->if_bpf, tap, sc->sc_txtap_len, m0);
1602 }
1603
1604 data->m = m0;
1605 data->ni = ni;
1606
1607 /* remember link conditions for rate adaptation algorithm */
1608 if (tp->ucastrate == IEEE80211_FIXED_RATE_NONE) {
1609 data->rix = ni->ni_txrate;
1610 /* XXX probably need last rssi value and not avg */
1611 data->rssi = ic->ic_node_getrssi(ni);
1612 } else
1613 data->rix = IEEE80211_FIXED_RATE_NONE;
1614
1615 if (!noack && !IEEE80211_IS_MULTICAST(wh->i_addr1)) {
1616 flags |= RT2661_TX_NEED_ACK;
1617
1618 dur = ieee80211_ack_duration(sc->sc_rates,
1619 rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE);
1620 *(uint16_t *)wh->i_dur = htole16(dur);
1621 }
1622
1623 rt2661_setup_tx_desc(sc, desc, flags, 0, m0->m_pkthdr.len, rate, segs,
1624 nsegs, ac);
1625
1626 bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE);
1627 bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE);
1628
1629 DPRINTFN(sc, 10, "sending data frame len=%u idx=%u rate=%u\n",
1630 m0->m_pkthdr.len, txq->cur, rate);
1631
1632 /* kick Tx */
1633 txq->queued++;
1634 txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT;
1635 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 1 << ac);
1636
1637 return 0;
1638}
1639
1640static void
1641rt2661_start_locked(struct ifnet *ifp)
1642{
1643 struct rt2661_softc *sc = ifp->if_softc;
1644 struct mbuf *m;
1645 struct ieee80211_node *ni;
1646 int ac;
1647
1648 RAL_LOCK_ASSERT(sc);
1649
1650 /* prevent management frames from being sent if we're not ready */
1651 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING) || sc->sc_invalid)
1652 return;
1653
1654 for (;;) {
1655 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
1656 if (m == NULL)
1657 break;
1658
1659 ac = M_WME_GETAC(m);
1660 if (sc->txq[ac].queued >= RT2661_TX_RING_COUNT - 1) {
1661 /* there is no place left in this ring */
1662 IFQ_DRV_PREPEND(&ifp->if_snd, m);
1663 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1664 break;
1665 }
1666
1667 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif;
1668 m = ieee80211_encap(ni, m);
1669 if (m == NULL) {
1670 ieee80211_free_node(ni);
1671 ifp->if_oerrors++;
1672 continue;
1673 }
1674
1675 if (rt2661_tx_data(sc, m, ni, ac) != 0) {
1676 ieee80211_free_node(ni);
1677 ifp->if_oerrors++;
1678 break;
1679 }
1680
1681 sc->sc_tx_timer = 5;
1682 }
1683}
1684
1685static void
1686rt2661_start(struct ifnet *ifp)
1687{
1688 struct rt2661_softc *sc = ifp->if_softc;
1689
1690 RAL_LOCK(sc);
1691 rt2661_start_locked(ifp);
1692 RAL_UNLOCK(sc);
1693}
1694
1695static int
1696rt2661_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
1697 const struct ieee80211_bpf_params *params)
1698{
1699 struct ieee80211com *ic = ni->ni_ic;
1700 struct ifnet *ifp = ic->ic_ifp;
1701 struct rt2661_softc *sc = ifp->if_softc;
1702
1703 RAL_LOCK(sc);
1704
1705 /* prevent management frames from being sent if we're not ready */
1706 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1707 RAL_UNLOCK(sc);
1708 m_freem(m);
1709 ieee80211_free_node(ni);
1710 return ENETDOWN;
1711 }
1712 if (sc->mgtq.queued >= RT2661_MGT_RING_COUNT) {
1713 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1714 RAL_UNLOCK(sc);
1715 m_freem(m);
1716 ieee80211_free_node(ni);
1717 return ENOBUFS; /* XXX */
1718 }
1719
1720 ifp->if_opackets++;
1721
1722 /*
1723 * Legacy path; interpret frame contents to decide
1724 * precisely how to send the frame.
1725 * XXX raw path
1726 */
1727 if (rt2661_tx_mgt(sc, m, ni) != 0)
1728 goto bad;
1729 sc->sc_tx_timer = 5;
1730
1731 RAL_UNLOCK(sc);
1732
1733 return 0;
1734bad:
1735 ifp->if_oerrors++;
1736 ieee80211_free_node(ni);
1737 RAL_UNLOCK(sc);
1738 return EIO; /* XXX */
1739}
1740
1741static void
1742rt2661_watchdog(void *arg)
1743{
1744 struct rt2661_softc *sc = (struct rt2661_softc *)arg;
1745 struct ifnet *ifp = sc->sc_ifp;
1746
1747 RAL_LOCK_ASSERT(sc);
1748
1749 KASSERT(ifp->if_drv_flags & IFF_DRV_RUNNING, ("not running"));
1750
1751 if (sc->sc_invalid) /* card ejected */
1752 return;
1753
1754 if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) {
1755 if_printf(ifp, "device timeout\n");
1756 rt2661_init_locked(sc);
1757 ifp->if_oerrors++;
1758 /* NB: callout is reset in rt2661_init() */
1759 return;
1760 }
1761 callout_reset(&sc->watchdog_ch, hz, rt2661_watchdog, sc);
1762}
1763
1764static int
1765rt2661_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1766{
1767 struct rt2661_softc *sc = ifp->if_softc;
1768 struct ieee80211com *ic = ifp->if_l2com;
1769 struct ifreq *ifr = (struct ifreq *) data;
1770 int error = 0, startall = 0;
1771
1772 switch (cmd) {
1773 case SIOCSIFFLAGS:
1774 RAL_LOCK(sc);
1775 if (ifp->if_flags & IFF_UP) {
1776 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1777 rt2661_init_locked(sc);
1778 startall = 1;
1779 } else
1780 rt2661_update_promisc(ifp);
1781 } else {
1782 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1783 rt2661_stop_locked(sc);
1784 }
1785 RAL_UNLOCK(sc);
1786 if (startall)
1787 ieee80211_start_all(ic);
1788 break;
1789 case SIOCGIFMEDIA:
1790 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd);
1791 break;
1792 case SIOCGIFADDR:
1793 error = ether_ioctl(ifp, cmd, data);
1794 break;
1795 default:
1796 error = EINVAL;
1797 break;
1798 }
1799 return error;
1800}
1801
1802static void
1803rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val)
1804{
1805 uint32_t tmp;
1806 int ntries;
1807
1808 for (ntries = 0; ntries < 100; ntries++) {
1809 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY))
1810 break;
1811 DELAY(1);
1812 }
1813 if (ntries == 100) {
1814 device_printf(sc->sc_dev, "could not write to BBP\n");
1815 return;
1816 }
1817
1818 tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val;
1819 RAL_WRITE(sc, RT2661_PHY_CSR3, tmp);
1820
1821 DPRINTFN(sc, 15, "BBP R%u <- 0x%02x\n", reg, val);
1822}
1823
1824static uint8_t
1825rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg)
1826{
1827 uint32_t val;
1828 int ntries;
1829
1830 for (ntries = 0; ntries < 100; ntries++) {
1831 if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY))
1832 break;
1833 DELAY(1);
1834 }
1835 if (ntries == 100) {
1836 device_printf(sc->sc_dev, "could not read from BBP\n");
1837 return 0;
1838 }
1839
1840 val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8;
1841 RAL_WRITE(sc, RT2661_PHY_CSR3, val);
1842
1843 for (ntries = 0; ntries < 100; ntries++) {
1844 val = RAL_READ(sc, RT2661_PHY_CSR3);
1845 if (!(val & RT2661_BBP_BUSY))
1846 return val & 0xff;
1847 DELAY(1);
1848 }
1849
1850 device_printf(sc->sc_dev, "could not read from BBP\n");
1851 return 0;
1852}
1853
1854static void
1855rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val)
1856{
1857 uint32_t tmp;
1858 int ntries;
1859
1860 for (ntries = 0; ntries < 100; ntries++) {
1861 if (!(RAL_READ(sc, RT2661_PHY_CSR4) & RT2661_RF_BUSY))
1862 break;
1863 DELAY(1);
1864 }
1865 if (ntries == 100) {
1866 device_printf(sc->sc_dev, "could not write to RF\n");
1867 return;
1868 }
1869
1870 tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 |
1871 (reg & 3);
1872 RAL_WRITE(sc, RT2661_PHY_CSR4, tmp);
1873
1874 /* remember last written value in sc */
1875 sc->rf_regs[reg] = val;
1876
1877 DPRINTFN(sc, 15, "RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff);
1878}
1879
1880static int
1881rt2661_tx_cmd(struct rt2661_softc *sc, uint8_t cmd, uint16_t arg)
1882{
1883 if (RAL_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY)
1884 return EIO; /* there is already a command pending */
1885
1886 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR,
1887 RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | arg);
1888
1889 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd);
1890
1891 return 0;
1892}
1893
1894static void
1895rt2661_select_antenna(struct rt2661_softc *sc)
1896{
1897 uint8_t bbp4, bbp77;
1898 uint32_t tmp;
1899
1900 bbp4 = rt2661_bbp_read(sc, 4);
1901 bbp77 = rt2661_bbp_read(sc, 77);
1902
1903 /* TBD */
1904
1905 /* make sure Rx is disabled before switching antenna */
1906 tmp = RAL_READ(sc, RT2661_TXRX_CSR0);
1907 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX);
1908
1909 rt2661_bbp_write(sc, 4, bbp4);
1910 rt2661_bbp_write(sc, 77, bbp77);
1911
1912 /* restore Rx filter */
1913 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
1914}
1915
1916/*
1917 * Enable multi-rate retries for frames sent at OFDM rates.
1918 * In 802.11b/g mode, allow fallback to CCK rates.
1919 */
1920static void
1921rt2661_enable_mrr(struct rt2661_softc *sc)
1922{
1923 struct ifnet *ifp = sc->sc_ifp;
1924 struct ieee80211com *ic = ifp->if_l2com;
1925 uint32_t tmp;
1926
1927 tmp = RAL_READ(sc, RT2661_TXRX_CSR4);
1928
1929 tmp &= ~RT2661_MRR_CCK_FALLBACK;
1930 if (!IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan))
1931 tmp |= RT2661_MRR_CCK_FALLBACK;
1932 tmp |= RT2661_MRR_ENABLED;
1933
1934 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp);
1935}
1936
1937static void
1938rt2661_set_txpreamble(struct rt2661_softc *sc)
1939{
1940 struct ifnet *ifp = sc->sc_ifp;
1941 struct ieee80211com *ic = ifp->if_l2com;
1942 uint32_t tmp;
1943
1944 tmp = RAL_READ(sc, RT2661_TXRX_CSR4);
1945
1946 tmp &= ~RT2661_SHORT_PREAMBLE;
1947 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
1948 tmp |= RT2661_SHORT_PREAMBLE;
1949
1950 RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp);
1951}
1952
1953static void
1954rt2661_set_basicrates(struct rt2661_softc *sc,
1955 const struct ieee80211_rateset *rs)
1956{
1957#define RV(r) ((r) & IEEE80211_RATE_VAL)
1958 struct ifnet *ifp = sc->sc_ifp;
1959 struct ieee80211com *ic = ifp->if_l2com;
1960 uint32_t mask = 0;
1961 uint8_t rate;
1962 int i, j;
1963
1964 for (i = 0; i < rs->rs_nrates; i++) {
1965 rate = rs->rs_rates[i];
1966
1967 if (!(rate & IEEE80211_RATE_BASIC))
1968 continue;
1969
1970 /*
1971 * Find h/w rate index. We know it exists because the rate
1972 * set has already been negotiated.
1973 */
1974 for (j = 0; ic->ic_sup_rates[IEEE80211_MODE_11G].rs_rates[j] != RV(rate); j++);
1975
1976 mask |= 1 << j;
1977 }
1978
1979 RAL_WRITE(sc, RT2661_TXRX_CSR5, mask);
1980
1981 DPRINTF(sc, "Setting basic rate mask to 0x%x\n", mask);
1982#undef RV
1983}
1984
1985/*
1986 * Reprogram MAC/BBP to switch to a new band. Values taken from the reference
1987 * driver.
1988 */
1989static void
1990rt2661_select_band(struct rt2661_softc *sc, struct ieee80211_channel *c)
1991{
1992 uint8_t bbp17, bbp35, bbp96, bbp97, bbp98, bbp104;
1993 uint32_t tmp;
1994
1995 /* update all BBP registers that depend on the band */
1996 bbp17 = 0x20; bbp96 = 0x48; bbp104 = 0x2c;
1997 bbp35 = 0x50; bbp97 = 0x48; bbp98 = 0x48;
1998 if (IEEE80211_IS_CHAN_5GHZ(c)) {
1999 bbp17 += 0x08; bbp96 += 0x10; bbp104 += 0x0c;
2000 bbp35 += 0x10; bbp97 += 0x10; bbp98 += 0x10;
2001 }
2002 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) ||
2003 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) {
2004 bbp17 += 0x10; bbp96 += 0x10; bbp104 += 0x10;
2005 }
2006
2007 rt2661_bbp_write(sc, 17, bbp17);
2008 rt2661_bbp_write(sc, 96, bbp96);
2009 rt2661_bbp_write(sc, 104, bbp104);
2010
2011 if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) ||
2012 (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) {
2013 rt2661_bbp_write(sc, 75, 0x80);
2014 rt2661_bbp_write(sc, 86, 0x80);
2015 rt2661_bbp_write(sc, 88, 0x80);
2016 }
2017
2018 rt2661_bbp_write(sc, 35, bbp35);
2019 rt2661_bbp_write(sc, 97, bbp97);
2020 rt2661_bbp_write(sc, 98, bbp98);
2021
2022 tmp = RAL_READ(sc, RT2661_PHY_CSR0);
2023 tmp &= ~(RT2661_PA_PE_2GHZ | RT2661_PA_PE_5GHZ);
2024 if (IEEE80211_IS_CHAN_2GHZ(c))
2025 tmp |= RT2661_PA_PE_2GHZ;
2026 else
2027 tmp |= RT2661_PA_PE_5GHZ;
2028 RAL_WRITE(sc, RT2661_PHY_CSR0, tmp);
2029}
2030
2031static void
2032rt2661_set_chan(struct rt2661_softc *sc, struct ieee80211_channel *c)
2033{
2034 struct ifnet *ifp = sc->sc_ifp;
2035 struct ieee80211com *ic = ifp->if_l2com;
2036 const struct rfprog *rfprog;
2037 uint8_t bbp3, bbp94 = RT2661_BBPR94_DEFAULT;
2038 int8_t power;
2039 u_int i, chan;
2040
2041 chan = ieee80211_chan2ieee(ic, c);
2042 KASSERT(chan != 0 && chan != IEEE80211_CHAN_ANY, ("chan 0x%x", chan));
2043
2044 sc->sc_rates = ieee80211_get_ratetable(c);
2045
2046 /* select the appropriate RF settings based on what EEPROM says */
2047 rfprog = (sc->rfprog == 0) ? rt2661_rf5225_1 : rt2661_rf5225_2;
2048
2049 /* find the settings for this channel (we know it exists) */
2050 for (i = 0; rfprog[i].chan != chan; i++);
2051
2052 power = sc->txpow[i];
2053 if (power < 0) {
2054 bbp94 += power;
2055 power = 0;
2056 } else if (power > 31) {
2057 bbp94 += power - 31;
2058 power = 31;
2059 }
2060
2061 /*
2062 * If we are switching from the 2GHz band to the 5GHz band or
2063 * vice-versa, BBP registers need to be reprogrammed.
2064 */
2065 if (c->ic_flags != sc->sc_curchan->ic_flags) {
2066 rt2661_select_band(sc, c);
2067 rt2661_select_antenna(sc);
2068 }
2069 sc->sc_curchan = c;
2070
2071 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1);
2072 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2);
2073 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7);
2074 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10);
2075
2076 DELAY(200);
2077
2078 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1);
2079 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2);
2080 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7 | 1);
2081 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10);
2082
2083 DELAY(200);
2084
2085 rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1);
2086 rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2);
2087 rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7);
2088 rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10);
2089
2090 /* enable smart mode for MIMO-capable RFs */
2091 bbp3 = rt2661_bbp_read(sc, 3);
2092
2093 bbp3 &= ~RT2661_SMART_MODE;
2094 if (sc->rf_rev == RT2661_RF_5325 || sc->rf_rev == RT2661_RF_2529)
2095 bbp3 |= RT2661_SMART_MODE;
2096
2097 rt2661_bbp_write(sc, 3, bbp3);
2098
2099 if (bbp94 != RT2661_BBPR94_DEFAULT)
2100 rt2661_bbp_write(sc, 94, bbp94);
2101
2102 /* 5GHz radio needs a 1ms delay here */
2103 if (IEEE80211_IS_CHAN_5GHZ(c))
2104 DELAY(1000);
2105}
2106
2107static void
2108rt2661_set_bssid(struct rt2661_softc *sc, const uint8_t *bssid)
2109{
2110 uint32_t tmp;
2111
2112 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24;
2113 RAL_WRITE(sc, RT2661_MAC_CSR4, tmp);
2114
2115 tmp = bssid[4] | bssid[5] << 8 | RT2661_ONE_BSSID << 16;
2116 RAL_WRITE(sc, RT2661_MAC_CSR5, tmp);
2117}
2118
2119static void
2120rt2661_set_macaddr(struct rt2661_softc *sc, const uint8_t *addr)
2121{
2122 uint32_t tmp;
2123
2124 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24;
2125 RAL_WRITE(sc, RT2661_MAC_CSR2, tmp);
2126
2127 tmp = addr[4] | addr[5] << 8;
2128 RAL_WRITE(sc, RT2661_MAC_CSR3, tmp);
2129}
2130
2131static void
2132rt2661_update_promisc(struct ifnet *ifp)
2133{
2134 struct rt2661_softc *sc = ifp->if_softc;
2135 uint32_t tmp;
2136
2137 tmp = RAL_READ(sc, RT2661_TXRX_CSR0);
2138
2139 tmp &= ~RT2661_DROP_NOT_TO_ME;
2140 if (!(ifp->if_flags & IFF_PROMISC))
2141 tmp |= RT2661_DROP_NOT_TO_ME;
2142
2143 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
2144
2145 DPRINTF(sc, "%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ?
2146 "entering" : "leaving");
2147}
2148
2149/*
2150 * Update QoS (802.11e) settings for each h/w Tx ring.
2151 */
2152static int
2153rt2661_wme_update(struct ieee80211com *ic)
2154{
2155 struct rt2661_softc *sc = ic->ic_ifp->if_softc;
2156 const struct wmeParams *wmep;
2157
2158 wmep = ic->ic_wme.wme_chanParams.cap_wmeParams;
2159
2160 /* XXX: not sure about shifts. */
2161 /* XXX: the reference driver plays with AC_VI settings too. */
2162
2163 /* update TxOp */
2164 RAL_WRITE(sc, RT2661_AC_TXOP_CSR0,
2165 wmep[WME_AC_BE].wmep_txopLimit << 16 |
2166 wmep[WME_AC_BK].wmep_txopLimit);
2167 RAL_WRITE(sc, RT2661_AC_TXOP_CSR1,
2168 wmep[WME_AC_VI].wmep_txopLimit << 16 |
2169 wmep[WME_AC_VO].wmep_txopLimit);
2170
2171 /* update CWmin */
2172 RAL_WRITE(sc, RT2661_CWMIN_CSR,
2173 wmep[WME_AC_BE].wmep_logcwmin << 12 |
2174 wmep[WME_AC_BK].wmep_logcwmin << 8 |
2175 wmep[WME_AC_VI].wmep_logcwmin << 4 |
2176 wmep[WME_AC_VO].wmep_logcwmin);
2177
2178 /* update CWmax */
2179 RAL_WRITE(sc, RT2661_CWMAX_CSR,
2180 wmep[WME_AC_BE].wmep_logcwmax << 12 |
2181 wmep[WME_AC_BK].wmep_logcwmax << 8 |
2182 wmep[WME_AC_VI].wmep_logcwmax << 4 |
2183 wmep[WME_AC_VO].wmep_logcwmax);
2184
2185 /* update Aifsn */
2186 RAL_WRITE(sc, RT2661_AIFSN_CSR,
2187 wmep[WME_AC_BE].wmep_aifsn << 12 |
2188 wmep[WME_AC_BK].wmep_aifsn << 8 |
2189 wmep[WME_AC_VI].wmep_aifsn << 4 |
2190 wmep[WME_AC_VO].wmep_aifsn);
2191
2192 return 0;
2193}
2194
2195static void
2196rt2661_update_slot(struct ifnet *ifp)
2197{
2198 struct rt2661_softc *sc = ifp->if_softc;
2199 struct ieee80211com *ic = ifp->if_l2com;
2200 uint8_t slottime;
2201 uint32_t tmp;
2202
2203 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20;
2204
2205 tmp = RAL_READ(sc, RT2661_MAC_CSR9);
2206 tmp = (tmp & ~0xff) | slottime;
2207 RAL_WRITE(sc, RT2661_MAC_CSR9, tmp);
2208}
2209
2210static const char *
2211rt2661_get_rf(int rev)
2212{
2213 switch (rev) {
2214 case RT2661_RF_5225: return "RT5225";
2215 case RT2661_RF_5325: return "RT5325 (MIMO XR)";
2216 case RT2661_RF_2527: return "RT2527";
2217 case RT2661_RF_2529: return "RT2529 (MIMO XR)";
2218 default: return "unknown";
2219 }
2220}
2221
2222static void
2223rt2661_read_eeprom(struct rt2661_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN])
2224{
2225 uint16_t val;
2226 int i;
2227
2228 /* read MAC address */
2229 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC01);
2230 macaddr[0] = val & 0xff;
2231 macaddr[1] = val >> 8;
2232
2233 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC23);
2234 macaddr[2] = val & 0xff;
2235 macaddr[3] = val >> 8;
2236
2237 val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC45);
2238 macaddr[4] = val & 0xff;
2239 macaddr[5] = val >> 8;
2240
2241 val = rt2661_eeprom_read(sc, RT2661_EEPROM_ANTENNA);
2242 /* XXX: test if different from 0xffff? */
2243 sc->rf_rev = (val >> 11) & 0x1f;
2244 sc->hw_radio = (val >> 10) & 0x1;
2245 sc->rx_ant = (val >> 4) & 0x3;
2246 sc->tx_ant = (val >> 2) & 0x3;
2247 sc->nb_ant = val & 0x3;
2248
2249 DPRINTF(sc, "RF revision=%d\n", sc->rf_rev);
2250
2251 val = rt2661_eeprom_read(sc, RT2661_EEPROM_CONFIG2);
2252 sc->ext_5ghz_lna = (val >> 6) & 0x1;
2253 sc->ext_2ghz_lna = (val >> 4) & 0x1;
2254
2255 DPRINTF(sc, "External 2GHz LNA=%d\nExternal 5GHz LNA=%d\n",
2256 sc->ext_2ghz_lna, sc->ext_5ghz_lna);
2257
2258 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_2GHZ_OFFSET);
2259 if ((val & 0xff) != 0xff)
2260 sc->rssi_2ghz_corr = (int8_t)(val & 0xff); /* signed */
2261
2262 /* Only [-10, 10] is valid */
2263 if (sc->rssi_2ghz_corr < -10 || sc->rssi_2ghz_corr > 10)
2264 sc->rssi_2ghz_corr = 0;
2265
2266 val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_5GHZ_OFFSET);
2267 if ((val & 0xff) != 0xff)
2268 sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */
2269
2270 /* Only [-10, 10] is valid */
2271 if (sc->rssi_5ghz_corr < -10 || sc->rssi_5ghz_corr > 10)
2272 sc->rssi_5ghz_corr = 0;
2273
2274 /* adjust RSSI correction for external low-noise amplifier */
2275 if (sc->ext_2ghz_lna)
2276 sc->rssi_2ghz_corr -= 14;
2277 if (sc->ext_5ghz_lna)
2278 sc->rssi_5ghz_corr -= 14;
2279
2280 DPRINTF(sc, "RSSI 2GHz corr=%d\nRSSI 5GHz corr=%d\n",
2281 sc->rssi_2ghz_corr, sc->rssi_5ghz_corr);
2282
2283 val = rt2661_eeprom_read(sc, RT2661_EEPROM_FREQ_OFFSET);
2284 if ((val >> 8) != 0xff)
2285 sc->rfprog = (val >> 8) & 0x3;
2286 if ((val & 0xff) != 0xff)
2287 sc->rffreq = val & 0xff;
2288
2289 DPRINTF(sc, "RF prog=%d\nRF freq=%d\n", sc->rfprog, sc->rffreq);
2290
2291 /* read Tx power for all a/b/g channels */
2292 for (i = 0; i < 19; i++) {
2293 val = rt2661_eeprom_read(sc, RT2661_EEPROM_TXPOWER + i);
2294 sc->txpow[i * 2] = (int8_t)(val >> 8); /* signed */
2295 DPRINTF(sc, "Channel=%d Tx power=%d\n",
2296 rt2661_rf5225_1[i * 2].chan, sc->txpow[i * 2]);
2297 sc->txpow[i * 2 + 1] = (int8_t)(val & 0xff); /* signed */
2298 DPRINTF(sc, "Channel=%d Tx power=%d\n",
2299 rt2661_rf5225_1[i * 2 + 1].chan, sc->txpow[i * 2 + 1]);
2300 }
2301
2302 /* read vendor-specific BBP values */
2303 for (i = 0; i < 16; i++) {
2304 val = rt2661_eeprom_read(sc, RT2661_EEPROM_BBP_BASE + i);
2305 if (val == 0 || val == 0xffff)
2306 continue; /* skip invalid entries */
2307 sc->bbp_prom[i].reg = val >> 8;
2308 sc->bbp_prom[i].val = val & 0xff;
2309 DPRINTF(sc, "BBP R%d=%02x\n", sc->bbp_prom[i].reg,
2310 sc->bbp_prom[i].val);
2311 }
2312}
2313
2314static int
2315rt2661_bbp_init(struct rt2661_softc *sc)
2316{
2317#define N(a) (sizeof (a) / sizeof ((a)[0]))
2318 int i, ntries;
2319 uint8_t val;
2320
2321 /* wait for BBP to be ready */
2322 for (ntries = 0; ntries < 100; ntries++) {
2323 val = rt2661_bbp_read(sc, 0);
2324 if (val != 0 && val != 0xff)
2325 break;
2326 DELAY(100);
2327 }
2328 if (ntries == 100) {
2329 device_printf(sc->sc_dev, "timeout waiting for BBP\n");
2330 return EIO;
2331 }
2332
2333 /* initialize BBP registers to default values */
2334 for (i = 0; i < N(rt2661_def_bbp); i++) {
2335 rt2661_bbp_write(sc, rt2661_def_bbp[i].reg,
2336 rt2661_def_bbp[i].val);
2337 }
2338
2339 /* write vendor-specific BBP values (from EEPROM) */
2340 for (i = 0; i < 16; i++) {
2341 if (sc->bbp_prom[i].reg == 0)
2342 continue;
2343 rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val);
2344 }
2345
2346 return 0;
2347#undef N
2348}
2349
2350static void
2351rt2661_init_locked(struct rt2661_softc *sc)
2352{
2353#define N(a) (sizeof (a) / sizeof ((a)[0]))
2354 struct ifnet *ifp = sc->sc_ifp;
2355 struct ieee80211com *ic = ifp->if_l2com;
2356 uint32_t tmp, sta[3];
2357 int i, error, ntries;
2358
2359 RAL_LOCK_ASSERT(sc);
2360
2361 if ((sc->sc_flags & RAL_FW_LOADED) == 0) {
2362 error = rt2661_load_microcode(sc);
2363 if (error != 0) {
2364 if_printf(ifp,
2365 "%s: could not load 8051 microcode, error %d\n",
2366 __func__, error);
2367 return;
2368 }
2369 sc->sc_flags |= RAL_FW_LOADED;
2370 }
2371
2372 rt2661_stop_locked(sc);
2373
2374 /* initialize Tx rings */
2375 RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr);
2376 RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr);
2377 RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr);
2378 RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr);
2379
2380 /* initialize Mgt ring */
2381 RAL_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.physaddr);
2382
2383 /* initialize Rx ring */
2384 RAL_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.physaddr);
2385
2386 /* initialize Tx rings sizes */
2387 RAL_WRITE(sc, RT2661_TX_RING_CSR0,
2388 RT2661_TX_RING_COUNT << 24 |
2389 RT2661_TX_RING_COUNT << 16 |
2390 RT2661_TX_RING_COUNT << 8 |
2391 RT2661_TX_RING_COUNT);
2392
2393 RAL_WRITE(sc, RT2661_TX_RING_CSR1,
2394 RT2661_TX_DESC_WSIZE << 16 |
2395 RT2661_TX_RING_COUNT << 8 | /* XXX: HCCA ring unused */
2396 RT2661_MGT_RING_COUNT);
2397
2398 /* initialize Rx rings */
2399 RAL_WRITE(sc, RT2661_RX_RING_CSR,
2400 RT2661_RX_DESC_BACK << 16 |
2401 RT2661_RX_DESC_WSIZE << 8 |
2402 RT2661_RX_RING_COUNT);
2403
2404 /* XXX: some magic here */
2405 RAL_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa);
2406
2407 /* load base addresses of all 5 Tx rings (4 data + 1 mgt) */
2408 RAL_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f);
2409
2410 /* load base address of Rx ring */
2411 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 2);
2412
2413 /* initialize MAC registers to default values */
2414 for (i = 0; i < N(rt2661_def_mac); i++)
2415 RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val);
2416
2417 rt2661_set_macaddr(sc, IF_LLADDR(ifp));
2418
2419 /* set host ready */
2420 RAL_WRITE(sc, RT2661_MAC_CSR1, 3);
2421 RAL_WRITE(sc, RT2661_MAC_CSR1, 0);
2422
2423 /* wait for BBP/RF to wakeup */
2424 for (ntries = 0; ntries < 1000; ntries++) {
2425 if (RAL_READ(sc, RT2661_MAC_CSR12) & 8)
2426 break;
2427 DELAY(1000);
2428 }
2429 if (ntries == 1000) {
2430 printf("timeout waiting for BBP/RF to wakeup\n");
2431 rt2661_stop_locked(sc);
2432 return;
2433 }
2434
2435 if (rt2661_bbp_init(sc) != 0) {
2436 rt2661_stop_locked(sc);
2437 return;
2438 }
2439
2440 /* select default channel */
2441 sc->sc_curchan = ic->ic_curchan;
2442 rt2661_select_band(sc, sc->sc_curchan);
2443 rt2661_select_antenna(sc);
2444 rt2661_set_chan(sc, sc->sc_curchan);
2445
2446 /* update Rx filter */
2447 tmp = RAL_READ(sc, RT2661_TXRX_CSR0) & 0xffff;
2448
2449 tmp |= RT2661_DROP_PHY_ERROR | RT2661_DROP_CRC_ERROR;
2450 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
2451 tmp |= RT2661_DROP_CTL | RT2661_DROP_VER_ERROR |
2452 RT2661_DROP_ACKCTS;
2453 if (ic->ic_opmode != IEEE80211_M_HOSTAP)
2454 tmp |= RT2661_DROP_TODS;
2455 if (!(ifp->if_flags & IFF_PROMISC))
2456 tmp |= RT2661_DROP_NOT_TO_ME;
2457 }
2458
2459 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
2460
2461 /* clear STA registers */
2462 RAL_READ_REGION_4(sc, RT2661_STA_CSR0, sta, N(sta));
2463
2464 /* initialize ASIC */
2465 RAL_WRITE(sc, RT2661_MAC_CSR1, 4);
2466
2467 /* clear any pending interrupt */
2468 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff);
2469
2470 /* enable interrupts */
2471 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10);
2472 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0);
2473
2474 /* kick Rx */
2475 RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 1);
2476
2477 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2478 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2479
2480 callout_reset(&sc->watchdog_ch, hz, rt2661_watchdog, sc);
2481#undef N
2482}
2483
2484static void
2485rt2661_init(void *priv)
2486{
2487 struct rt2661_softc *sc = priv;
2488 struct ifnet *ifp = sc->sc_ifp;
2489 struct ieee80211com *ic = ifp->if_l2com;
2490
2491 RAL_LOCK(sc);
2492 rt2661_init_locked(sc);
2493 RAL_UNLOCK(sc);
2494
2495 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2496 ieee80211_start_all(ic); /* start all vap's */
2497}
2498
2499void
2500rt2661_stop_locked(struct rt2661_softc *sc)
2501{
2502 struct ifnet *ifp = sc->sc_ifp;
2503 uint32_t tmp;
2504 volatile int *flags = &sc->sc_flags;
2505
2506 while (*flags & RAL_INPUT_RUNNING)
2507 msleep(sc, &sc->sc_mtx, 0, "ralrunning", hz/10);
2508
2509 callout_stop(&sc->watchdog_ch);
2510 sc->sc_tx_timer = 0;
2511
2512 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2513 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2514
2515 /* abort Tx (for all 5 Tx rings) */
2516 RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16);
2517
2518 /* disable Rx (value remains after reset!) */
2519 tmp = RAL_READ(sc, RT2661_TXRX_CSR0);
2520 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX);
2521
2522 /* reset ASIC */
2523 RAL_WRITE(sc, RT2661_MAC_CSR1, 3);
2524 RAL_WRITE(sc, RT2661_MAC_CSR1, 0);
2525
2526 /* disable interrupts */
2527 RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffffff);
2528 RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff);
2529
2530 /* clear any pending interrupt */
2531 RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff);
2532 RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff);
2533
2534 /* reset Tx and Rx rings */
2535 rt2661_reset_tx_ring(sc, &sc->txq[0]);
2536 rt2661_reset_tx_ring(sc, &sc->txq[1]);
2537 rt2661_reset_tx_ring(sc, &sc->txq[2]);
2538 rt2661_reset_tx_ring(sc, &sc->txq[3]);
2539 rt2661_reset_tx_ring(sc, &sc->mgtq);
2540 rt2661_reset_rx_ring(sc, &sc->rxq);
2541 }
2542}
2543
2544void
2545rt2661_stop(void *priv)
2546{
2547 struct rt2661_softc *sc = priv;
2548
2549 RAL_LOCK(sc);
2550 rt2661_stop_locked(sc);
2551 RAL_UNLOCK(sc);
2552}
2553
2554static int
2555rt2661_load_microcode(struct rt2661_softc *sc)
2556{
2557 struct ifnet *ifp = sc->sc_ifp;
2558 const struct firmware *fp;
2559 const char *imagename;
2560 int ntries, error;
2561
2562 RAL_LOCK_ASSERT(sc);
2563
2564 switch (sc->sc_id) {
2565 case 0x0301: imagename = "rt2561sfw"; break;
2566 case 0x0302: imagename = "rt2561fw"; break;
2567 case 0x0401: imagename = "rt2661fw"; break;
2568 default:
2569 if_printf(ifp, "%s: unexpected pci device id 0x%x, "
2570 "don't know how to retrieve firmware\n",
2571 __func__, sc->sc_id);
2572 return EINVAL;
2573 }
2574 RAL_UNLOCK(sc);
2575 fp = firmware_get(imagename);
2576 RAL_LOCK(sc);
2577 if (fp == NULL) {
2578 if_printf(ifp, "%s: unable to retrieve firmware image %s\n",
2579 __func__, imagename);
2580 return EINVAL;
2581 }
2582
2583 /*
2584 * Load 8051 microcode into NIC.
2585 */
2586 /* reset 8051 */
2587 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET);
2588
2589 /* cancel any pending Host to MCU command */
2590 RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0);
2591 RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff);
2592 RAL_WRITE(sc, RT2661_HOST_CMD_CSR, 0);
2593
2594 /* write 8051's microcode */
2595 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET | RT2661_MCU_SEL);
2596 RAL_WRITE_REGION_1(sc, RT2661_MCU_CODE_BASE, fp->data, fp->datasize);
2597 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET);
2598
2599 /* kick 8051's ass */
2600 RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, 0);
2601
2602 /* wait for 8051 to initialize */
2603 for (ntries = 0; ntries < 500; ntries++) {
2604 if (RAL_READ(sc, RT2661_MCU_CNTL_CSR) & RT2661_MCU_READY)
2605 break;
2606 DELAY(100);
2607 }
2608 if (ntries == 500) {
2609 if_printf(ifp, "%s: timeout waiting for MCU to initialize\n",
2610 __func__);
2611 error = EIO;
2612 } else
2613 error = 0;
2614
2615 firmware_put(fp, FIRMWARE_UNLOAD);
2616 return error;
2617}
2618
2619#ifdef notyet
2620/*
2621 * Dynamically tune Rx sensitivity (BBP register 17) based on average RSSI and
2622 * false CCA count. This function is called periodically (every seconds) when
2623 * in the RUN state. Values taken from the reference driver.
2624 */
2625static void
2626rt2661_rx_tune(struct rt2661_softc *sc)
2627{
2628 uint8_t bbp17;
2629 uint16_t cca;
2630 int lo, hi, dbm;
2631
2632 /*
2633 * Tuning range depends on operating band and on the presence of an
2634 * external low-noise amplifier.
2635 */
2636 lo = 0x20;
2637 if (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan))
2638 lo += 0x08;
2639 if ((IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan) && sc->ext_2ghz_lna) ||
2640 (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan) && sc->ext_5ghz_lna))
2641 lo += 0x10;
2642 hi = lo + 0x20;
2643
2644 /* retrieve false CCA count since last call (clear on read) */
2645 cca = RAL_READ(sc, RT2661_STA_CSR1) & 0xffff;
2646
2647 if (dbm >= -35) {
2648 bbp17 = 0x60;
2649 } else if (dbm >= -58) {
2650 bbp17 = hi;
2651 } else if (dbm >= -66) {
2652 bbp17 = lo + 0x10;
2653 } else if (dbm >= -74) {
2654 bbp17 = lo + 0x08;
2655 } else {
2656 /* RSSI < -74dBm, tune using false CCA count */
2657
2658 bbp17 = sc->bbp17; /* current value */
2659
2660 hi -= 2 * (-74 - dbm);
2661 if (hi < lo)
2662 hi = lo;
2663
2664 if (bbp17 > hi) {
2665 bbp17 = hi;
2666
2667 } else if (cca > 512) {
2668 if (++bbp17 > hi)
2669 bbp17 = hi;
2670 } else if (cca < 100) {
2671 if (--bbp17 < lo)
2672 bbp17 = lo;
2673 }
2674 }
2675
2676 if (bbp17 != sc->bbp17) {
2677 rt2661_bbp_write(sc, 17, bbp17);
2678 sc->bbp17 = bbp17;
2679 }
2680}
2681
2682/*
2683 * Enter/Leave radar detection mode.
2684 * This is for 802.11h additional regulatory domains.
2685 */
2686static void
2687rt2661_radar_start(struct rt2661_softc *sc)
2688{
2689 uint32_t tmp;
2690
2691 /* disable Rx */
2692 tmp = RAL_READ(sc, RT2661_TXRX_CSR0);
2693 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX);
2694
2695 rt2661_bbp_write(sc, 82, 0x20);
2696 rt2661_bbp_write(sc, 83, 0x00);
2697 rt2661_bbp_write(sc, 84, 0x40);
2698
2699 /* save current BBP registers values */
2700 sc->bbp18 = rt2661_bbp_read(sc, 18);
2701 sc->bbp21 = rt2661_bbp_read(sc, 21);
2702 sc->bbp22 = rt2661_bbp_read(sc, 22);
2703 sc->bbp16 = rt2661_bbp_read(sc, 16);
2704 sc->bbp17 = rt2661_bbp_read(sc, 17);
2705 sc->bbp64 = rt2661_bbp_read(sc, 64);
2706
2707 rt2661_bbp_write(sc, 18, 0xff);
2708 rt2661_bbp_write(sc, 21, 0x3f);
2709 rt2661_bbp_write(sc, 22, 0x3f);
2710 rt2661_bbp_write(sc, 16, 0xbd);
2711 rt2661_bbp_write(sc, 17, sc->ext_5ghz_lna ? 0x44 : 0x34);
2712 rt2661_bbp_write(sc, 64, 0x21);
2713
2714 /* restore Rx filter */
2715 RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
2716}
2717
2718static int
2719rt2661_radar_stop(struct rt2661_softc *sc)
2720{
2721 uint8_t bbp66;
2722
2723 /* read radar detection result */
2724 bbp66 = rt2661_bbp_read(sc, 66);
2725
2726 /* restore BBP registers values */
2727 rt2661_bbp_write(sc, 16, sc->bbp16);
2728 rt2661_bbp_write(sc, 17, sc->bbp17);
2729 rt2661_bbp_write(sc, 18, sc->bbp18);
2730 rt2661_bbp_write(sc, 21, sc->bbp21);
2731 rt2661_bbp_write(sc, 22, sc->bbp22);
2732 rt2661_bbp_write(sc, 64, sc->bbp64);
2733
2734 return bbp66 == 1;
2735}
2736#endif
2737
2738static int
2739rt2661_prepare_beacon(struct rt2661_softc *sc, struct ieee80211vap *vap)
2740{
2741 struct ieee80211com *ic = vap->iv_ic;
2742 struct ieee80211_beacon_offsets bo;
2743 struct rt2661_tx_desc desc;
2744 struct mbuf *m0;
2745 int rate;
2746
2747 m0 = ieee80211_beacon_alloc(vap->iv_bss, &bo);
2748 if (m0 == NULL) {
2749 device_printf(sc->sc_dev, "could not allocate beacon frame\n");
2750 return ENOBUFS;
2751 }
2752
2753 /* send beacons at the lowest available rate */
2754 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan) ? 12 : 2;
2755
2756 rt2661_setup_tx_desc(sc, &desc, RT2661_TX_TIMESTAMP, RT2661_TX_HWSEQ,
2757 m0->m_pkthdr.len, rate, NULL, 0, RT2661_QID_MGT);
2758
2759 /* copy the first 24 bytes of Tx descriptor into NIC memory */
2760 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0, (uint8_t *)&desc, 24);
2761
2762 /* copy beacon header and payload into NIC memory */
2763 RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0 + 24,
2764 mtod(m0, uint8_t *), m0->m_pkthdr.len);
2765
2766 m_freem(m0);
2767
2768 return 0;
2769}
2770
2771/*
2772 * Enable TSF synchronization and tell h/w to start sending beacons for IBSS
2773 * and HostAP operating modes.
2774 */
2775static void
2776rt2661_enable_tsf_sync(struct rt2661_softc *sc)
2777{
2778 struct ifnet *ifp = sc->sc_ifp;
2779 struct ieee80211com *ic = ifp->if_l2com;
2780 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
2781 uint32_t tmp;
2782
2783 if (vap->iv_opmode != IEEE80211_M_STA) {
2784 /*
2785 * Change default 16ms TBTT adjustment to 8ms.
2786 * Must be done before enabling beacon generation.
2787 */
2788 RAL_WRITE(sc, RT2661_TXRX_CSR10, 1 << 12 | 8);
2789 }
2790
2791 tmp = RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000;
2792
2793 /* set beacon interval (in 1/16ms unit) */
2794 tmp |= vap->iv_bss->ni_intval * 16;
2795
2796 tmp |= RT2661_TSF_TICKING | RT2661_ENABLE_TBTT;
2797 if (vap->iv_opmode == IEEE80211_M_STA)
2798 tmp |= RT2661_TSF_MODE(1);
2799 else
2800 tmp |= RT2661_TSF_MODE(2) | RT2661_GENERATE_BEACON;
2801
2802 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp);
2803}
2804
2805/*
2806 * Retrieve the "Received Signal Strength Indicator" from the raw values
2807 * contained in Rx descriptors. The computation depends on which band the
2808 * frame was received. Correction values taken from the reference driver.
2809 */
2810static int
2811rt2661_get_rssi(struct rt2661_softc *sc, uint8_t raw)
2812{
2813 int lna, agc, rssi;
2814
2815 lna = (raw >> 5) & 0x3;
2816 agc = raw & 0x1f;
2817
2818 if (lna == 0) {
2819 /*
2820 * No mapping available.
2821 *
2822 * NB: Since RSSI is relative to noise floor, -1 is
2823 * adequate for caller to know error happened.
2824 */
2825 return -1;
2826 }
2827
2828 rssi = (2 * agc) - RT2661_NOISE_FLOOR;
2829
2830 if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) {
2831 rssi += sc->rssi_2ghz_corr;
2832
2833 if (lna == 1)
2834 rssi -= 64;
2835 else if (lna == 2)
2836 rssi -= 74;
2837 else if (lna == 3)
2838 rssi -= 90;
2839 } else {
2840 rssi += sc->rssi_5ghz_corr;
2841
2842 if (lna == 1)
2843 rssi -= 64;
2844 else if (lna == 2)
2845 rssi -= 86;
2846 else if (lna == 3)
2847 rssi -= 100;
2848 }
2849 return rssi;
2850}
2851
2852static void
2853rt2661_scan_start(struct ieee80211com *ic)
2854{
2855 struct ifnet *ifp = ic->ic_ifp;
2856 struct rt2661_softc *sc = ifp->if_softc;
2857 uint32_t tmp;
2858
2859 /* abort TSF synchronization */
2860 tmp = RAL_READ(sc, RT2661_TXRX_CSR9);
2861 RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0xffffff);
2862 rt2661_set_bssid(sc, ifp->if_broadcastaddr);
2863}
2864
2865static void
2866rt2661_scan_end(struct ieee80211com *ic)
2867{
2868 struct ifnet *ifp = ic->ic_ifp;
2869 struct rt2661_softc *sc = ifp->if_softc;
2870 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
2871
2872 rt2661_enable_tsf_sync(sc);
2873 /* XXX keep local copy */
2874 rt2661_set_bssid(sc, vap->iv_bss->ni_bssid);
2875}
2876
2877static void
2878rt2661_set_channel(struct ieee80211com *ic)
2879{
2880 struct ifnet *ifp = ic->ic_ifp;
2881 struct rt2661_softc *sc = ifp->if_softc;
2882
2883 RAL_LOCK(sc);
2884 rt2661_set_chan(sc, ic->ic_curchan);
2885
2886 sc->sc_txtap.wt_chan_freq = htole16(ic->ic_curchan->ic_freq);
2887 sc->sc_txtap.wt_chan_flags = htole16(ic->ic_curchan->ic_flags);
2888 sc->sc_rxtap.wr_chan_freq = htole16(ic->ic_curchan->ic_freq);
2889 sc->sc_rxtap.wr_chan_flags = htole16(ic->ic_curchan->ic_flags);
2890 RAL_UNLOCK(sc);
2891
2892}