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pdqreg.h (67899) pdqreg.h (93383)
1/* $NetBSD: pdqreg.h,v 1.14 2001/06/13 10:46:03 wiz Exp $ */
2
1/*-
2 * Copyright (c) 1995, 1996 Matt Thomas <matt@3am-software.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the author may not be used to endorse or promote products
3/*-
4 * Copyright (c) 1995, 1996 Matt Thomas <matt@3am-software.com>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. The name of the author may not be used to endorse or promote products
11 * derived from this software withough specific prior written permission
13 * derived from this software without specific prior written permission
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
24 * $FreeBSD: head/sys/dev/pdq/pdqreg.h 67899 2000-10-29 16:57:42Z phk $
26 * Id: pdqreg.h,v 1.11 1997/03/21 21:16:04 thomas Exp
27 * $FreeBSD: head/sys/dev/pdq/pdqreg.h 93383 2002-03-29 11:22:22Z mdodd $
25 *
26 */
27
28/*
29 * DEC PDQ FDDI Controller; PDQ port driver definitions
30 *
31 */
32
33#ifndef _PDQREG_H
34#define _PDQREG_H
35
28 *
29 */
30
31/*
32 * DEC PDQ FDDI Controller; PDQ port driver definitions
33 *
34 */
35
36#ifndef _PDQREG_H
37#define _PDQREG_H
38
39#if !defined(KERNEL) && !defined(_KERNEL)
40#include <stddef.h>
41#elif !defined(offsetof)
42#define offsetof(t, m) ((char *) (&((t *)0L)->m) - (char *) 0L)
43#endif
36#if defined(PDQTEST) && !defined(PDQ_NDEBUG)
37#include <assert.h>
38#define PDQ_ASSERT assert
39#else
40#define PDQ_ASSERT(x) do { } while(0)
41#endif
42
43#define PDQ_RING_SIZE(array) ((sizeof(array) / sizeof(array[0])))

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298 rxd_seg_len_hi : 9,
299 rxd_seg_len_lo : 2,
300 rxd_sop : 1);
301 pdq_uint32_t rxd_pa_lo;
302} pdq_rxdesc_t;
303
304typedef union {
305 pdq_uint32_t rxs_status;
44#if defined(PDQTEST) && !defined(PDQ_NDEBUG)
45#include <assert.h>
46#define PDQ_ASSERT assert
47#else
48#define PDQ_ASSERT(x) do { } while(0)
49#endif
50
51#define PDQ_RING_SIZE(array) ((sizeof(array) / sizeof(array[0])))

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306 rxd_seg_len_hi : 9,
307 rxd_seg_len_lo : 2,
308 rxd_sop : 1);
309 pdq_uint32_t rxd_pa_lo;
310} pdq_rxdesc_t;
311
312typedef union {
313 pdq_uint32_t rxs_status;
306 pdq_uint32_t PDQ_BITFIELD12(rxs_len : 13,
307 rxs_rcc_ss : 2,
308 rxs_rcc_dd : 2,
309 rxs_rcc_reason : 3,
310 rxs_rcc_badcrc : 1,
311 rxs_rcc_badpdu : 1,
312 rxs_fsb__reserved : 2,
313 rxs_fsb_c : 1,
314 rxs_fsb_a : 1,
315 rxs_fsb_e : 1,
316 rxs_fsc : 3,
317 rxs__reserved : 2);
314 struct {
315 pdq_uint32_t PDQ_BITFIELD12(st_len : 13,
316 st_rcc_ss : 2,
317 st_rcc_dd : 2,
318 st_rcc_reason : 3,
319 st_rcc_badcrc : 1,
320 st_rcc_badpdu : 1,
321 st_fsb__reserved : 2,
322 st_fsb_c : 1,
323 st_fsb_a : 1,
324 st_fsb_e : 1,
325 st_fsc : 3,
326 st__reserved : 2);
327 } rxs_st;
318} pdq_rxstatus_t;
328} pdq_rxstatus_t;
329#define rxs_len rxs_st.st_len
330#define rxs_rcc_ss rxs_st.st_rcc_ss
331#define rxs_rcc_dd rxs_st.st_rcc_dd
332#define rxs_rcc_reason rxs_st.st_rcc_reason
333#define rxs_rcc_badcrc rxs_st.st_rcc_badcrc
334#define rxs_rcc_badpdu rxs_st.st_rcc_badpdu
335#define rxs_fsb_c rxs_st.st_fsb_c
336#define rxs_fsb_a rxs_st.st_fsb_a
337#define rxs_fsb_e rxs_st.st_fsb_e
338#define rxs_fsc rxs_st.st_fsc
319
339
340#define PDQ_RXS_RCC_DD_NO_MATCH 0x00
341#define PDQ_RXS_RCC_DD_PROMISC_MATCH 0x01
342#define PDQ_RXS_RCC_DD_CAM_MATCH 0x02
343#define PDQ_RXS_RCC_DD_MLA_MATCH 0x03
344
320typedef struct {
321 pdq_uint32_t PDQ_BITFIELD5(txd_pa_hi : 16,
322 txd_seg_len : 13,
323 txd_mbz : 1,
324 txd_eop : 1,
325 txd_sop : 1);
326 pdq_uint32_t txd_pa_lo;
327} pdq_txdesc_t;

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332 pdq_rxdesc_t pdqdb_host_smt[64]; /* 512; 0x1000..0x11FF */
333 pdq_rxdesc_t pdqdb_unsolicited_events[16]; /* 128; 0x1200..0x127F */
334 pdq_rxdesc_t pdqdb_command_responses[16]; /* 128; 0x1280..0x12FF */
335 pdq_txdesc_t pdqdb_command_requests[16]; /* 128; 0x1300..0x137F */
336 /*
337 * The rest of the descriptor block is unused.
338 * As such we could use it for other things.
339 */
345typedef struct {
346 pdq_uint32_t PDQ_BITFIELD5(txd_pa_hi : 16,
347 txd_seg_len : 13,
348 txd_mbz : 1,
349 txd_eop : 1,
350 txd_sop : 1);
351 pdq_uint32_t txd_pa_lo;
352} pdq_txdesc_t;

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357 pdq_rxdesc_t pdqdb_host_smt[64]; /* 512; 0x1000..0x11FF */
358 pdq_rxdesc_t pdqdb_unsolicited_events[16]; /* 128; 0x1200..0x127F */
359 pdq_rxdesc_t pdqdb_command_responses[16]; /* 128; 0x1280..0x12FF */
360 pdq_txdesc_t pdqdb_command_requests[16]; /* 128; 0x1300..0x137F */
361 /*
362 * The rest of the descriptor block is unused.
363 * As such we could use it for other things.
364 */
340 pdq_consumer_block_t pdqdb_consumer; /* 64; 0x1380..0x13BF */
341 void *pdqdb_receive_buffers[256]; /* 1024/2048; 0x13C0..0x17BF 0x13C0..0x1BBF */
342 void *pdqdb_host_smt_buffers[64]; /* 256/ 512; 0x17C0..0x18BF 0x1BC0..0x1DBF */
365 pdq_uint32_t pdqdb__filler1[16]; /* 64; 0x1380..0x13BF */
366 pdq_consumer_block_t pdqdb_consumer; /* 64; 0x13C0..0x13FF */
343 /*
344 * The maximum command size is 512 so as long as thes
345 * command is at least that long all will be fine.
346 */
367 /*
368 * The maximum command size is 512 so as long as thes
369 * command is at least that long all will be fine.
370 */
347#if defined(__alpha) || defined(__alpha__)
348 pdq_uint32_t pdqdb_command_pool[144];
349#else
350 pdq_uint32_t pdqdb_command_pool[464];
351#endif
371 pdq_uint32_t pdqdb__filler2[64]; /* 256; 0x1400..0x14FF */
372 pdq_uint8_t pdqdb_cmd_request_buf[1024]; /* 1024; 0x1500..0x18FF */
373 pdq_uint8_t pdqdb_cmd_response_buf[1024]; /* 1024; 0x1900..0x1CFF */
374 pdq_uint32_t pdqdb__filler3[128]; /* 512; 0x1D00..0x1EFF */
375 pdq_uint8_t pdqdb_tx_hdr[4]; /* 4; 0x1F00..0x1F03 */
376 pdq_uint32_t pdqdb__filler4[63]; /* 252; 0x1F04..0x1FFF */
352} pdq_descriptor_block_t;
353
377} pdq_descriptor_block_t;
378
379#define PDQ_SIZE_COMMAND_RESPONSE 512
380
381typedef enum {
382 PDQC_START=0,
383 PDQC_FILTER_SET=1,
384 PDQC_FILTER_GET=2,
385 PDQC_CHARS_SET=3,
386 PDQC_STATUS_CHARS_GET=4,
387 PDQC_COUNTERS_GET=5,
388 PDQC_COUNTERS_SET=6,
389 PDQC_ADDR_FILTER_SET=7,
390 PDQC_ADDR_FILTER_GET=8,
391 PDQC_ERROR_LOG_CLEAR=9,
392 PDQC_ERROR_LOG_GET=10,
393 PDQC_FDDI_MIB_GET=11,
394 PDQC_DEC_EXT_MIB_GET=12,
395 PDQC_DEV_SPECIFIC_GET=13,
396 PDQC_SNMP_SET=14,
397 PDQC_SMT_MIB_GET=16,
398 PDQC_SMT_MIB_SET=17,
399 PDQC_BOGUS_CMD=18
400} pdq_cmd_code_t;
401
354typedef struct {
355 /*
356 * These value manage the available space in command/response
357 * buffer area.
358 */
402typedef struct {
403 /*
404 * These value manage the available space in command/response
405 * buffer area.
406 */
359 pdq_physaddr_t ci_pa_bufstart;
360 pdq_uint8_t *ci_bufstart;
407 pdq_physaddr_t ci_pa_request_bufstart;
408 pdq_uint8_t *ci_request_bufstart;
409 pdq_physaddr_t ci_pa_response_bufstart;
410 pdq_uint8_t *ci_response_bufstart;
361 /*
362 * Bitmask of commands to sent to the PDQ
363 */
364 pdq_uint32_t ci_pending_commands;
365 /*
366 * Variables to maintain the PDQ queues.
367 */
368 pdq_uint32_t ci_command_active;
369 pdq_uint32_t ci_request_producer;
370 pdq_uint32_t ci_response_producer;
371 pdq_uint32_t ci_request_completion;
372 pdq_uint32_t ci_response_completion;
411 /*
412 * Bitmask of commands to sent to the PDQ
413 */
414 pdq_uint32_t ci_pending_commands;
415 /*
416 * Variables to maintain the PDQ queues.
417 */
418 pdq_uint32_t ci_command_active;
419 pdq_uint32_t ci_request_producer;
420 pdq_uint32_t ci_response_producer;
421 pdq_uint32_t ci_request_completion;
422 pdq_uint32_t ci_response_completion;
423 /*
424 *
425 */
426 pdq_physaddr_t ci_pa_request_descriptors;
427 pdq_physaddr_t ci_pa_response_descriptors;
428
429 pdq_cmd_code_t ci_queued_commands[16];
373} pdq_command_info_t;
374
375#define PDQ_SIZE_UNSOLICITED_EVENT 512
376#define PDQ_NUM_UNSOLICITED_EVENTS (PDQ_OS_PAGESIZE / PDQ_SIZE_UNSOLICITED_EVENT)
377
378typedef struct _pdq_unsolicited_event_t pdq_unsolicited_event_t;
379
380typedef struct {
381 pdq_physaddr_t ui_pa_bufstart;
430} pdq_command_info_t;
431
432#define PDQ_SIZE_UNSOLICITED_EVENT 512
433#define PDQ_NUM_UNSOLICITED_EVENTS (PDQ_OS_PAGESIZE / PDQ_SIZE_UNSOLICITED_EVENT)
434
435typedef struct _pdq_unsolicited_event_t pdq_unsolicited_event_t;
436
437typedef struct {
438 pdq_physaddr_t ui_pa_bufstart;
439 pdq_physaddr_t ui_pa_descriptors;
382 pdq_unsolicited_event_t *ui_events;
383
384 pdq_uint32_t ui_free;
385 pdq_uint32_t ui_producer;
386 pdq_uint32_t ui_completion;
387} pdq_unsolicited_info_t;
388
389#define PDQ_RX_FC_OFFSET (sizeof(pdq_rxstatus_t) + 3)

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404
405typedef struct {
406 void *q_head;
407 void *q_tail;
408} pdq_databuf_queue_t;
409
410typedef struct {
411 void *rx_buffers;
440 pdq_unsolicited_event_t *ui_events;
441
442 pdq_uint32_t ui_free;
443 pdq_uint32_t ui_producer;
444 pdq_uint32_t ui_completion;
445} pdq_unsolicited_info_t;
446
447#define PDQ_RX_FC_OFFSET (sizeof(pdq_rxstatus_t) + 3)

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462
463typedef struct {
464 void *q_head;
465 void *q_tail;
466} pdq_databuf_queue_t;
467
468typedef struct {
469 void *rx_buffers;
470 pdq_physaddr_t rx_pa_descriptors;
412
413 pdq_uint32_t rx_target;
414 pdq_uint32_t rx_free;
415 pdq_uint32_t rx_producer;
416 pdq_uint32_t rx_completion;
417} pdq_rx_info_t;
418
419typedef struct {
420 pdq_databuf_queue_t tx_txq;
421 pdq_txdesc_t tx_hdrdesc;
422 pdq_uint8_t tx_descriptor_count[256];
471
472 pdq_uint32_t rx_target;
473 pdq_uint32_t rx_free;
474 pdq_uint32_t rx_producer;
475 pdq_uint32_t rx_completion;
476} pdq_rx_info_t;
477
478typedef struct {
479 pdq_databuf_queue_t tx_txq;
480 pdq_txdesc_t tx_hdrdesc;
481 pdq_uint8_t tx_descriptor_count[256];
482 pdq_physaddr_t tx_pa_descriptors;
423
424 pdq_uint32_t tx_free;
425 pdq_uint32_t tx_producer;
426 pdq_uint32_t tx_completion;
427} pdq_tx_info_t;
428
483
484 pdq_uint32_t tx_free;
485 pdq_uint32_t tx_producer;
486 pdq_uint32_t tx_completion;
487} pdq_tx_info_t;
488
489typedef struct _pdq_os_ctx_t pdq_os_ctx_t;
429struct _pdq_t {
430 pdq_csrs_t pdq_csrs;
431 pdq_pci_csrs_t pdq_pci_csrs;
432 pdq_type_t pdq_type;
433 pdq_chip_rev_t pdq_chip_rev;
434 pdq_lanaddr_t pdq_hwaddr;
435 pdq_fwrev_t pdq_fwrev;
436 pdq_descriptor_block_t *pdq_dbp;
437 volatile pdq_consumer_block_t *pdq_cbp;
490struct _pdq_t {
491 pdq_csrs_t pdq_csrs;
492 pdq_pci_csrs_t pdq_pci_csrs;
493 pdq_type_t pdq_type;
494 pdq_chip_rev_t pdq_chip_rev;
495 pdq_lanaddr_t pdq_hwaddr;
496 pdq_fwrev_t pdq_fwrev;
497 pdq_descriptor_block_t *pdq_dbp;
498 volatile pdq_consumer_block_t *pdq_cbp;
499 pdq_uint32_t pdq_intrmask;
438 pdq_uint32_t pdq_flags;
439#define PDQ_PROMISC 0x0001
440#define PDQ_ALLMULTI 0x0002
441#define PDQ_PASS_SMT 0x0004
442#define PDQ_RUNNING 0x0008
443#define PDQ_PRINTCHARS 0x0010
444#define PDQ_TXOK 0x0020
500 pdq_uint32_t pdq_flags;
501#define PDQ_PROMISC 0x0001
502#define PDQ_ALLMULTI 0x0002
503#define PDQ_PASS_SMT 0x0004
504#define PDQ_RUNNING 0x0008
505#define PDQ_PRINTCHARS 0x0010
506#define PDQ_TXOK 0x0020
507#define PDQ_WANT_FDX 0x0040
508#define PDQ_IS_FDX 0x0080
509#define PDQ_IS_ONRING 0x0100
445 const char *pdq_os_name;
510 const char *pdq_os_name;
446 void *pdq_os_ctx;
511 pdq_os_ctx_t *pdq_os_ctx;
447 pdq_uint32_t pdq_unit;
448 pdq_command_info_t pdq_command_info;
449 pdq_unsolicited_info_t pdq_unsolicited_info;
450 pdq_tx_info_t pdq_tx_info;
451 pdq_rx_info_t pdq_rx_info;
452 pdq_rx_info_t pdq_host_smt_info;
512 pdq_uint32_t pdq_unit;
513 pdq_command_info_t pdq_command_info;
514 pdq_unsolicited_info_t pdq_unsolicited_info;
515 pdq_tx_info_t pdq_tx_info;
516 pdq_rx_info_t pdq_rx_info;
517 pdq_rx_info_t pdq_host_smt_info;
453 pdq_uint8_t pdq_tx_hdr[3];
518 void *pdq_receive_buffers[256];
519 void *pdq_host_smt_buffers[64];
520 pdq_physaddr_t pdq_pa_consumer_block;
521 pdq_physaddr_t pdq_pa_descriptor_block;
454};
455
522};
523
456typedef enum {
457 PDQC_START=0,
458 PDQC_FILTER_SET=1,
459 PDQC_FILTER_GET=2,
460 PDQC_CHARS_SET=3,
461 PDQC_STATUS_CHARS_GET=4,
462 PDQC_COUNTERS_GET=5,
463 PDQC_COUNTERS_SET=6,
464 PDQC_ADDR_FILTER_SET=7,
465 PDQC_ADDR_FILTER_GET=8,
466 PDQC_ERROR_LOG_CLEAR=9,
467 PDQC_ERROR_LOG_GET=10,
468 PDQC_FDDI_MIB_GET=11,
469 PDQC_DEC_EXT_MIB_GET=12,
470 PDQC_DEV_SPECIFIC_GET=13,
471 PDQC_SNMP_SET=14,
472 PDQC_SMT_MIB_GET=16,
473 PDQC_SMT_MIB_SET=17
474} pdq_cmd_code_t;
524#define PDQ_DB_BUSPA(pdq, m) \
525 ((pdq)->pdq_pa_descriptor_block + \
526 ((u_int8_t *) (m) - (u_int8_t *) (pdq)->pdq_dbp))
475
527
528
476typedef enum {
477 PDQR_SUCCESS=0,
478 PDQR_FAILURE=1,
479 PDQR_WARNING=2,
480 PDQR_LOOP_MODE_BAD=3,
481 PDQR_ITEM_CODE_BAD=4,
482 PDQR_TVX_BAD=5,
483 PDQR_TREQ_BAD=6,

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551 PDQI_PATH_TMAX_LOWER_BOUND=39,
552 PDQI_PATH_MAX_TREQ=40,
553 PDQI_MAC_TREQ=41,
554 PDQI_EMAC_RING_PURGER=42,
555 PDQI_EMAC_RTOKEN_TIMEOUT=43,
556 PDQI_FULL_DUPLEX_ENABLE=44
557} pdq_item_code_t;
558
529typedef enum {
530 PDQR_SUCCESS=0,
531 PDQR_FAILURE=1,
532 PDQR_WARNING=2,
533 PDQR_LOOP_MODE_BAD=3,
534 PDQR_ITEM_CODE_BAD=4,
535 PDQR_TVX_BAD=5,
536 PDQR_TREQ_BAD=6,

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604 PDQI_PATH_TMAX_LOWER_BOUND=39,
605 PDQI_PATH_MAX_TREQ=40,
606 PDQI_MAC_TREQ=41,
607 PDQI_EMAC_RING_PURGER=42,
608 PDQI_EMAC_RTOKEN_TIMEOUT=43,
609 PDQI_FULL_DUPLEX_ENABLE=44
610} pdq_item_code_t;
611
612typedef enum {
613 PDQSNMP_EOL=0,
614 PDQSNMP_FULL_DUPLEX_ENABLE=0x2F11
615} pdq_snmp_item_code_t;
616
559enum _pdq_boolean_t {
560 PDQ_FALSE=0,
561 PDQ_TRUE=1
562};
563
564typedef enum {
565 PDQ_FILTER_BLOCK=0,
566 PDQ_FILTER_PASS=1

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951 pdq_boolean_t fdx_enable;
952 pdq_boolean_t fdx_operational;
953 pdq_fdx_state_t fdx_state;
954 } dec_ext_mib_get;
955} pdq_response_dec_ext_mib_get_t;
956
957#define PDQ_SIZE_RESPONSE_DEC_EXT_MIB_GET 0x50
958
617enum _pdq_boolean_t {
618 PDQ_FALSE=0,
619 PDQ_TRUE=1
620};
621
622typedef enum {
623 PDQ_FILTER_BLOCK=0,
624 PDQ_FILTER_PASS=1

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1009 pdq_boolean_t fdx_enable;
1010 pdq_boolean_t fdx_operational;
1011 pdq_fdx_state_t fdx_state;
1012 } dec_ext_mib_get;
1013} pdq_response_dec_ext_mib_get_t;
1014
1015#define PDQ_SIZE_RESPONSE_DEC_EXT_MIB_GET 0x50
1016
1017typedef struct {
1018 pdq_cmd_code_t snmp_set_op;
1019 struct {
1020 pdq_item_code_t item_code;
1021 pdq_uint32_t item_value;
1022 pdq_port_type_t item_port;
1023 } snmp_set_items[7];
1024 pdq_item_code_t snmp_set_eol_item_code;
1025} pdq_cmd_snmp_set_t;
1026
959typedef enum {
960 PDQ_CALLER_ID_NONE=0,
961 PDQ_CALLER_ID_SELFTEST=1,
962 PDQ_CALLER_ID_MFG=2,
963 PDQ_CALLER_ID_FIRMWARE=5,
964 PDQ_CALLER_ID_CONSOLE=8
965} pdq_caller_id_t;
966

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989typedef enum {
990 PDQ_UNSOLICITED_EVENT=0,
991 PDQ_UNSOLICITED_COUNTERS=1
992} pdq_event_t;
993
994typedef enum {
995 PDQ_ENTITY_STATION=0,
996 PDQ_ENTITY_LINK=1,
1027typedef enum {
1028 PDQ_CALLER_ID_NONE=0,
1029 PDQ_CALLER_ID_SELFTEST=1,
1030 PDQ_CALLER_ID_MFG=2,
1031 PDQ_CALLER_ID_FIRMWARE=5,
1032 PDQ_CALLER_ID_CONSOLE=8
1033} pdq_caller_id_t;
1034

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1057typedef enum {
1058 PDQ_UNSOLICITED_EVENT=0,
1059 PDQ_UNSOLICITED_COUNTERS=1
1060} pdq_event_t;
1061
1062typedef enum {
1063 PDQ_ENTITY_STATION=0,
1064 PDQ_ENTITY_LINK=1,
997 PDQ_ENTITY_PHY_PORT=2
1065 PDQ_ENTITY_PHY_PORT=2,
1066 PDQ_ENTITY_MAX=3
998} pdq_entity_t;
999
1000typedef enum {
1067} pdq_entity_t;
1068
1069typedef enum {
1001 PDQ_STATION_EVENT_TRACE_RECEIVED=1
1070 PDQ_STATION_EVENT_TRACE_RECEIVED=1,
1071 PDQ_STATION_EVENT_MAX=2
1002} pdq_station_event_t;
1003
1004typedef enum {
1005 PDQ_STATION_EVENT_ARGUMENT_REASON=0, /* pdq_uint32_t */
1006 PDQ_STATION_EVENT_ARGUMENT_EOL=0xFF
1007} pdq_station_event_argument_t;
1008
1009typedef enum {

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1017 PDQ_LINK_EVENT_RING_INITIALIZATION_INITIATED=10,
1018 PDQ_LINK_EVENT_RING_INITIALIZATION_RECEIVED=11,
1019 PDQ_LINK_EVENT_RING_BEACON_INITIATED=12,
1020 PDQ_LINK_EVENT_DUPLICATE_ADDRESS_FAILURE=13,
1021 PDQ_LINK_EVENT_DUPLICATE_TOKEN_DETECTED=14,
1022 PDQ_LINK_EVENT_RING_PURGE_ERROR=15,
1023 PDQ_LINK_EVENT_FCI_STRIP_ERROR=16,
1024 PDQ_LINK_EVENT_TRACE_INITIATED=17,
1072} pdq_station_event_t;
1073
1074typedef enum {
1075 PDQ_STATION_EVENT_ARGUMENT_REASON=0, /* pdq_uint32_t */
1076 PDQ_STATION_EVENT_ARGUMENT_EOL=0xFF
1077} pdq_station_event_argument_t;
1078
1079typedef enum {

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1087 PDQ_LINK_EVENT_RING_INITIALIZATION_INITIATED=10,
1088 PDQ_LINK_EVENT_RING_INITIALIZATION_RECEIVED=11,
1089 PDQ_LINK_EVENT_RING_BEACON_INITIATED=12,
1090 PDQ_LINK_EVENT_DUPLICATE_ADDRESS_FAILURE=13,
1091 PDQ_LINK_EVENT_DUPLICATE_TOKEN_DETECTED=14,
1092 PDQ_LINK_EVENT_RING_PURGE_ERROR=15,
1093 PDQ_LINK_EVENT_FCI_STRIP_ERROR=16,
1094 PDQ_LINK_EVENT_TRACE_INITIATED=17,
1025 PDQ_LINK_EVENT_DIRECTED_BEACON_RECEIVED=18
1095 PDQ_LINK_EVENT_DIRECTED_BEACON_RECEIVED=18,
1096 PDQ_LINK_EVENT_MAX=19
1026} pdq_link_event_t;
1027
1028typedef enum {
1029 PDQ_LINK_EVENT_ARGUMENT_REASON=0, /* pdq_rireason_t */
1030 PDQ_LINK_EVENT_ARGUMENT_DATA_LINK_HEADER=1, /* pdq_dlhdr_t */
1031 PDQ_LINK_EVENT_ARGUMENT_SOURCE=2, /* pdq_lanaddr_t */
1032 PDQ_LINK_EVENT_ARGUMENT_UPSTREAM_NEIGHBOR=3,/* pdq_lanaddr_t */
1033 PDQ_LINK_EVENT_ARGUMENT_EOL=0xFF
1034} pdq_link_event_argument_t;
1035
1036typedef enum {
1037 PDQ_PHY_EVENT_LEM_ERROR_MONITOR_REJECT=0,
1038 PDQ_PHY_EVENT_ELASTICITY_BUFFER_ERROR=1,
1097} pdq_link_event_t;
1098
1099typedef enum {
1100 PDQ_LINK_EVENT_ARGUMENT_REASON=0, /* pdq_rireason_t */
1101 PDQ_LINK_EVENT_ARGUMENT_DATA_LINK_HEADER=1, /* pdq_dlhdr_t */
1102 PDQ_LINK_EVENT_ARGUMENT_SOURCE=2, /* pdq_lanaddr_t */
1103 PDQ_LINK_EVENT_ARGUMENT_UPSTREAM_NEIGHBOR=3,/* pdq_lanaddr_t */
1104 PDQ_LINK_EVENT_ARGUMENT_EOL=0xFF
1105} pdq_link_event_argument_t;
1106
1107typedef enum {
1108 PDQ_PHY_EVENT_LEM_ERROR_MONITOR_REJECT=0,
1109 PDQ_PHY_EVENT_ELASTICITY_BUFFER_ERROR=1,
1039 PDQ_PHY_EVENT_LINK_CONFIDENCE_TEST_REJECT=2
1110 PDQ_PHY_EVENT_LINK_CONFIDENCE_TEST_REJECT=2,
1111 PDQ_PHY_EVENT_MAX=3
1040} pdq_phy_event_t;
1041
1042typedef enum {
1043 PDQ_PHY_EVENT_ARGUMENT_DIRECTION=0, /* pdq_lct_direction_t */
1044 PDQ_PHY_EVENT_ARGUMENT_EOL=0xFF
1045} pdq_phy_event_arguments;
1046
1047struct _pdq_unsolicited_event_t {

--- 17 unchanged lines hidden --- 		1112} pdq_phy_event_t;
1113
1114typedef enum {
1115 PDQ_PHY_EVENT_ARGUMENT_DIRECTION=0, /* pdq_lct_direction_t */
1116 PDQ_PHY_EVENT_ARGUMENT_EOL=0xFF
1117} pdq_phy_event_arguments;
1118
1119struct _pdq_unsolicited_event_t {

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