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if_fpa.c (70594) if_fpa.c (93383)
1/*-
2 * Copyright (c) 1995, 1996 Matt Thomas <matt@3am-software.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 7 unchanged lines hidden (view full) ---

16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
1/*-
2 * Copyright (c) 1995, 1996 Matt Thomas <matt@3am-software.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 7 unchanged lines hidden (view full) ---

16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * $FreeBSD: head/sys/dev/pdq/if_fpa.c 70594 2001-01-02 09:30:48Z peter $
24 * $FreeBSD: head/sys/dev/pdq/if_fpa.c 93383 2002-03-29 11:22:22Z mdodd $
25 *
26 */
27
28/*
29 * DEC PDQ FDDI Controller; code for BSD derived operating systems
30 *
31 * This module supports the DEC DEFPA PCI FDDI Controller
32 */
33
34#include <sys/param.h>
25 *
26 */
27
28/*
29 * DEC PDQ FDDI Controller; code for BSD derived operating systems
30 *
31 * This module supports the DEC DEFPA PCI FDDI Controller
32 */
33
34#include <sys/param.h>
35#include <sys/systm.h>
35#include <sys/kernel.h>
36#include <sys/socket.h>
37
36#include <sys/kernel.h>
37#include <sys/socket.h>
38
38#include <net/if.h>
39#include <sys/module.h>
40#include <sys/bus.h>
39
41
40#include <net/ethernet.h>
41#include <net/if_arp.h>
42#include <dev/pdq/pdqvar.h>
43#include <dev/pdq/pdqreg.h>
42#include <machine/bus_memio.h>
43#include <machine/bus_pio.h>
44#include <machine/bus.h>
45#include <machine/resource.h>
44#include <machine/bus.h>
45#include <machine/resource.h>
46#include <sys/bus.h>
47#include <sys/rman.h>
48#include <pci/pcivar.h>
49#include <pci/pcireg.h>
46#include <sys/rman.h>
50
47
48#include <net/if.h>
49#include <net/if_arp.h>
50#include <net/if_media.h>
51#include <net/fddi.h>
51
52
53#include <dev/pci/pcivar.h>
54#include <dev/pci/pcireg.h>
55
56#include <dev/pdq/pdq_freebsd.h>
57#include <dev/pdq/pdqreg.h>
58
52#define DEC_VENDORID 0x1011
53#define DEFPA_CHIPID 0x000F
54
55#define DEFPA_LATENCY 0x88
56
57#define PCI_CFLT 0x0C /* Configuration Latency */
58#define PCI_CBMA 0x10 /* Configuration Base Memory Address */
59#define PCI_CBIO 0x14 /* Configuration Base I/O Address */
60
59#define DEC_VENDORID 0x1011
60#define DEFPA_CHIPID 0x000F
61
62#define DEFPA_LATENCY 0x88
63
64#define PCI_CFLT 0x0C /* Configuration Latency */
65#define PCI_CBMA 0x10 /* Configuration Base Memory Address */
66#define PCI_CBIO 0x14 /* Configuration Base I/O Address */
67
68static int pdq_pci_probe (device_t);
69static int pdq_pci_attach (device_t);
70static int pdq_pci_detach (device_t);
71static void pdq_pci_shutdown (device_t);
72static void pdq_pci_ifintr (void *);
73
61static void
62pdq_pci_ifintr(void *arg)
63{
74static void
75pdq_pci_ifintr(void *arg)
76{
77 device_t dev;
64 pdq_softc_t *sc;
65
78 pdq_softc_t *sc;
79
66 sc = device_get_softc(arg);
80 dev = (device_t)arg;
81 sc = device_get_softc(dev);
82
83 PDQ_LOCK(sc);
67 (void) pdq_interrupt(sc->sc_pdq);
84 (void) pdq_interrupt(sc->sc_pdq);
85 PDQ_UNLOCK(sc);
86
87 return;
68}
69
70/*
71 * This is the PCI configuration support.
72 */
73static int
74pdq_pci_probe(device_t dev)
75{
76 if (pci_get_vendor(dev) == DEC_VENDORID &&
77 pci_get_device(dev) == DEFPA_CHIPID) {
78 device_set_desc(dev, "Digital DEFPA PCI FDDI Controller");
88}
89
90/*
91 * This is the PCI configuration support.
92 */
93static int
94pdq_pci_probe(device_t dev)
95{
96 if (pci_get_vendor(dev) == DEC_VENDORID &&
97 pci_get_device(dev) == DEFPA_CHIPID) {
98 device_set_desc(dev, "Digital DEFPA PCI FDDI Controller");
79 return 0;
99 return (0);
80 }
100 }
81 return ENXIO;
101
102 return (ENXIO);
82}
83
84static int
85pdq_pci_attach(device_t dev)
86{
87 pdq_softc_t *sc;
103}
104
105static int
106pdq_pci_attach(device_t dev)
107{
108 pdq_softc_t *sc;
88 int data;
89 struct resource *memres, *irqres;
90 int rid;
91 void *ih;
109 struct ifnet *ifp;
110 u_int32_t command;
111 int error;
92
112
93 memres = NULL;
94 irqres = NULL;
95 sc = device_get_softc(dev);
113 sc = device_get_softc(dev);
114 ifp = &sc->arpcom.ac_if;
96
115
97 data = pci_read_config(dev, PCIR_LATTIMER, 1);
98 if (data < DEFPA_LATENCY) {
99 data = DEFPA_LATENCY;
100 pci_write_config(dev, PCIR_LATTIMER, data, 1);
116 sc->dev = dev;
117
118 /*
119 * Map control/status registers.
120 */
121 pci_enable_busmaster(dev);
122 pci_enable_io(dev, SYS_RES_IOPORT);
123 pci_enable_io(dev, SYS_RES_MEMORY);
124 command = pci_read_config(dev, PCIR_COMMAND, 4);
125
126 if (!(command & PCIM_CMD_PORTEN)) {
127 device_printf(dev, "Failed to enable PCI I/O ports.\n");
128 error = ENXIO;
129 goto bad;
101 }
102
130 }
131
103 rid = PCI_CBMA;
104 memres = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 0, ~0, 1, RF_ACTIVE);
105 if (!memres)
132 if (!(command & PCIM_CMD_MEMEN)) {
133 device_printf(dev, "Failed to enable PCI memory mapping.\n");
134 error = ENXIO;
106 goto bad;
135 goto bad;
136 }
107
137
108 sc->sc_if.if_name = "fpa";
109 sc->sc_if.if_unit = device_get_unit(dev);
110 sc->sc_membase = (pdq_bus_memaddr_t) rman_get_virtual(memres);
111 sc->sc_pdq = pdq_initialize(PDQ_BUS_PCI, sc->sc_membase,
112 sc->sc_if.if_name, sc->sc_if.if_unit,
113 (void *) sc, PDQ_DEFPA);
114 if (sc->sc_pdq == NULL)
138 command = pci_read_config(dev, PCIR_LATTIMER, 1);
139 if (command < DEFPA_LATENCY) {
140 command = DEFPA_LATENCY;
141 pci_write_config(dev, PCIR_LATTIMER, command, 1);
142 }
143
144 sc->mem_rid = PCI_CBMA;
145 sc->mem_type = SYS_RES_MEMORY;
146 sc->mem = bus_alloc_resource(dev, sc->mem_type, &sc->mem_rid,
147 0, ~0, 1, RF_ACTIVE);
148 if (!sc->mem) {
149 device_printf(dev, "Unable to allocate I/O space resource.\n");
150 error = ENXIO;
115 goto bad;
151 goto bad;
116 bcopy((caddr_t) sc->sc_pdq->pdq_hwaddr.lanaddr_bytes, sc->sc_ac.ac_enaddr, 6);
117 pdq_ifattach(sc, NULL);
118 rid = 0;
119 irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
120 RF_SHAREABLE | RF_ACTIVE);
121 if (!irqres)
152 }
153 sc->mem_bsh = rman_get_bushandle(sc->mem);
154 sc->mem_bst = rman_get_bustag(sc->mem);
155
156 sc->irq_rid = 0;
157 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irq_rid,
158 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE);
159 if (!sc->irq) {
160 device_printf(dev, "Unable to allocate interrupt resource.\n");
161 error = ENXIO;
122 goto bad;
162 goto bad;
123 if (bus_setup_intr(dev, irqres, INTR_TYPE_NET, pdq_pci_ifintr,
124 (void *)dev, &ih))
163 }
164
165 ifp->if_name = "fpa";
166 ifp->if_unit = device_get_unit(dev);
167
168 sc->sc_pdq = pdq_initialize(sc->mem_bst, sc->mem_bsh,
169 ifp->if_name, ifp->if_unit,
170 (void *)sc, PDQ_DEFPA);
171 if (sc->sc_pdq == NULL) {
172 device_printf(dev, "Initialization failed.\n");
173 error = ENXIO;
125 goto bad;
174 goto bad;
126 return 0;
175 }
127
176
177 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET,
178 pdq_pci_ifintr, dev, &sc->irq_ih);
179 if (error) {
180 device_printf(dev, "Failed to setup interrupt handler.\n");
181 error = ENXIO;
182 goto bad;
183 }
184
185 bcopy((caddr_t) sc->sc_pdq->pdq_hwaddr.lanaddr_bytes,
186 (caddr_t) sc->arpcom.ac_enaddr, FDDI_ADDR_LEN);
187 pdq_ifattach(sc);
188
189 return (0);
128bad:
190bad:
129 if (memres)
130 bus_release_resource(dev, SYS_RES_MEMORY, PCI_CBMA, memres);
131 if (irqres)
132 bus_release_resource(dev, SYS_RES_IRQ, 0, irqres);
133 return ENXIO;
191 pdq_free(dev);
192 return (error);
134}
135
193}
194
195static int
196pdq_pci_detach (dev)
197 device_t dev;
198{
199 pdq_softc_t *sc;
200
201 sc = device_get_softc(dev);
202 pdq_ifdetach(sc);
203
204 return (0);
205}
206
136static void
137pdq_pci_shutdown(device_t dev)
138{
139 pdq_softc_t *sc;
140
141 sc = device_get_softc(dev);
142 pdq_hwreset(sc->sc_pdq);
207static void
208pdq_pci_shutdown(device_t dev)
209{
210 pdq_softc_t *sc;
211
212 sc = device_get_softc(dev);
213 pdq_hwreset(sc->sc_pdq);
214
215 return;
143}
144
145static device_method_t pdq_pci_methods[] = {
146 /* Device interface */
147 DEVMETHOD(device_probe, pdq_pci_probe),
148 DEVMETHOD(device_attach, pdq_pci_attach),
216}
217
218static device_method_t pdq_pci_methods[] = {
219 /* Device interface */
220 DEVMETHOD(device_probe, pdq_pci_probe),
221 DEVMETHOD(device_attach, pdq_pci_attach),
222 DEVMETHOD(device_detach, pdq_pci_detach),
149 DEVMETHOD(device_shutdown, pdq_pci_shutdown),
223 DEVMETHOD(device_shutdown, pdq_pci_shutdown),
224
150 { 0, 0 }
151};
225 { 0, 0 }
226};
227
152static driver_t pdq_pci_driver = {
153 "fpa",
154 pdq_pci_methods,
155 sizeof(pdq_softc_t),
156};
228static driver_t pdq_pci_driver = {
229 "fpa",
230 pdq_pci_methods,
231 sizeof(pdq_softc_t),
232};
157static devclass_t pdq_devclass;
233
158DRIVER_MODULE(if_fpa, pci, pdq_pci_driver, pdq_devclass, 0, 0);
234DRIVER_MODULE(if_fpa, pci, pdq_pci_driver, pdq_devclass, 0, 0);
235/* MODULE_DEPEND(if_fpa, pci, 1, 1, 1); */
236MODULE_DEPEND(if_fpa, fddi, 1, 1, 1);