1/*-
2 * Copyright (c) 2003
3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#include <sys/cdefs.h>
34__FBSDID("$FreeBSD: head/sys/dev/mii/rgephy.c 164830 2006-12-02 19:36:25Z marius $");
35
36/*
37 * Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY.
38 */
39
40#include <sys/param.h>
41#include <sys/systm.h>
42#include <sys/kernel.h>
43#include <sys/module.h>
44#include <sys/socket.h>
45#include <sys/bus.h>
46
47#include <net/if.h>
48#include <net/if_arp.h>
49#include <net/if_media.h>
50
51#include <dev/mii/mii.h>
52#include <dev/mii/miivar.h>
53#include "miidevs.h"
54
55#include <dev/mii/rgephyreg.h>
56
57#include "miibus_if.h"
58
59#include <machine/bus.h>
60#include <pci/if_rlreg.h>
61
62static int rgephy_probe(device_t);
63static int rgephy_attach(device_t);
64
65static device_method_t rgephy_methods[] = {
66 /* device interface */
67 DEVMETHOD(device_probe, rgephy_probe),
68 DEVMETHOD(device_attach, rgephy_attach),
69 DEVMETHOD(device_detach, mii_phy_detach),
70 DEVMETHOD(device_shutdown, bus_generic_shutdown),
71 { 0, 0 }
72};
73
74static devclass_t rgephy_devclass;
75
76static driver_t rgephy_driver = {
77 "rgephy",
78 rgephy_methods,
79 sizeof(struct mii_softc)
80};
81
82DRIVER_MODULE(rgephy, miibus, rgephy_driver, rgephy_devclass, 0, 0);
83
84static int rgephy_service(struct mii_softc *, struct mii_data *, int);
85static void rgephy_status(struct mii_softc *);
86static int rgephy_mii_phy_auto(struct mii_softc *);
87static void rgephy_reset(struct mii_softc *);
88static void rgephy_loop(struct mii_softc *);
89static void rgephy_load_dspcode(struct mii_softc *);
90
91static const struct mii_phydesc rgephys[] = {
92 MII_PHY_DESC(xxREALTEK, RTL8169S),
93 MII_PHY_END
94};
95
96static int
97rgephy_probe(device_t dev)
98{
99
100 return (mii_phy_dev_probe(dev, rgephys, BUS_PROBE_DEFAULT));
101}
102
103static int
104rgephy_attach(device_t dev)
105{
106 struct mii_softc *sc;
107 struct mii_attach_args *ma;
108 struct mii_data *mii;
109 const char *sep = "";
110
111 sc = device_get_softc(dev);
112 ma = device_get_ivars(dev);
113 sc->mii_dev = device_get_parent(dev);
114 mii = device_get_softc(sc->mii_dev);
115 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
116
117 sc->mii_inst = mii->mii_instance;
118 sc->mii_phy = ma->mii_phyno;
119 sc->mii_service = rgephy_service;
120 sc->mii_pdata = mii;
121
122 sc->mii_flags |= MIIF_NOISOLATE;
123 mii->mii_instance++;
124
125#define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL)
126#define PRINT(s) printf("%s%s", sep, s); sep = ", "
127
128 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst),
129 BMCR_ISO);
130#if 0
131 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst),
132 BMCR_LOOP|BMCR_S100);
133#endif
134
135 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
136 sc->mii_capabilities &= ~BMSR_ANEG;
137
138 device_printf(dev, " ");
139 mii_add_media(sc);
140 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, sc->mii_inst),
141 RGEPHY_BMCR_FDX);
142 PRINT(", 1000baseTX");
143 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX, sc->mii_inst), 0);
144 PRINT("1000baseTX-FDX");
145 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0);
146 PRINT("auto");
147
148 printf("\n");
149#undef ADD
150#undef PRINT
151
152 rgephy_reset(sc);
153 MIIBUS_MEDIAINIT(sc->mii_dev);
154 return (0);
155}
156
157static int
158rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
159{
160 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
161 int reg, speed, gig, anar;
162
163 switch (cmd) {
164 case MII_POLLSTAT:
165 /*
166 * If we're not polling our PHY instance, just return.
167 */
168 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
169 return (0);
170 break;
171
172 case MII_MEDIACHG:
173 /*
174 * If the media indicates a different PHY instance,
175 * isolate ourselves.
176 */
177 if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
178 reg = PHY_READ(sc, MII_BMCR);
179 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
180 return (0);
181 }
182
183 /*
184 * If the interface is not up, don't do anything.
185 */
186 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
187 break;
188
189 rgephy_reset(sc); /* XXX hardware bug work-around */
190
191 anar = PHY_READ(sc, RGEPHY_MII_ANAR);
192 anar &= ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX |
193 RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10);
194
195 switch (IFM_SUBTYPE(ife->ifm_media)) {
196 case IFM_AUTO:
197#ifdef foo
198 /*
199 * If we're already in auto mode, just return.
200 */
201 if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN)
202 return (0);
203#endif
204 (void) rgephy_mii_phy_auto(sc);
205 break;
206 case IFM_1000_T:
207 speed = RGEPHY_S1000;
208 goto setit;
209 case IFM_100_TX:
210 speed = RGEPHY_S100;
211 anar |= RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX;
212 goto setit;
213 case IFM_10_T:
214 speed = RGEPHY_S10;
215 anar |= RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10;
216setit:
217 rgephy_loop(sc);
218 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
219 speed |= RGEPHY_BMCR_FDX;
220 gig = RGEPHY_1000CTL_AFD;
221 anar &= ~(RGEPHY_ANAR_TX | RGEPHY_ANAR_10);
222 } else {
223 gig = RGEPHY_1000CTL_AHD;
224 anar &=
225 ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_10_FD);
226 }
227
228 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) {
229 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 0);
230 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar);
231 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed |
232 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
233 break;
234 }
235
236 /*
237 * When setting the link manually, one side must
238 * be the master and the other the slave. However
239 * ifmedia doesn't give us a good way to specify
240 * this, so we fake it by using one of the LINK
241 * flags. If LINK0 is set, we program the PHY to
242 * be a master, otherwise it's a slave.
243 */
244 if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
245 PHY_WRITE(sc, RGEPHY_MII_1000CTL,
246 gig|RGEPHY_1000CTL_MSE|RGEPHY_1000CTL_MSC);
247 } else {
248 PHY_WRITE(sc, RGEPHY_MII_1000CTL,
249 gig|RGEPHY_1000CTL_MSE);
250 }
251 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed |
252 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
253 break;
254#ifdef foo
255 case IFM_NONE:
256 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
257 break;
258#endif
259 case IFM_100_T4:
260 default:
261 return (EINVAL);
262 }
263 break;
264
265 case MII_TICK:
266 /*
267 * If we're not currently selected, just return.
268 */
269 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
270 return (0);
271
272 /*
273 * Is the interface even up?
274 */
275 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
276 return (0);
277
278 /*
279 * Only used for autonegotiation.
280 */
281 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
282 break;
283
284 /*
285 * Check to see if we have link. If we do, we don't
286 * need to restart the autonegotiation process. Read
287 * the BMSR twice in case it's latched.
288 */
289 reg = PHY_READ(sc, RL_GMEDIASTAT);
290 if (reg & RL_GMEDIASTAT_LINK)
291 break;
292
293 /*
294 * Only retry autonegotiation every 5 seconds.
295 */
296 if (++sc->mii_ticks <= MII_ANEGTICKS)
297 break;
298
299 sc->mii_ticks = 0;
300 rgephy_mii_phy_auto(sc);
301 return (0);
302 }
303
304 /* Update the media status. */
305 rgephy_status(sc);
306
307 /*
308 * Callback if something changed. Note that we need to poke
309 * the DSP on the RealTek PHYs if the media changes.
310 *
311 */
312 if (sc->mii_media_active != mii->mii_media_active ||
313 sc->mii_media_status != mii->mii_media_status ||
314 cmd == MII_MEDIACHG) {
315 rgephy_load_dspcode(sc);
316 }
317 mii_phy_update(sc, cmd);
318 return (0);
319}
320
321static void
322rgephy_status(struct mii_softc *sc)
323{
324 struct mii_data *mii = sc->mii_pdata;
325 int bmsr, bmcr;
326
327 mii->mii_media_status = IFM_AVALID;
328 mii->mii_media_active = IFM_ETHER;
329
330 bmsr = PHY_READ(sc, RL_GMEDIASTAT);
331
332 if (bmsr & RL_GMEDIASTAT_LINK)
333 mii->mii_media_status |= IFM_ACTIVE;
334 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
335
336 bmcr = PHY_READ(sc, RGEPHY_MII_BMCR);
337
338 if (bmcr & RGEPHY_BMCR_LOOP)
339 mii->mii_media_active |= IFM_LOOP;
340
341 if (bmcr & RGEPHY_BMCR_AUTOEN) {
342 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) {
343 /* Erg, still trying, I guess... */
344 mii->mii_media_active |= IFM_NONE;
345 return;
346 }
347 }
348
349 bmsr = PHY_READ(sc, RL_GMEDIASTAT);
350 if (bmsr & RL_GMEDIASTAT_1000MBPS)
351 mii->mii_media_active |= IFM_1000_T;
352 else if (bmsr & RL_GMEDIASTAT_100MBPS)
353 mii->mii_media_active |= IFM_100_TX;
354 else if (bmsr & RL_GMEDIASTAT_10MBPS)
355 mii->mii_media_active |= IFM_10_T;
356 else
357 mii->mii_media_active |= IFM_NONE;
358 if (bmsr & RL_GMEDIASTAT_FDX)
359 mii->mii_media_active |= IFM_FDX;
360}
361
362static int
363rgephy_mii_phy_auto(struct mii_softc *mii)
364{
365
366 rgephy_loop(mii);
367 rgephy_reset(mii);
368
369 PHY_WRITE(mii, RGEPHY_MII_ANAR,
370 BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA);
371 DELAY(1000);
372 PHY_WRITE(mii, RGEPHY_MII_1000CTL,
373 RGEPHY_1000CTL_AHD|RGEPHY_1000CTL_AFD);
374 DELAY(1000);
375 PHY_WRITE(mii, RGEPHY_MII_BMCR,
376 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
377 DELAY(100);
378
379 return (EJUSTRETURN);
380}
381
382static void
383rgephy_loop(struct mii_softc *sc)
384{
385 int i;
386
387 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN);
388 DELAY(1000);
389
390 for (i = 0; i < 15000; i++) {
391 if (!(PHY_READ(sc, RGEPHY_MII_BMSR) & RGEPHY_BMSR_LINK)) {
392#if 0
393 device_printf(sc->mii_dev, "looped %d\n", i);
394#endif
395 break;
396 }
397 DELAY(10);
398 }
399}
400
401#define PHY_SETBIT(x, y, z) \
402 PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
403#define PHY_CLRBIT(x, y, z) \
404 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
405
406/*
407 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of
408 * existing revisions of the 8169S/8110S chips need to be tuned in
409 * order to reliably negotiate a 1000Mbps link. This is only needed
410 * for rev 0 and rev 1 of the PHY. Later versions work without
411 * any fixups.
412 */
413static void
414rgephy_load_dspcode(struct mii_softc *sc)
415{
416 int val;
417 uint16_t id2;
418
419 id2 = PHY_READ(sc, MII_PHYIDR2);
420
421 if (MII_REV(id2) > 1)
422 return;
423
424 PHY_WRITE(sc, 31, 0x0001);
425 PHY_WRITE(sc, 21, 0x1000);
426 PHY_WRITE(sc, 24, 0x65C7);
427 PHY_CLRBIT(sc, 4, 0x0800);
428 val = PHY_READ(sc, 4) & 0xFFF;
429 PHY_WRITE(sc, 4, val);
430 PHY_WRITE(sc, 3, 0x00A1);
431 PHY_WRITE(sc, 2, 0x0008);
432 PHY_WRITE(sc, 1, 0x1020);
433 PHY_WRITE(sc, 0, 0x1000);
434 PHY_SETBIT(sc, 4, 0x0800);
435 PHY_CLRBIT(sc, 4, 0x0800);
436 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000;
437 PHY_WRITE(sc, 4, val);
438 PHY_WRITE(sc, 3, 0xFF41);
439 PHY_WRITE(sc, 2, 0xDE60);
440 PHY_WRITE(sc, 1, 0x0140);
441 PHY_WRITE(sc, 0, 0x0077);
442 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000;
443 PHY_WRITE(sc, 4, val);
444 PHY_WRITE(sc, 3, 0xDF01);
445 PHY_WRITE(sc, 2, 0xDF20);
446 PHY_WRITE(sc, 1, 0xFF95);
447 PHY_WRITE(sc, 0, 0xFA00);
448 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000;
449 PHY_WRITE(sc, 4, val);
450 PHY_WRITE(sc, 3, 0xFF41);
451 PHY_WRITE(sc, 2, 0xDE20);
452 PHY_WRITE(sc, 1, 0x0140);
453 PHY_WRITE(sc, 0, 0x00BB);
454 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000;
455 PHY_WRITE(sc, 4, val);
456 PHY_WRITE(sc, 3, 0xDF01);
457 PHY_WRITE(sc, 2, 0xDF20);
458 PHY_WRITE(sc, 1, 0xFF95);
459 PHY_WRITE(sc, 0, 0xBF00);
460 PHY_SETBIT(sc, 4, 0x0800);
461 PHY_CLRBIT(sc, 4, 0x0800);
462 PHY_WRITE(sc, 31, 0x0000);
463
464 DELAY(40);
465}
466
467static void
468rgephy_reset(struct mii_softc *sc)
469{
470
471 mii_phy_reset(sc);
472 DELAY(1000);
473 rgephy_load_dspcode(sc);
474}
2 * Copyright (c) 2003
3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Bill Paul.
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#include <sys/cdefs.h>
34__FBSDID("$FreeBSD: head/sys/dev/mii/rgephy.c 164830 2006-12-02 19:36:25Z marius $");
35
36/*
37 * Driver for the RealTek 8169S/8110S internal 10/100/1000 PHY.
38 */
39
40#include <sys/param.h>
41#include <sys/systm.h>
42#include <sys/kernel.h>
43#include <sys/module.h>
44#include <sys/socket.h>
45#include <sys/bus.h>
46
47#include <net/if.h>
48#include <net/if_arp.h>
49#include <net/if_media.h>
50
51#include <dev/mii/mii.h>
52#include <dev/mii/miivar.h>
53#include "miidevs.h"
54
55#include <dev/mii/rgephyreg.h>
56
57#include "miibus_if.h"
58
59#include <machine/bus.h>
60#include <pci/if_rlreg.h>
61
62static int rgephy_probe(device_t);
63static int rgephy_attach(device_t);
64
65static device_method_t rgephy_methods[] = {
66 /* device interface */
67 DEVMETHOD(device_probe, rgephy_probe),
68 DEVMETHOD(device_attach, rgephy_attach),
69 DEVMETHOD(device_detach, mii_phy_detach),
70 DEVMETHOD(device_shutdown, bus_generic_shutdown),
71 { 0, 0 }
72};
73
74static devclass_t rgephy_devclass;
75
76static driver_t rgephy_driver = {
77 "rgephy",
78 rgephy_methods,
79 sizeof(struct mii_softc)
80};
81
82DRIVER_MODULE(rgephy, miibus, rgephy_driver, rgephy_devclass, 0, 0);
83
84static int rgephy_service(struct mii_softc *, struct mii_data *, int);
85static void rgephy_status(struct mii_softc *);
86static int rgephy_mii_phy_auto(struct mii_softc *);
87static void rgephy_reset(struct mii_softc *);
88static void rgephy_loop(struct mii_softc *);
89static void rgephy_load_dspcode(struct mii_softc *);
90
91static const struct mii_phydesc rgephys[] = {
92 MII_PHY_DESC(xxREALTEK, RTL8169S),
93 MII_PHY_END
94};
95
96static int
97rgephy_probe(device_t dev)
98{
99
100 return (mii_phy_dev_probe(dev, rgephys, BUS_PROBE_DEFAULT));
101}
102
103static int
104rgephy_attach(device_t dev)
105{
106 struct mii_softc *sc;
107 struct mii_attach_args *ma;
108 struct mii_data *mii;
109 const char *sep = "";
110
111 sc = device_get_softc(dev);
112 ma = device_get_ivars(dev);
113 sc->mii_dev = device_get_parent(dev);
114 mii = device_get_softc(sc->mii_dev);
115 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
116
117 sc->mii_inst = mii->mii_instance;
118 sc->mii_phy = ma->mii_phyno;
119 sc->mii_service = rgephy_service;
120 sc->mii_pdata = mii;
121
122 sc->mii_flags |= MIIF_NOISOLATE;
123 mii->mii_instance++;
124
125#define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL)
126#define PRINT(s) printf("%s%s", sep, s); sep = ", "
127
128 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst),
129 BMCR_ISO);
130#if 0
131 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst),
132 BMCR_LOOP|BMCR_S100);
133#endif
134
135 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
136 sc->mii_capabilities &= ~BMSR_ANEG;
137
138 device_printf(dev, " ");
139 mii_add_media(sc);
140 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, 0, sc->mii_inst),
141 RGEPHY_BMCR_FDX);
142 PRINT(", 1000baseTX");
143 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_T, IFM_FDX, sc->mii_inst), 0);
144 PRINT("1000baseTX-FDX");
145 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0);
146 PRINT("auto");
147
148 printf("\n");
149#undef ADD
150#undef PRINT
151
152 rgephy_reset(sc);
153 MIIBUS_MEDIAINIT(sc->mii_dev);
154 return (0);
155}
156
157static int
158rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
159{
160 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
161 int reg, speed, gig, anar;
162
163 switch (cmd) {
164 case MII_POLLSTAT:
165 /*
166 * If we're not polling our PHY instance, just return.
167 */
168 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
169 return (0);
170 break;
171
172 case MII_MEDIACHG:
173 /*
174 * If the media indicates a different PHY instance,
175 * isolate ourselves.
176 */
177 if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
178 reg = PHY_READ(sc, MII_BMCR);
179 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
180 return (0);
181 }
182
183 /*
184 * If the interface is not up, don't do anything.
185 */
186 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
187 break;
188
189 rgephy_reset(sc); /* XXX hardware bug work-around */
190
191 anar = PHY_READ(sc, RGEPHY_MII_ANAR);
192 anar &= ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX |
193 RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10);
194
195 switch (IFM_SUBTYPE(ife->ifm_media)) {
196 case IFM_AUTO:
197#ifdef foo
198 /*
199 * If we're already in auto mode, just return.
200 */
201 if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN)
202 return (0);
203#endif
204 (void) rgephy_mii_phy_auto(sc);
205 break;
206 case IFM_1000_T:
207 speed = RGEPHY_S1000;
208 goto setit;
209 case IFM_100_TX:
210 speed = RGEPHY_S100;
211 anar |= RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX;
212 goto setit;
213 case IFM_10_T:
214 speed = RGEPHY_S10;
215 anar |= RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10;
216setit:
217 rgephy_loop(sc);
218 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
219 speed |= RGEPHY_BMCR_FDX;
220 gig = RGEPHY_1000CTL_AFD;
221 anar &= ~(RGEPHY_ANAR_TX | RGEPHY_ANAR_10);
222 } else {
223 gig = RGEPHY_1000CTL_AHD;
224 anar &=
225 ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_10_FD);
226 }
227
228 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T) {
229 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 0);
230 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar);
231 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed |
232 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
233 break;
234 }
235
236 /*
237 * When setting the link manually, one side must
238 * be the master and the other the slave. However
239 * ifmedia doesn't give us a good way to specify
240 * this, so we fake it by using one of the LINK
241 * flags. If LINK0 is set, we program the PHY to
242 * be a master, otherwise it's a slave.
243 */
244 if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
245 PHY_WRITE(sc, RGEPHY_MII_1000CTL,
246 gig|RGEPHY_1000CTL_MSE|RGEPHY_1000CTL_MSC);
247 } else {
248 PHY_WRITE(sc, RGEPHY_MII_1000CTL,
249 gig|RGEPHY_1000CTL_MSE);
250 }
251 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed |
252 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
253 break;
254#ifdef foo
255 case IFM_NONE:
256 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
257 break;
258#endif
259 case IFM_100_T4:
260 default:
261 return (EINVAL);
262 }
263 break;
264
265 case MII_TICK:
266 /*
267 * If we're not currently selected, just return.
268 */
269 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
270 return (0);
271
272 /*
273 * Is the interface even up?
274 */
275 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
276 return (0);
277
278 /*
279 * Only used for autonegotiation.
280 */
281 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
282 break;
283
284 /*
285 * Check to see if we have link. If we do, we don't
286 * need to restart the autonegotiation process. Read
287 * the BMSR twice in case it's latched.
288 */
289 reg = PHY_READ(sc, RL_GMEDIASTAT);
290 if (reg & RL_GMEDIASTAT_LINK)
291 break;
292
293 /*
294 * Only retry autonegotiation every 5 seconds.
295 */
296 if (++sc->mii_ticks <= MII_ANEGTICKS)
297 break;
298
299 sc->mii_ticks = 0;
300 rgephy_mii_phy_auto(sc);
301 return (0);
302 }
303
304 /* Update the media status. */
305 rgephy_status(sc);
306
307 /*
308 * Callback if something changed. Note that we need to poke
309 * the DSP on the RealTek PHYs if the media changes.
310 *
311 */
312 if (sc->mii_media_active != mii->mii_media_active ||
313 sc->mii_media_status != mii->mii_media_status ||
314 cmd == MII_MEDIACHG) {
315 rgephy_load_dspcode(sc);
316 }
317 mii_phy_update(sc, cmd);
318 return (0);
319}
320
321static void
322rgephy_status(struct mii_softc *sc)
323{
324 struct mii_data *mii = sc->mii_pdata;
325 int bmsr, bmcr;
326
327 mii->mii_media_status = IFM_AVALID;
328 mii->mii_media_active = IFM_ETHER;
329
330 bmsr = PHY_READ(sc, RL_GMEDIASTAT);
331
332 if (bmsr & RL_GMEDIASTAT_LINK)
333 mii->mii_media_status |= IFM_ACTIVE;
334 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
335
336 bmcr = PHY_READ(sc, RGEPHY_MII_BMCR);
337
338 if (bmcr & RGEPHY_BMCR_LOOP)
339 mii->mii_media_active |= IFM_LOOP;
340
341 if (bmcr & RGEPHY_BMCR_AUTOEN) {
342 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) {
343 /* Erg, still trying, I guess... */
344 mii->mii_media_active |= IFM_NONE;
345 return;
346 }
347 }
348
349 bmsr = PHY_READ(sc, RL_GMEDIASTAT);
350 if (bmsr & RL_GMEDIASTAT_1000MBPS)
351 mii->mii_media_active |= IFM_1000_T;
352 else if (bmsr & RL_GMEDIASTAT_100MBPS)
353 mii->mii_media_active |= IFM_100_TX;
354 else if (bmsr & RL_GMEDIASTAT_10MBPS)
355 mii->mii_media_active |= IFM_10_T;
356 else
357 mii->mii_media_active |= IFM_NONE;
358 if (bmsr & RL_GMEDIASTAT_FDX)
359 mii->mii_media_active |= IFM_FDX;
360}
361
362static int
363rgephy_mii_phy_auto(struct mii_softc *mii)
364{
365
366 rgephy_loop(mii);
367 rgephy_reset(mii);
368
369 PHY_WRITE(mii, RGEPHY_MII_ANAR,
370 BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA);
371 DELAY(1000);
372 PHY_WRITE(mii, RGEPHY_MII_1000CTL,
373 RGEPHY_1000CTL_AHD|RGEPHY_1000CTL_AFD);
374 DELAY(1000);
375 PHY_WRITE(mii, RGEPHY_MII_BMCR,
376 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
377 DELAY(100);
378
379 return (EJUSTRETURN);
380}
381
382static void
383rgephy_loop(struct mii_softc *sc)
384{
385 int i;
386
387 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN);
388 DELAY(1000);
389
390 for (i = 0; i < 15000; i++) {
391 if (!(PHY_READ(sc, RGEPHY_MII_BMSR) & RGEPHY_BMSR_LINK)) {
392#if 0
393 device_printf(sc->mii_dev, "looped %d\n", i);
394#endif
395 break;
396 }
397 DELAY(10);
398 }
399}
400
401#define PHY_SETBIT(x, y, z) \
402 PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
403#define PHY_CLRBIT(x, y, z) \
404 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
405
406/*
407 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of
408 * existing revisions of the 8169S/8110S chips need to be tuned in
409 * order to reliably negotiate a 1000Mbps link. This is only needed
410 * for rev 0 and rev 1 of the PHY. Later versions work without
411 * any fixups.
412 */
413static void
414rgephy_load_dspcode(struct mii_softc *sc)
415{
416 int val;
417 uint16_t id2;
418
419 id2 = PHY_READ(sc, MII_PHYIDR2);
420
421 if (MII_REV(id2) > 1)
422 return;
423
424 PHY_WRITE(sc, 31, 0x0001);
425 PHY_WRITE(sc, 21, 0x1000);
426 PHY_WRITE(sc, 24, 0x65C7);
427 PHY_CLRBIT(sc, 4, 0x0800);
428 val = PHY_READ(sc, 4) & 0xFFF;
429 PHY_WRITE(sc, 4, val);
430 PHY_WRITE(sc, 3, 0x00A1);
431 PHY_WRITE(sc, 2, 0x0008);
432 PHY_WRITE(sc, 1, 0x1020);
433 PHY_WRITE(sc, 0, 0x1000);
434 PHY_SETBIT(sc, 4, 0x0800);
435 PHY_CLRBIT(sc, 4, 0x0800);
436 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000;
437 PHY_WRITE(sc, 4, val);
438 PHY_WRITE(sc, 3, 0xFF41);
439 PHY_WRITE(sc, 2, 0xDE60);
440 PHY_WRITE(sc, 1, 0x0140);
441 PHY_WRITE(sc, 0, 0x0077);
442 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000;
443 PHY_WRITE(sc, 4, val);
444 PHY_WRITE(sc, 3, 0xDF01);
445 PHY_WRITE(sc, 2, 0xDF20);
446 PHY_WRITE(sc, 1, 0xFF95);
447 PHY_WRITE(sc, 0, 0xFA00);
448 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000;
449 PHY_WRITE(sc, 4, val);
450 PHY_WRITE(sc, 3, 0xFF41);
451 PHY_WRITE(sc, 2, 0xDE20);
452 PHY_WRITE(sc, 1, 0x0140);
453 PHY_WRITE(sc, 0, 0x00BB);
454 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000;
455 PHY_WRITE(sc, 4, val);
456 PHY_WRITE(sc, 3, 0xDF01);
457 PHY_WRITE(sc, 2, 0xDF20);
458 PHY_WRITE(sc, 1, 0xFF95);
459 PHY_WRITE(sc, 0, 0xBF00);
460 PHY_SETBIT(sc, 4, 0x0800);
461 PHY_CLRBIT(sc, 4, 0x0800);
462 PHY_WRITE(sc, 31, 0x0000);
463
464 DELAY(40);
465}
466
467static void
468rgephy_reset(struct mii_softc *sc)
469{
470
471 mii_phy_reset(sc);
472 DELAY(1000);
473 rgephy_load_dspcode(sc);
474}