mfireg.h (184897) | mfireg.h (196200) |
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1/*- 2 * Copyright (c) 2006 IronPort Systems 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 40 unchanged lines hidden (view full) --- 49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 50 * SUCH DAMAGE. 51 */ 52 53#ifndef _MFIREG_H 54#define _MFIREG_H 55 56#include <sys/cdefs.h> | 1/*- 2 * Copyright (c) 2006 IronPort Systems 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 40 unchanged lines hidden (view full) --- 49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 50 * SUCH DAMAGE. 51 */ 52 53#ifndef _MFIREG_H 54#define _MFIREG_H 55 56#include <sys/cdefs.h> |
57__FBSDID("$FreeBSD: head/sys/dev/mfi/mfireg.h 184897 2008-11-12 22:44:50Z ambrisko $"); | 57__FBSDID("$FreeBSD: head/sys/dev/mfi/mfireg.h 196200 2009-08-13 23:18:45Z scottl $"); |
58 59/* 60 * MegaRAID SAS MFI firmware definitions 61 * 62 * Calling this driver 'MegaRAID SAS' is a bit misleading. It's a completely 63 * new firmware interface from the old AMI MegaRAID one, and there is no 64 * reason why this interface should be limited to just SAS. In any case, LSI 65 * seems to also call this interface 'MFI', so that will be used here. --- 18 unchanged lines hidden (view full) --- 84 85/* 86 * 1078 specific related register 87 */ 88#define MFI_ODR0 0x9c /* outbound doorbell register0 */ 89#define MFI_ODCR0 0xa0 /* outbound doorbell clear register0 */ 90#define MFI_OSP0 0xb0 /* outbound scratch pad0 */ 91#define MFI_1078_EIM 0x80000004 /* 1078 enable intrrupt mask */ | 58 59/* 60 * MegaRAID SAS MFI firmware definitions 61 * 62 * Calling this driver 'MegaRAID SAS' is a bit misleading. It's a completely 63 * new firmware interface from the old AMI MegaRAID one, and there is no 64 * reason why this interface should be limited to just SAS. In any case, LSI 65 * seems to also call this interface 'MFI', so that will be used here. --- 18 unchanged lines hidden (view full) --- 84 85/* 86 * 1078 specific related register 87 */ 88#define MFI_ODR0 0x9c /* outbound doorbell register0 */ 89#define MFI_ODCR0 0xa0 /* outbound doorbell clear register0 */ 90#define MFI_OSP0 0xb0 /* outbound scratch pad0 */ 91#define MFI_1078_EIM 0x80000004 /* 1078 enable intrrupt mask */ |
92#define MFI_RMI 0x2 /* reply message interrupt */ | 92#define MFI_RMI 0x2 /* reply message interrupt */ |
93#define MFI_1078_RM 0x80000000 /* reply 1078 message interrupt */ 94#define MFI_ODC 0x4 /* outbound doorbell change interrupt */ 95 96/* 97 * GEN2 specific changes 98 */ 99#define MFI_GEN2_EIM 0x00000005 /* GEN2 enable interrupt mask */ 100#define MFI_GEN2_RM 0x00000001 /* reply GEN2 message interrupt */ --- 45 unchanged lines hidden (view full) --- 146 MFI_DCMD_CTRL_GETINFO = 0x01010000, 147 MFI_DCMD_CTRL_MFC_DEFAULTS_GET =0x010e0201, 148 MFI_DCMD_CTRL_MFC_DEFAULTS_SET =0x010e0202, 149 MFI_DCMD_CTRL_FLUSHCACHE = 0x01101000, 150 MFI_DCMD_CTRL_SHUTDOWN = 0x01050000, 151 MFI_DCMD_CTRL_EVENT_GETINFO = 0x01040100, 152 MFI_DCMD_CTRL_EVENT_GET = 0x01040300, 153 MFI_DCMD_CTRL_EVENT_WAIT = 0x01040500, | 93#define MFI_1078_RM 0x80000000 /* reply 1078 message interrupt */ 94#define MFI_ODC 0x4 /* outbound doorbell change interrupt */ 95 96/* 97 * GEN2 specific changes 98 */ 99#define MFI_GEN2_EIM 0x00000005 /* GEN2 enable interrupt mask */ 100#define MFI_GEN2_RM 0x00000001 /* reply GEN2 message interrupt */ --- 45 unchanged lines hidden (view full) --- 146 MFI_DCMD_CTRL_GETINFO = 0x01010000, 147 MFI_DCMD_CTRL_MFC_DEFAULTS_GET =0x010e0201, 148 MFI_DCMD_CTRL_MFC_DEFAULTS_SET =0x010e0202, 149 MFI_DCMD_CTRL_FLUSHCACHE = 0x01101000, 150 MFI_DCMD_CTRL_SHUTDOWN = 0x01050000, 151 MFI_DCMD_CTRL_EVENT_GETINFO = 0x01040100, 152 MFI_DCMD_CTRL_EVENT_GET = 0x01040300, 153 MFI_DCMD_CTRL_EVENT_WAIT = 0x01040500, |
154 MFI_DCMD_PR_GET_STATUS = 0x01070100, 155 MFI_DCMD_PR_GET_PROPERTIES = 0x01070200, 156 MFI_DCMD_PR_SET_PROPERTIES = 0x01070300, 157 MFI_DCMD_PR_START = 0x01070400, 158 MFI_DCMD_PR_STOP = 0x01070500, 159 MFI_DCMD_TIME_SECS_GET = 0x01080201, 160 MFI_DCMD_FLASH_FW_OPEN = 0x010f0100, 161 MFI_DCMD_FLASH_FW_DOWNLOAD = 0x010f0200, 162 MFI_DCMD_FLASH_FW_FLASH = 0x010f0300, 163 MFI_DCMD_FLASH_FW_CLOSE = 0x010f0400, 164 MFI_DCMD_PD_GET_LIST = 0x02010000, 165 MFI_DCMD_PD_GET_INFO = 0x02020000, 166 MFI_DCMD_PD_STATE_SET = 0x02030100, 167 MFI_DCMD_PD_REBUILD_START = 0x02040100, 168 MFI_DCMD_PD_REBUILD_ABORT = 0x02040200, 169 MFI_DCMD_PD_CLEAR_START = 0x02050100, 170 MFI_DCMD_PD_CLEAR_ABORT = 0x02050200, 171 MFI_DCMD_PD_GET_PROGRESS = 0x02060000, 172 MFI_DCMD_PD_LOCATE_START = 0x02070100, 173 MFI_DCMD_PD_LOCATE_STOP = 0x02070200, |
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154 MFI_DCMD_LD_GET_LIST = 0x03010000, 155 MFI_DCMD_LD_GET_INFO = 0x03020000, 156 MFI_DCMD_LD_GET_PROP = 0x03030000, 157 MFI_DCMD_LD_SET_PROP = 0x03040000, | 174 MFI_DCMD_LD_GET_LIST = 0x03010000, 175 MFI_DCMD_LD_GET_INFO = 0x03020000, 176 MFI_DCMD_LD_GET_PROP = 0x03030000, 177 MFI_DCMD_LD_SET_PROP = 0x03040000, |
178 MFI_DCMD_LD_INIT_START = 0x03060100, |
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158 MFI_DCMD_LD_DELETE = 0x03090000, 159 MFI_DCMD_CFG_READ = 0x04010000, 160 MFI_DCMD_CFG_ADD = 0x04020000, 161 MFI_DCMD_CFG_CLEAR = 0x04030000, | 179 MFI_DCMD_LD_DELETE = 0x03090000, 180 MFI_DCMD_CFG_READ = 0x04010000, 181 MFI_DCMD_CFG_ADD = 0x04020000, 182 MFI_DCMD_CFG_CLEAR = 0x04030000, |
183 MFI_DCMD_CFG_MAKE_SPARE = 0x04040000, 184 MFI_DCMD_CFG_REMOVE_SPARE = 0x04050000, |
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162 MFI_DCMD_CFG_FOREIGN_IMPORT = 0x04060400, | 185 MFI_DCMD_CFG_FOREIGN_IMPORT = 0x04060400, |
186 MFI_DCMD_BBU_GET_STATUS = 0x05010000, 187 MFI_DCMD_BBU_GET_CAPACITY_INFO =0x05020000, 188 MFI_DCMD_BBU_GET_DESIGN_INFO = 0x05030000, |
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163 MFI_DCMD_CLUSTER = 0x08000000, 164 MFI_DCMD_CLUSTER_RESET_ALL = 0x08010100, 165 MFI_DCMD_CLUSTER_RESET_LD = 0x08010200 166} mfi_dcmd_t; 167 168/* Modifiers for MFI_DCMD_CTRL_FLUSHCACHE */ 169#define MFI_FLUSHCACHE_CTRL 0x01 170#define MFI_FLUSHCACHE_DISK 0x02 --- 69 unchanged lines hidden (view full) --- 240 MFI_STAT_TIME_NOT_SET, 241 MFI_STAT_WRONG_STATE, 242 MFI_STAT_LD_OFFLINE, 243 MFI_STAT_PEER_NOTIFICATION_REJECTED, 244 MFI_STAT_PEER_NOTIFICATION_FAILED, 245 MFI_STAT_RESERVATION_IN_PROGRESS, 246 MFI_STAT_I2C_ERRORS_DETECTED, 247 MFI_STAT_PCI_ERRORS_DETECTED, | 189 MFI_DCMD_CLUSTER = 0x08000000, 190 MFI_DCMD_CLUSTER_RESET_ALL = 0x08010100, 191 MFI_DCMD_CLUSTER_RESET_LD = 0x08010200 192} mfi_dcmd_t; 193 194/* Modifiers for MFI_DCMD_CTRL_FLUSHCACHE */ 195#define MFI_FLUSHCACHE_CTRL 0x01 196#define MFI_FLUSHCACHE_DISK 0x02 --- 69 unchanged lines hidden (view full) --- 266 MFI_STAT_TIME_NOT_SET, 267 MFI_STAT_WRONG_STATE, 268 MFI_STAT_LD_OFFLINE, 269 MFI_STAT_PEER_NOTIFICATION_REJECTED, 270 MFI_STAT_PEER_NOTIFICATION_FAILED, 271 MFI_STAT_RESERVATION_IN_PROGRESS, 272 MFI_STAT_I2C_ERRORS_DETECTED, 273 MFI_STAT_PCI_ERRORS_DETECTED, |
274 MFI_STAT_DIAG_FAILED, 275 MFI_STAT_BOOT_MSG_PENDING, 276 MFI_STAT_FOREIGN_CONFIG_INCOMPLETE, |
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248 MFI_STAT_INVALID_STATUS = 0xFF 249} mfi_status_t; 250 251typedef enum { 252 MFI_EVT_CLASS_DEBUG = -2, 253 MFI_EVT_CLASS_PROGRESS = -1, 254 MFI_EVT_CLASS_INFO = 0, 255 MFI_EVT_CLASS_WARNING = 1, --- 42 unchanged lines hidden (view full) --- 298 MR_LD_CACHE_WRITE_BACK = 0x01, 299 MR_LD_CACHE_WRITE_ADAPTIVE = 0x02, 300 MR_LD_CACHE_READ_AHEAD = 0x04, 301 MR_LD_CACHE_READ_ADAPTIVE = 0x08, 302 MR_LD_CACHE_WRITE_CACHE_BAD_BBU=0x10, 303 MR_LD_CACHE_ALLOW_WRITE_CACHE = 0x20, 304 MR_LD_CACHE_ALLOW_READ_CACHE = 0x40 305} mfi_ld_cache; | 277 MFI_STAT_INVALID_STATUS = 0xFF 278} mfi_status_t; 279 280typedef enum { 281 MFI_EVT_CLASS_DEBUG = -2, 282 MFI_EVT_CLASS_PROGRESS = -1, 283 MFI_EVT_CLASS_INFO = 0, 284 MFI_EVT_CLASS_WARNING = 1, --- 42 unchanged lines hidden (view full) --- 327 MR_LD_CACHE_WRITE_BACK = 0x01, 328 MR_LD_CACHE_WRITE_ADAPTIVE = 0x02, 329 MR_LD_CACHE_READ_AHEAD = 0x04, 330 MR_LD_CACHE_READ_ADAPTIVE = 0x08, 331 MR_LD_CACHE_WRITE_CACHE_BAD_BBU=0x10, 332 MR_LD_CACHE_ALLOW_WRITE_CACHE = 0x20, 333 MR_LD_CACHE_ALLOW_READ_CACHE = 0x40 334} mfi_ld_cache; |
335#define MR_LD_CACHE_MASK 0x7f |
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306 | 336 |
337#define MR_LD_CACHE_POLICY_READ_AHEAD_NONE 0 338#define MR_LD_CACHE_POLICY_READ_AHEAD_ALWAYS MR_LD_CACHE_READ_AHEAD 339#define MR_LD_CACHE_POLICY_READ_AHEAD_ADAPTIVE \ 340 (MR_LD_CACHE_READ_AHEAD | MR_LD_CACHE_READ_ADAPTIVE) 341#define MR_LD_CACHE_POLICY_WRITE_THROUGH 0 342#define MR_LD_CACHE_POLICY_WRITE_BACK MR_LD_CACHE_WRITE_BACK 343#define MR_LD_CACHE_POLICY_IO_CACHED \ 344 (MR_LD_CACHE_ALLOW_WRITE_CACHE | MR_LD_CACHE_ALLOW_READ_CACHE) 345#define MR_LD_CACHE_POLICY_IO_DIRECT 0 346 |
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307typedef enum { 308 MR_PD_CACHE_UNCHANGED = 0, 309 MR_PD_CACHE_ENABLE = 1, 310 MR_PD_CACHE_DISABLE = 2 311} mfi_pd_cache; 312 313/* 314 * Other propertities and definitions 315 */ 316#define MFI_MAX_PD_CHANNELS 2 317#define MFI_MAX_LD_CHANNELS 2 318#define MFI_MAX_CHANNELS (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS) 319#define MFI_MAX_CHANNEL_DEVS 128 320#define MFI_DEFAULT_ID -1 321#define MFI_MAX_LUN 8 322#define MFI_MAX_LD 64 | 347typedef enum { 348 MR_PD_CACHE_UNCHANGED = 0, 349 MR_PD_CACHE_ENABLE = 1, 350 MR_PD_CACHE_DISABLE = 2 351} mfi_pd_cache; 352 353/* 354 * Other propertities and definitions 355 */ 356#define MFI_MAX_PD_CHANNELS 2 357#define MFI_MAX_LD_CHANNELS 2 358#define MFI_MAX_CHANNELS (MFI_MAX_PD_CHANNELS + MFI_MAX_LD_CHANNELS) 359#define MFI_MAX_CHANNEL_DEVS 128 360#define MFI_DEFAULT_ID -1 361#define MFI_MAX_LUN 8 362#define MFI_MAX_LD 64 |
363#define MFI_MAX_PD 256 |
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323 324#define MFI_FRAME_SIZE 64 325#define MFI_MBOX_SIZE 12 326 327/* Firmware flashing can take 40s */ 328#define MFI_POLL_TIMEOUT_SECS 50 329 330/* Allow for speedier math calculations */ --- 530 unchanged lines hidden (view full) --- 861 } ddf; 862 struct { 863 uint32_t reserved; 864 } non_disk; 865 uint32_t type; 866} __packed; 867 868struct mfi_pd_progress { | 364 365#define MFI_FRAME_SIZE 64 366#define MFI_MBOX_SIZE 12 367 368/* Firmware flashing can take 40s */ 369#define MFI_POLL_TIMEOUT_SECS 50 370 371/* Allow for speedier math calculations */ --- 530 unchanged lines hidden (view full) --- 902 } ddf; 903 struct { 904 uint32_t reserved; 905 } non_disk; 906 uint32_t type; 907} __packed; 908 909struct mfi_pd_progress { |
869 struct { 870 uint32_t rbld : 1; 871 uint32_t patrol : 1; 872 uint32_t clear : 1; 873 uint32_t reserved: 29; 874 } active; | 910 uint32_t active; 911#define MFI_PD_PROGRESS_REBUILD (1<<0) 912#define MFI_PD_PROGRESS_PATROL (1<<1) 913#define MFI_PD_PROGRESS_CLEAR (1<<2) |
875 struct mfi_progress rbld; 876 struct mfi_progress patrol; 877 struct mfi_progress clear; 878 struct mfi_progress reserved[4]; 879} __packed; 880 881struct mfi_pd_info { 882 union mfi_pd_ref ref; 883 uint8_t inquiry_data[96]; 884 uint8_t vpd_page83[64]; 885 uint8_t not_supported; 886 uint8_t scsi_dev_type; 887 uint8_t connected_port_bitmap; 888 uint8_t device_speed; 889 uint32_t media_err_count; 890 uint32_t other_err_count; 891 uint32_t pred_fail_count; 892 uint32_t last_pred_fail_event_seq_num; | 914 struct mfi_progress rbld; 915 struct mfi_progress patrol; 916 struct mfi_progress clear; 917 struct mfi_progress reserved[4]; 918} __packed; 919 920struct mfi_pd_info { 921 union mfi_pd_ref ref; 922 uint8_t inquiry_data[96]; 923 uint8_t vpd_page83[64]; 924 uint8_t not_supported; 925 uint8_t scsi_dev_type; 926 uint8_t connected_port_bitmap; 927 uint8_t device_speed; 928 uint32_t media_err_count; 929 uint32_t other_err_count; 930 uint32_t pred_fail_count; 931 uint32_t last_pred_fail_event_seq_num; |
893 uint16_t fw_state; 894 uint8_t disable_for_removal; | 932 uint16_t fw_state; /* MFI_PD_STATE_* */ 933 uint8_t disabled_for_removal; |
895 uint8_t link_speed; 896 union mfi_pd_ddf_type state; 897 struct { 898 uint8_t count; 899 uint8_t is_path_broken; 900 uint8_t reserved[6]; 901 uint64_t sas_addr[4]; 902 } path_info; --- 10 unchanged lines hidden (view full) --- 913 uint8_t reserved[512-358]; 914} __packed; 915 916struct mfi_pd_address { 917 uint16_t device_id; 918 uint16_t encl_device_id; 919 uint8_t encl_index; 920 uint8_t slot_number; | 934 uint8_t link_speed; 935 union mfi_pd_ddf_type state; 936 struct { 937 uint8_t count; 938 uint8_t is_path_broken; 939 uint8_t reserved[6]; 940 uint64_t sas_addr[4]; 941 } path_info; --- 10 unchanged lines hidden (view full) --- 952 uint8_t reserved[512-358]; 953} __packed; 954 955struct mfi_pd_address { 956 uint16_t device_id; 957 uint16_t encl_device_id; 958 uint8_t encl_index; 959 uint8_t slot_number; |
921 uint8_t scsi_dev_type; | 960 uint8_t scsi_dev_type; /* 0 = disk */ |
922 uint8_t connect_port_bitmap; 923 uint64_t sas_addr[2]; 924} __packed; 925 926struct mfi_pd_list { 927 uint32_t size; 928 uint32_t count; | 961 uint8_t connect_port_bitmap; 962 uint64_t sas_addr[2]; 963} __packed; 964 965struct mfi_pd_list { 966 uint32_t size; 967 uint32_t count; |
929 uint8_t data; 930 /* 931 struct mfi_pd_address addr[]; 932 */ | 968 struct mfi_pd_address addr[0]; |
933} __packed; 934 | 969} __packed; 970 |
971enum mfi_pd_state { 972 MFI_PD_STATE_UNCONFIGURED_GOOD = 0x00, 973 MFI_PD_STATE_UNCONFIGURED_BAD = 0x01, 974 MFI_PD_STATE_HOT_SPARE = 0x02, 975 MFI_PD_STATE_OFFLINE = 0x10, 976 MFI_PD_STATE_FAILED = 0x11, 977 MFI_PD_STATE_REBUILD = 0x14, 978 MFI_PD_STATE_ONLINE = 0x18 979}; 980 |
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935union mfi_ld_ref { 936 struct { 937 uint8_t target_id; 938 uint8_t reserved; 939 uint16_t seq; 940 } v; 941 uint32_t ref; 942} __packed; --- 38 unchanged lines hidden (view full) --- 981 uint8_t primary_raid_level; 982 uint8_t raid_level_qualifier; 983 uint8_t secondary_raid_level; 984 uint8_t stripe_size; 985 uint8_t num_drives; 986 uint8_t span_depth; 987 uint8_t state; 988 uint8_t init_state; | 981union mfi_ld_ref { 982 struct { 983 uint8_t target_id; 984 uint8_t reserved; 985 uint16_t seq; 986 } v; 987 uint32_t ref; 988} __packed; --- 38 unchanged lines hidden (view full) --- 1027 uint8_t primary_raid_level; 1028 uint8_t raid_level_qualifier; 1029 uint8_t secondary_raid_level; 1030 uint8_t stripe_size; 1031 uint8_t num_drives; 1032 uint8_t span_depth; 1033 uint8_t state; 1034 uint8_t init_state; |
1035#define MFI_LD_PARAMS_INIT_NO 0 1036#define MFI_LD_PARAMS_INIT_QUICK 1 1037#define MFI_LD_PARAMS_INIT_FULL 2 |
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989 uint8_t is_consistent; 990 uint8_t reserved[23]; 991} __packed; 992 993struct mfi_ld_progress { 994 uint32_t active; 995#define MFI_LD_PROGRESS_CC (1<<0) 996#define MFI_LD_PROGRESS_BGI (1<<1) 997#define MFI_LD_PROGRESS_FGI (1<<2) | 1038 uint8_t is_consistent; 1039 uint8_t reserved[23]; 1040} __packed; 1041 1042struct mfi_ld_progress { 1043 uint32_t active; 1044#define MFI_LD_PROGRESS_CC (1<<0) 1045#define MFI_LD_PROGRESS_BGI (1<<1) 1046#define MFI_LD_PROGRESS_FGI (1<<2) |
998#define MFI_LD_PORGRESS_RECON (1<<3) | 1047#define MFI_LD_PROGRESS_RECON (1<<3) |
999 struct mfi_progress cc; 1000 struct mfi_progress bgi; 1001 struct mfi_progress fgi; 1002 struct mfi_progress recon; 1003 struct mfi_progress reserved[4]; 1004} __packed; 1005 1006struct mfi_span { --- 16 unchanged lines hidden (view full) --- 1023 struct mfi_ld_progress progress; 1024 uint16_t cluster_owner; 1025 uint8_t reconstruct_active; 1026 uint8_t reserved1[1]; 1027 uint8_t vpd_page83[64]; 1028 uint8_t reserved2[16]; 1029} __packed; 1030 | 1048 struct mfi_progress cc; 1049 struct mfi_progress bgi; 1050 struct mfi_progress fgi; 1051 struct mfi_progress recon; 1052 struct mfi_progress reserved[4]; 1053} __packed; 1054 1055struct mfi_span { --- 16 unchanged lines hidden (view full) --- 1072 struct mfi_ld_progress progress; 1073 uint16_t cluster_owner; 1074 uint8_t reconstruct_active; 1075 uint8_t reserved1[1]; 1076 uint8_t vpd_page83[64]; 1077 uint8_t reserved2[16]; 1078} __packed; 1079 |
1031union mfi_spare_type { 1032 struct { 1033 uint8_t is_dedicate :1; 1034 uint8_t is_revertable :1; 1035 uint8_t is_encl_affinity :1; 1036 uint8_t reserved :5; 1037 } v; 1038 uint8_t type; 1039} __packed; 1040 | |
1041#define MAX_ARRAYS 16 1042struct mfi_spare { 1043 union mfi_pd_ref ref; | 1080#define MAX_ARRAYS 16 1081struct mfi_spare { 1082 union mfi_pd_ref ref; |
1044 union mfi_spare_type spare_type; | 1083 uint8_t spare_type; 1084#define MFI_SPARE_DEDICATED (1 << 0) 1085#define MFI_SPARE_REVERTIBLE (1 << 1) 1086#define MFI_SPARE_ENCL_AFFINITY (1 << 2) |
1045 uint8_t reserved[2]; 1046 uint8_t array_count; | 1087 uint8_t reserved[2]; 1088 uint8_t array_count; |
1047 uint16_t array_refd[MAX_ARRAYS]; | 1089 uint16_t array_ref[MAX_ARRAYS]; |
1048} __packed; 1049 | 1090} __packed; 1091 |
1050#define MAX_ROW_SIZE 32 | |
1051struct mfi_array { 1052 uint64_t size; 1053 uint8_t num_drives; 1054 uint8_t reserved; 1055 uint16_t array_ref; 1056 uint8_t pad[20]; 1057 struct { | 1092struct mfi_array { 1093 uint64_t size; 1094 uint8_t num_drives; 1095 uint8_t reserved; 1096 uint16_t array_ref; 1097 uint8_t pad[20]; 1098 struct { |
1058 union mfi_pd_ref ref; 1059 uint16_t fw_state; | 1099 union mfi_pd_ref ref; /* 0xffff == missing drive */ 1100 uint16_t fw_state; /* MFI_PD_STATE_* */ |
1060 struct { 1061 uint8_t pd; 1062 uint8_t slot; 1063 } encl; | 1101 struct { 1102 uint8_t pd; 1103 uint8_t slot; 1104 } encl; |
1064 } pd[MAX_ROW_SIZE]; | 1105 } pd[0]; |
1065} __packed; 1066 1067struct mfi_config_data { 1068 uint32_t size; 1069 uint16_t array_count; 1070 uint16_t array_size; 1071 uint16_t log_drv_count; 1072 uint16_t log_drv_size; 1073 uint16_t spares_count; 1074 uint16_t spares_size; 1075 uint8_t reserved[16]; | 1106} __packed; 1107 1108struct mfi_config_data { 1109 uint32_t size; 1110 uint16_t array_count; 1111 uint16_t array_size; 1112 uint16_t log_drv_count; 1113 uint16_t log_drv_size; 1114 uint16_t spares_count; 1115 uint16_t spares_size; 1116 uint8_t reserved[16]; |
1076 uint8_t data; 1077 /* 1078 struct mfi_array array[]; 1079 struct mfi_ld_config ld[]; 1080 struct mfi_spare spare[]; 1081 */ | 1117 struct mfi_array array[0]; 1118 struct mfi_ld_config ld[0]; 1119 struct mfi_spare spare[0]; |
1082} __packed; 1083 | 1120} __packed; 1121 |
1122struct mfi_bbu_capacity_info { 1123 uint16_t relative_charge; 1124 uint16_t absolute_charge; 1125 uint16_t remaining_capacity; 1126 uint16_t full_charge_capacity; 1127 uint16_t run_time_to_empty; 1128 uint16_t average_time_to_empty; 1129 uint16_t average_time_to_full; 1130 uint16_t cycle_count; 1131 uint16_t max_error; 1132 uint16_t remaining_capacity_alarm; 1133 uint16_t remaining_time_alarm; 1134 uint8_t reserved[26]; 1135} __packed; 1136 1137struct mfi_bbu_design_info { 1138 uint32_t mfg_date; 1139 uint16_t design_capacity; 1140 uint16_t design_voltage; 1141 uint16_t spec_info; 1142 uint16_t serial_number; 1143 uint16_t pack_stat_config; 1144 uint8_t mfg_name[12]; 1145 uint8_t device_name[8]; 1146 uint8_t device_chemistry[8]; 1147 uint8_t mfg_data[8]; 1148 uint8_t reserved[17]; 1149} __packed; 1150 1151struct mfi_ibbu_state { 1152 uint16_t gas_guage_status; 1153 uint16_t relative_charge; 1154 uint16_t charger_system_state; 1155 uint16_t charger_system_ctrl; 1156 uint16_t charging_current; 1157 uint16_t absolute_charge; 1158 uint16_t max_error; 1159 uint8_t reserved[18]; 1160} __packed; 1161 1162struct mfi_bbu_state { 1163 uint16_t gas_guage_status; 1164 uint16_t relative_charge; 1165 uint16_t charger_status; 1166 uint16_t remaining_capacity; 1167 uint16_t full_charge_capacity; 1168 uint8_t is_SOH_good; 1169 uint8_t reserved[21]; 1170} __packed; 1171 1172union mfi_bbu_status_detail { 1173 struct mfi_ibbu_state ibbu; 1174 struct mfi_bbu_state bbu; 1175}; 1176 1177struct mfi_bbu_status { 1178 uint8_t battery_type; 1179#define MFI_BBU_TYPE_NONE 0 1180#define MFI_BBU_TYPE_IBBU 1 1181#define MFI_BBU_TYPE_BBU 2 1182 uint8_t reserved; 1183 uint16_t voltage; 1184 int16_t current; 1185 uint16_t temperature; 1186 uint32_t fw_status; 1187#define MFI_BBU_STATE_PACK_MISSING (1 << 0) 1188#define MFI_BBU_STATE_VOLTAGE_LOW (1 << 1) 1189#define MFI_BBU_STATE_TEMPERATURE_HIGH (1 << 2) 1190#define MFI_BBU_STATE_CHARGE_ACTIVE (1 << 0) 1191#define MFI_BBU_STATE_DISCHARGE_ACTIVE (1 << 0) 1192 uint8_t pad[20]; 1193 union mfi_bbu_status_detail detail; 1194} __packed; 1195 1196enum mfi_pr_state { 1197 MFI_PR_STATE_STOPPED = 0, 1198 MFI_PR_STATE_READY = 1, 1199 MFI_PR_STATE_ACTIVE = 2, 1200 MFI_PR_STATE_ABORTED = 0xff 1201}; 1202 1203struct mfi_pr_status { 1204 uint32_t num_iteration; 1205 uint8_t state; 1206 uint8_t num_pd_done; 1207 uint8_t reserved[10]; 1208}; 1209 1210enum mfi_pr_opmode { 1211 MFI_PR_OPMODE_AUTO = 0, 1212 MFI_PR_OPMODE_MANUAL = 1, 1213 MFI_PR_OPMODE_DISABLED = 2 1214}; 1215 1216struct mfi_pr_properties { 1217 uint8_t op_mode; 1218 uint8_t max_pd; 1219 uint8_t reserved; 1220 uint8_t exclude_ld_count; 1221 uint16_t excluded_ld[MFI_MAX_LD]; 1222 uint8_t cur_pd_map[MFI_MAX_PD / 8]; 1223 uint8_t last_pd_map[MFI_MAX_PD / 8]; 1224 uint32_t next_exec; 1225 uint32_t exec_freq; 1226 uint32_t clear_freq; 1227}; 1228 |
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1084#define MFI_SCSI_MAX_TARGETS 128 1085#define MFI_SCSI_MAX_LUNS 8 1086#define MFI_SCSI_INITIATOR_ID 255 1087#define MFI_SCSI_MAX_CMDS 8 1088#define MFI_SCSI_MAX_CDB_LEN 16 1089 1090#endif /* _MFIREG_H */ | 1229#define MFI_SCSI_MAX_TARGETS 128 1230#define MFI_SCSI_MAX_LUNS 8 1231#define MFI_SCSI_INITIATOR_ID 255 1232#define MFI_SCSI_MAX_CMDS 8 1233#define MFI_SCSI_MAX_CDB_LEN 16 1234 1235#endif /* _MFIREG_H */ |