| mc146818reg.h (166149) | mc146818reg.h (201008) |
|---|---|
| 1/*- 2 * Copyright (c) 1995 Carnegie-Mellon University. 3 * All rights reserved. | 1/*- 2 * Copyright (c) 1995 Carnegie-Mellon University. 3 * All rights reserved. |
| 4 * | 4 * |
| 5 * Permission to use, copy, modify and distribute this software and 6 * its documentation is hereby granted, provided that both the copyright 7 * notice and this permission notice appear in all copies of the 8 * software, derivative works or modified versions, and any portions 9 * thereof, and that both notices appear in supporting documentation. | 5 * Permission to use, copy, modify and distribute this software and 6 * its documentation is hereby granted, provided that both the copyright 7 * notice and this permission notice appear in all copies of the 8 * software, derivative works or modified versions, and any portions 9 * thereof, and that both notices appear in supporting documentation. |
| 10 * 11 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 12 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND | 10 * 11 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 12 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND |
| 13 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. | 13 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. |
| 14 * | 14 * |
| 15 * Carnegie Mellon requests users of this software to return to 16 * 17 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 18 * School of Computer Science 19 * Carnegie Mellon University 20 * Pittsburgh PA 15213-3890 21 * 22 * any improvements or extensions that they make and grant Carnegie the 23 * rights to redistribute these changes. 24 * | 15 * Carnegie Mellon requests users of this software to return to 16 * 17 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU 18 * School of Computer Science 19 * Carnegie Mellon University 20 * Pittsburgh PA 15213-3890 21 * 22 * any improvements or extensions that they make and grant Carnegie the 23 * rights to redistribute these changes. 24 * |
| 25 * from: NetBSD: mc146818reg.h,v 1.5 2003/11/02 11:07:45 wiz Exp | 25 * $NetBSD: mc146818reg.h,v 1.9 2006/03/08 23:46:25 lukem Exp $ |
| 26 * | 26 * |
| 27 * $FreeBSD: head/sys/dev/mc146818/mc146818reg.h 166149 2007-01-20 14:57:51Z marius $ | 27 * $FreeBSD: head/sys/dev/mc146818/mc146818reg.h 201008 2009-12-25 22:53:46Z marius $ |
| 28 */ 29 30/* 31 * Definitions for the Motorola MC146818A Real Time Clock. 32 * They also apply for the (compatible) Dallas Semiconductor DS1287A RTC. 33 * 34 * Though there are undoubtedly other (better) sources, this material was 35 * culled from the DEC "KN121 System Module Programmer's Reference --- 81 unchanged lines hidden (view full) --- 117 118#define MC_NVRAM_START 0xe /* start of NVRAM: offset 14 */ 119#define MC_NVRAM_SIZE 50 /* 50 bytes of NVRAM */ 120 121/* 122 * Periodic Interrupt Rate Select constants (Control register A) 123 */ 124#define MC_RATE_NONE 0x0 /* No periodic interrupt */ | 28 */ 29 30/* 31 * Definitions for the Motorola MC146818A Real Time Clock. 32 * They also apply for the (compatible) Dallas Semiconductor DS1287A RTC. 33 * 34 * Though there are undoubtedly other (better) sources, this material was 35 * culled from the DEC "KN121 System Module Programmer's Reference --- 81 unchanged lines hidden (view full) --- 117 118#define MC_NVRAM_START 0xe /* start of NVRAM: offset 14 */ 119#define MC_NVRAM_SIZE 50 /* 50 bytes of NVRAM */ 120 121/* 122 * Periodic Interrupt Rate Select constants (Control register A) 123 */ 124#define MC_RATE_NONE 0x0 /* No periodic interrupt */ |
| 125#define MC_RATE_1 0x1 /* 256 Hz if MC_BASE_32_KHz, else 32768 Hz */ 126#define MC_RATE_2 0x2 /* 128 Hz if MC_BASE_32_KHz, else 16384 Hz */ | 125#define MC_RATE_1 0x1 /* 256 Hz if MC_BASE_32_KHz, else 32768 Hz */ 126#define MC_RATE_2 0x2 /* 128 Hz if MC_BASE_32_KHz, else 16384 Hz */ |
| 127#define MC_RATE_8192_Hz 0x3 /* 122.070 us period */ 128#define MC_RATE_4096_Hz 0x4 /* 244.141 us period */ 129#define MC_RATE_2048_Hz 0x5 /* 488.281 us period */ 130#define MC_RATE_1024_Hz 0x6 /* 976.562 us period */ 131#define MC_RATE_512_Hz 0x7 /* 1.953125 ms period */ 132#define MC_RATE_256_Hz 0x8 /* 3.90625 ms period */ 133#define MC_RATE_128_Hz 0x9 /* 7.8125 ms period */ 134#define MC_RATE_64_Hz 0xa /* 15.625 ms period */ 135#define MC_RATE_32_Hz 0xb /* 31.25 ms period */ 136#define MC_RATE_16_Hz 0xc /* 62.5 ms period */ 137#define MC_RATE_8_Hz 0xd /* 125 ms period */ 138#define MC_RATE_4_Hz 0xe /* 250 ms period */ 139#define MC_RATE_2_Hz 0xf /* 500 ms period */ 140 141/* 142 * Time base (divisor select) constants (Control register A) 143 */ | 127#define MC_RATE_8192_Hz 0x3 /* 122.070 us period */ 128#define MC_RATE_4096_Hz 0x4 /* 244.141 us period */ 129#define MC_RATE_2048_Hz 0x5 /* 488.281 us period */ 130#define MC_RATE_1024_Hz 0x6 /* 976.562 us period */ 131#define MC_RATE_512_Hz 0x7 /* 1.953125 ms period */ 132#define MC_RATE_256_Hz 0x8 /* 3.90625 ms period */ 133#define MC_RATE_128_Hz 0x9 /* 7.8125 ms period */ 134#define MC_RATE_64_Hz 0xa /* 15.625 ms period */ 135#define MC_RATE_32_Hz 0xb /* 31.25 ms period */ 136#define MC_RATE_16_Hz 0xc /* 62.5 ms period */ 137#define MC_RATE_8_Hz 0xd /* 125 ms period */ 138#define MC_RATE_4_Hz 0xe /* 250 ms period */ 139#define MC_RATE_2_Hz 0xf /* 500 ms period */ 140 141/* 142 * Time base (divisor select) constants (Control register A) 143 */ |
| 144#define MC_BASE_4_MHz 0x00 /* 4MHz crystal */ 145#define MC_BASE_1_MHz MC_REGA_DV0 /* 1MHz crystal */ 146#define MC_BASE_32_KHz MC_REGA_DV1 /* 32KHz crystal */ | 144#define MC_BASE_4_MHz 0x00 /* 4 MHz crystal */ 145#define MC_BASE_1_MHz MC_REGA_DV0 /* 1 MHz crystal */ 146#define MC_BASE_32_KHz MC_REGA_DV1 /* 32 KHz crystal */ |
| 147#define MC_BASE_NONE (MC_REGA_DV2 | MC_REGA_DV1) /* actually also resets */ 148#define MC_BASE_RESET (MC_REGA_DV2 | MC_REGA_DV1 | MC_REGA_DV0) | 147#define MC_BASE_NONE (MC_REGA_DV2 | MC_REGA_DV1) /* actually also resets */ 148#define MC_BASE_RESET (MC_REGA_DV2 | MC_REGA_DV1 | MC_REGA_DV0) |