1/*-
2 * Copyright (c) 2007-2009
3 * Damien Bergamini <damien.bergamini@free.fr>
4 * Copyright (c) 2008
5 * Benjamin Close <benjsc@FreeBSD.org>
6 * Copyright (c) 2008 Sam Leffler, Errno Consulting
7 *
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 */
20
21/*
22 * Driver for Intel WiFi Link 4965 and 1000/5000/6000 Series 802.11 network
23 * adapters.
24 */
25
26#include <sys/cdefs.h>
27__FBSDID("$FreeBSD: head/sys/dev/iwn/if_iwn.c 252717 2013-07-04 19:45:34Z adrian $");
28
29#include "opt_wlan.h"
30
31#include <sys/param.h>
32#include <sys/sockio.h>
33#include <sys/sysctl.h>
34#include <sys/mbuf.h>
35#include <sys/kernel.h>
36#include <sys/socket.h>
37#include <sys/systm.h>
38#include <sys/malloc.h>
39#include <sys/bus.h>
40#include <sys/rman.h>
41#include <sys/endian.h>
42#include <sys/firmware.h>
43#include <sys/limits.h>
44#include <sys/module.h>
45#include <sys/queue.h>
46#include <sys/taskqueue.h>
47
48#include <machine/bus.h>
49#include <machine/resource.h>
50#include <machine/clock.h>
51
52#include <dev/pci/pcireg.h>
53#include <dev/pci/pcivar.h>
54
55#include <net/bpf.h>
56#include <net/if.h>
57#include <net/if_arp.h>
58#include <net/ethernet.h>
59#include <net/if_dl.h>
60#include <net/if_media.h>
61#include <net/if_types.h>
62
63#include <netinet/in.h>
64#include <netinet/in_systm.h>
65#include <netinet/in_var.h>
66#include <netinet/if_ether.h>
67#include <netinet/ip.h>
68
69#include <net80211/ieee80211_var.h>
70#include <net80211/ieee80211_radiotap.h>
71#include <net80211/ieee80211_regdomain.h>
72#include <net80211/ieee80211_ratectl.h>
73
74#include <dev/iwn/if_iwnreg.h>
75#include <dev/iwn/if_iwnvar.h>
76
77struct iwn_ident {
78 uint16_t vendor;
79 uint16_t device;
80 const char *name;
81};
82
83static const struct iwn_ident iwn_ident_table[] = {
84 { 0x8086, 0x0082, "Intel Centrino Advanced-N 6205" },
85 { 0x8086, 0x0083, "Intel Centrino Wireless-N 1000" },
86 { 0x8086, 0x0084, "Intel Centrino Wireless-N 1000" },
87 { 0x8086, 0x0085, "Intel Centrino Advanced-N 6205" },
88 { 0x8086, 0x0087, "Intel Centrino Advanced-N + WiMAX 6250" },
89 { 0x8086, 0x0089, "Intel Centrino Advanced-N + WiMAX 6250" },
90 { 0x8086, 0x008a, "Intel Centrino Wireless-N 1030" },
91 { 0x8086, 0x008b, "Intel Centrino Wireless-N 1030" },
92 { 0x8086, 0x0090, "Intel Centrino Advanced-N 6230" },
93 { 0x8086, 0x0091, "Intel Centrino Advanced-N 6230" },
94 { 0x8086, 0x0885, "Intel Centrino Wireless-N + WiMAX 6150" },
95 { 0x8086, 0x0886, "Intel Centrino Wireless-N + WiMAX 6150" },
96 { 0x8086, 0x0896, "Intel Centrino Wireless-N 130" },
97 { 0x8086, 0x0897, "Intel Centrino Wireless-N 130" },
98 { 0x8086, 0x08ae, "Intel Centrino Wireless-N 100" },
99 { 0x8086, 0x08af, "Intel Centrino Wireless-N 100" },
100 { 0x8086, 0x4229, "Intel Wireless WiFi Link 4965" },
101 { 0x8086, 0x422b, "Intel Centrino Ultimate-N 6300" },
102 { 0x8086, 0x422c, "Intel Centrino Advanced-N 6200" },
103 { 0x8086, 0x422d, "Intel Wireless WiFi Link 4965" },
104 { 0x8086, 0x4230, "Intel Wireless WiFi Link 4965" },
105 { 0x8086, 0x4232, "Intel WiFi Link 5100" },
106 { 0x8086, 0x4233, "Intel Wireless WiFi Link 4965" },
107 { 0x8086, 0x4235, "Intel Ultimate N WiFi Link 5300" },
108 { 0x8086, 0x4236, "Intel Ultimate N WiFi Link 5300" },
109 { 0x8086, 0x4237, "Intel WiFi Link 5100" },
110 { 0x8086, 0x4238, "Intel Centrino Ultimate-N 6300" },
111 { 0x8086, 0x4239, "Intel Centrino Advanced-N 6200" },
112 { 0x8086, 0x423a, "Intel WiMAX/WiFi Link 5350" },
113 { 0x8086, 0x423b, "Intel WiMAX/WiFi Link 5350" },
114 { 0x8086, 0x423c, "Intel WiMAX/WiFi Link 5150" },
115 { 0x8086, 0x423d, "Intel WiMAX/WiFi Link 5150" },
116 { 0, 0, NULL }
117};
118
119static int iwn_probe(device_t);
120static int iwn_attach(device_t);
121static int iwn4965_attach(struct iwn_softc *, uint16_t);
122static int iwn5000_attach(struct iwn_softc *, uint16_t);
123static void iwn_radiotap_attach(struct iwn_softc *);
124static void iwn_sysctlattach(struct iwn_softc *);
125static struct ieee80211vap *iwn_vap_create(struct ieee80211com *,
126 const char [IFNAMSIZ], int, enum ieee80211_opmode, int,
127 const uint8_t [IEEE80211_ADDR_LEN],
128 const uint8_t [IEEE80211_ADDR_LEN]);
129static void iwn_vap_delete(struct ieee80211vap *);
130static int iwn_detach(device_t);
131static int iwn_shutdown(device_t);
132static int iwn_suspend(device_t);
133static int iwn_resume(device_t);
134static int iwn_nic_lock(struct iwn_softc *);
135static int iwn_eeprom_lock(struct iwn_softc *);
136static int iwn_init_otprom(struct iwn_softc *);
137static int iwn_read_prom_data(struct iwn_softc *, uint32_t, void *, int);
138static void iwn_dma_map_addr(void *, bus_dma_segment_t *, int, int);
139static int iwn_dma_contig_alloc(struct iwn_softc *, struct iwn_dma_info *,
140 void **, bus_size_t, bus_size_t);
141static void iwn_dma_contig_free(struct iwn_dma_info *);
142static int iwn_alloc_sched(struct iwn_softc *);
143static void iwn_free_sched(struct iwn_softc *);
144static int iwn_alloc_kw(struct iwn_softc *);
145static void iwn_free_kw(struct iwn_softc *);
146static int iwn_alloc_ict(struct iwn_softc *);
147static void iwn_free_ict(struct iwn_softc *);
148static int iwn_alloc_fwmem(struct iwn_softc *);
149static void iwn_free_fwmem(struct iwn_softc *);
150static int iwn_alloc_rx_ring(struct iwn_softc *, struct iwn_rx_ring *);
151static void iwn_reset_rx_ring(struct iwn_softc *, struct iwn_rx_ring *);
152static void iwn_free_rx_ring(struct iwn_softc *, struct iwn_rx_ring *);
153static int iwn_alloc_tx_ring(struct iwn_softc *, struct iwn_tx_ring *,
154 int);
155static void iwn_reset_tx_ring(struct iwn_softc *, struct iwn_tx_ring *);
156static void iwn_free_tx_ring(struct iwn_softc *, struct iwn_tx_ring *);
157static void iwn5000_ict_reset(struct iwn_softc *);
158static int iwn_read_eeprom(struct iwn_softc *,
159 uint8_t macaddr[IEEE80211_ADDR_LEN]);
160static void iwn4965_read_eeprom(struct iwn_softc *);
161static void iwn4965_print_power_group(struct iwn_softc *, int);
162static void iwn5000_read_eeprom(struct iwn_softc *);
163static uint32_t iwn_eeprom_channel_flags(struct iwn_eeprom_chan *);
164static void iwn_read_eeprom_band(struct iwn_softc *, int);
165static void iwn_read_eeprom_ht40(struct iwn_softc *, int);
166static void iwn_read_eeprom_channels(struct iwn_softc *, int, uint32_t);
167static struct iwn_eeprom_chan *iwn_find_eeprom_channel(struct iwn_softc *,
168 struct ieee80211_channel *);
169static int iwn_setregdomain(struct ieee80211com *,
170 struct ieee80211_regdomain *, int,
171 struct ieee80211_channel[]);
172static void iwn_read_eeprom_enhinfo(struct iwn_softc *);
173static struct ieee80211_node *iwn_node_alloc(struct ieee80211vap *,
174 const uint8_t mac[IEEE80211_ADDR_LEN]);
175static void iwn_newassoc(struct ieee80211_node *, int);
176static int iwn_media_change(struct ifnet *);
177static int iwn_newstate(struct ieee80211vap *, enum ieee80211_state, int);
178static void iwn_calib_timeout(void *);
179static void iwn_rx_phy(struct iwn_softc *, struct iwn_rx_desc *,
180 struct iwn_rx_data *);
181static void iwn_rx_done(struct iwn_softc *, struct iwn_rx_desc *,
182 struct iwn_rx_data *);
183static void iwn_rx_compressed_ba(struct iwn_softc *, struct iwn_rx_desc *,
184 struct iwn_rx_data *);
185static void iwn5000_rx_calib_results(struct iwn_softc *,
186 struct iwn_rx_desc *, struct iwn_rx_data *);
187static void iwn_rx_statistics(struct iwn_softc *, struct iwn_rx_desc *,
188 struct iwn_rx_data *);
189static void iwn4965_tx_done(struct iwn_softc *, struct iwn_rx_desc *,
190 struct iwn_rx_data *);
191static void iwn5000_tx_done(struct iwn_softc *, struct iwn_rx_desc *,
192 struct iwn_rx_data *);
193static void iwn_tx_done(struct iwn_softc *, struct iwn_rx_desc *, int,
194 uint8_t);
195static void iwn_ampdu_tx_done(struct iwn_softc *, int, int, int, void *);
196static void iwn_cmd_done(struct iwn_softc *, struct iwn_rx_desc *);
197static void iwn_notif_intr(struct iwn_softc *);
198static void iwn_wakeup_intr(struct iwn_softc *);
199static void iwn_rftoggle_intr(struct iwn_softc *);
200static void iwn_fatal_intr(struct iwn_softc *);
201static void iwn_intr(void *);
202static void iwn4965_update_sched(struct iwn_softc *, int, int, uint8_t,
203 uint16_t);
204static void iwn5000_update_sched(struct iwn_softc *, int, int, uint8_t,
205 uint16_t);
206#ifdef notyet
207static void iwn5000_reset_sched(struct iwn_softc *, int, int);
208#endif
209static int iwn_tx_data(struct iwn_softc *, struct mbuf *,
210 struct ieee80211_node *);
211static int iwn_tx_data_raw(struct iwn_softc *, struct mbuf *,
212 struct ieee80211_node *,
213 const struct ieee80211_bpf_params *params);
214static int iwn_raw_xmit(struct ieee80211_node *, struct mbuf *,
215 const struct ieee80211_bpf_params *);
216static void iwn_start(struct ifnet *);
217static void iwn_start_locked(struct ifnet *);
218static void iwn_watchdog(void *);
219static int iwn_ioctl(struct ifnet *, u_long, caddr_t);
220static int iwn_cmd(struct iwn_softc *, int, const void *, int, int);
221static int iwn4965_add_node(struct iwn_softc *, struct iwn_node_info *,
222 int);
223static int iwn5000_add_node(struct iwn_softc *, struct iwn_node_info *,
224 int);
225static int iwn_set_link_quality(struct iwn_softc *,
226 struct ieee80211_node *);
227static int iwn_add_broadcast_node(struct iwn_softc *, int);
228static int iwn_updateedca(struct ieee80211com *);
229static void iwn_update_mcast(struct ifnet *);
230static void iwn_set_led(struct iwn_softc *, uint8_t, uint8_t, uint8_t);
231static int iwn_set_critical_temp(struct iwn_softc *);
232static int iwn_set_timing(struct iwn_softc *, struct ieee80211_node *);
233static void iwn4965_power_calibration(struct iwn_softc *, int);
234static int iwn4965_set_txpower(struct iwn_softc *,
235 struct ieee80211_channel *, int);
236static int iwn5000_set_txpower(struct iwn_softc *,
237 struct ieee80211_channel *, int);
238static int iwn4965_get_rssi(struct iwn_softc *, struct iwn_rx_stat *);
239static int iwn5000_get_rssi(struct iwn_softc *, struct iwn_rx_stat *);
240static int iwn_get_noise(const struct iwn_rx_general_stats *);
241static int iwn4965_get_temperature(struct iwn_softc *);
242static int iwn5000_get_temperature(struct iwn_softc *);
243static int iwn_init_sensitivity(struct iwn_softc *);
244static void iwn_collect_noise(struct iwn_softc *,
245 const struct iwn_rx_general_stats *);
246static int iwn4965_init_gains(struct iwn_softc *);
247static int iwn5000_init_gains(struct iwn_softc *);
248static int iwn4965_set_gains(struct iwn_softc *);
249static int iwn5000_set_gains(struct iwn_softc *);
250static void iwn_tune_sensitivity(struct iwn_softc *,
251 const struct iwn_rx_stats *);
252static int iwn_send_sensitivity(struct iwn_softc *);
253static int iwn_set_pslevel(struct iwn_softc *, int, int, int);
254static int iwn_send_btcoex(struct iwn_softc *);
255static int iwn_send_advanced_btcoex(struct iwn_softc *);
256static int iwn5000_runtime_calib(struct iwn_softc *);
257static int iwn_config(struct iwn_softc *);
258static uint8_t *ieee80211_add_ssid(uint8_t *, const uint8_t *, u_int);
259static int iwn_scan(struct iwn_softc *);
260static int iwn_auth(struct iwn_softc *, struct ieee80211vap *vap);
261static int iwn_run(struct iwn_softc *, struct ieee80211vap *vap);
262static int iwn_ampdu_rx_start(struct ieee80211_node *,
263 struct ieee80211_rx_ampdu *, int, int, int);
264static void iwn_ampdu_rx_stop(struct ieee80211_node *,
265 struct ieee80211_rx_ampdu *);
266static int iwn_addba_request(struct ieee80211_node *,
267 struct ieee80211_tx_ampdu *, int, int, int);
268static int iwn_addba_response(struct ieee80211_node *,
269 struct ieee80211_tx_ampdu *, int, int, int);
270static int iwn_ampdu_tx_start(struct ieee80211com *,
271 struct ieee80211_node *, uint8_t);
272static void iwn_ampdu_tx_stop(struct ieee80211_node *,
273 struct ieee80211_tx_ampdu *);
274static void iwn4965_ampdu_tx_start(struct iwn_softc *,
275 struct ieee80211_node *, int, uint8_t, uint16_t);
276static void iwn4965_ampdu_tx_stop(struct iwn_softc *, int,
277 uint8_t, uint16_t);
278static void iwn5000_ampdu_tx_start(struct iwn_softc *,
279 struct ieee80211_node *, int, uint8_t, uint16_t);
280static void iwn5000_ampdu_tx_stop(struct iwn_softc *, int,
281 uint8_t, uint16_t);
282static int iwn5000_query_calibration(struct iwn_softc *);
283static int iwn5000_send_calibration(struct iwn_softc *);
284static int iwn5000_send_wimax_coex(struct iwn_softc *);
285static int iwn5000_crystal_calib(struct iwn_softc *);
286static int iwn5000_temp_offset_calib(struct iwn_softc *);
287static int iwn4965_post_alive(struct iwn_softc *);
288static int iwn5000_post_alive(struct iwn_softc *);
289static int iwn4965_load_bootcode(struct iwn_softc *, const uint8_t *,
290 int);
291static int iwn4965_load_firmware(struct iwn_softc *);
292static int iwn5000_load_firmware_section(struct iwn_softc *, uint32_t,
293 const uint8_t *, int);
294static int iwn5000_load_firmware(struct iwn_softc *);
295static int iwn_read_firmware_leg(struct iwn_softc *,
296 struct iwn_fw_info *);
297static int iwn_read_firmware_tlv(struct iwn_softc *,
298 struct iwn_fw_info *, uint16_t);
299static int iwn_read_firmware(struct iwn_softc *);
300static int iwn_clock_wait(struct iwn_softc *);
301static int iwn_apm_init(struct iwn_softc *);
302static void iwn_apm_stop_master(struct iwn_softc *);
303static void iwn_apm_stop(struct iwn_softc *);
304static int iwn4965_nic_config(struct iwn_softc *);
305static int iwn5000_nic_config(struct iwn_softc *);
306static int iwn_hw_prepare(struct iwn_softc *);
307static int iwn_hw_init(struct iwn_softc *);
308static void iwn_hw_stop(struct iwn_softc *);
309static void iwn_radio_on(void *, int);
310static void iwn_radio_off(void *, int);
311static void iwn_init_locked(struct iwn_softc *);
312static void iwn_init(void *);
313static void iwn_stop_locked(struct iwn_softc *);
314static void iwn_stop(struct iwn_softc *);
315static void iwn_scan_start(struct ieee80211com *);
316static void iwn_scan_end(struct ieee80211com *);
317static void iwn_set_channel(struct ieee80211com *);
318static void iwn_scan_curchan(struct ieee80211_scan_state *, unsigned long);
319static void iwn_scan_mindwell(struct ieee80211_scan_state *);
320static void iwn_hw_reset(void *, int);
321
322#define IWN_DEBUG
323#ifdef IWN_DEBUG
324enum {
325 IWN_DEBUG_XMIT = 0x00000001, /* basic xmit operation */
326 IWN_DEBUG_RECV = 0x00000002, /* basic recv operation */
327 IWN_DEBUG_STATE = 0x00000004, /* 802.11 state transitions */
328 IWN_DEBUG_TXPOW = 0x00000008, /* tx power processing */
329 IWN_DEBUG_RESET = 0x00000010, /* reset processing */
330 IWN_DEBUG_OPS = 0x00000020, /* iwn_ops processing */
331 IWN_DEBUG_BEACON = 0x00000040, /* beacon handling */
332 IWN_DEBUG_WATCHDOG = 0x00000080, /* watchdog timeout */
333 IWN_DEBUG_INTR = 0x00000100, /* ISR */
334 IWN_DEBUG_CALIBRATE = 0x00000200, /* periodic calibration */
335 IWN_DEBUG_NODE = 0x00000400, /* node management */
336 IWN_DEBUG_LED = 0x00000800, /* led management */
337 IWN_DEBUG_CMD = 0x00001000, /* cmd submission */
338 IWN_DEBUG_FATAL = 0x80000000, /* fatal errors */
339 IWN_DEBUG_ANY = 0xffffffff
340};
341
342#define DPRINTF(sc, m, fmt, ...) do { \
343 if (sc->sc_debug & (m)) \
344 printf(fmt, __VA_ARGS__); \
345} while (0)
346
347static const char *
348iwn_intr_str(uint8_t cmd)
349{
350 switch (cmd) {
351 /* Notifications */
352 case IWN_UC_READY: return "UC_READY";
353 case IWN_ADD_NODE_DONE: return "ADD_NODE_DONE";
354 case IWN_TX_DONE: return "TX_DONE";
355 case IWN_START_SCAN: return "START_SCAN";
356 case IWN_STOP_SCAN: return "STOP_SCAN";
357 case IWN_RX_STATISTICS: return "RX_STATS";
358 case IWN_BEACON_STATISTICS: return "BEACON_STATS";
359 case IWN_STATE_CHANGED: return "STATE_CHANGED";
360 case IWN_BEACON_MISSED: return "BEACON_MISSED";
361 case IWN_RX_PHY: return "RX_PHY";
362 case IWN_MPDU_RX_DONE: return "MPDU_RX_DONE";
363 case IWN_RX_DONE: return "RX_DONE";
364
365 /* Command Notifications */
366 case IWN_CMD_RXON: return "IWN_CMD_RXON";
367 case IWN_CMD_RXON_ASSOC: return "IWN_CMD_RXON_ASSOC";
368 case IWN_CMD_EDCA_PARAMS: return "IWN_CMD_EDCA_PARAMS";
369 case IWN_CMD_TIMING: return "IWN_CMD_TIMING";
370 case IWN_CMD_LINK_QUALITY: return "IWN_CMD_LINK_QUALITY";
371 case IWN_CMD_SET_LED: return "IWN_CMD_SET_LED";
372 case IWN5000_CMD_WIMAX_COEX: return "IWN5000_CMD_WIMAX_COEX";
373 case IWN5000_CMD_CALIB_CONFIG: return "IWN5000_CMD_CALIB_CONFIG";
374 case IWN5000_CMD_CALIB_RESULT: return "IWN5000_CMD_CALIB_RESULT";
375 case IWN5000_CMD_CALIB_COMPLETE: return "IWN5000_CMD_CALIB_COMPLETE";
376 case IWN_CMD_SET_POWER_MODE: return "IWN_CMD_SET_POWER_MODE";
377 case IWN_CMD_SCAN: return "IWN_CMD_SCAN";
378 case IWN_CMD_SCAN_RESULTS: return "IWN_CMD_SCAN_RESULTS";
379 case IWN_CMD_TXPOWER: return "IWN_CMD_TXPOWER";
380 case IWN_CMD_TXPOWER_DBM: return "IWN_CMD_TXPOWER_DBM";
381 case IWN5000_CMD_TX_ANT_CONFIG: return "IWN5000_CMD_TX_ANT_CONFIG";
382 case IWN_CMD_BT_COEX: return "IWN_CMD_BT_COEX";
383 case IWN_CMD_SET_CRITICAL_TEMP: return "IWN_CMD_SET_CRITICAL_TEMP";
384 case IWN_CMD_SET_SENSITIVITY: return "IWN_CMD_SET_SENSITIVITY";
385 case IWN_CMD_PHY_CALIB: return "IWN_CMD_PHY_CALIB";
386 }
387 return "UNKNOWN INTR NOTIF/CMD";
388}
389#else
390#define DPRINTF(sc, m, fmt, ...) do { (void) sc; } while (0)
391#endif
392
393static device_method_t iwn_methods[] = {
394 /* Device interface */
395 DEVMETHOD(device_probe, iwn_probe),
396 DEVMETHOD(device_attach, iwn_attach),
397 DEVMETHOD(device_detach, iwn_detach),
398 DEVMETHOD(device_shutdown, iwn_shutdown),
399 DEVMETHOD(device_suspend, iwn_suspend),
400 DEVMETHOD(device_resume, iwn_resume),
401 { 0, 0 }
402};
403
404static driver_t iwn_driver = {
405 "iwn",
406 iwn_methods,
407 sizeof(struct iwn_softc)
408};
409static devclass_t iwn_devclass;
410
411DRIVER_MODULE(iwn, pci, iwn_driver, iwn_devclass, 0, 0);
412
413MODULE_VERSION(iwn, 1);
414
415MODULE_DEPEND(iwn, firmware, 1, 1, 1);
416MODULE_DEPEND(iwn, pci, 1, 1, 1);
417MODULE_DEPEND(iwn, wlan, 1, 1, 1);
418
419static int
420iwn_probe(device_t dev)
421{
422 const struct iwn_ident *ident;
423
424 for (ident = iwn_ident_table; ident->name != NULL; ident++) {
425 if (pci_get_vendor(dev) == ident->vendor &&
426 pci_get_device(dev) == ident->device) {
427 device_set_desc(dev, ident->name);
428 return 0;
429 }
430 }
431 return ENXIO;
432}
433
434static int
435iwn_attach(device_t dev)
436{
437 struct iwn_softc *sc = (struct iwn_softc *)device_get_softc(dev);
438 struct ieee80211com *ic;
439 struct ifnet *ifp;
440 uint32_t reg;
441 int i, error, result;
442 uint8_t macaddr[IEEE80211_ADDR_LEN];
443
444 sc->sc_dev = dev;
445
446 /*
447 * Get the offset of the PCI Express Capability Structure in PCI
448 * Configuration Space.
449 */
450 error = pci_find_cap(dev, PCIY_EXPRESS, &sc->sc_cap_off);
451 if (error != 0) {
452 device_printf(dev, "PCIe capability structure not found!\n");
453 return error;
454 }
455
456 /* Clear device-specific "PCI retry timeout" register (41h). */
457 pci_write_config(dev, 0x41, 0, 1);
458
459 /* Hardware bug workaround. */
460 reg = pci_read_config(dev, PCIR_COMMAND, 1);
461 if (reg & PCIM_CMD_INTxDIS) {
462 DPRINTF(sc, IWN_DEBUG_RESET, "%s: PCIe INTx Disable set\n",
463 __func__);
464 reg &= ~PCIM_CMD_INTxDIS;
465 pci_write_config(dev, PCIR_COMMAND, reg, 1);
466 }
467
468 /* Enable bus-mastering. */
469 pci_enable_busmaster(dev);
470
471 sc->mem_rid = PCIR_BAR(0);
472 sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
473 RF_ACTIVE);
474 if (sc->mem == NULL) {
475 device_printf(dev, "can't map mem space\n");
476 error = ENOMEM;
477 return error;
478 }
479 sc->sc_st = rman_get_bustag(sc->mem);
480 sc->sc_sh = rman_get_bushandle(sc->mem);
481
482 sc->irq_rid = 0;
483 if ((result = pci_msi_count(dev)) == 1 &&
484 pci_alloc_msi(dev, &result) == 0)
485 sc->irq_rid = 1;
486 /* Install interrupt handler. */
487 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
488 RF_ACTIVE | RF_SHAREABLE);
489 if (sc->irq == NULL) {
490 device_printf(dev, "can't map interrupt\n");
491 error = ENOMEM;
492 goto fail;
493 }
494
495 IWN_LOCK_INIT(sc);
496
497 /* Read hardware revision and attach. */
498 sc->hw_type = (IWN_READ(sc, IWN_HW_REV) >> 4) & 0xf;
499 if (sc->hw_type == IWN_HW_REV_TYPE_4965)
500 error = iwn4965_attach(sc, pci_get_device(dev));
501 else
502 error = iwn5000_attach(sc, pci_get_device(dev));
503 if (error != 0) {
504 device_printf(dev, "could not attach device, error %d\n",
505 error);
506 goto fail;
507 }
508
509 if ((error = iwn_hw_prepare(sc)) != 0) {
510 device_printf(dev, "hardware not ready, error %d\n", error);
511 goto fail;
512 }
513
514 /* Allocate DMA memory for firmware transfers. */
515 if ((error = iwn_alloc_fwmem(sc)) != 0) {
516 device_printf(dev,
517 "could not allocate memory for firmware, error %d\n",
518 error);
519 goto fail;
520 }
521
522 /* Allocate "Keep Warm" page. */
523 if ((error = iwn_alloc_kw(sc)) != 0) {
524 device_printf(dev,
525 "could not allocate keep warm page, error %d\n", error);
526 goto fail;
527 }
528
529 /* Allocate ICT table for 5000 Series. */
530 if (sc->hw_type != IWN_HW_REV_TYPE_4965 &&
531 (error = iwn_alloc_ict(sc)) != 0) {
532 device_printf(dev, "could not allocate ICT table, error %d\n",
533 error);
534 goto fail;
535 }
536
537 /* Allocate TX scheduler "rings". */
538 if ((error = iwn_alloc_sched(sc)) != 0) {
539 device_printf(dev,
540 "could not allocate TX scheduler rings, error %d\n", error);
541 goto fail;
542 }
543
544 /* Allocate TX rings (16 on 4965AGN, 20 on >=5000). */
545 for (i = 0; i < sc->ntxqs; i++) {
546 if ((error = iwn_alloc_tx_ring(sc, &sc->txq[i], i)) != 0) {
547 device_printf(dev,
548 "could not allocate TX ring %d, error %d\n", i,
549 error);
550 goto fail;
551 }
552 }
553
554 /* Allocate RX ring. */
555 if ((error = iwn_alloc_rx_ring(sc, &sc->rxq)) != 0) {
556 device_printf(dev, "could not allocate RX ring, error %d\n",
557 error);
558 goto fail;
559 }
560
561 /* Clear pending interrupts. */
562 IWN_WRITE(sc, IWN_INT, 0xffffffff);
563
564 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211);
565 if (ifp == NULL) {
566 device_printf(dev, "can not allocate ifnet structure\n");
567 goto fail;
568 }
569
570 ic = ifp->if_l2com;
571 ic->ic_ifp = ifp;
572 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
573 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
574
575 /* Set device capabilities. */
576 ic->ic_caps =
577 IEEE80211_C_STA /* station mode supported */
578 | IEEE80211_C_MONITOR /* monitor mode supported */
579 | IEEE80211_C_BGSCAN /* background scanning */
580 | IEEE80211_C_TXPMGT /* tx power management */
581 | IEEE80211_C_SHSLOT /* short slot time supported */
582 | IEEE80211_C_WPA
583 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
584#if 0
585 | IEEE80211_C_IBSS /* ibss/adhoc mode */
586#endif
587 | IEEE80211_C_WME /* WME */
588 | IEEE80211_C_PMGT /* Station-side power mgmt */
589 ;
590
591 /* Read MAC address, channels, etc from EEPROM. */
592 if ((error = iwn_read_eeprom(sc, macaddr)) != 0) {
593 device_printf(dev, "could not read EEPROM, error %d\n",
594 error);
595 goto fail;
596 }
597
598 /* Count the number of available chains. */
599 sc->ntxchains =
600 ((sc->txchainmask >> 2) & 1) +
601 ((sc->txchainmask >> 1) & 1) +
602 ((sc->txchainmask >> 0) & 1);
603 sc->nrxchains =
604 ((sc->rxchainmask >> 2) & 1) +
605 ((sc->rxchainmask >> 1) & 1) +
606 ((sc->rxchainmask >> 0) & 1);
607 if (bootverbose) {
608 device_printf(dev, "MIMO %dT%dR, %.4s, address %6D\n",
609 sc->ntxchains, sc->nrxchains, sc->eeprom_domain,
610 macaddr, ":");
611 }
612
613 if (sc->sc_flags & IWN_FLAG_HAS_11N) {
614 ic->ic_rxstream = sc->nrxchains;
615 ic->ic_txstream = sc->ntxchains;
616 ic->ic_htcaps =
617 IEEE80211_HTCAP_SMPS_OFF /* SMPS mode disabled */
618 | IEEE80211_HTCAP_SHORTGI20 /* short GI in 20MHz */
619 | IEEE80211_HTCAP_CHWIDTH40 /* 40MHz channel width*/
620 | IEEE80211_HTCAP_SHORTGI40 /* short GI in 40MHz */
621#ifdef notyet
622 | IEEE80211_HTCAP_GREENFIELD
623#if IWN_RBUF_SIZE == 8192
624 | IEEE80211_HTCAP_MAXAMSDU_7935 /* max A-MSDU length */
625#else
626 | IEEE80211_HTCAP_MAXAMSDU_3839 /* max A-MSDU length */
627#endif
628#endif
629 /* s/w capabilities */
630 | IEEE80211_HTC_HT /* HT operation */
631 | IEEE80211_HTC_AMPDU /* tx A-MPDU */
632#ifdef notyet
633 | IEEE80211_HTC_AMSDU /* tx A-MSDU */
634#endif
635 ;
636 }
637
638 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
639 ifp->if_softc = sc;
640 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
641 ifp->if_init = iwn_init;
642 ifp->if_ioctl = iwn_ioctl;
643 ifp->if_start = iwn_start;
644 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
645 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
646 IFQ_SET_READY(&ifp->if_snd);
647
648 ieee80211_ifattach(ic, macaddr);
649 ic->ic_vap_create = iwn_vap_create;
650 ic->ic_vap_delete = iwn_vap_delete;
651 ic->ic_raw_xmit = iwn_raw_xmit;
652 ic->ic_node_alloc = iwn_node_alloc;
653 sc->sc_ampdu_rx_start = ic->ic_ampdu_rx_start;
654 ic->ic_ampdu_rx_start = iwn_ampdu_rx_start;
655 sc->sc_ampdu_rx_stop = ic->ic_ampdu_rx_stop;
656 ic->ic_ampdu_rx_stop = iwn_ampdu_rx_stop;
657 sc->sc_addba_request = ic->ic_addba_request;
658 ic->ic_addba_request = iwn_addba_request;
659 sc->sc_addba_response = ic->ic_addba_response;
660 ic->ic_addba_response = iwn_addba_response;
661 sc->sc_addba_stop = ic->ic_addba_stop;
662 ic->ic_addba_stop = iwn_ampdu_tx_stop;
663 ic->ic_newassoc = iwn_newassoc;
664 ic->ic_wme.wme_update = iwn_updateedca;
665 ic->ic_update_mcast = iwn_update_mcast;
666 ic->ic_scan_start = iwn_scan_start;
667 ic->ic_scan_end = iwn_scan_end;
668 ic->ic_set_channel = iwn_set_channel;
669 ic->ic_scan_curchan = iwn_scan_curchan;
670 ic->ic_scan_mindwell = iwn_scan_mindwell;
671 ic->ic_setregdomain = iwn_setregdomain;
672
673 iwn_radiotap_attach(sc);
674
675 callout_init_mtx(&sc->calib_to, &sc->sc_mtx, 0);
676 callout_init_mtx(&sc->watchdog_to, &sc->sc_mtx, 0);
677 TASK_INIT(&sc->sc_reinit_task, 0, iwn_hw_reset, sc);
678 TASK_INIT(&sc->sc_radioon_task, 0, iwn_radio_on, sc);
679 TASK_INIT(&sc->sc_radiooff_task, 0, iwn_radio_off, sc);
680
681 iwn_sysctlattach(sc);
682
683 /*
684 * Hook our interrupt after all initialization is complete.
685 */
686 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE,
687 NULL, iwn_intr, sc, &sc->sc_ih);
688 if (error != 0) {
689 device_printf(dev, "can't establish interrupt, error %d\n",
690 error);
691 goto fail;
692 }
693
694 if (bootverbose)
695 ieee80211_announce(ic);
696 return 0;
697fail:
698 iwn_detach(dev);
699 return error;
700}
701
702static int
703iwn4965_attach(struct iwn_softc *sc, uint16_t pid)
704{
705 struct iwn_ops *ops = &sc->ops;
706
707 ops->load_firmware = iwn4965_load_firmware;
708 ops->read_eeprom = iwn4965_read_eeprom;
709 ops->post_alive = iwn4965_post_alive;
710 ops->nic_config = iwn4965_nic_config;
711 ops->update_sched = iwn4965_update_sched;
712 ops->get_temperature = iwn4965_get_temperature;
713 ops->get_rssi = iwn4965_get_rssi;
714 ops->set_txpower = iwn4965_set_txpower;
715 ops->init_gains = iwn4965_init_gains;
716 ops->set_gains = iwn4965_set_gains;
717 ops->add_node = iwn4965_add_node;
718 ops->tx_done = iwn4965_tx_done;
719 ops->ampdu_tx_start = iwn4965_ampdu_tx_start;
720 ops->ampdu_tx_stop = iwn4965_ampdu_tx_stop;
721 sc->ntxqs = IWN4965_NTXQUEUES;
722 sc->firstaggqueue = IWN4965_FIRSTAGGQUEUE;
723 sc->ndmachnls = IWN4965_NDMACHNLS;
724 sc->broadcast_id = IWN4965_ID_BROADCAST;
725 sc->rxonsz = IWN4965_RXONSZ;
726 sc->schedsz = IWN4965_SCHEDSZ;
727 sc->fw_text_maxsz = IWN4965_FW_TEXT_MAXSZ;
728 sc->fw_data_maxsz = IWN4965_FW_DATA_MAXSZ;
729 sc->fwsz = IWN4965_FWSZ;
730 sc->sched_txfact_addr = IWN4965_SCHED_TXFACT;
731 sc->limits = &iwn4965_sensitivity_limits;
732 sc->fwname = "iwn4965fw";
733 /* Override chains masks, ROM is known to be broken. */
734 sc->txchainmask = IWN_ANT_AB;
735 sc->rxchainmask = IWN_ANT_ABC;
736
737 return 0;
738}
739
740static int
741iwn5000_attach(struct iwn_softc *sc, uint16_t pid)
742{
743 struct iwn_ops *ops = &sc->ops;
744
745 ops->load_firmware = iwn5000_load_firmware;
746 ops->read_eeprom = iwn5000_read_eeprom;
747 ops->post_alive = iwn5000_post_alive;
748 ops->nic_config = iwn5000_nic_config;
749 ops->update_sched = iwn5000_update_sched;
750 ops->get_temperature = iwn5000_get_temperature;
751 ops->get_rssi = iwn5000_get_rssi;
752 ops->set_txpower = iwn5000_set_txpower;
753 ops->init_gains = iwn5000_init_gains;
754 ops->set_gains = iwn5000_set_gains;
755 ops->add_node = iwn5000_add_node;
756 ops->tx_done = iwn5000_tx_done;
757 ops->ampdu_tx_start = iwn5000_ampdu_tx_start;
758 ops->ampdu_tx_stop = iwn5000_ampdu_tx_stop;
759 sc->ntxqs = IWN5000_NTXQUEUES;
760 sc->firstaggqueue = IWN5000_FIRSTAGGQUEUE;
761 sc->ndmachnls = IWN5000_NDMACHNLS;
762 sc->broadcast_id = IWN5000_ID_BROADCAST;
763 sc->rxonsz = IWN5000_RXONSZ;
764 sc->schedsz = IWN5000_SCHEDSZ;
765 sc->fw_text_maxsz = IWN5000_FW_TEXT_MAXSZ;
766 sc->fw_data_maxsz = IWN5000_FW_DATA_MAXSZ;
767 sc->fwsz = IWN5000_FWSZ;
768 sc->sched_txfact_addr = IWN5000_SCHED_TXFACT;
769 sc->reset_noise_gain = IWN5000_PHY_CALIB_RESET_NOISE_GAIN;
770 sc->noise_gain = IWN5000_PHY_CALIB_NOISE_GAIN;
771
772 switch (sc->hw_type) {
773 case IWN_HW_REV_TYPE_5100:
774 sc->limits = &iwn5000_sensitivity_limits;
775 sc->fwname = "iwn5000fw";
776 /* Override chains masks, ROM is known to be broken. */
777 sc->txchainmask = IWN_ANT_B;
778 sc->rxchainmask = IWN_ANT_AB;
779 break;
780 case IWN_HW_REV_TYPE_5150:
781 sc->limits = &iwn5150_sensitivity_limits;
782 sc->fwname = "iwn5150fw";
783 break;
784 case IWN_HW_REV_TYPE_5300:
785 case IWN_HW_REV_TYPE_5350:
786 sc->limits = &iwn5000_sensitivity_limits;
787 sc->fwname = "iwn5000fw";
788 break;
789 case IWN_HW_REV_TYPE_1000:
790 sc->limits = &iwn1000_sensitivity_limits;
791 sc->fwname = "iwn1000fw";
792 break;
793 case IWN_HW_REV_TYPE_6000:
794 sc->limits = &iwn6000_sensitivity_limits;
795 sc->fwname = "iwn6000fw";
796 if (pid == 0x422c || pid == 0x4239) {
797 sc->sc_flags |= IWN_FLAG_INTERNAL_PA;
798 /* Override chains masks, ROM is known to be broken. */
799 sc->txchainmask = IWN_ANT_BC;
800 sc->rxchainmask = IWN_ANT_BC;
801 }
802 break;
803 case IWN_HW_REV_TYPE_6050:
804 sc->limits = &iwn6000_sensitivity_limits;
805 sc->fwname = "iwn6050fw";
806 /* Override chains masks, ROM is known to be broken. */
807 sc->txchainmask = IWN_ANT_AB;
808 sc->rxchainmask = IWN_ANT_AB;
809 break;
810 case IWN_HW_REV_TYPE_6005:
811 sc->limits = &iwn6000_sensitivity_limits;
812 if (pid != 0x0082 && pid != 0x0085) {
813 sc->fwname = "iwn6000g2bfw";
814 sc->sc_flags |= IWN_FLAG_ADV_BTCOEX;
815 } else
816 sc->fwname = "iwn6000g2afw";
817 break;
818 default:
819 device_printf(sc->sc_dev, "adapter type %d not supported\n",
820 sc->hw_type);
821 return ENOTSUP;
822 }
823 return 0;
824}
825
826/*
827 * Attach the interface to 802.11 radiotap.
828 */
829static void
830iwn_radiotap_attach(struct iwn_softc *sc)
831{
832 struct ifnet *ifp = sc->sc_ifp;
833 struct ieee80211com *ic = ifp->if_l2com;
834
835 ieee80211_radiotap_attach(ic,
836 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap),
837 IWN_TX_RADIOTAP_PRESENT,
838 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap),
839 IWN_RX_RADIOTAP_PRESENT);
840}
841
842static void
843iwn_sysctlattach(struct iwn_softc *sc)
844{
845 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev);
846 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev);
847
848#ifdef IWN_DEBUG
849 sc->sc_debug = 0;
850 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
851 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "control debugging printfs");
852#endif
853}
854
855static struct ieee80211vap *
856iwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
857 enum ieee80211_opmode opmode, int flags,
858 const uint8_t bssid[IEEE80211_ADDR_LEN],
859 const uint8_t mac[IEEE80211_ADDR_LEN])
860{
861 struct iwn_vap *ivp;
862 struct ieee80211vap *vap;
863
864 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */
865 return NULL;
866 ivp = (struct iwn_vap *) malloc(sizeof(struct iwn_vap),
867 M_80211_VAP, M_NOWAIT | M_ZERO);
868 if (ivp == NULL)
869 return NULL;
870 vap = &ivp->iv_vap;
871 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid, mac);
872 vap->iv_bmissthreshold = 10; /* override default */
873 /* Override with driver methods. */
874 ivp->iv_newstate = vap->iv_newstate;
875 vap->iv_newstate = iwn_newstate;
876
877 ieee80211_ratectl_init(vap);
878 /* Complete setup. */
879 ieee80211_vap_attach(vap, iwn_media_change, ieee80211_media_status);
880 ic->ic_opmode = opmode;
881 return vap;
882}
883
884static void
885iwn_vap_delete(struct ieee80211vap *vap)
886{
887 struct iwn_vap *ivp = IWN_VAP(vap);
888
889 ieee80211_ratectl_deinit(vap);
890 ieee80211_vap_detach(vap);
891 free(ivp, M_80211_VAP);
892}
893
894static int
895iwn_detach(device_t dev)
896{
897 struct iwn_softc *sc = device_get_softc(dev);
898 struct ifnet *ifp = sc->sc_ifp;
899 struct ieee80211com *ic;
900 int qid;
901
902 if (ifp != NULL) {
903 ic = ifp->if_l2com;
904
905 ieee80211_draintask(ic, &sc->sc_reinit_task);
906 ieee80211_draintask(ic, &sc->sc_radioon_task);
907 ieee80211_draintask(ic, &sc->sc_radiooff_task);
908
909 iwn_stop(sc);
910 callout_drain(&sc->watchdog_to);
911 callout_drain(&sc->calib_to);
912 ieee80211_ifdetach(ic);
913 }
914
915 /* Uninstall interrupt handler. */
916 if (sc->irq != NULL) {
917 bus_teardown_intr(dev, sc->irq, sc->sc_ih);
918 bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq);
919 if (sc->irq_rid == 1)
920 pci_release_msi(dev);
921 }
922
923 /* Free DMA resources. */
924 iwn_free_rx_ring(sc, &sc->rxq);
925 for (qid = 0; qid < sc->ntxqs; qid++)
926 iwn_free_tx_ring(sc, &sc->txq[qid]);
927 iwn_free_sched(sc);
928 iwn_free_kw(sc);
929 if (sc->ict != NULL)
930 iwn_free_ict(sc);
931 iwn_free_fwmem(sc);
932
933 if (sc->mem != NULL)
934 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid, sc->mem);
935
936 if (ifp != NULL)
937 if_free(ifp);
938
939 IWN_LOCK_DESTROY(sc);
940 return 0;
941}
942
943static int
944iwn_shutdown(device_t dev)
945{
946 struct iwn_softc *sc = device_get_softc(dev);
947
948 iwn_stop(sc);
949 return 0;
950}
951
952static int
953iwn_suspend(device_t dev)
954{
955 struct iwn_softc *sc = device_get_softc(dev);
956 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
957
958 ieee80211_suspend_all(ic);
959 return 0;
960}
961
962static int
963iwn_resume(device_t dev)
964{
965 struct iwn_softc *sc = device_get_softc(dev);
966 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
967
968 /* Clear device-specific "PCI retry timeout" register (41h). */
969 pci_write_config(dev, 0x41, 0, 1);
970
971 ieee80211_resume_all(ic);
972 return 0;
973}
974
975static int
976iwn_nic_lock(struct iwn_softc *sc)
977{
978 int ntries;
979
980 /* Request exclusive access to NIC. */
981 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ);
982
983 /* Spin until we actually get the lock. */
984 for (ntries = 0; ntries < 1000; ntries++) {
985 if ((IWN_READ(sc, IWN_GP_CNTRL) &
986 (IWN_GP_CNTRL_MAC_ACCESS_ENA | IWN_GP_CNTRL_SLEEP)) ==
987 IWN_GP_CNTRL_MAC_ACCESS_ENA)
988 return 0;
989 DELAY(10);
990 }
991 return ETIMEDOUT;
992}
993
994static __inline void
995iwn_nic_unlock(struct iwn_softc *sc)
996{
997 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_MAC_ACCESS_REQ);
998}
999
1000static __inline uint32_t
1001iwn_prph_read(struct iwn_softc *sc, uint32_t addr)
1002{
1003 IWN_WRITE(sc, IWN_PRPH_RADDR, IWN_PRPH_DWORD | addr);
1004 IWN_BARRIER_READ_WRITE(sc);
1005 return IWN_READ(sc, IWN_PRPH_RDATA);
1006}
1007
1008static __inline void
1009iwn_prph_write(struct iwn_softc *sc, uint32_t addr, uint32_t data)
1010{
1011 IWN_WRITE(sc, IWN_PRPH_WADDR, IWN_PRPH_DWORD | addr);
1012 IWN_BARRIER_WRITE(sc);
1013 IWN_WRITE(sc, IWN_PRPH_WDATA, data);
1014}
1015
1016static __inline void
1017iwn_prph_setbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask)
1018{
1019 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) | mask);
1020}
1021
1022static __inline void
1023iwn_prph_clrbits(struct iwn_softc *sc, uint32_t addr, uint32_t mask)
1024{
1025 iwn_prph_write(sc, addr, iwn_prph_read(sc, addr) & ~mask);
1026}
1027
1028static __inline void
1029iwn_prph_write_region_4(struct iwn_softc *sc, uint32_t addr,
1030 const uint32_t *data, int count)
1031{
1032 for (; count > 0; count--, data++, addr += 4)
1033 iwn_prph_write(sc, addr, *data);
1034}
1035
1036static __inline uint32_t
1037iwn_mem_read(struct iwn_softc *sc, uint32_t addr)
1038{
1039 IWN_WRITE(sc, IWN_MEM_RADDR, addr);
1040 IWN_BARRIER_READ_WRITE(sc);
1041 return IWN_READ(sc, IWN_MEM_RDATA);
1042}
1043
1044static __inline void
1045iwn_mem_write(struct iwn_softc *sc, uint32_t addr, uint32_t data)
1046{
1047 IWN_WRITE(sc, IWN_MEM_WADDR, addr);
1048 IWN_BARRIER_WRITE(sc);
1049 IWN_WRITE(sc, IWN_MEM_WDATA, data);
1050}
1051
1052static __inline void
1053iwn_mem_write_2(struct iwn_softc *sc, uint32_t addr, uint16_t data)
1054{
1055 uint32_t tmp;
1056
1057 tmp = iwn_mem_read(sc, addr & ~3);
1058 if (addr & 3)
1059 tmp = (tmp & 0x0000ffff) | data << 16;
1060 else
1061 tmp = (tmp & 0xffff0000) | data;
1062 iwn_mem_write(sc, addr & ~3, tmp);
1063}
1064
1065static __inline void
1066iwn_mem_read_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t *data,
1067 int count)
1068{
1069 for (; count > 0; count--, addr += 4)
1070 *data++ = iwn_mem_read(sc, addr);
1071}
1072
1073static __inline void
1074iwn_mem_set_region_4(struct iwn_softc *sc, uint32_t addr, uint32_t val,
1075 int count)
1076{
1077 for (; count > 0; count--, addr += 4)
1078 iwn_mem_write(sc, addr, val);
1079}
1080
1081static int
1082iwn_eeprom_lock(struct iwn_softc *sc)
1083{
1084 int i, ntries;
1085
1086 for (i = 0; i < 100; i++) {
1087 /* Request exclusive access to EEPROM. */
1088 IWN_SETBITS(sc, IWN_HW_IF_CONFIG,
1089 IWN_HW_IF_CONFIG_EEPROM_LOCKED);
1090
1091 /* Spin until we actually get the lock. */
1092 for (ntries = 0; ntries < 100; ntries++) {
1093 if (IWN_READ(sc, IWN_HW_IF_CONFIG) &
1094 IWN_HW_IF_CONFIG_EEPROM_LOCKED)
1095 return 0;
1096 DELAY(10);
1097 }
1098 }
1099 return ETIMEDOUT;
1100}
1101
1102static __inline void
1103iwn_eeprom_unlock(struct iwn_softc *sc)
1104{
1105 IWN_CLRBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_EEPROM_LOCKED);
1106}
1107
1108/*
1109 * Initialize access by host to One Time Programmable ROM.
1110 * NB: This kind of ROM can be found on 1000 or 6000 Series only.
1111 */
1112static int
1113iwn_init_otprom(struct iwn_softc *sc)
1114{
1115 uint16_t prev, base, next;
1116 int count, error;
1117
1118 /* Wait for clock stabilization before accessing prph. */
1119 if ((error = iwn_clock_wait(sc)) != 0)
1120 return error;
1121
1122 if ((error = iwn_nic_lock(sc)) != 0)
1123 return error;
1124 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ);
1125 DELAY(5);
1126 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_RESET_REQ);
1127 iwn_nic_unlock(sc);
1128
1129 /* Set auto clock gate disable bit for HW with OTP shadow RAM. */
1130 if (sc->hw_type != IWN_HW_REV_TYPE_1000) {
1131 IWN_SETBITS(sc, IWN_DBG_LINK_PWR_MGMT,
1132 IWN_RESET_LINK_PWR_MGMT_DIS);
1133 }
1134 IWN_CLRBITS(sc, IWN_EEPROM_GP, IWN_EEPROM_GP_IF_OWNER);
1135 /* Clear ECC status. */
1136 IWN_SETBITS(sc, IWN_OTP_GP,
1137 IWN_OTP_GP_ECC_CORR_STTS | IWN_OTP_GP_ECC_UNCORR_STTS);
1138
1139 /*
1140 * Find the block before last block (contains the EEPROM image)
1141 * for HW without OTP shadow RAM.
1142 */
1143 if (sc->hw_type == IWN_HW_REV_TYPE_1000) {
1144 /* Switch to absolute addressing mode. */
1145 IWN_CLRBITS(sc, IWN_OTP_GP, IWN_OTP_GP_RELATIVE_ACCESS);
1146 base = prev = 0;
1147 for (count = 0; count < IWN1000_OTP_NBLOCKS; count++) {
1148 error = iwn_read_prom_data(sc, base, &next, 2);
1149 if (error != 0)
1150 return error;
1151 if (next == 0) /* End of linked-list. */
1152 break;
1153 prev = base;
1154 base = le16toh(next);
1155 }
1156 if (count == 0 || count == IWN1000_OTP_NBLOCKS)
1157 return EIO;
1158 /* Skip "next" word. */
1159 sc->prom_base = prev + 1;
1160 }
1161 return 0;
1162}
1163
1164static int
1165iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int count)
1166{
1167 uint8_t *out = data;
1168 uint32_t val, tmp;
1169 int ntries;
1170
1171 addr += sc->prom_base;
1172 for (; count > 0; count -= 2, addr++) {
1173 IWN_WRITE(sc, IWN_EEPROM, addr << 2);
1174 for (ntries = 0; ntries < 10; ntries++) {
1175 val = IWN_READ(sc, IWN_EEPROM);
1176 if (val & IWN_EEPROM_READ_VALID)
1177 break;
1178 DELAY(5);
1179 }
1180 if (ntries == 10) {
1181 device_printf(sc->sc_dev,
1182 "timeout reading ROM at 0x%x\n", addr);
1183 return ETIMEDOUT;
1184 }
1185 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) {
1186 /* OTPROM, check for ECC errors. */
1187 tmp = IWN_READ(sc, IWN_OTP_GP);
1188 if (tmp & IWN_OTP_GP_ECC_UNCORR_STTS) {
1189 device_printf(sc->sc_dev,
1190 "OTPROM ECC error at 0x%x\n", addr);
1191 return EIO;
1192 }
1193 if (tmp & IWN_OTP_GP_ECC_CORR_STTS) {
1194 /* Correctable ECC error, clear bit. */
1195 IWN_SETBITS(sc, IWN_OTP_GP,
1196 IWN_OTP_GP_ECC_CORR_STTS);
1197 }
1198 }
1199 *out++ = val >> 16;
1200 if (count > 1)
1201 *out++ = val >> 24;
1202 }
1203 return 0;
1204}
1205
1206static void
1207iwn_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1208{
1209 if (error != 0)
1210 return;
1211 KASSERT(nsegs == 1, ("too many DMA segments, %d should be 1", nsegs));
1212 *(bus_addr_t *)arg = segs[0].ds_addr;
1213}
1214
1215static int
1216iwn_dma_contig_alloc(struct iwn_softc *sc, struct iwn_dma_info *dma,
1217 void **kvap, bus_size_t size, bus_size_t alignment)
1218{
1219 int error;
1220
1221 dma->tag = NULL;
1222 dma->size = size;
1223
1224 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), alignment,
1225 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, size,
1226 1, size, BUS_DMA_NOWAIT, NULL, NULL, &dma->tag);
1227 if (error != 0)
1228 goto fail;
1229
1230 error = bus_dmamem_alloc(dma->tag, (void **)&dma->vaddr,
1231 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &dma->map);
1232 if (error != 0)
1233 goto fail;
1234
1235 error = bus_dmamap_load(dma->tag, dma->map, dma->vaddr, size,
1236 iwn_dma_map_addr, &dma->paddr, BUS_DMA_NOWAIT);
1237 if (error != 0)
1238 goto fail;
1239
1240 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE);
1241
1242 if (kvap != NULL)
1243 *kvap = dma->vaddr;
1244
1245 return 0;
1246
1247fail: iwn_dma_contig_free(dma);
1248 return error;
1249}
1250
1251static void
1252iwn_dma_contig_free(struct iwn_dma_info *dma)
1253{
1254 if (dma->map != NULL) {
1255 if (dma->vaddr != NULL) {
1256 bus_dmamap_sync(dma->tag, dma->map,
1257 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1258 bus_dmamap_unload(dma->tag, dma->map);
1259 bus_dmamem_free(dma->tag, dma->vaddr, dma->map);
1260 dma->vaddr = NULL;
1261 }
1262 bus_dmamap_destroy(dma->tag, dma->map);
1263 dma->map = NULL;
1264 }
1265 if (dma->tag != NULL) {
1266 bus_dma_tag_destroy(dma->tag);
1267 dma->tag = NULL;
1268 }
1269}
1270
1271static int
1272iwn_alloc_sched(struct iwn_softc *sc)
1273{
1274 /* TX scheduler rings must be aligned on a 1KB boundary. */
1275 return iwn_dma_contig_alloc(sc, &sc->sched_dma, (void **)&sc->sched,
1276 sc->schedsz, 1024);
1277}
1278
1279static void
1280iwn_free_sched(struct iwn_softc *sc)
1281{
1282 iwn_dma_contig_free(&sc->sched_dma);
1283}
1284
1285static int
1286iwn_alloc_kw(struct iwn_softc *sc)
1287{
1288 /* "Keep Warm" page must be aligned on a 4KB boundary. */
1289 return iwn_dma_contig_alloc(sc, &sc->kw_dma, NULL, 4096, 4096);
1290}
1291
1292static void
1293iwn_free_kw(struct iwn_softc *sc)
1294{
1295 iwn_dma_contig_free(&sc->kw_dma);
1296}
1297
1298static int
1299iwn_alloc_ict(struct iwn_softc *sc)
1300{
1301 /* ICT table must be aligned on a 4KB boundary. */
1302 return iwn_dma_contig_alloc(sc, &sc->ict_dma, (void **)&sc->ict,
1303 IWN_ICT_SIZE, 4096);
1304}
1305
1306static void
1307iwn_free_ict(struct iwn_softc *sc)
1308{
1309 iwn_dma_contig_free(&sc->ict_dma);
1310}
1311
1312static int
1313iwn_alloc_fwmem(struct iwn_softc *sc)
1314{
1315 /* Must be aligned on a 16-byte boundary. */
1316 return iwn_dma_contig_alloc(sc, &sc->fw_dma, NULL, sc->fwsz, 16);
1317}
1318
1319static void
1320iwn_free_fwmem(struct iwn_softc *sc)
1321{
1322 iwn_dma_contig_free(&sc->fw_dma);
1323}
1324
1325static int
1326iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring)
1327{
1328 bus_size_t size;
1329 int i, error;
1330
1331 ring->cur = 0;
1332
1333 /* Allocate RX descriptors (256-byte aligned). */
1334 size = IWN_RX_RING_COUNT * sizeof (uint32_t);
1335 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, (void **)&ring->desc,
1336 size, 256);
1337 if (error != 0) {
1338 device_printf(sc->sc_dev,
1339 "%s: could not allocate RX ring DMA memory, error %d\n",
1340 __func__, error);
1341 goto fail;
1342 }
1343
1344 /* Allocate RX status area (16-byte aligned). */
1345 error = iwn_dma_contig_alloc(sc, &ring->stat_dma, (void **)&ring->stat,
1346 sizeof (struct iwn_rx_status), 16);
1347 if (error != 0) {
1348 device_printf(sc->sc_dev,
1349 "%s: could not allocate RX status DMA memory, error %d\n",
1350 __func__, error);
1351 goto fail;
1352 }
1353
1354 /* Create RX buffer DMA tag. */
1355 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
1356 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1357 IWN_RBUF_SIZE, 1, IWN_RBUF_SIZE, BUS_DMA_NOWAIT, NULL, NULL,
1358 &ring->data_dmat);
1359 if (error != 0) {
1360 device_printf(sc->sc_dev,
1361 "%s: could not create RX buf DMA tag, error %d\n",
1362 __func__, error);
1363 goto fail;
1364 }
1365
1366 /*
1367 * Allocate and map RX buffers.
1368 */
1369 for (i = 0; i < IWN_RX_RING_COUNT; i++) {
1370 struct iwn_rx_data *data = &ring->data[i];
1371 bus_addr_t paddr;
1372
1373 error = bus_dmamap_create(ring->data_dmat, 0, &data->map);
1374 if (error != 0) {
1375 device_printf(sc->sc_dev,
1376 "%s: could not create RX buf DMA map, error %d\n",
1377 __func__, error);
1378 goto fail;
1379 }
1380
1381 data->m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR,
1382 IWN_RBUF_SIZE);
1383 if (data->m == NULL) {
1384 device_printf(sc->sc_dev,
1385 "%s: could not allocate RX mbuf\n", __func__);
1386 error = ENOBUFS;
1387 goto fail;
1388 }
1389
1390 error = bus_dmamap_load(ring->data_dmat, data->map,
1391 mtod(data->m, void *), IWN_RBUF_SIZE, iwn_dma_map_addr,
1392 &paddr, BUS_DMA_NOWAIT);
1393 if (error != 0 && error != EFBIG) {
1394 device_printf(sc->sc_dev,
1395 "%s: can't not map mbuf, error %d\n", __func__,
1396 error);
1397 goto fail;
1398 }
1399
1400 /* Set physical address of RX buffer (256-byte aligned). */
1401 ring->desc[i] = htole32(paddr >> 8);
1402 }
1403
1404 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
1405 BUS_DMASYNC_PREWRITE);
1406
1407 return 0;
1408
1409fail: iwn_free_rx_ring(sc, ring);
1410 return error;
1411}
1412
1413static void
1414iwn_reset_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring)
1415{
1416 int ntries;
1417
1418 if (iwn_nic_lock(sc) == 0) {
1419 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0);
1420 for (ntries = 0; ntries < 1000; ntries++) {
1421 if (IWN_READ(sc, IWN_FH_RX_STATUS) &
1422 IWN_FH_RX_STATUS_IDLE)
1423 break;
1424 DELAY(10);
1425 }
1426 iwn_nic_unlock(sc);
1427 }
1428 ring->cur = 0;
1429 sc->last_rx_valid = 0;
1430}
1431
1432static void
1433iwn_free_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring)
1434{
1435 int i;
1436
1437 iwn_dma_contig_free(&ring->desc_dma);
1438 iwn_dma_contig_free(&ring->stat_dma);
1439
1440 for (i = 0; i < IWN_RX_RING_COUNT; i++) {
1441 struct iwn_rx_data *data = &ring->data[i];
1442
1443 if (data->m != NULL) {
1444 bus_dmamap_sync(ring->data_dmat, data->map,
1445 BUS_DMASYNC_POSTREAD);
1446 bus_dmamap_unload(ring->data_dmat, data->map);
1447 m_freem(data->m);
1448 data->m = NULL;
1449 }
1450 if (data->map != NULL)
1451 bus_dmamap_destroy(ring->data_dmat, data->map);
1452 }
1453 if (ring->data_dmat != NULL) {
1454 bus_dma_tag_destroy(ring->data_dmat);
1455 ring->data_dmat = NULL;
1456 }
1457}
1458
1459static int
1460iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid)
1461{
1462 bus_addr_t paddr;
1463 bus_size_t size;
1464 int i, error;
1465
1466 ring->qid = qid;
1467 ring->queued = 0;
1468 ring->cur = 0;
1469
1470 /* Allocate TX descriptors (256-byte aligned). */
1471 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_desc);
1472 error = iwn_dma_contig_alloc(sc, &ring->desc_dma, (void **)&ring->desc,
1473 size, 256);
1474 if (error != 0) {
1475 device_printf(sc->sc_dev,
1476 "%s: could not allocate TX ring DMA memory, error %d\n",
1477 __func__, error);
1478 goto fail;
1479 }
1480
1481 size = IWN_TX_RING_COUNT * sizeof (struct iwn_tx_cmd);
1482 error = iwn_dma_contig_alloc(sc, &ring->cmd_dma, (void **)&ring->cmd,
1483 size, 4);
1484 if (error != 0) {
1485 device_printf(sc->sc_dev,
1486 "%s: could not allocate TX cmd DMA memory, error %d\n",
1487 __func__, error);
1488 goto fail;
1489 }
1490
1491 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
1492 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
1493 IWN_MAX_SCATTER - 1, MCLBYTES, BUS_DMA_NOWAIT, NULL, NULL,
1494 &ring->data_dmat);
1495 if (error != 0) {
1496 device_printf(sc->sc_dev,
1497 "%s: could not create TX buf DMA tag, error %d\n",
1498 __func__, error);
1499 goto fail;
1500 }
1501
1502 paddr = ring->cmd_dma.paddr;
1503 for (i = 0; i < IWN_TX_RING_COUNT; i++) {
1504 struct iwn_tx_data *data = &ring->data[i];
1505
1506 data->cmd_paddr = paddr;
1507 data->scratch_paddr = paddr + 12;
1508 paddr += sizeof (struct iwn_tx_cmd);
1509
1510 error = bus_dmamap_create(ring->data_dmat, 0, &data->map);
1511 if (error != 0) {
1512 device_printf(sc->sc_dev,
1513 "%s: could not create TX buf DMA map, error %d\n",
1514 __func__, error);
1515 goto fail;
1516 }
1517 }
1518 return 0;
1519
1520fail: iwn_free_tx_ring(sc, ring);
1521 return error;
1522}
1523
1524static void
1525iwn_reset_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring)
1526{
1527 int i;
1528
1529 for (i = 0; i < IWN_TX_RING_COUNT; i++) {
1530 struct iwn_tx_data *data = &ring->data[i];
1531
1532 if (data->m != NULL) {
1533 bus_dmamap_sync(ring->data_dmat, data->map,
1534 BUS_DMASYNC_POSTWRITE);
1535 bus_dmamap_unload(ring->data_dmat, data->map);
1536 m_freem(data->m);
1537 data->m = NULL;
1538 }
1539 }
1540 /* Clear TX descriptors. */
1541 memset(ring->desc, 0, ring->desc_dma.size);
1542 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
1543 BUS_DMASYNC_PREWRITE);
1544 sc->qfullmsk &= ~(1 << ring->qid);
1545 ring->queued = 0;
1546 ring->cur = 0;
1547}
1548
1549static void
1550iwn_free_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring)
1551{
1552 int i;
1553
1554 iwn_dma_contig_free(&ring->desc_dma);
1555 iwn_dma_contig_free(&ring->cmd_dma);
1556
1557 for (i = 0; i < IWN_TX_RING_COUNT; i++) {
1558 struct iwn_tx_data *data = &ring->data[i];
1559
1560 if (data->m != NULL) {
1561 bus_dmamap_sync(ring->data_dmat, data->map,
1562 BUS_DMASYNC_POSTWRITE);
1563 bus_dmamap_unload(ring->data_dmat, data->map);
1564 m_freem(data->m);
1565 }
1566 if (data->map != NULL)
1567 bus_dmamap_destroy(ring->data_dmat, data->map);
1568 }
1569 if (ring->data_dmat != NULL) {
1570 bus_dma_tag_destroy(ring->data_dmat);
1571 ring->data_dmat = NULL;
1572 }
1573}
1574
1575static void
1576iwn5000_ict_reset(struct iwn_softc *sc)
1577{
1578 /* Disable interrupts. */
1579 IWN_WRITE(sc, IWN_INT_MASK, 0);
1580
1581 /* Reset ICT table. */
1582 memset(sc->ict, 0, IWN_ICT_SIZE);
1583 sc->ict_cur = 0;
1584
1585 /* Set physical address of ICT table (4KB aligned). */
1586 DPRINTF(sc, IWN_DEBUG_RESET, "%s: enabling ICT\n", __func__);
1587 IWN_WRITE(sc, IWN_DRAM_INT_TBL, IWN_DRAM_INT_TBL_ENABLE |
1588 IWN_DRAM_INT_TBL_WRAP_CHECK | sc->ict_dma.paddr >> 12);
1589
1590 /* Enable periodic RX interrupt. */
1591 sc->int_mask |= IWN_INT_RX_PERIODIC;
1592 /* Switch to ICT interrupt mode in driver. */
1593 sc->sc_flags |= IWN_FLAG_USE_ICT;
1594
1595 /* Re-enable interrupts. */
1596 IWN_WRITE(sc, IWN_INT, 0xffffffff);
1597 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
1598}
1599
1600static int
1601iwn_read_eeprom(struct iwn_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN])
1602{
1603 struct iwn_ops *ops = &sc->ops;
1604 uint16_t val;
1605 int error;
1606
1607 /* Check whether adapter has an EEPROM or an OTPROM. */
1608 if (sc->hw_type >= IWN_HW_REV_TYPE_1000 &&
1609 (IWN_READ(sc, IWN_OTP_GP) & IWN_OTP_GP_DEV_SEL_OTP))
1610 sc->sc_flags |= IWN_FLAG_HAS_OTPROM;
1611 DPRINTF(sc, IWN_DEBUG_RESET, "%s found\n",
1612 (sc->sc_flags & IWN_FLAG_HAS_OTPROM) ? "OTPROM" : "EEPROM");
1613
1614 /* Adapter has to be powered on for EEPROM access to work. */
1615 if ((error = iwn_apm_init(sc)) != 0) {
1616 device_printf(sc->sc_dev,
1617 "%s: could not power ON adapter, error %d\n", __func__,
1618 error);
1619 return error;
1620 }
1621
1622 if ((IWN_READ(sc, IWN_EEPROM_GP) & 0x7) == 0) {
1623 device_printf(sc->sc_dev, "%s: bad ROM signature\n", __func__);
1624 return EIO;
1625 }
1626 if ((error = iwn_eeprom_lock(sc)) != 0) {
1627 device_printf(sc->sc_dev, "%s: could not lock ROM, error %d\n",
1628 __func__, error);
1629 return error;
1630 }
1631 if (sc->sc_flags & IWN_FLAG_HAS_OTPROM) {
1632 if ((error = iwn_init_otprom(sc)) != 0) {
1633 device_printf(sc->sc_dev,
1634 "%s: could not initialize OTPROM, error %d\n",
1635 __func__, error);
1636 return error;
1637 }
1638 }
1639
1640 iwn_read_prom_data(sc, IWN_EEPROM_SKU_CAP, &val, 2);
1641 DPRINTF(sc, IWN_DEBUG_RESET, "SKU capabilities=0x%04x\n", le16toh(val));
1642 /* Check if HT support is bonded out. */
1643 if (val & htole16(IWN_EEPROM_SKU_CAP_11N))
1644 sc->sc_flags |= IWN_FLAG_HAS_11N;
1645
1646 iwn_read_prom_data(sc, IWN_EEPROM_RFCFG, &val, 2);
1647 sc->rfcfg = le16toh(val);
1648 DPRINTF(sc, IWN_DEBUG_RESET, "radio config=0x%04x\n", sc->rfcfg);
1649 /* Read Tx/Rx chains from ROM unless it's known to be broken. */
1650 if (sc->txchainmask == 0)
1651 sc->txchainmask = IWN_RFCFG_TXANTMSK(sc->rfcfg);
1652 if (sc->rxchainmask == 0)
1653 sc->rxchainmask = IWN_RFCFG_RXANTMSK(sc->rfcfg);
1654
1655 /* Read MAC address. */
1656 iwn_read_prom_data(sc, IWN_EEPROM_MAC, macaddr, 6);
1657
1658 /* Read adapter-specific information from EEPROM. */
1659 ops->read_eeprom(sc);
1660
1661 iwn_apm_stop(sc); /* Power OFF adapter. */
1662
1663 iwn_eeprom_unlock(sc);
1664 return 0;
1665}
1666
1667static void
1668iwn4965_read_eeprom(struct iwn_softc *sc)
1669{
1670 uint32_t addr;
1671 uint16_t val;
1672 int i;
1673
1674 /* Read regulatory domain (4 ASCII characters). */
1675 iwn_read_prom_data(sc, IWN4965_EEPROM_DOMAIN, sc->eeprom_domain, 4);
1676
1677 /* Read the list of authorized channels (20MHz ones only). */
1678 for (i = 0; i < 7; i++) {
1679 addr = iwn4965_regulatory_bands[i];
1680 iwn_read_eeprom_channels(sc, i, addr);
1681 }
1682
1683 /* Read maximum allowed TX power for 2GHz and 5GHz bands. */
1684 iwn_read_prom_data(sc, IWN4965_EEPROM_MAXPOW, &val, 2);
1685 sc->maxpwr2GHz = val & 0xff;
1686 sc->maxpwr5GHz = val >> 8;
1687 /* Check that EEPROM values are within valid range. */
1688 if (sc->maxpwr5GHz < 20 || sc->maxpwr5GHz > 50)
1689 sc->maxpwr5GHz = 38;
1690 if (sc->maxpwr2GHz < 20 || sc->maxpwr2GHz > 50)
1691 sc->maxpwr2GHz = 38;
1692 DPRINTF(sc, IWN_DEBUG_RESET, "maxpwr 2GHz=%d 5GHz=%d\n",
1693 sc->maxpwr2GHz, sc->maxpwr5GHz);
1694
1695 /* Read samples for each TX power group. */
1696 iwn_read_prom_data(sc, IWN4965_EEPROM_BANDS, sc->bands,
1697 sizeof sc->bands);
1698
1699 /* Read voltage at which samples were taken. */
1700 iwn_read_prom_data(sc, IWN4965_EEPROM_VOLTAGE, &val, 2);
1701 sc->eeprom_voltage = (int16_t)le16toh(val);
1702 DPRINTF(sc, IWN_DEBUG_RESET, "voltage=%d (in 0.3V)\n",
1703 sc->eeprom_voltage);
1704
1705#ifdef IWN_DEBUG
1706 /* Print samples. */
1707 if (sc->sc_debug & IWN_DEBUG_ANY) {
1708 for (i = 0; i < IWN_NBANDS; i++)
1709 iwn4965_print_power_group(sc, i);
1710 }
1711#endif
1712}
1713
1714#ifdef IWN_DEBUG
1715static void
1716iwn4965_print_power_group(struct iwn_softc *sc, int i)
1717{
1718 struct iwn4965_eeprom_band *band = &sc->bands[i];
1719 struct iwn4965_eeprom_chan_samples *chans = band->chans;
1720 int j, c;
1721
1722 printf("===band %d===\n", i);
1723 printf("chan lo=%d, chan hi=%d\n", band->lo, band->hi);
1724 printf("chan1 num=%d\n", chans[0].num);
1725 for (c = 0; c < 2; c++) {
1726 for (j = 0; j < IWN_NSAMPLES; j++) {
1727 printf("chain %d, sample %d: temp=%d gain=%d "
1728 "power=%d pa_det=%d\n", c, j,
1729 chans[0].samples[c][j].temp,
1730 chans[0].samples[c][j].gain,
1731 chans[0].samples[c][j].power,
1732 chans[0].samples[c][j].pa_det);
1733 }
1734 }
1735 printf("chan2 num=%d\n", chans[1].num);
1736 for (c = 0; c < 2; c++) {
1737 for (j = 0; j < IWN_NSAMPLES; j++) {
1738 printf("chain %d, sample %d: temp=%d gain=%d "
1739 "power=%d pa_det=%d\n", c, j,
1740 chans[1].samples[c][j].temp,
1741 chans[1].samples[c][j].gain,
1742 chans[1].samples[c][j].power,
1743 chans[1].samples[c][j].pa_det);
1744 }
1745 }
1746}
1747#endif
1748
1749static void
1750iwn5000_read_eeprom(struct iwn_softc *sc)
1751{
1752 struct iwn5000_eeprom_calib_hdr hdr;
1753 int32_t volt;
1754 uint32_t base, addr;
1755 uint16_t val;
1756 int i;
1757
1758 /* Read regulatory domain (4 ASCII characters). */
1759 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2);
1760 base = le16toh(val);
1761 iwn_read_prom_data(sc, base + IWN5000_EEPROM_DOMAIN,
1762 sc->eeprom_domain, 4);
1763
1764 /* Read the list of authorized channels (20MHz ones only). */
1765 for (i = 0; i < 7; i++) {
1766 if (sc->hw_type >= IWN_HW_REV_TYPE_6000)
1767 addr = base + iwn6000_regulatory_bands[i];
1768 else
1769 addr = base + iwn5000_regulatory_bands[i];
1770 iwn_read_eeprom_channels(sc, i, addr);
1771 }
1772
1773 /* Read enhanced TX power information for 6000 Series. */
1774 if (sc->hw_type >= IWN_HW_REV_TYPE_6000)
1775 iwn_read_eeprom_enhinfo(sc);
1776
1777 iwn_read_prom_data(sc, IWN5000_EEPROM_CAL, &val, 2);
1778 base = le16toh(val);
1779 iwn_read_prom_data(sc, base, &hdr, sizeof hdr);
1780 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
1781 "%s: calib version=%u pa type=%u voltage=%u\n", __func__,
1782 hdr.version, hdr.pa_type, le16toh(hdr.volt));
1783 sc->calib_ver = hdr.version;
1784
1785 if (sc->hw_type == IWN_HW_REV_TYPE_5150) {
1786 /* Compute temperature offset. */
1787 iwn_read_prom_data(sc, base + IWN5000_EEPROM_TEMP, &val, 2);
1788 sc->eeprom_temp = le16toh(val);
1789 iwn_read_prom_data(sc, base + IWN5000_EEPROM_VOLT, &val, 2);
1790 volt = le16toh(val);
1791 sc->temp_off = sc->eeprom_temp - (volt / -5);
1792 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "temp=%d volt=%d offset=%dK\n",
1793 sc->eeprom_temp, volt, sc->temp_off);
1794 } else {
1795 /* Read crystal calibration. */
1796 iwn_read_prom_data(sc, base + IWN5000_EEPROM_CRYSTAL,
1797 &sc->eeprom_crystal, sizeof (uint32_t));
1798 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "crystal calibration 0x%08x\n",
1799 le32toh(sc->eeprom_crystal));
1800 }
1801}
1802
1803/*
1804 * Translate EEPROM flags to net80211.
1805 */
1806static uint32_t
1807iwn_eeprom_channel_flags(struct iwn_eeprom_chan *channel)
1808{
1809 uint32_t nflags;
1810
1811 nflags = 0;
1812 if ((channel->flags & IWN_EEPROM_CHAN_ACTIVE) == 0)
1813 nflags |= IEEE80211_CHAN_PASSIVE;
1814 if ((channel->flags & IWN_EEPROM_CHAN_IBSS) == 0)
1815 nflags |= IEEE80211_CHAN_NOADHOC;
1816 if (channel->flags & IWN_EEPROM_CHAN_RADAR) {
1817 nflags |= IEEE80211_CHAN_DFS;
1818 /* XXX apparently IBSS may still be marked */
1819 nflags |= IEEE80211_CHAN_NOADHOC;
1820 }
1821
1822 return nflags;
1823}
1824
1825static void
1826iwn_read_eeprom_band(struct iwn_softc *sc, int n)
1827{
1828 struct ifnet *ifp = sc->sc_ifp;
1829 struct ieee80211com *ic = ifp->if_l2com;
1830 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n];
1831 const struct iwn_chan_band *band = &iwn_bands[n];
1832 struct ieee80211_channel *c;
1833 uint8_t chan;
1834 int i, nflags;
1835
1836 for (i = 0; i < band->nchan; i++) {
1837 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) {
1838 DPRINTF(sc, IWN_DEBUG_RESET,
1839 "skip chan %d flags 0x%x maxpwr %d\n",
1840 band->chan[i], channels[i].flags,
1841 channels[i].maxpwr);
1842 continue;
1843 }
1844 chan = band->chan[i];
1845 nflags = iwn_eeprom_channel_flags(&channels[i]);
1846
1847 c = &ic->ic_channels[ic->ic_nchans++];
1848 c->ic_ieee = chan;
1849 c->ic_maxregpower = channels[i].maxpwr;
1850 c->ic_maxpower = 2*c->ic_maxregpower;
1851
1852 if (n == 0) { /* 2GHz band */
1853 c->ic_freq = ieee80211_ieee2mhz(chan, IEEE80211_CHAN_G);
1854 /* G =>'s B is supported */
1855 c->ic_flags = IEEE80211_CHAN_B | nflags;
1856 c = &ic->ic_channels[ic->ic_nchans++];
1857 c[0] = c[-1];
1858 c->ic_flags = IEEE80211_CHAN_G | nflags;
1859 } else { /* 5GHz band */
1860 c->ic_freq = ieee80211_ieee2mhz(chan, IEEE80211_CHAN_A);
1861 c->ic_flags = IEEE80211_CHAN_A | nflags;
1862 }
1863
1864 /* Save maximum allowed TX power for this channel. */
1865 sc->maxpwr[chan] = channels[i].maxpwr;
1866
1867 DPRINTF(sc, IWN_DEBUG_RESET,
1868 "add chan %d flags 0x%x maxpwr %d\n", chan,
1869 channels[i].flags, channels[i].maxpwr);
1870
1871 if (sc->sc_flags & IWN_FLAG_HAS_11N) {
1872 /* add HT20, HT40 added separately */
1873 c = &ic->ic_channels[ic->ic_nchans++];
1874 c[0] = c[-1];
1875 c->ic_flags |= IEEE80211_CHAN_HT20;
1876 }
1877 }
1878}
1879
1880static void
1881iwn_read_eeprom_ht40(struct iwn_softc *sc, int n)
1882{
1883 struct ifnet *ifp = sc->sc_ifp;
1884 struct ieee80211com *ic = ifp->if_l2com;
1885 struct iwn_eeprom_chan *channels = sc->eeprom_channels[n];
1886 const struct iwn_chan_band *band = &iwn_bands[n];
1887 struct ieee80211_channel *c, *cent, *extc;
1888 uint8_t chan;
1889 int i, nflags;
1890
1891 if (!(sc->sc_flags & IWN_FLAG_HAS_11N))
1892 return;
1893
1894 for (i = 0; i < band->nchan; i++) {
1895 if (!(channels[i].flags & IWN_EEPROM_CHAN_VALID)) {
1896 DPRINTF(sc, IWN_DEBUG_RESET,
1897 "skip chan %d flags 0x%x maxpwr %d\n",
1898 band->chan[i], channels[i].flags,
1899 channels[i].maxpwr);
1900 continue;
1901 }
1902 chan = band->chan[i];
1903 nflags = iwn_eeprom_channel_flags(&channels[i]);
1904
1905 /*
1906 * Each entry defines an HT40 channel pair; find the
1907 * center channel, then the extension channel above.
1908 */
1909 cent = ieee80211_find_channel_byieee(ic, chan,
1910 (n == 5 ? IEEE80211_CHAN_G : IEEE80211_CHAN_A));
1911 if (cent == NULL) { /* XXX shouldn't happen */
1912 device_printf(sc->sc_dev,
1913 "%s: no entry for channel %d\n", __func__, chan);
1914 continue;
1915 }
1916 extc = ieee80211_find_channel(ic, cent->ic_freq+20,
1917 (n == 5 ? IEEE80211_CHAN_G : IEEE80211_CHAN_A));
1918 if (extc == NULL) {
1919 DPRINTF(sc, IWN_DEBUG_RESET,
1920 "%s: skip chan %d, extension channel not found\n",
1921 __func__, chan);
1922 continue;
1923 }
1924
1925 DPRINTF(sc, IWN_DEBUG_RESET,
1926 "add ht40 chan %d flags 0x%x maxpwr %d\n",
1927 chan, channels[i].flags, channels[i].maxpwr);
1928
1929 c = &ic->ic_channels[ic->ic_nchans++];
1930 c[0] = cent[0];
1931 c->ic_extieee = extc->ic_ieee;
1932 c->ic_flags &= ~IEEE80211_CHAN_HT;
1933 c->ic_flags |= IEEE80211_CHAN_HT40U | nflags;
1934 c = &ic->ic_channels[ic->ic_nchans++];
1935 c[0] = extc[0];
1936 c->ic_extieee = cent->ic_ieee;
1937 c->ic_flags &= ~IEEE80211_CHAN_HT;
1938 c->ic_flags |= IEEE80211_CHAN_HT40D | nflags;
1939 }
1940}
1941
1942static void
1943iwn_read_eeprom_channels(struct iwn_softc *sc, int n, uint32_t addr)
1944{
1945 struct ifnet *ifp = sc->sc_ifp;
1946 struct ieee80211com *ic = ifp->if_l2com;
1947
1948 iwn_read_prom_data(sc, addr, &sc->eeprom_channels[n],
1949 iwn_bands[n].nchan * sizeof (struct iwn_eeprom_chan));
1950
1951 if (n < 5)
1952 iwn_read_eeprom_band(sc, n);
1953 else
1954 iwn_read_eeprom_ht40(sc, n);
1955 ieee80211_sort_channels(ic->ic_channels, ic->ic_nchans);
1956}
1957
1958static struct iwn_eeprom_chan *
1959iwn_find_eeprom_channel(struct iwn_softc *sc, struct ieee80211_channel *c)
1960{
1961 int band, chan, i, j;
1962
1963 if (IEEE80211_IS_CHAN_HT40(c)) {
1964 band = IEEE80211_IS_CHAN_5GHZ(c) ? 6 : 5;
1965 if (IEEE80211_IS_CHAN_HT40D(c))
1966 chan = c->ic_extieee;
1967 else
1968 chan = c->ic_ieee;
1969 for (i = 0; i < iwn_bands[band].nchan; i++) {
1970 if (iwn_bands[band].chan[i] == chan)
1971 return &sc->eeprom_channels[band][i];
1972 }
1973 } else {
1974 for (j = 0; j < 5; j++) {
1975 for (i = 0; i < iwn_bands[j].nchan; i++) {
1976 if (iwn_bands[j].chan[i] == c->ic_ieee)
1977 return &sc->eeprom_channels[j][i];
1978 }
1979 }
1980 }
1981 return NULL;
1982}
1983
1984/*
1985 * Enforce flags read from EEPROM.
1986 */
1987static int
1988iwn_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *rd,
1989 int nchan, struct ieee80211_channel chans[])
1990{
1991 struct iwn_softc *sc = ic->ic_ifp->if_softc;
1992 int i;
1993
1994 for (i = 0; i < nchan; i++) {
1995 struct ieee80211_channel *c = &chans[i];
1996 struct iwn_eeprom_chan *channel;
1997
1998 channel = iwn_find_eeprom_channel(sc, c);
1999 if (channel == NULL) {
2000 if_printf(ic->ic_ifp,
2001 "%s: invalid channel %u freq %u/0x%x\n",
2002 __func__, c->ic_ieee, c->ic_freq, c->ic_flags);
2003 return EINVAL;
2004 }
2005 c->ic_flags |= iwn_eeprom_channel_flags(channel);
2006 }
2007
2008 return 0;
2009}
2010
2011static void
2012iwn_read_eeprom_enhinfo(struct iwn_softc *sc)
2013{
2014 struct iwn_eeprom_enhinfo enhinfo[35];
2015 struct ifnet *ifp = sc->sc_ifp;
2016 struct ieee80211com *ic = ifp->if_l2com;
2017 struct ieee80211_channel *c;
2018 uint16_t val, base;
2019 int8_t maxpwr;
2020 uint8_t flags;
2021 int i, j;
2022
2023 iwn_read_prom_data(sc, IWN5000_EEPROM_REG, &val, 2);
2024 base = le16toh(val);
2025 iwn_read_prom_data(sc, base + IWN6000_EEPROM_ENHINFO,
2026 enhinfo, sizeof enhinfo);
2027
2028 for (i = 0; i < nitems(enhinfo); i++) {
2029 flags = enhinfo[i].flags;
2030 if (!(flags & IWN_ENHINFO_VALID))
2031 continue; /* Skip invalid entries. */
2032
2033 maxpwr = 0;
2034 if (sc->txchainmask & IWN_ANT_A)
2035 maxpwr = MAX(maxpwr, enhinfo[i].chain[0]);
2036 if (sc->txchainmask & IWN_ANT_B)
2037 maxpwr = MAX(maxpwr, enhinfo[i].chain[1]);
2038 if (sc->txchainmask & IWN_ANT_C)
2039 maxpwr = MAX(maxpwr, enhinfo[i].chain[2]);
2040 if (sc->ntxchains == 2)
2041 maxpwr = MAX(maxpwr, enhinfo[i].mimo2);
2042 else if (sc->ntxchains == 3)
2043 maxpwr = MAX(maxpwr, enhinfo[i].mimo3);
2044
2045 for (j = 0; j < ic->ic_nchans; j++) {
2046 c = &ic->ic_channels[j];
2047 if ((flags & IWN_ENHINFO_5GHZ)) {
2048 if (!IEEE80211_IS_CHAN_A(c))
2049 continue;
2050 } else if ((flags & IWN_ENHINFO_OFDM)) {
2051 if (!IEEE80211_IS_CHAN_G(c))
2052 continue;
2053 } else if (!IEEE80211_IS_CHAN_B(c))
2054 continue;
2055 if ((flags & IWN_ENHINFO_HT40)) {
2056 if (!IEEE80211_IS_CHAN_HT40(c))
2057 continue;
2058 } else {
2059 if (IEEE80211_IS_CHAN_HT40(c))
2060 continue;
2061 }
2062 if (enhinfo[i].chan != 0 &&
2063 enhinfo[i].chan != c->ic_ieee)
2064 continue;
2065
2066 DPRINTF(sc, IWN_DEBUG_RESET,
2067 "channel %d(%x), maxpwr %d\n", c->ic_ieee,
2068 c->ic_flags, maxpwr / 2);
2069 c->ic_maxregpower = maxpwr / 2;
2070 c->ic_maxpower = maxpwr;
2071 }
2072 }
2073}
2074
2075static struct ieee80211_node *
2076iwn_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN])
2077{
2078 return malloc(sizeof (struct iwn_node), M_80211_NODE,M_NOWAIT | M_ZERO);
2079}
2080
2081static __inline int
2082rate2plcp(int rate)
2083{
2084 switch (rate & 0xff) {
2085 case 12: return 0xd;
2086 case 18: return 0xf;
2087 case 24: return 0x5;
2088 case 36: return 0x7;
2089 case 48: return 0x9;
2090 case 72: return 0xb;
2091 case 96: return 0x1;
2092 case 108: return 0x3;
2093 case 2: return 10;
2094 case 4: return 20;
2095 case 11: return 55;
2096 case 22: return 110;
2097 }
2098 return 0;
2099}
2100
2101static void
2102iwn_newassoc(struct ieee80211_node *ni, int isnew)
2103{
2104#define RV(v) ((v) & IEEE80211_RATE_VAL)
2105 struct ieee80211com *ic = ni->ni_ic;
2106 struct iwn_softc *sc = ic->ic_ifp->if_softc;
2107 struct iwn_node *wn = (void *)ni;
2108 uint8_t txant1, txant2;
2109 int i, plcp, rate, ridx;
2110
2111 /* Use the first valid TX antenna. */
2112 txant1 = IWN_LSB(sc->txchainmask);
2113 txant2 = IWN_LSB(sc->txchainmask & ~txant1);
2114
2115 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) {
2116 ridx = ni->ni_rates.rs_nrates - 1;
2117 for (i = ni->ni_htrates.rs_nrates - 1; i >= 0; i--) {
2118 plcp = RV(ni->ni_htrates.rs_rates[i]) | IWN_RFLAG_MCS;
2119 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan)) {
2120 plcp |= IWN_RFLAG_HT40;
2121 if (ni->ni_htcap & IEEE80211_HTCAP_SHORTGI40)
2122 plcp |= IWN_RFLAG_SGI;
2123 } else if (ni->ni_htcap & IEEE80211_HTCAP_SHORTGI20)
2124 plcp |= IWN_RFLAG_SGI;
2125 if (RV(ni->ni_htrates.rs_rates[i]) > 7)
2126 plcp |= IWN_RFLAG_ANT(txant1 | txant2);
2127 else
2128 plcp |= IWN_RFLAG_ANT(txant1);
2129 if (ridx >= 0) {
2130 rate = RV(ni->ni_rates.rs_rates[ridx]);
2131 wn->ridx[rate] = plcp;
2132 }
2133 wn->ridx[IEEE80211_RATE_MCS | i] = plcp;
2134 ridx--;
2135 }
2136 } else {
2137 for (i = 0; i < ni->ni_rates.rs_nrates; i++) {
2138 rate = RV(ni->ni_rates.rs_rates[i]);
2139 plcp = rate2plcp(rate);
2140 ridx = ic->ic_rt->rateCodeToIndex[rate];
2141 if (ridx < IWN_RIDX_OFDM6 &&
2142 IEEE80211_IS_CHAN_2GHZ(ni->ni_chan))
2143 plcp |= IWN_RFLAG_CCK;
2144 plcp |= IWN_RFLAG_ANT(txant1);
2145 wn->ridx[rate] = htole32(plcp);
2146 }
2147 }
2148#undef RV
2149}
2150
2151static int
2152iwn_media_change(struct ifnet *ifp)
2153{
2154 int error;
2155
2156 error = ieee80211_media_change(ifp);
2157 /* NB: only the fixed rate can change and that doesn't need a reset */
2158 return (error == ENETRESET ? 0 : error);
2159}
2160
2161static int
2162iwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
2163{
2164 struct iwn_vap *ivp = IWN_VAP(vap);
2165 struct ieee80211com *ic = vap->iv_ic;
2166 struct iwn_softc *sc = ic->ic_ifp->if_softc;
2167 int error = 0;
2168
2169 DPRINTF(sc, IWN_DEBUG_STATE, "%s: %s -> %s\n", __func__,
2170 ieee80211_state_name[vap->iv_state], ieee80211_state_name[nstate]);
2171
2172 IEEE80211_UNLOCK(ic);
2173 IWN_LOCK(sc);
2174 callout_stop(&sc->calib_to);
2175
2176 switch (nstate) {
2177 case IEEE80211_S_ASSOC:
2178 if (vap->iv_state != IEEE80211_S_RUN)
2179 break;
2180 /* FALLTHROUGH */
2181 case IEEE80211_S_AUTH:
2182 if (vap->iv_state == IEEE80211_S_AUTH)
2183 break;
2184
2185 /*
2186 * !AUTH -> AUTH transition requires state reset to handle
2187 * reassociations correctly.
2188 */
2189 sc->rxon.associd = 0;
2190 sc->rxon.filter &= ~htole32(IWN_FILTER_BSS);
2191 sc->calib.state = IWN_CALIB_STATE_INIT;
2192
2193 if ((error = iwn_auth(sc, vap)) != 0) {
2194 device_printf(sc->sc_dev,
2195 "%s: could not move to auth state\n", __func__);
2196 }
2197 break;
2198
2199 case IEEE80211_S_RUN:
2200 /*
2201 * RUN -> RUN transition; Just restart the timers.
2202 */
2203 if (vap->iv_state == IEEE80211_S_RUN) {
2204 sc->calib_cnt = 0;
2205 break;
2206 }
2207
2208 /*
2209 * !RUN -> RUN requires setting the association id
2210 * which is done with a firmware cmd. We also defer
2211 * starting the timers until that work is done.
2212 */
2213 if ((error = iwn_run(sc, vap)) != 0) {
2214 device_printf(sc->sc_dev,
2215 "%s: could not move to run state\n", __func__);
2216 }
2217 break;
2218
2219 case IEEE80211_S_INIT:
2220 sc->calib.state = IWN_CALIB_STATE_INIT;
2221 break;
2222
2223 default:
2224 break;
2225 }
2226 IWN_UNLOCK(sc);
2227 IEEE80211_LOCK(ic);
2228 if (error != 0)
2229 return error;
2230 return ivp->iv_newstate(vap, nstate, arg);
2231}
2232
2233static void
2234iwn_calib_timeout(void *arg)
2235{
2236 struct iwn_softc *sc = arg;
2237
2238 IWN_LOCK_ASSERT(sc);
2239
2240 /* Force automatic TX power calibration every 60 secs. */
2241 if (++sc->calib_cnt >= 120) {
2242 uint32_t flags = 0;
2243
2244 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s\n",
2245 "sending request for statistics");
2246 (void)iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags,
2247 sizeof flags, 1);
2248 sc->calib_cnt = 0;
2249 }
2250 callout_reset(&sc->calib_to, msecs_to_ticks(500), iwn_calib_timeout,
2251 sc);
2252}
2253
2254/*
2255 * Process an RX_PHY firmware notification. This is usually immediately
2256 * followed by an MPDU_RX_DONE notification.
2257 */
2258static void
2259iwn_rx_phy(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2260 struct iwn_rx_data *data)
2261{
2262 struct iwn_rx_stat *stat = (struct iwn_rx_stat *)(desc + 1);
2263
2264 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: received PHY stats\n", __func__);
2265 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD);
2266
2267 /* Save RX statistics, they will be used on MPDU_RX_DONE. */
2268 memcpy(&sc->last_rx_stat, stat, sizeof (*stat));
2269 sc->last_rx_valid = 1;
2270}
2271
2272/*
2273 * Process an RX_DONE (4965AGN only) or MPDU_RX_DONE firmware notification.
2274 * Each MPDU_RX_DONE notification must be preceded by an RX_PHY one.
2275 */
2276static void
2277iwn_rx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2278 struct iwn_rx_data *data)
2279{
2280 struct iwn_ops *ops = &sc->ops;
2281 struct ifnet *ifp = sc->sc_ifp;
2282 struct ieee80211com *ic = ifp->if_l2com;
2283 struct iwn_rx_ring *ring = &sc->rxq;
2284 struct ieee80211_frame *wh;
2285 struct ieee80211_node *ni;
2286 struct mbuf *m, *m1;
2287 struct iwn_rx_stat *stat;
2288 caddr_t head;
2289 bus_addr_t paddr;
2290 uint32_t flags;
2291 int error, len, rssi, nf;
2292
2293 if (desc->type == IWN_MPDU_RX_DONE) {
2294 /* Check for prior RX_PHY notification. */
2295 if (!sc->last_rx_valid) {
2296 DPRINTF(sc, IWN_DEBUG_ANY,
2297 "%s: missing RX_PHY\n", __func__);
2298 return;
2299 }
2300 stat = &sc->last_rx_stat;
2301 } else
2302 stat = (struct iwn_rx_stat *)(desc + 1);
2303
2304 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD);
2305
2306 if (stat->cfg_phy_len > IWN_STAT_MAXLEN) {
2307 device_printf(sc->sc_dev,
2308 "%s: invalid RX statistic header, len %d\n", __func__,
2309 stat->cfg_phy_len);
2310 return;
2311 }
2312 if (desc->type == IWN_MPDU_RX_DONE) {
2313 struct iwn_rx_mpdu *mpdu = (struct iwn_rx_mpdu *)(desc + 1);
2314 head = (caddr_t)(mpdu + 1);
2315 len = le16toh(mpdu->len);
2316 } else {
2317 head = (caddr_t)(stat + 1) + stat->cfg_phy_len;
2318 len = le16toh(stat->len);
2319 }
2320
2321 flags = le32toh(*(uint32_t *)(head + len));
2322
2323 /* Discard frames with a bad FCS early. */
2324 if ((flags & IWN_RX_NOERROR) != IWN_RX_NOERROR) {
2325 DPRINTF(sc, IWN_DEBUG_RECV, "%s: RX flags error %x\n",
2326 __func__, flags);
2327 ifp->if_ierrors++;
2328 return;
2329 }
2330 /* Discard frames that are too short. */
2331 if (len < sizeof (*wh)) {
2332 DPRINTF(sc, IWN_DEBUG_RECV, "%s: frame too short: %d\n",
2333 __func__, len);
2334 ifp->if_ierrors++;
2335 return;
2336 }
2337
2338 m1 = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, IWN_RBUF_SIZE);
2339 if (m1 == NULL) {
2340 DPRINTF(sc, IWN_DEBUG_ANY, "%s: no mbuf to restock ring\n",
2341 __func__);
2342 ifp->if_ierrors++;
2343 return;
2344 }
2345 bus_dmamap_unload(ring->data_dmat, data->map);
2346
2347 error = bus_dmamap_load(ring->data_dmat, data->map, mtod(m1, void *),
2348 IWN_RBUF_SIZE, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT);
2349 if (error != 0 && error != EFBIG) {
2350 device_printf(sc->sc_dev,
2351 "%s: bus_dmamap_load failed, error %d\n", __func__, error);
2352 m_freem(m1);
2353
2354 /* Try to reload the old mbuf. */
2355 error = bus_dmamap_load(ring->data_dmat, data->map,
2356 mtod(data->m, void *), IWN_RBUF_SIZE, iwn_dma_map_addr,
2357 &paddr, BUS_DMA_NOWAIT);
2358 if (error != 0 && error != EFBIG) {
2359 panic("%s: could not load old RX mbuf", __func__);
2360 }
2361 /* Physical address may have changed. */
2362 ring->desc[ring->cur] = htole32(paddr >> 8);
2363 bus_dmamap_sync(ring->data_dmat, ring->desc_dma.map,
2364 BUS_DMASYNC_PREWRITE);
2365 ifp->if_ierrors++;
2366 return;
2367 }
2368
2369 m = data->m;
2370 data->m = m1;
2371 /* Update RX descriptor. */
2372 ring->desc[ring->cur] = htole32(paddr >> 8);
2373 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
2374 BUS_DMASYNC_PREWRITE);
2375
2376 /* Finalize mbuf. */
2377 m->m_pkthdr.rcvif = ifp;
2378 m->m_data = head;
2379 m->m_pkthdr.len = m->m_len = len;
2380
2381 /* Grab a reference to the source node. */
2382 wh = mtod(m, struct ieee80211_frame *);
2383 ni = ieee80211_find_rxnode(ic, (struct ieee80211_frame_min *)wh);
2384 nf = (ni != NULL && ni->ni_vap->iv_state == IEEE80211_S_RUN &&
2385 (ic->ic_flags & IEEE80211_F_SCAN) == 0) ? sc->noise : -95;
2386
2387 rssi = ops->get_rssi(sc, stat);
2388
2389 if (ieee80211_radiotap_active(ic)) {
2390 struct iwn_rx_radiotap_header *tap = &sc->sc_rxtap;
2391
2392 tap->wr_flags = 0;
2393 if (stat->flags & htole16(IWN_STAT_FLAG_SHPREAMBLE))
2394 tap->wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
2395 tap->wr_dbm_antsignal = (int8_t)rssi;
2396 tap->wr_dbm_antnoise = (int8_t)nf;
2397 tap->wr_tsft = stat->tstamp;
2398 switch (stat->rate) {
2399 /* CCK rates. */
2400 case 10: tap->wr_rate = 2; break;
2401 case 20: tap->wr_rate = 4; break;
2402 case 55: tap->wr_rate = 11; break;
2403 case 110: tap->wr_rate = 22; break;
2404 /* OFDM rates. */
2405 case 0xd: tap->wr_rate = 12; break;
2406 case 0xf: tap->wr_rate = 18; break;
2407 case 0x5: tap->wr_rate = 24; break;
2408 case 0x7: tap->wr_rate = 36; break;
2409 case 0x9: tap->wr_rate = 48; break;
2410 case 0xb: tap->wr_rate = 72; break;
2411 case 0x1: tap->wr_rate = 96; break;
2412 case 0x3: tap->wr_rate = 108; break;
2413 /* Unknown rate: should not happen. */
2414 default: tap->wr_rate = 0;
2415 }
2416 }
2417
2418 IWN_UNLOCK(sc);
2419
2420 /* Send the frame to the 802.11 layer. */
2421 if (ni != NULL) {
2422 if (ni->ni_flags & IEEE80211_NODE_HT)
2423 m->m_flags |= M_AMPDU;
2424 (void)ieee80211_input(ni, m, rssi - nf, nf);
2425 /* Node is no longer needed. */
2426 ieee80211_free_node(ni);
2427 } else
2428 (void)ieee80211_input_all(ic, m, rssi - nf, nf);
2429
2430 IWN_LOCK(sc);
2431}
2432
2433/* Process an incoming Compressed BlockAck. */
2434static void
2435iwn_rx_compressed_ba(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2436 struct iwn_rx_data *data)
2437{
2438 struct iwn_ops *ops = &sc->ops;
2439 struct ifnet *ifp = sc->sc_ifp;
2440 struct iwn_node *wn;
2441 struct ieee80211_node *ni;
2442 struct iwn_compressed_ba *ba = (struct iwn_compressed_ba *)(desc + 1);
2443 struct iwn_tx_ring *txq;
2444 struct iwn_tx_data *txdata;
2445 struct ieee80211_tx_ampdu *tap;
2446 struct mbuf *m;
2447 uint64_t bitmap;
2448 uint16_t ssn;
2449 uint8_t tid;
2450 int ackfailcnt = 0, i, lastidx, qid, *res, shift;
2451
2452 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD);
2453
2454 qid = le16toh(ba->qid);
2455 txq = &sc->txq[ba->qid];
2456 tap = sc->qid2tap[ba->qid];
2457 tid = tap->txa_tid;
2458 wn = (void *)tap->txa_ni;
2459
2460 res = NULL;
2461 ssn = 0;
2462 if (!IEEE80211_AMPDU_RUNNING(tap)) {
2463 res = tap->txa_private;
2464 ssn = tap->txa_start & 0xfff;
2465 }
2466
2467 for (lastidx = le16toh(ba->ssn) & 0xff; txq->read != lastidx;) {
2468 txdata = &txq->data[txq->read];
2469
2470 /* Unmap and free mbuf. */
2471 bus_dmamap_sync(txq->data_dmat, txdata->map,
2472 BUS_DMASYNC_POSTWRITE);
2473 bus_dmamap_unload(txq->data_dmat, txdata->map);
2474 m = txdata->m, txdata->m = NULL;
2475 ni = txdata->ni, txdata->ni = NULL;
2476
2477 KASSERT(ni != NULL, ("no node"));
2478 KASSERT(m != NULL, ("no mbuf"));
2479
2480 if (m->m_flags & M_TXCB)
2481 ieee80211_process_callback(ni, m, 1);
2482
2483 m_freem(m);
2484 ieee80211_free_node(ni);
2485
2486 txq->queued--;
2487 txq->read = (txq->read + 1) % IWN_TX_RING_COUNT;
2488 }
2489
2490 if (txq->queued == 0 && res != NULL) {
2491 iwn_nic_lock(sc);
2492 ops->ampdu_tx_stop(sc, qid, tid, ssn);
2493 iwn_nic_unlock(sc);
2494 sc->qid2tap[qid] = NULL;
2495 free(res, M_DEVBUF);
2496 return;
2497 }
2498
2499 if (wn->agg[tid].bitmap == 0)
2500 return;
2501
2502 shift = wn->agg[tid].startidx - ((le16toh(ba->seq) >> 4) & 0xff);
2503 if (shift < 0)
2504 shift += 0x100;
2505
2506 if (wn->agg[tid].nframes > (64 - shift))
2507 return;
2508
2509 ni = tap->txa_ni;
2510 bitmap = (le64toh(ba->bitmap) >> shift) & wn->agg[tid].bitmap;
2511 for (i = 0; bitmap; i++) {
2512 if ((bitmap & 1) == 0) {
2513 ifp->if_oerrors++;
2514 ieee80211_ratectl_tx_complete(ni->ni_vap, ni,
2515 IEEE80211_RATECTL_TX_FAILURE, &ackfailcnt, NULL);
2516 } else {
2517 ifp->if_opackets++;
2518 ieee80211_ratectl_tx_complete(ni->ni_vap, ni,
2519 IEEE80211_RATECTL_TX_SUCCESS, &ackfailcnt, NULL);
2520 }
2521 bitmap >>= 1;
2522 }
2523}
2524
2525/*
2526 * Process a CALIBRATION_RESULT notification sent by the initialization
2527 * firmware on response to a CMD_CALIB_CONFIG command (5000 only).
2528 */
2529static void
2530iwn5000_rx_calib_results(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2531 struct iwn_rx_data *data)
2532{
2533 struct iwn_phy_calib *calib = (struct iwn_phy_calib *)(desc + 1);
2534 int len, idx = -1;
2535
2536 /* Runtime firmware should not send such a notification. */
2537 if (sc->sc_flags & IWN_FLAG_CALIB_DONE)
2538 return;
2539
2540 len = (le32toh(desc->len) & 0x3fff) - 4;
2541 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD);
2542
2543 switch (calib->code) {
2544 case IWN5000_PHY_CALIB_DC:
2545 if ((sc->sc_flags & IWN_FLAG_INTERNAL_PA) == 0 &&
2546 (sc->hw_type == IWN_HW_REV_TYPE_5150 ||
2547 sc->hw_type >= IWN_HW_REV_TYPE_6000) &&
2548 sc->hw_type != IWN_HW_REV_TYPE_6050)
2549 idx = 0;
2550 break;
2551 case IWN5000_PHY_CALIB_LO:
2552 idx = 1;
2553 break;
2554 case IWN5000_PHY_CALIB_TX_IQ:
2555 idx = 2;
2556 break;
2557 case IWN5000_PHY_CALIB_TX_IQ_PERIODIC:
2558 if (sc->hw_type < IWN_HW_REV_TYPE_6000 &&
2559 sc->hw_type != IWN_HW_REV_TYPE_5150)
2560 idx = 3;
2561 break;
2562 case IWN5000_PHY_CALIB_BASE_BAND:
2563 idx = 4;
2564 break;
2565 }
2566 if (idx == -1) /* Ignore other results. */
2567 return;
2568
2569 /* Save calibration result. */
2570 if (sc->calibcmd[idx].buf != NULL)
2571 free(sc->calibcmd[idx].buf, M_DEVBUF);
2572 sc->calibcmd[idx].buf = malloc(len, M_DEVBUF, M_NOWAIT);
2573 if (sc->calibcmd[idx].buf == NULL) {
2574 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
2575 "not enough memory for calibration result %d\n",
2576 calib->code);
2577 return;
2578 }
2579 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
2580 "saving calibration result code=%d len=%d\n", calib->code, len);
2581 sc->calibcmd[idx].len = len;
2582 memcpy(sc->calibcmd[idx].buf, calib, len);
2583}
2584
2585/*
2586 * Process an RX_STATISTICS or BEACON_STATISTICS firmware notification.
2587 * The latter is sent by the firmware after each received beacon.
2588 */
2589static void
2590iwn_rx_statistics(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2591 struct iwn_rx_data *data)
2592{
2593 struct iwn_ops *ops = &sc->ops;
2594 struct ifnet *ifp = sc->sc_ifp;
2595 struct ieee80211com *ic = ifp->if_l2com;
2596 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
2597 struct iwn_calib_state *calib = &sc->calib;
2598 struct iwn_stats *stats = (struct iwn_stats *)(desc + 1);
2599 int temp;
2600
2601 /* Ignore statistics received during a scan. */
2602 if (vap->iv_state != IEEE80211_S_RUN ||
2603 (ic->ic_flags & IEEE80211_F_SCAN))
2604 return;
2605
2606 bus_dmamap_sync(sc->rxq.data_dmat, data->map, BUS_DMASYNC_POSTREAD);
2607
2608 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: received statistics, cmd %d\n",
2609 __func__, desc->type);
2610 sc->calib_cnt = 0; /* Reset TX power calibration timeout. */
2611
2612 /* Test if temperature has changed. */
2613 if (stats->general.temp != sc->rawtemp) {
2614 /* Convert "raw" temperature to degC. */
2615 sc->rawtemp = stats->general.temp;
2616 temp = ops->get_temperature(sc);
2617 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d\n",
2618 __func__, temp);
2619
2620 /* Update TX power if need be (4965AGN only). */
2621 if (sc->hw_type == IWN_HW_REV_TYPE_4965)
2622 iwn4965_power_calibration(sc, temp);
2623 }
2624
2625 if (desc->type != IWN_BEACON_STATISTICS)
2626 return; /* Reply to a statistics request. */
2627
2628 sc->noise = iwn_get_noise(&stats->rx.general);
2629 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: noise %d\n", __func__, sc->noise);
2630
2631 /* Test that RSSI and noise are present in stats report. */
2632 if (le32toh(stats->rx.general.flags) != 1) {
2633 DPRINTF(sc, IWN_DEBUG_ANY, "%s\n",
2634 "received statistics without RSSI");
2635 return;
2636 }
2637
2638 if (calib->state == IWN_CALIB_STATE_ASSOC)
2639 iwn_collect_noise(sc, &stats->rx.general);
2640 else if (calib->state == IWN_CALIB_STATE_RUN)
2641 iwn_tune_sensitivity(sc, &stats->rx);
2642}
2643
2644/*
2645 * Process a TX_DONE firmware notification. Unfortunately, the 4965AGN
2646 * and 5000 adapters have different incompatible TX status formats.
2647 */
2648static void
2649iwn4965_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2650 struct iwn_rx_data *data)
2651{
2652 struct iwn4965_tx_stat *stat = (struct iwn4965_tx_stat *)(desc + 1);
2653 struct iwn_tx_ring *ring;
2654 int qid;
2655
2656 qid = desc->qid & 0xf;
2657 ring = &sc->txq[qid];
2658
2659 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: "
2660 "qid %d idx %d retries %d nkill %d rate %x duration %d status %x\n",
2661 __func__, desc->qid, desc->idx, stat->ackfailcnt,
2662 stat->btkillcnt, stat->rate, le16toh(stat->duration),
2663 le32toh(stat->status));
2664
2665 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD);
2666 if (qid >= sc->firstaggqueue) {
2667 iwn_ampdu_tx_done(sc, qid, desc->idx, stat->nframes,
2668 &stat->status);
2669 } else {
2670 iwn_tx_done(sc, desc, stat->ackfailcnt,
2671 le32toh(stat->status) & 0xff);
2672 }
2673}
2674
2675static void
2676iwn5000_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc,
2677 struct iwn_rx_data *data)
2678{
2679 struct iwn5000_tx_stat *stat = (struct iwn5000_tx_stat *)(desc + 1);
2680 struct iwn_tx_ring *ring;
2681 int qid;
2682
2683 qid = desc->qid & 0xf;
2684 ring = &sc->txq[qid];
2685
2686 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: "
2687 "qid %d idx %d retries %d nkill %d rate %x duration %d status %x\n",
2688 __func__, desc->qid, desc->idx, stat->ackfailcnt,
2689 stat->btkillcnt, stat->rate, le16toh(stat->duration),
2690 le32toh(stat->status));
2691
2692#ifdef notyet
2693 /* Reset TX scheduler slot. */
2694 iwn5000_reset_sched(sc, desc->qid & 0xf, desc->idx);
2695#endif
2696
2697 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTREAD);
2698 if (qid >= sc->firstaggqueue) {
2699 iwn_ampdu_tx_done(sc, qid, desc->idx, stat->nframes,
2700 &stat->status);
2701 } else {
2702 iwn_tx_done(sc, desc, stat->ackfailcnt,
2703 le16toh(stat->status) & 0xff);
2704 }
2705}
2706
2707/*
2708 * Adapter-independent backend for TX_DONE firmware notifications.
2709 */
2710static void
2711iwn_tx_done(struct iwn_softc *sc, struct iwn_rx_desc *desc, int ackfailcnt,
2712 uint8_t status)
2713{
2714 struct ifnet *ifp = sc->sc_ifp;
2715 struct iwn_tx_ring *ring = &sc->txq[desc->qid & 0xf];
2716 struct iwn_tx_data *data = &ring->data[desc->idx];
2717 struct mbuf *m;
2718 struct ieee80211_node *ni;
2719 struct ieee80211vap *vap;
2720
2721 KASSERT(data->ni != NULL, ("no node"));
2722
2723 /* Unmap and free mbuf. */
2724 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_POSTWRITE);
2725 bus_dmamap_unload(ring->data_dmat, data->map);
2726 m = data->m, data->m = NULL;
2727 ni = data->ni, data->ni = NULL;
2728 vap = ni->ni_vap;
2729
2730 if (m->m_flags & M_TXCB) {
2731 /*
2732 * Channels marked for "radar" require traffic to be received
2733 * to unlock before we can transmit. Until traffic is seen
2734 * any attempt to transmit is returned immediately with status
2735 * set to IWN_TX_FAIL_TX_LOCKED. Unfortunately this can easily
2736 * happen on first authenticate after scanning. To workaround
2737 * this we ignore a failure of this sort in AUTH state so the
2738 * 802.11 layer will fall back to using a timeout to wait for
2739 * the AUTH reply. This allows the firmware time to see
2740 * traffic so a subsequent retry of AUTH succeeds. It's
2741 * unclear why the firmware does not maintain state for
2742 * channels recently visited as this would allow immediate
2743 * use of the channel after a scan (where we see traffic).
2744 */
2745 if (status == IWN_TX_FAIL_TX_LOCKED &&
2746 ni->ni_vap->iv_state == IEEE80211_S_AUTH)
2747 ieee80211_process_callback(ni, m, 0);
2748 else
2749 ieee80211_process_callback(ni, m,
2750 (status & IWN_TX_FAIL) != 0);
2751 }
2752
2753 /*
2754 * Update rate control statistics for the node.
2755 */
2756 if (status & IWN_TX_FAIL) {
2757 ifp->if_oerrors++;
2758 ieee80211_ratectl_tx_complete(vap, ni,
2759 IEEE80211_RATECTL_TX_FAILURE, &ackfailcnt, NULL);
2760 } else {
2761 ifp->if_opackets++;
2762 ieee80211_ratectl_tx_complete(vap, ni,
2763 IEEE80211_RATECTL_TX_SUCCESS, &ackfailcnt, NULL);
2764 }
2765 m_freem(m);
2766 ieee80211_free_node(ni);
2767
2768 sc->sc_tx_timer = 0;
2769 if (--ring->queued < IWN_TX_RING_LOMARK) {
2770 sc->qfullmsk &= ~(1 << ring->qid);
2771 if (sc->qfullmsk == 0 &&
2772 (ifp->if_drv_flags & IFF_DRV_OACTIVE)) {
2773 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2774 iwn_start_locked(ifp);
2775 }
2776 }
2777}
2778
2779/*
2780 * Process a "command done" firmware notification. This is where we wakeup
2781 * processes waiting for a synchronous command completion.
2782 */
2783static void
2784iwn_cmd_done(struct iwn_softc *sc, struct iwn_rx_desc *desc)
2785{
2786 struct iwn_tx_ring *ring = &sc->txq[4];
2787 struct iwn_tx_data *data;
2788
2789 if ((desc->qid & 0xf) != 4)
2790 return; /* Not a command ack. */
2791
2792 data = &ring->data[desc->idx];
2793
2794 /* If the command was mapped in an mbuf, free it. */
2795 if (data->m != NULL) {
2796 bus_dmamap_sync(ring->data_dmat, data->map,
2797 BUS_DMASYNC_POSTWRITE);
2798 bus_dmamap_unload(ring->data_dmat, data->map);
2799 m_freem(data->m);
2800 data->m = NULL;
2801 }
2802 wakeup(&ring->desc[desc->idx]);
2803}
2804
2805static void
2806iwn_ampdu_tx_done(struct iwn_softc *sc, int qid, int idx, int nframes,
2807 void *stat)
2808{
2809 struct iwn_ops *ops = &sc->ops;
2810 struct ifnet *ifp = sc->sc_ifp;
2811 struct iwn_tx_ring *ring = &sc->txq[qid];
2812 struct iwn_tx_data *data;
2813 struct mbuf *m;
2814 struct iwn_node *wn;
2815 struct ieee80211_node *ni;
2816 struct ieee80211_tx_ampdu *tap;
2817 uint64_t bitmap;
2818 uint32_t *status = stat;
2819 uint16_t *aggstatus = stat;
2820 uint16_t ssn;
2821 uint8_t tid;
2822 int bit, i, lastidx, *res, seqno, shift, start;
2823
2824#ifdef NOT_YET
2825 if (nframes == 1) {
2826 if ((*status & 0xff) != 1 && (*status & 0xff) != 2)
2827 printf("ieee80211_send_bar()\n");
2828 }
2829#endif
2830
2831 bitmap = 0;
2832 start = idx;
2833 for (i = 0; i < nframes; i++) {
2834 if (le16toh(aggstatus[i * 2]) & 0xc)
2835 continue;
2836
2837 idx = le16toh(aggstatus[2*i + 1]) & 0xff;
2838 bit = idx - start;
2839 shift = 0;
2840 if (bit >= 64) {
2841 shift = 0x100 - idx + start;
2842 bit = 0;
2843 start = idx;
2844 } else if (bit <= -64)
2845 bit = 0x100 - start + idx;
2846 else if (bit < 0) {
2847 shift = start - idx;
2848 start = idx;
2849 bit = 0;
2850 }
2851 bitmap = bitmap << shift;
2852 bitmap |= 1ULL << bit;
2853 }
2854 tap = sc->qid2tap[qid];
2855 tid = tap->txa_tid;
2856 wn = (void *)tap->txa_ni;
2857 wn->agg[tid].bitmap = bitmap;
2858 wn->agg[tid].startidx = start;
2859 wn->agg[tid].nframes = nframes;
2860
2861 res = NULL;
2862 ssn = 0;
2863 if (!IEEE80211_AMPDU_RUNNING(tap)) {
2864 res = tap->txa_private;
2865 ssn = tap->txa_start & 0xfff;
2866 }
2867
2868 seqno = le32toh(*(status + nframes)) & 0xfff;
2869 for (lastidx = (seqno & 0xff); ring->read != lastidx;) {
2870 data = &ring->data[ring->read];
2871
2872 /* Unmap and free mbuf. */
2873 bus_dmamap_sync(ring->data_dmat, data->map,
2874 BUS_DMASYNC_POSTWRITE);
2875 bus_dmamap_unload(ring->data_dmat, data->map);
2876 m = data->m, data->m = NULL;
2877 ni = data->ni, data->ni = NULL;
2878
2879 KASSERT(ni != NULL, ("no node"));
2880 KASSERT(m != NULL, ("no mbuf"));
2881
2882 if (m->m_flags & M_TXCB)
2883 ieee80211_process_callback(ni, m, 1);
2884
2885 m_freem(m);
2886 ieee80211_free_node(ni);
2887
2888 ring->queued--;
2889 ring->read = (ring->read + 1) % IWN_TX_RING_COUNT;
2890 }
2891
2892 if (ring->queued == 0 && res != NULL) {
2893 iwn_nic_lock(sc);
2894 ops->ampdu_tx_stop(sc, qid, tid, ssn);
2895 iwn_nic_unlock(sc);
2896 sc->qid2tap[qid] = NULL;
2897 free(res, M_DEVBUF);
2898 return;
2899 }
2900
2901 sc->sc_tx_timer = 0;
2902 if (ring->queued < IWN_TX_RING_LOMARK) {
2903 sc->qfullmsk &= ~(1 << ring->qid);
2904 if (sc->qfullmsk == 0 &&
2905 (ifp->if_drv_flags & IFF_DRV_OACTIVE)) {
2906 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2907 iwn_start_locked(ifp);
2908 }
2909 }
2910}
2911
2912/*
2913 * Process an INT_FH_RX or INT_SW_RX interrupt.
2914 */
2915static void
2916iwn_notif_intr(struct iwn_softc *sc)
2917{
2918 struct iwn_ops *ops = &sc->ops;
2919 struct ifnet *ifp = sc->sc_ifp;
2920 struct ieee80211com *ic = ifp->if_l2com;
2921 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
2922 uint16_t hw;
2923
2924 bus_dmamap_sync(sc->rxq.stat_dma.tag, sc->rxq.stat_dma.map,
2925 BUS_DMASYNC_POSTREAD);
2926
2927 hw = le16toh(sc->rxq.stat->closed_count) & 0xfff;
2928 while (sc->rxq.cur != hw) {
2929 struct iwn_rx_data *data = &sc->rxq.data[sc->rxq.cur];
2930 struct iwn_rx_desc *desc;
2931
2932 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
2933 BUS_DMASYNC_POSTREAD);
2934 desc = mtod(data->m, struct iwn_rx_desc *);
2935
2936 DPRINTF(sc, IWN_DEBUG_RECV,
2937 "%s: qid %x idx %d flags %x type %d(%s) len %d\n",
2938 __func__, desc->qid & 0xf, desc->idx, desc->flags,
2939 desc->type, iwn_intr_str(desc->type),
2940 le16toh(desc->len));
2941
2942 if (!(desc->qid & 0x80)) /* Reply to a command. */
2943 iwn_cmd_done(sc, desc);
2944
2945 switch (desc->type) {
2946 case IWN_RX_PHY:
2947 iwn_rx_phy(sc, desc, data);
2948 break;
2949
2950 case IWN_RX_DONE: /* 4965AGN only. */
2951 case IWN_MPDU_RX_DONE:
2952 /* An 802.11 frame has been received. */
2953 iwn_rx_done(sc, desc, data);
2954 break;
2955
2956 case IWN_RX_COMPRESSED_BA:
2957 /* A Compressed BlockAck has been received. */
2958 iwn_rx_compressed_ba(sc, desc, data);
2959 break;
2960
2961 case IWN_TX_DONE:
2962 /* An 802.11 frame has been transmitted. */
2963 ops->tx_done(sc, desc, data);
2964 break;
2965
2966 case IWN_RX_STATISTICS:
2967 case IWN_BEACON_STATISTICS:
2968 iwn_rx_statistics(sc, desc, data);
2969 break;
2970
2971 case IWN_BEACON_MISSED:
2972 {
2973 struct iwn_beacon_missed *miss =
2974 (struct iwn_beacon_missed *)(desc + 1);
2975 int misses;
2976
2977 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
2978 BUS_DMASYNC_POSTREAD);
2979 misses = le32toh(miss->consecutive);
2980
2981 DPRINTF(sc, IWN_DEBUG_STATE,
2982 "%s: beacons missed %d/%d\n", __func__,
2983 misses, le32toh(miss->total));
2984 /*
2985 * If more than 5 consecutive beacons are missed,
2986 * reinitialize the sensitivity state machine.
2987 */
2988 if (vap->iv_state == IEEE80211_S_RUN &&
2989 (ic->ic_flags & IEEE80211_F_SCAN) == 0) {
2990 if (misses > 5)
2991 (void)iwn_init_sensitivity(sc);
2992 if (misses >= vap->iv_bmissthreshold) {
2993 IWN_UNLOCK(sc);
2994 ieee80211_beacon_miss(ic);
2995 IWN_LOCK(sc);
2996 }
2997 }
2998 break;
2999 }
3000 case IWN_UC_READY:
3001 {
3002 struct iwn_ucode_info *uc =
3003 (struct iwn_ucode_info *)(desc + 1);
3004
3005 /* The microcontroller is ready. */
3006 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
3007 BUS_DMASYNC_POSTREAD);
3008 DPRINTF(sc, IWN_DEBUG_RESET,
3009 "microcode alive notification version=%d.%d "
3010 "subtype=%x alive=%x\n", uc->major, uc->minor,
3011 uc->subtype, le32toh(uc->valid));
3012
3013 if (le32toh(uc->valid) != 1) {
3014 device_printf(sc->sc_dev,
3015 "microcontroller initialization failed");
3016 break;
3017 }
3018 if (uc->subtype == IWN_UCODE_INIT) {
3019 /* Save microcontroller report. */
3020 memcpy(&sc->ucode_info, uc, sizeof (*uc));
3021 }
3022 /* Save the address of the error log in SRAM. */
3023 sc->errptr = le32toh(uc->errptr);
3024 break;
3025 }
3026 case IWN_STATE_CHANGED:
3027 {
3028 uint32_t *status = (uint32_t *)(desc + 1);
3029
3030 /*
3031 * State change allows hardware switch change to be
3032 * noted. However, we handle this in iwn_intr as we
3033 * get both the enable/disble intr.
3034 */
3035 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
3036 BUS_DMASYNC_POSTREAD);
3037 DPRINTF(sc, IWN_DEBUG_INTR, "state changed to %x\n",
3038 le32toh(*status));
3039 break;
3040 }
3041 case IWN_START_SCAN:
3042 {
3043 struct iwn_start_scan *scan =
3044 (struct iwn_start_scan *)(desc + 1);
3045
3046 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
3047 BUS_DMASYNC_POSTREAD);
3048 DPRINTF(sc, IWN_DEBUG_ANY,
3049 "%s: scanning channel %d status %x\n",
3050 __func__, scan->chan, le32toh(scan->status));
3051 break;
3052 }
3053 case IWN_STOP_SCAN:
3054 {
3055 struct iwn_stop_scan *scan =
3056 (struct iwn_stop_scan *)(desc + 1);
3057
3058 bus_dmamap_sync(sc->rxq.data_dmat, data->map,
3059 BUS_DMASYNC_POSTREAD);
3060 DPRINTF(sc, IWN_DEBUG_STATE,
3061 "scan finished nchan=%d status=%d chan=%d\n",
3062 scan->nchan, scan->status, scan->chan);
3063
3064 IWN_UNLOCK(sc);
3065 ieee80211_scan_next(vap);
3066 IWN_LOCK(sc);
3067 break;
3068 }
3069 case IWN5000_CALIBRATION_RESULT:
3070 iwn5000_rx_calib_results(sc, desc, data);
3071 break;
3072
3073 case IWN5000_CALIBRATION_DONE:
3074 sc->sc_flags |= IWN_FLAG_CALIB_DONE;
3075 wakeup(sc);
3076 break;
3077 }
3078
3079 sc->rxq.cur = (sc->rxq.cur + 1) % IWN_RX_RING_COUNT;
3080 }
3081
3082 /* Tell the firmware what we have processed. */
3083 hw = (hw == 0) ? IWN_RX_RING_COUNT - 1 : hw - 1;
3084 IWN_WRITE(sc, IWN_FH_RX_WPTR, hw & ~7);
3085}
3086
3087/*
3088 * Process an INT_WAKEUP interrupt raised when the microcontroller wakes up
3089 * from power-down sleep mode.
3090 */
3091static void
3092iwn_wakeup_intr(struct iwn_softc *sc)
3093{
3094 int qid;
3095
3096 DPRINTF(sc, IWN_DEBUG_RESET, "%s: ucode wakeup from power-down sleep\n",
3097 __func__);
3098
3099 /* Wakeup RX and TX rings. */
3100 IWN_WRITE(sc, IWN_FH_RX_WPTR, sc->rxq.cur & ~7);
3101 for (qid = 0; qid < sc->ntxqs; qid++) {
3102 struct iwn_tx_ring *ring = &sc->txq[qid];
3103 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | ring->cur);
3104 }
3105}
3106
3107static void
3108iwn_rftoggle_intr(struct iwn_softc *sc)
3109{
3110 struct ifnet *ifp = sc->sc_ifp;
3111 struct ieee80211com *ic = ifp->if_l2com;
3112 uint32_t tmp = IWN_READ(sc, IWN_GP_CNTRL);
3113
3114 IWN_LOCK_ASSERT(sc);
3115
3116 device_printf(sc->sc_dev, "RF switch: radio %s\n",
3117 (tmp & IWN_GP_CNTRL_RFKILL) ? "enabled" : "disabled");
3118 if (tmp & IWN_GP_CNTRL_RFKILL)
3119 ieee80211_runtask(ic, &sc->sc_radioon_task);
3120 else
3121 ieee80211_runtask(ic, &sc->sc_radiooff_task);
3122}
3123
3124/*
3125 * Dump the error log of the firmware when a firmware panic occurs. Although
3126 * we can't debug the firmware because it is neither open source nor free, it
3127 * can help us to identify certain classes of problems.
3128 */
3129static void
3130iwn_fatal_intr(struct iwn_softc *sc)
3131{
3132 struct iwn_fw_dump dump;
3133 int i;
3134
3135 IWN_LOCK_ASSERT(sc);
3136
3137 /* Force a complete recalibration on next init. */
3138 sc->sc_flags &= ~IWN_FLAG_CALIB_DONE;
3139
3140 /* Check that the error log address is valid. */
3141 if (sc->errptr < IWN_FW_DATA_BASE ||
3142 sc->errptr + sizeof (dump) >
3143 IWN_FW_DATA_BASE + sc->fw_data_maxsz) {
3144 printf("%s: bad firmware error log address 0x%08x\n", __func__,
3145 sc->errptr);
3146 return;
3147 }
3148 if (iwn_nic_lock(sc) != 0) {
3149 printf("%s: could not read firmware error log\n", __func__);
3150 return;
3151 }
3152 /* Read firmware error log from SRAM. */
3153 iwn_mem_read_region_4(sc, sc->errptr, (uint32_t *)&dump,
3154 sizeof (dump) / sizeof (uint32_t));
3155 iwn_nic_unlock(sc);
3156
3157 if (dump.valid == 0) {
3158 printf("%s: firmware error log is empty\n", __func__);
3159 return;
3160 }
3161 printf("firmware error log:\n");
3162 printf(" error type = \"%s\" (0x%08X)\n",
3163 (dump.id < nitems(iwn_fw_errmsg)) ?
3164 iwn_fw_errmsg[dump.id] : "UNKNOWN",
3165 dump.id);
3166 printf(" program counter = 0x%08X\n", dump.pc);
3167 printf(" source line = 0x%08X\n", dump.src_line);
3168 printf(" error data = 0x%08X%08X\n",
3169 dump.error_data[0], dump.error_data[1]);
3170 printf(" branch link = 0x%08X%08X\n",
3171 dump.branch_link[0], dump.branch_link[1]);
3172 printf(" interrupt link = 0x%08X%08X\n",
3173 dump.interrupt_link[0], dump.interrupt_link[1]);
3174 printf(" time = %u\n", dump.time[0]);
3175
3176 /* Dump driver status (TX and RX rings) while we're here. */
3177 printf("driver status:\n");
3178 for (i = 0; i < sc->ntxqs; i++) {
3179 struct iwn_tx_ring *ring = &sc->txq[i];
3180 printf(" tx ring %2d: qid=%-2d cur=%-3d queued=%-3d\n",
3181 i, ring->qid, ring->cur, ring->queued);
3182 }
3183 printf(" rx ring: cur=%d\n", sc->rxq.cur);
3184}
3185
3186static void
3187iwn_intr(void *arg)
3188{
3189 struct iwn_softc *sc = arg;
3190 struct ifnet *ifp = sc->sc_ifp;
3191 uint32_t r1, r2, tmp;
3192
3193 IWN_LOCK(sc);
3194
3195 /* Disable interrupts. */
3196 IWN_WRITE(sc, IWN_INT_MASK, 0);
3197
3198 /* Read interrupts from ICT (fast) or from registers (slow). */
3199 if (sc->sc_flags & IWN_FLAG_USE_ICT) {
3200 tmp = 0;
3201 while (sc->ict[sc->ict_cur] != 0) {
3202 tmp |= sc->ict[sc->ict_cur];
3203 sc->ict[sc->ict_cur] = 0; /* Acknowledge. */
3204 sc->ict_cur = (sc->ict_cur + 1) % IWN_ICT_COUNT;
3205 }
3206 tmp = le32toh(tmp);
3207 if (tmp == 0xffffffff) /* Shouldn't happen. */
3208 tmp = 0;
3209 else if (tmp & 0xc0000) /* Workaround a HW bug. */
3210 tmp |= 0x8000;
3211 r1 = (tmp & 0xff00) << 16 | (tmp & 0xff);
3212 r2 = 0; /* Unused. */
3213 } else {
3214 r1 = IWN_READ(sc, IWN_INT);
3215 if (r1 == 0xffffffff || (r1 & 0xfffffff0) == 0xa5a5a5a0)
3216 return; /* Hardware gone! */
3217 r2 = IWN_READ(sc, IWN_FH_INT);
3218 }
3219
3220 DPRINTF(sc, IWN_DEBUG_INTR, "interrupt reg1=%x reg2=%x\n", r1, r2);
3221
3222 if (r1 == 0 && r2 == 0)
3223 goto done; /* Interrupt not for us. */
3224
3225 /* Acknowledge interrupts. */
3226 IWN_WRITE(sc, IWN_INT, r1);
3227 if (!(sc->sc_flags & IWN_FLAG_USE_ICT))
3228 IWN_WRITE(sc, IWN_FH_INT, r2);
3229
3230 if (r1 & IWN_INT_RF_TOGGLED) {
3231 iwn_rftoggle_intr(sc);
3232 goto done;
3233 }
3234 if (r1 & IWN_INT_CT_REACHED) {
3235 device_printf(sc->sc_dev, "%s: critical temperature reached!\n",
3236 __func__);
3237 }
3238 if (r1 & (IWN_INT_SW_ERR | IWN_INT_HW_ERR)) {
3239 device_printf(sc->sc_dev, "%s: fatal firmware error\n",
3240 __func__);
3241 /* Dump firmware error log and stop. */
3242 iwn_fatal_intr(sc);
3243 ifp->if_flags &= ~IFF_UP;
3244 iwn_stop_locked(sc);
3245 goto done;
3246 }
3247 if ((r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX | IWN_INT_RX_PERIODIC)) ||
3248 (r2 & IWN_FH_INT_RX)) {
3249 if (sc->sc_flags & IWN_FLAG_USE_ICT) {
3250 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX))
3251 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_RX);
3252 IWN_WRITE_1(sc, IWN_INT_PERIODIC,
3253 IWN_INT_PERIODIC_DIS);
3254 iwn_notif_intr(sc);
3255 if (r1 & (IWN_INT_FH_RX | IWN_INT_SW_RX)) {
3256 IWN_WRITE_1(sc, IWN_INT_PERIODIC,
3257 IWN_INT_PERIODIC_ENA);
3258 }
3259 } else
3260 iwn_notif_intr(sc);
3261 }
3262
3263 if ((r1 & IWN_INT_FH_TX) || (r2 & IWN_FH_INT_TX)) {
3264 if (sc->sc_flags & IWN_FLAG_USE_ICT)
3265 IWN_WRITE(sc, IWN_FH_INT, IWN_FH_INT_TX);
3266 wakeup(sc); /* FH DMA transfer completed. */
3267 }
3268
3269 if (r1 & IWN_INT_ALIVE)
3270 wakeup(sc); /* Firmware is alive. */
3271
3272 if (r1 & IWN_INT_WAKEUP)
3273 iwn_wakeup_intr(sc);
3274
3275done:
3276 /* Re-enable interrupts. */
3277 if (ifp->if_flags & IFF_UP)
3278 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
3279
3280 IWN_UNLOCK(sc);
3281}
3282
3283/*
3284 * Update TX scheduler ring when transmitting an 802.11 frame (4965AGN and
3285 * 5000 adapters use a slightly different format).
3286 */
3287static void
3288iwn4965_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id,
3289 uint16_t len)
3290{
3291 uint16_t *w = &sc->sched[qid * IWN4965_SCHED_COUNT + idx];
3292
3293 *w = htole16(len + 8);
3294 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
3295 BUS_DMASYNC_PREWRITE);
3296 if (idx < IWN_SCHED_WINSZ) {
3297 *(w + IWN_TX_RING_COUNT) = *w;
3298 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
3299 BUS_DMASYNC_PREWRITE);
3300 }
3301}
3302
3303static void
3304iwn5000_update_sched(struct iwn_softc *sc, int qid, int idx, uint8_t id,
3305 uint16_t len)
3306{
3307 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx];
3308
3309 *w = htole16(id << 12 | (len + 8));
3310 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
3311 BUS_DMASYNC_PREWRITE);
3312 if (idx < IWN_SCHED_WINSZ) {
3313 *(w + IWN_TX_RING_COUNT) = *w;
3314 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
3315 BUS_DMASYNC_PREWRITE);
3316 }
3317}
3318
3319#ifdef notyet
3320static void
3321iwn5000_reset_sched(struct iwn_softc *sc, int qid, int idx)
3322{
3323 uint16_t *w = &sc->sched[qid * IWN5000_SCHED_COUNT + idx];
3324
3325 *w = (*w & htole16(0xf000)) | htole16(1);
3326 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
3327 BUS_DMASYNC_PREWRITE);
3328 if (idx < IWN_SCHED_WINSZ) {
3329 *(w + IWN_TX_RING_COUNT) = *w;
3330 bus_dmamap_sync(sc->sched_dma.tag, sc->sched_dma.map,
3331 BUS_DMASYNC_PREWRITE);
3332 }
3333}
3334#endif
3335
3336static int
3337iwn_tx_data(struct iwn_softc *sc, struct mbuf *m, struct ieee80211_node *ni)
3338{
3339 struct iwn_ops *ops = &sc->ops;
3340 const struct ieee80211_txparam *tp;
3341 struct ieee80211vap *vap = ni->ni_vap;
3342 struct ieee80211com *ic = ni->ni_ic;
3343 struct iwn_node *wn = (void *)ni;
3344 struct iwn_tx_ring *ring;
3345 struct iwn_tx_desc *desc;
3346 struct iwn_tx_data *data;
3347 struct iwn_tx_cmd *cmd;
3348 struct iwn_cmd_data *tx;
3349 struct ieee80211_frame *wh;
3350 struct ieee80211_key *k = NULL;
3351 struct mbuf *m1;
3352 uint32_t flags;
3353 uint16_t qos;
3354 u_int hdrlen;
3355 bus_dma_segment_t *seg, segs[IWN_MAX_SCATTER];
3356 uint8_t tid, ridx, txant, type;
3357 int ac, i, totlen, error, pad, nsegs = 0, rate;
3358
3359 IWN_LOCK_ASSERT(sc);
3360
3361 wh = mtod(m, struct ieee80211_frame *);
3362 hdrlen = ieee80211_anyhdrsize(wh);
3363 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
3364
3365 /* Select EDCA Access Category and TX ring for this frame. */
3366 if (IEEE80211_QOS_HAS_SEQ(wh)) {
3367 qos = ((const struct ieee80211_qosframe *)wh)->i_qos[0];
3368 tid = qos & IEEE80211_QOS_TID;
3369 } else {
3370 qos = 0;
3371 tid = 0;
3372 }
3373 ac = M_WME_GETAC(m);
3374 if (m->m_flags & M_AMPDU_MPDU) {
3375 struct ieee80211_tx_ampdu *tap = &ni->ni_tx_ampdu[ac];
3376
3377 if (!IEEE80211_AMPDU_RUNNING(tap)) {
3378 m_freem(m);
3379 return EINVAL;
3380 }
3381
3382 ac = *(int *)tap->txa_private;
3383 *(uint16_t *)wh->i_seq =
3384 htole16(ni->ni_txseqs[tid] << IEEE80211_SEQ_SEQ_SHIFT);
3385 ni->ni_txseqs[tid]++;
3386 }
3387 ring = &sc->txq[ac];
3388 desc = &ring->desc[ring->cur];
3389 data = &ring->data[ring->cur];
3390
3391 /* Choose a TX rate index. */
3392 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)];
3393 if (type == IEEE80211_FC0_TYPE_MGT)
3394 rate = tp->mgmtrate;
3395 else if (IEEE80211_IS_MULTICAST(wh->i_addr1))
3396 rate = tp->mcastrate;
3397 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE)
3398 rate = tp->ucastrate;
3399 else {
3400 /* XXX pass pktlen */
3401 (void) ieee80211_ratectl_rate(ni, NULL, 0);
3402 rate = ni->ni_txrate;
3403 }
3404 ridx = ic->ic_rt->rateCodeToIndex[rate];
3405
3406 /* Encrypt the frame if need be. */
3407 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
3408 /* Retrieve key for TX. */
3409 k = ieee80211_crypto_encap(ni, m);
3410 if (k == NULL) {
3411 m_freem(m);
3412 return ENOBUFS;
3413 }
3414 /* 802.11 header may have moved. */
3415 wh = mtod(m, struct ieee80211_frame *);
3416 }
3417 totlen = m->m_pkthdr.len;
3418
3419 if (ieee80211_radiotap_active_vap(vap)) {
3420 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap;
3421
3422 tap->wt_flags = 0;
3423 tap->wt_rate = rate;
3424 if (k != NULL)
3425 tap->wt_flags |= IEEE80211_RADIOTAP_F_WEP;
3426
3427 ieee80211_radiotap_tx(vap, m);
3428 }
3429
3430 /* Prepare TX firmware command. */
3431 cmd = &ring->cmd[ring->cur];
3432 cmd->code = IWN_CMD_TX_DATA;
3433 cmd->flags = 0;
3434 cmd->qid = ring->qid;
3435 cmd->idx = ring->cur;
3436
3437 tx = (struct iwn_cmd_data *)cmd->data;
3438 /* NB: No need to clear tx, all fields are reinitialized here. */
3439 tx->scratch = 0; /* clear "scratch" area */
3440
3441 flags = 0;
3442 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
3443 /* Unicast frame, check if an ACK is expected. */
3444 if (!qos || (qos & IEEE80211_QOS_ACKPOLICY) !=
3445 IEEE80211_QOS_ACKPOLICY_NOACK)
3446 flags |= IWN_TX_NEED_ACK;
3447 }
3448 if ((wh->i_fc[0] &
3449 (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) ==
3450 (IEEE80211_FC0_TYPE_CTL | IEEE80211_FC0_SUBTYPE_BAR))
3451 flags |= IWN_TX_IMM_BA; /* Cannot happen yet. */
3452
3453 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG)
3454 flags |= IWN_TX_MORE_FRAG; /* Cannot happen yet. */
3455
3456 /* Check if frame must be protected using RTS/CTS or CTS-to-self. */
3457 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) {
3458 /* NB: Group frames are sent using CCK in 802.11b/g. */
3459 if (totlen + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) {
3460 flags |= IWN_TX_NEED_RTS;
3461 } else if ((ic->ic_flags & IEEE80211_F_USEPROT) &&
3462 ridx >= IWN_RIDX_OFDM6) {
3463 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY)
3464 flags |= IWN_TX_NEED_CTS;
3465 else if (ic->ic_protmode == IEEE80211_PROT_RTSCTS)
3466 flags |= IWN_TX_NEED_RTS;
3467 }
3468 if (flags & (IWN_TX_NEED_RTS | IWN_TX_NEED_CTS)) {
3469 if (sc->hw_type != IWN_HW_REV_TYPE_4965) {
3470 /* 5000 autoselects RTS/CTS or CTS-to-self. */
3471 flags &= ~(IWN_TX_NEED_RTS | IWN_TX_NEED_CTS);
3472 flags |= IWN_TX_NEED_PROTECTION;
3473 } else
3474 flags |= IWN_TX_FULL_TXOP;
3475 }
3476 }
3477
3478 if (IEEE80211_IS_MULTICAST(wh->i_addr1) ||
3479 type != IEEE80211_FC0_TYPE_DATA)
3480 tx->id = sc->broadcast_id;
3481 else
3482 tx->id = wn->id;
3483
3484 if (type == IEEE80211_FC0_TYPE_MGT) {
3485 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
3486
3487 /* Tell HW to set timestamp in probe responses. */
3488 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)
3489 flags |= IWN_TX_INSERT_TSTAMP;
3490 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ ||
3491 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ)
3492 tx->timeout = htole16(3);
3493 else
3494 tx->timeout = htole16(2);
3495 } else
3496 tx->timeout = htole16(0);
3497
3498 if (hdrlen & 3) {
3499 /* First segment length must be a multiple of 4. */
3500 flags |= IWN_TX_NEED_PADDING;
3501 pad = 4 - (hdrlen & 3);
3502 } else
3503 pad = 0;
3504
3505 tx->len = htole16(totlen);
3506 tx->tid = tid;
3507 tx->rts_ntries = 60;
3508 tx->data_ntries = 15;
3509 tx->lifetime = htole32(IWN_LIFETIME_INFINITE);
3510 tx->rate = wn->ridx[rate];
3511 if (tx->id == sc->broadcast_id) {
3512 /* Group or management frame. */
3513 tx->linkq = 0;
3514 /* XXX Alternate between antenna A and B? */
3515 txant = IWN_LSB(sc->txchainmask);
3516 tx->rate |= htole32(IWN_RFLAG_ANT(txant));
3517 } else {
3518 tx->linkq = ni->ni_rates.rs_nrates - ridx - 1;
3519 flags |= IWN_TX_LINKQ; /* enable MRR */
3520 }
3521 /* Set physical address of "scratch area". */
3522 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr));
3523 tx->hiaddr = IWN_HIADDR(data->scratch_paddr);
3524
3525 /* Copy 802.11 header in TX command. */
3526 memcpy((uint8_t *)(tx + 1), wh, hdrlen);
3527
3528 /* Trim 802.11 header. */
3529 m_adj(m, hdrlen);
3530 tx->security = 0;
3531 tx->flags = htole32(flags);
3532
3533 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, segs,
3534 &nsegs, BUS_DMA_NOWAIT);
3535 if (error != 0) {
3536 if (error != EFBIG) {
3537 device_printf(sc->sc_dev,
3538 "%s: can't map mbuf (error %d)\n", __func__, error);
3539 m_freem(m);
3540 return error;
3541 }
3542 /* Too many DMA segments, linearize mbuf. */
3543 m1 = m_collapse(m, M_NOWAIT, IWN_MAX_SCATTER);
3544 if (m1 == NULL) {
3545 device_printf(sc->sc_dev,
3546 "%s: could not defrag mbuf\n", __func__);
3547 m_freem(m);
3548 return ENOBUFS;
3549 }
3550 m = m1;
3551
3552 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m,
3553 segs, &nsegs, BUS_DMA_NOWAIT);
3554 if (error != 0) {
3555 device_printf(sc->sc_dev,
3556 "%s: can't map mbuf (error %d)\n", __func__, error);
3557 m_freem(m);
3558 return error;
3559 }
3560 }
3561
3562 data->m = m;
3563 data->ni = ni;
3564
3565 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: qid %d idx %d len %d nsegs %d\n",
3566 __func__, ring->qid, ring->cur, m->m_pkthdr.len, nsegs);
3567
3568 /* Fill TX descriptor. */
3569 desc->nsegs = 1;
3570 if (m->m_len != 0)
3571 desc->nsegs += nsegs;
3572 /* First DMA segment is used by the TX command. */
3573 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr));
3574 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) |
3575 (4 + sizeof (*tx) + hdrlen + pad) << 4);
3576 /* Other DMA segments are for data payload. */
3577 seg = &segs[0];
3578 for (i = 1; i <= nsegs; i++) {
3579 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr));
3580 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) |
3581 seg->ds_len << 4);
3582 seg++;
3583 }
3584
3585 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE);
3586 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map,
3587 BUS_DMASYNC_PREWRITE);
3588 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
3589 BUS_DMASYNC_PREWRITE);
3590
3591 /* Update TX scheduler. */
3592 if (ring->qid >= sc->firstaggqueue)
3593 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen);
3594
3595 /* Kick TX ring. */
3596 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT;
3597 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
3598
3599 /* Mark TX ring as full if we reach a certain threshold. */
3600 if (++ring->queued > IWN_TX_RING_HIMARK)
3601 sc->qfullmsk |= 1 << ring->qid;
3602
3603 return 0;
3604}
3605
3606static int
3607iwn_tx_data_raw(struct iwn_softc *sc, struct mbuf *m,
3608 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params)
3609{
3610 struct iwn_ops *ops = &sc->ops;
3611 struct ifnet *ifp = sc->sc_ifp;
3612 struct ieee80211vap *vap = ni->ni_vap;
3613 struct ieee80211com *ic = ifp->if_l2com;
3614 struct iwn_tx_cmd *cmd;
3615 struct iwn_cmd_data *tx;
3616 struct ieee80211_frame *wh;
3617 struct iwn_tx_ring *ring;
3618 struct iwn_tx_desc *desc;
3619 struct iwn_tx_data *data;
3620 struct mbuf *m1;
3621 bus_dma_segment_t *seg, segs[IWN_MAX_SCATTER];
3622 uint32_t flags;
3623 u_int hdrlen;
3624 int ac, totlen, error, pad, nsegs = 0, i, rate;
3625 uint8_t ridx, type, txant;
3626
3627 IWN_LOCK_ASSERT(sc);
3628
3629 wh = mtod(m, struct ieee80211_frame *);
3630 hdrlen = ieee80211_anyhdrsize(wh);
3631 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
3632
3633 ac = params->ibp_pri & 3;
3634
3635 ring = &sc->txq[ac];
3636 desc = &ring->desc[ring->cur];
3637 data = &ring->data[ring->cur];
3638
3639 /* Choose a TX rate index. */
3640 rate = params->ibp_rate0;
3641 ridx = ic->ic_rt->rateCodeToIndex[rate];
3642 if (ridx == (uint8_t)-1) {
3643 /* XXX fall back to mcast/mgmt rate? */
3644 m_freem(m);
3645 return EINVAL;
3646 }
3647
3648 totlen = m->m_pkthdr.len;
3649
3650 /* Prepare TX firmware command. */
3651 cmd = &ring->cmd[ring->cur];
3652 cmd->code = IWN_CMD_TX_DATA;
3653 cmd->flags = 0;
3654 cmd->qid = ring->qid;
3655 cmd->idx = ring->cur;
3656
3657 tx = (struct iwn_cmd_data *)cmd->data;
3658 /* NB: No need to clear tx, all fields are reinitialized here. */
3659 tx->scratch = 0; /* clear "scratch" area */
3660
3661 flags = 0;
3662 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0)
3663 flags |= IWN_TX_NEED_ACK;
3664 if (params->ibp_flags & IEEE80211_BPF_RTS) {
3665 if (sc->hw_type != IWN_HW_REV_TYPE_4965) {
3666 /* 5000 autoselects RTS/CTS or CTS-to-self. */
3667 flags &= ~IWN_TX_NEED_RTS;
3668 flags |= IWN_TX_NEED_PROTECTION;
3669 } else
3670 flags |= IWN_TX_NEED_RTS | IWN_TX_FULL_TXOP;
3671 }
3672 if (params->ibp_flags & IEEE80211_BPF_CTS) {
3673 if (sc->hw_type != IWN_HW_REV_TYPE_4965) {
3674 /* 5000 autoselects RTS/CTS or CTS-to-self. */
3675 flags &= ~IWN_TX_NEED_CTS;
3676 flags |= IWN_TX_NEED_PROTECTION;
3677 } else
3678 flags |= IWN_TX_NEED_CTS | IWN_TX_FULL_TXOP;
3679 }
3680 if (type == IEEE80211_FC0_TYPE_MGT) {
3681 uint8_t subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
3682
3683 /* Tell HW to set timestamp in probe responses. */
3684 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)
3685 flags |= IWN_TX_INSERT_TSTAMP;
3686
3687 if (subtype == IEEE80211_FC0_SUBTYPE_ASSOC_REQ ||
3688 subtype == IEEE80211_FC0_SUBTYPE_REASSOC_REQ)
3689 tx->timeout = htole16(3);
3690 else
3691 tx->timeout = htole16(2);
3692 } else
3693 tx->timeout = htole16(0);
3694
3695 if (hdrlen & 3) {
3696 /* First segment length must be a multiple of 4. */
3697 flags |= IWN_TX_NEED_PADDING;
3698 pad = 4 - (hdrlen & 3);
3699 } else
3700 pad = 0;
3701
3702 if (ieee80211_radiotap_active_vap(vap)) {
3703 struct iwn_tx_radiotap_header *tap = &sc->sc_txtap;
3704
3705 tap->wt_flags = 0;
3706 tap->wt_rate = rate;
3707
3708 ieee80211_radiotap_tx(vap, m);
3709 }
3710
3711 tx->len = htole16(totlen);
3712 tx->tid = 0;
3713 tx->id = sc->broadcast_id;
3714 tx->rts_ntries = params->ibp_try1;
3715 tx->data_ntries = params->ibp_try0;
3716 tx->lifetime = htole32(IWN_LIFETIME_INFINITE);
3717 tx->rate = htole32(rate2plcp(rate));
3718 if (ridx < IWN_RIDX_OFDM6 &&
3719 IEEE80211_IS_CHAN_2GHZ(ni->ni_chan))
3720 tx->rate |= htole32(IWN_RFLAG_CCK);
3721 /* Group or management frame. */
3722 tx->linkq = 0;
3723 txant = IWN_LSB(sc->txchainmask);
3724 tx->rate |= htole32(IWN_RFLAG_ANT(txant));
3725 /* Set physical address of "scratch area". */
3726 tx->loaddr = htole32(IWN_LOADDR(data->scratch_paddr));
3727 tx->hiaddr = IWN_HIADDR(data->scratch_paddr);
3728
3729 /* Copy 802.11 header in TX command. */
3730 memcpy((uint8_t *)(tx + 1), wh, hdrlen);
3731
3732 /* Trim 802.11 header. */
3733 m_adj(m, hdrlen);
3734 tx->security = 0;
3735 tx->flags = htole32(flags);
3736
3737 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m, segs,
3738 &nsegs, BUS_DMA_NOWAIT);
3739 if (error != 0) {
3740 if (error != EFBIG) {
3741 device_printf(sc->sc_dev,
3742 "%s: can't map mbuf (error %d)\n", __func__, error);
3743 m_freem(m);
3744 return error;
3745 }
3746 /* Too many DMA segments, linearize mbuf. */
3747 m1 = m_collapse(m, M_NOWAIT, IWN_MAX_SCATTER);
3748 if (m1 == NULL) {
3749 device_printf(sc->sc_dev,
3750 "%s: could not defrag mbuf\n", __func__);
3751 m_freem(m);
3752 return ENOBUFS;
3753 }
3754 m = m1;
3755
3756 error = bus_dmamap_load_mbuf_sg(ring->data_dmat, data->map, m,
3757 segs, &nsegs, BUS_DMA_NOWAIT);
3758 if (error != 0) {
3759 device_printf(sc->sc_dev,
3760 "%s: can't map mbuf (error %d)\n", __func__, error);
3761 m_freem(m);
3762 return error;
3763 }
3764 }
3765
3766 data->m = m;
3767 data->ni = ni;
3768
3769 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: qid %d idx %d len %d nsegs %d\n",
3770 __func__, ring->qid, ring->cur, m->m_pkthdr.len, nsegs);
3771
3772 /* Fill TX descriptor. */
3773 desc->nsegs = 1;
3774 if (m->m_len != 0)
3775 desc->nsegs += nsegs;
3776 /* First DMA segment is used by the TX command. */
3777 desc->segs[0].addr = htole32(IWN_LOADDR(data->cmd_paddr));
3778 desc->segs[0].len = htole16(IWN_HIADDR(data->cmd_paddr) |
3779 (4 + sizeof (*tx) + hdrlen + pad) << 4);
3780 /* Other DMA segments are for data payload. */
3781 seg = &segs[0];
3782 for (i = 1; i <= nsegs; i++) {
3783 desc->segs[i].addr = htole32(IWN_LOADDR(seg->ds_addr));
3784 desc->segs[i].len = htole16(IWN_HIADDR(seg->ds_addr) |
3785 seg->ds_len << 4);
3786 seg++;
3787 }
3788
3789 bus_dmamap_sync(ring->data_dmat, data->map, BUS_DMASYNC_PREWRITE);
3790 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map,
3791 BUS_DMASYNC_PREWRITE);
3792 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
3793 BUS_DMASYNC_PREWRITE);
3794
3795 /* Update TX scheduler. */
3796 if (ring->qid >= sc->firstaggqueue)
3797 ops->update_sched(sc, ring->qid, ring->cur, tx->id, totlen);
3798
3799 /* Kick TX ring. */
3800 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT;
3801 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
3802
3803 /* Mark TX ring as full if we reach a certain threshold. */
3804 if (++ring->queued > IWN_TX_RING_HIMARK)
3805 sc->qfullmsk |= 1 << ring->qid;
3806
3807 return 0;
3808}
3809
3810static int
3811iwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
3812 const struct ieee80211_bpf_params *params)
3813{
3814 struct ieee80211com *ic = ni->ni_ic;
3815 struct ifnet *ifp = ic->ic_ifp;
3816 struct iwn_softc *sc = ifp->if_softc;
3817 int error = 0;
3818
3819 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
3820 ieee80211_free_node(ni);
3821 m_freem(m);
3822 return ENETDOWN;
3823 }
3824
3825 IWN_LOCK(sc);
3826 if (params == NULL) {
3827 /*
3828 * Legacy path; interpret frame contents to decide
3829 * precisely how to send the frame.
3830 */
3831 error = iwn_tx_data(sc, m, ni);
3832 } else {
3833 /*
3834 * Caller supplied explicit parameters to use in
3835 * sending the frame.
3836 */
3837 error = iwn_tx_data_raw(sc, m, ni, params);
3838 }
3839 if (error != 0) {
3840 /* NB: m is reclaimed on tx failure */
3841 ieee80211_free_node(ni);
3842 ifp->if_oerrors++;
3843 }
3844 sc->sc_tx_timer = 5;
3845
3846 IWN_UNLOCK(sc);
3847 return error;
3848}
3849
3850static void
3851iwn_start(struct ifnet *ifp)
3852{
3853 struct iwn_softc *sc = ifp->if_softc;
3854
3855 IWN_LOCK(sc);
3856 iwn_start_locked(ifp);
3857 IWN_UNLOCK(sc);
3858}
3859
3860static void
3861iwn_start_locked(struct ifnet *ifp)
3862{
3863 struct iwn_softc *sc = ifp->if_softc;
3864 struct ieee80211_node *ni;
3865 struct mbuf *m;
3866
3867 IWN_LOCK_ASSERT(sc);
3868
3869 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 ||
3870 (ifp->if_drv_flags & IFF_DRV_OACTIVE))
3871 return;
3872
3873 for (;;) {
3874 if (sc->qfullmsk != 0) {
3875 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3876 break;
3877 }
3878 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
3879 if (m == NULL)
3880 break;
3881 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
3882 if (iwn_tx_data(sc, m, ni) != 0) {
3883 ieee80211_free_node(ni);
3884 ifp->if_oerrors++;
3885 continue;
3886 }
3887 sc->sc_tx_timer = 5;
3888 }
3889}
3890
3891static void
3892iwn_watchdog(void *arg)
3893{
3894 struct iwn_softc *sc = arg;
3895 struct ifnet *ifp = sc->sc_ifp;
3896 struct ieee80211com *ic = ifp->if_l2com;
3897
3898 IWN_LOCK_ASSERT(sc);
3899
3900 KASSERT(ifp->if_drv_flags & IFF_DRV_RUNNING, ("not running"));
3901
3902 if (sc->sc_tx_timer > 0) {
3903 if (--sc->sc_tx_timer == 0) {
3904 if_printf(ifp, "device timeout\n");
3905 ieee80211_runtask(ic, &sc->sc_reinit_task);
3906 return;
3907 }
3908 }
3909 callout_reset(&sc->watchdog_to, hz, iwn_watchdog, sc);
3910}
3911
3912static int
3913iwn_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
3914{
3915 struct iwn_softc *sc = ifp->if_softc;
3916 struct ieee80211com *ic = ifp->if_l2com;
3917 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
3918 struct ifreq *ifr = (struct ifreq *) data;
3919 int error = 0, startall = 0, stop = 0;
3920
3921 switch (cmd) {
3922 case SIOCGIFADDR:
3923 error = ether_ioctl(ifp, cmd, data);
3924 break;
3925 case SIOCSIFFLAGS:
3926 IWN_LOCK(sc);
3927 if (ifp->if_flags & IFF_UP) {
3928 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3929 iwn_init_locked(sc);
3930 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)
3931 startall = 1;
3932 else
3933 stop = 1;
3934 }
3935 } else {
3936 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3937 iwn_stop_locked(sc);
3938 }
3939 IWN_UNLOCK(sc);
3940 if (startall)
3941 ieee80211_start_all(ic);
3942 else if (vap != NULL && stop)
3943 ieee80211_stop(vap);
3944 break;
3945 case SIOCGIFMEDIA:
3946 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd);
3947 break;
3948 default:
3949 error = EINVAL;
3950 break;
3951 }
3952 return error;
3953}
3954
3955/*
3956 * Send a command to the firmware.
3957 */
3958static int
3959iwn_cmd(struct iwn_softc *sc, int code, const void *buf, int size, int async)
3960{
3961 struct iwn_tx_ring *ring = &sc->txq[4];
3962 struct iwn_tx_desc *desc;
3963 struct iwn_tx_data *data;
3964 struct iwn_tx_cmd *cmd;
3965 struct mbuf *m;
3966 bus_addr_t paddr;
3967 int totlen, error;
3968
3969 if (async == 0)
3970 IWN_LOCK_ASSERT(sc);
3971
3972 desc = &ring->desc[ring->cur];
3973 data = &ring->data[ring->cur];
3974 totlen = 4 + size;
3975
3976 if (size > sizeof cmd->data) {
3977 /* Command is too large to fit in a descriptor. */
3978 if (totlen > MCLBYTES)
3979 return EINVAL;
3980 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUMPAGESIZE);
3981 if (m == NULL)
3982 return ENOMEM;
3983 cmd = mtod(m, struct iwn_tx_cmd *);
3984 error = bus_dmamap_load(ring->data_dmat, data->map, cmd,
3985 totlen, iwn_dma_map_addr, &paddr, BUS_DMA_NOWAIT);
3986 if (error != 0) {
3987 m_freem(m);
3988 return error;
3989 }
3990 data->m = m;
3991 } else {
3992 cmd = &ring->cmd[ring->cur];
3993 paddr = data->cmd_paddr;
3994 }
3995
3996 cmd->code = code;
3997 cmd->flags = 0;
3998 cmd->qid = ring->qid;
3999 cmd->idx = ring->cur;
4000 memcpy(cmd->data, buf, size);
4001
4002 desc->nsegs = 1;
4003 desc->segs[0].addr = htole32(IWN_LOADDR(paddr));
4004 desc->segs[0].len = htole16(IWN_HIADDR(paddr) | totlen << 4);
4005
4006 DPRINTF(sc, IWN_DEBUG_CMD, "%s: %s (0x%x) flags %d qid %d idx %d\n",
4007 __func__, iwn_intr_str(cmd->code), cmd->code,
4008 cmd->flags, cmd->qid, cmd->idx);
4009
4010 if (size > sizeof cmd->data) {
4011 bus_dmamap_sync(ring->data_dmat, data->map,
4012 BUS_DMASYNC_PREWRITE);
4013 } else {
4014 bus_dmamap_sync(ring->data_dmat, ring->cmd_dma.map,
4015 BUS_DMASYNC_PREWRITE);
4016 }
4017 bus_dmamap_sync(ring->desc_dma.tag, ring->desc_dma.map,
4018 BUS_DMASYNC_PREWRITE);
4019
4020 /* Kick command ring. */
4021 ring->cur = (ring->cur + 1) % IWN_TX_RING_COUNT;
4022 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, ring->qid << 8 | ring->cur);
4023
4024 return async ? 0 : msleep(desc, &sc->sc_mtx, PCATCH, "iwncmd", hz);
4025}
4026
4027static int
4028iwn4965_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async)
4029{
4030 struct iwn4965_node_info hnode;
4031 caddr_t src, dst;
4032
4033 /*
4034 * We use the node structure for 5000 Series internally (it is
4035 * a superset of the one for 4965AGN). We thus copy the common
4036 * fields before sending the command.
4037 */
4038 src = (caddr_t)node;
4039 dst = (caddr_t)&hnode;
4040 memcpy(dst, src, 48);
4041 /* Skip TSC, RX MIC and TX MIC fields from ``src''. */
4042 memcpy(dst + 48, src + 72, 20);
4043 return iwn_cmd(sc, IWN_CMD_ADD_NODE, &hnode, sizeof hnode, async);
4044}
4045
4046static int
4047iwn5000_add_node(struct iwn_softc *sc, struct iwn_node_info *node, int async)
4048{
4049 /* Direct mapping. */
4050 return iwn_cmd(sc, IWN_CMD_ADD_NODE, node, sizeof (*node), async);
4051}
4052
4053static int
4054iwn_set_link_quality(struct iwn_softc *sc, struct ieee80211_node *ni)
4055{
4056#define RV(v) ((v) & IEEE80211_RATE_VAL)
4057 struct iwn_node *wn = (void *)ni;
4058 struct ieee80211_rateset *rs = &ni->ni_rates;
4059 struct iwn_cmd_link_quality linkq;
4060 uint8_t txant;
4061 int i, rate, txrate;
4062
4063 /* Use the first valid TX antenna. */
4064 txant = IWN_LSB(sc->txchainmask);
4065
4066 memset(&linkq, 0, sizeof linkq);
4067 linkq.id = wn->id;
4068 linkq.antmsk_1stream = txant;
4069 linkq.antmsk_2stream = IWN_ANT_AB;
4070 linkq.ampdu_max = 64;
4071 linkq.ampdu_threshold = 3;
4072 linkq.ampdu_limit = htole16(4000); /* 4ms */
4073
4074 /* Start at highest available bit-rate. */
4075 if (IEEE80211_IS_CHAN_HT(ni->ni_chan))
4076 txrate = ni->ni_htrates.rs_nrates - 1;
4077 else
4078 txrate = rs->rs_nrates - 1;
4079 for (i = 0; i < IWN_MAX_TX_RETRIES; i++) {
4080 if (IEEE80211_IS_CHAN_HT(ni->ni_chan))
4081 rate = IEEE80211_RATE_MCS | txrate;
4082 else
4083 rate = RV(rs->rs_rates[txrate]);
4084 linkq.retry[i] = wn->ridx[rate];
4085
4086 if ((le32toh(wn->ridx[rate]) & IWN_RFLAG_MCS) &&
4087 RV(le32toh(wn->ridx[rate])) > 7)
4088 linkq.mimo = i + 1;
4089
4090 /* Next retry at immediate lower bit-rate. */
4091 if (txrate > 0)
4092 txrate--;
4093 }
4094 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, 1);
4095#undef RV
4096}
4097
4098/*
4099 * Broadcast node is used to send group-addressed and management frames.
4100 */
4101static int
4102iwn_add_broadcast_node(struct iwn_softc *sc, int async)
4103{
4104 struct iwn_ops *ops = &sc->ops;
4105 struct ifnet *ifp = sc->sc_ifp;
4106 struct ieee80211com *ic = ifp->if_l2com;
4107 struct iwn_node_info node;
4108 struct iwn_cmd_link_quality linkq;
4109 uint8_t txant;
4110 int i, error;
4111
4112 memset(&node, 0, sizeof node);
4113 IEEE80211_ADDR_COPY(node.macaddr, ifp->if_broadcastaddr);
4114 node.id = sc->broadcast_id;
4115 DPRINTF(sc, IWN_DEBUG_RESET, "%s: adding broadcast node\n", __func__);
4116 if ((error = ops->add_node(sc, &node, async)) != 0)
4117 return error;
4118
4119 /* Use the first valid TX antenna. */
4120 txant = IWN_LSB(sc->txchainmask);
4121
4122 memset(&linkq, 0, sizeof linkq);
4123 linkq.id = sc->broadcast_id;
4124 linkq.antmsk_1stream = txant;
4125 linkq.antmsk_2stream = IWN_ANT_AB;
4126 linkq.ampdu_max = 64;
4127 linkq.ampdu_threshold = 3;
4128 linkq.ampdu_limit = htole16(4000); /* 4ms */
4129
4130 /* Use lowest mandatory bit-rate. */
4131 if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan))
4132 linkq.retry[0] = htole32(0xd);
4133 else
4134 linkq.retry[0] = htole32(10 | IWN_RFLAG_CCK);
4135 linkq.retry[0] |= htole32(IWN_RFLAG_ANT(txant));
4136 /* Use same bit-rate for all TX retries. */
4137 for (i = 1; i < IWN_MAX_TX_RETRIES; i++) {
4138 linkq.retry[i] = linkq.retry[0];
4139 }
4140 return iwn_cmd(sc, IWN_CMD_LINK_QUALITY, &linkq, sizeof linkq, async);
4141}
4142
4143static int
4144iwn_updateedca(struct ieee80211com *ic)
4145{
4146#define IWN_EXP2(x) ((1 << (x)) - 1) /* CWmin = 2^ECWmin - 1 */
4147 struct iwn_softc *sc = ic->ic_ifp->if_softc;
4148 struct iwn_edca_params cmd;
4149 int aci;
4150
4151 memset(&cmd, 0, sizeof cmd);
4152 cmd.flags = htole32(IWN_EDCA_UPDATE);
4153 for (aci = 0; aci < WME_NUM_AC; aci++) {
4154 const struct wmeParams *ac =
4155 &ic->ic_wme.wme_chanParams.cap_wmeParams[aci];
4156 cmd.ac[aci].aifsn = ac->wmep_aifsn;
4157 cmd.ac[aci].cwmin = htole16(IWN_EXP2(ac->wmep_logcwmin));
4158 cmd.ac[aci].cwmax = htole16(IWN_EXP2(ac->wmep_logcwmax));
4159 cmd.ac[aci].txoplimit =
4160 htole16(IEEE80211_TXOP_TO_US(ac->wmep_txopLimit));
4161 }
4162 IEEE80211_UNLOCK(ic);
4163 IWN_LOCK(sc);
4164 (void)iwn_cmd(sc, IWN_CMD_EDCA_PARAMS, &cmd, sizeof cmd, 1);
4165 IWN_UNLOCK(sc);
4166 IEEE80211_LOCK(ic);
4167 return 0;
4168#undef IWN_EXP2
4169}
4170
4171static void
4172iwn_update_mcast(struct ifnet *ifp)
4173{
4174 /* Ignore */
4175}
4176
4177static void
4178iwn_set_led(struct iwn_softc *sc, uint8_t which, uint8_t off, uint8_t on)
4179{
4180 struct iwn_cmd_led led;
4181
4182 /* Clear microcode LED ownership. */
4183 IWN_CLRBITS(sc, IWN_LED, IWN_LED_BSM_CTRL);
4184
4185 led.which = which;
4186 led.unit = htole32(10000); /* on/off in unit of 100ms */
4187 led.off = off;
4188 led.on = on;
4189 (void)iwn_cmd(sc, IWN_CMD_SET_LED, &led, sizeof led, 1);
4190}
4191
4192/*
4193 * Set the critical temperature at which the firmware will stop the radio
4194 * and notify us.
4195 */
4196static int
4197iwn_set_critical_temp(struct iwn_softc *sc)
4198{
4199 struct iwn_critical_temp crit;
4200 int32_t temp;
4201
4202 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CTEMP_STOP_RF);
4203
4204 if (sc->hw_type == IWN_HW_REV_TYPE_5150)
4205 temp = (IWN_CTOK(110) - sc->temp_off) * -5;
4206 else if (sc->hw_type == IWN_HW_REV_TYPE_4965)
4207 temp = IWN_CTOK(110);
4208 else
4209 temp = 110;
4210 memset(&crit, 0, sizeof crit);
4211 crit.tempR = htole32(temp);
4212 DPRINTF(sc, IWN_DEBUG_RESET, "setting critical temp to %d\n", temp);
4213 return iwn_cmd(sc, IWN_CMD_SET_CRITICAL_TEMP, &crit, sizeof crit, 0);
4214}
4215
4216static int
4217iwn_set_timing(struct iwn_softc *sc, struct ieee80211_node *ni)
4218{
4219 struct iwn_cmd_timing cmd;
4220 uint64_t val, mod;
4221
4222 memset(&cmd, 0, sizeof cmd);
4223 memcpy(&cmd.tstamp, ni->ni_tstamp.data, sizeof (uint64_t));
4224 cmd.bintval = htole16(ni->ni_intval);
4225 cmd.lintval = htole16(10);
4226
4227 /* Compute remaining time until next beacon. */
4228 val = (uint64_t)ni->ni_intval * IEEE80211_DUR_TU;
4229 mod = le64toh(cmd.tstamp) % val;
4230 cmd.binitval = htole32((uint32_t)(val - mod));
4231
4232 DPRINTF(sc, IWN_DEBUG_RESET, "timing bintval=%u tstamp=%ju, init=%u\n",
4233 ni->ni_intval, le64toh(cmd.tstamp), (uint32_t)(val - mod));
4234
4235 return iwn_cmd(sc, IWN_CMD_TIMING, &cmd, sizeof cmd, 1);
4236}
4237
4238static void
4239iwn4965_power_calibration(struct iwn_softc *sc, int temp)
4240{
4241 struct ifnet *ifp = sc->sc_ifp;
4242 struct ieee80211com *ic = ifp->if_l2com;
4243
4244 /* Adjust TX power if need be (delta >= 3 degC). */
4245 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d->%d\n",
4246 __func__, sc->temp, temp);
4247 if (abs(temp - sc->temp) >= 3) {
4248 /* Record temperature of last calibration. */
4249 sc->temp = temp;
4250 (void)iwn4965_set_txpower(sc, ic->ic_bsschan, 1);
4251 }
4252}
4253
4254/*
4255 * Set TX power for current channel (each rate has its own power settings).
4256 * This function takes into account the regulatory information from EEPROM,
4257 * the current temperature and the current voltage.
4258 */
4259static int
4260iwn4965_set_txpower(struct iwn_softc *sc, struct ieee80211_channel *ch,
4261 int async)
4262{
4263/* Fixed-point arithmetic division using a n-bit fractional part. */
4264#define fdivround(a, b, n) \
4265 ((((1 << n) * (a)) / (b) + (1 << n) / 2) / (1 << n))
4266/* Linear interpolation. */
4267#define interpolate(x, x1, y1, x2, y2, n) \
4268 ((y1) + fdivround(((int)(x) - (x1)) * ((y2) - (y1)), (x2) - (x1), n))
4269
4270 static const int tdiv[IWN_NATTEN_GROUPS] = { 9, 8, 8, 8, 6 };
4271 struct iwn_ucode_info *uc = &sc->ucode_info;
4272 struct iwn4965_cmd_txpower cmd;
4273 struct iwn4965_eeprom_chan_samples *chans;
4274 const uint8_t *rf_gain, *dsp_gain;
4275 int32_t vdiff, tdiff;
4276 int i, c, grp, maxpwr;
4277 uint8_t chan;
4278
4279 /* Retrieve current channel from last RXON. */
4280 chan = sc->rxon.chan;
4281 DPRINTF(sc, IWN_DEBUG_RESET, "setting TX power for channel %d\n",
4282 chan);
4283
4284 memset(&cmd, 0, sizeof cmd);
4285 cmd.band = IEEE80211_IS_CHAN_5GHZ(ch) ? 0 : 1;
4286 cmd.chan = chan;
4287
4288 if (IEEE80211_IS_CHAN_5GHZ(ch)) {
4289 maxpwr = sc->maxpwr5GHz;
4290 rf_gain = iwn4965_rf_gain_5ghz;
4291 dsp_gain = iwn4965_dsp_gain_5ghz;
4292 } else {
4293 maxpwr = sc->maxpwr2GHz;
4294 rf_gain = iwn4965_rf_gain_2ghz;
4295 dsp_gain = iwn4965_dsp_gain_2ghz;
4296 }
4297
4298 /* Compute voltage compensation. */
4299 vdiff = ((int32_t)le32toh(uc->volt) - sc->eeprom_voltage) / 7;
4300 if (vdiff > 0)
4301 vdiff *= 2;
4302 if (abs(vdiff) > 2)
4303 vdiff = 0;
4304 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
4305 "%s: voltage compensation=%d (UCODE=%d, EEPROM=%d)\n",
4306 __func__, vdiff, le32toh(uc->volt), sc->eeprom_voltage);
4307
4308 /* Get channel attenuation group. */
4309 if (chan <= 20) /* 1-20 */
4310 grp = 4;
4311 else if (chan <= 43) /* 34-43 */
4312 grp = 0;
4313 else if (chan <= 70) /* 44-70 */
4314 grp = 1;
4315 else if (chan <= 124) /* 71-124 */
4316 grp = 2;
4317 else /* 125-200 */
4318 grp = 3;
4319 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
4320 "%s: chan %d, attenuation group=%d\n", __func__, chan, grp);
4321
4322 /* Get channel sub-band. */
4323 for (i = 0; i < IWN_NBANDS; i++)
4324 if (sc->bands[i].lo != 0 &&
4325 sc->bands[i].lo <= chan && chan <= sc->bands[i].hi)
4326 break;
4327 if (i == IWN_NBANDS) /* Can't happen in real-life. */
4328 return EINVAL;
4329 chans = sc->bands[i].chans;
4330 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
4331 "%s: chan %d sub-band=%d\n", __func__, chan, i);
4332
4333 for (c = 0; c < 2; c++) {
4334 uint8_t power, gain, temp;
4335 int maxchpwr, pwr, ridx, idx;
4336
4337 power = interpolate(chan,
4338 chans[0].num, chans[0].samples[c][1].power,
4339 chans[1].num, chans[1].samples[c][1].power, 1);
4340 gain = interpolate(chan,
4341 chans[0].num, chans[0].samples[c][1].gain,
4342 chans[1].num, chans[1].samples[c][1].gain, 1);
4343 temp = interpolate(chan,
4344 chans[0].num, chans[0].samples[c][1].temp,
4345 chans[1].num, chans[1].samples[c][1].temp, 1);
4346 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
4347 "%s: Tx chain %d: power=%d gain=%d temp=%d\n",
4348 __func__, c, power, gain, temp);
4349
4350 /* Compute temperature compensation. */
4351 tdiff = ((sc->temp - temp) * 2) / tdiv[grp];
4352 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
4353 "%s: temperature compensation=%d (current=%d, EEPROM=%d)\n",
4354 __func__, tdiff, sc->temp, temp);
4355
4356 for (ridx = 0; ridx <= IWN_RIDX_MAX; ridx++) {
4357 /* Convert dBm to half-dBm. */
4358 maxchpwr = sc->maxpwr[chan] * 2;
4359 if ((ridx / 8) & 1)
4360 maxchpwr -= 6; /* MIMO 2T: -3dB */
4361
4362 pwr = maxpwr;
4363
4364 /* Adjust TX power based on rate. */
4365 if ((ridx % 8) == 5)
4366 pwr -= 15; /* OFDM48: -7.5dB */
4367 else if ((ridx % 8) == 6)
4368 pwr -= 17; /* OFDM54: -8.5dB */
4369 else if ((ridx % 8) == 7)
4370 pwr -= 20; /* OFDM60: -10dB */
4371 else
4372 pwr -= 10; /* Others: -5dB */
4373
4374 /* Do not exceed channel max TX power. */
4375 if (pwr > maxchpwr)
4376 pwr = maxchpwr;
4377
4378 idx = gain - (pwr - power) - tdiff - vdiff;
4379 if ((ridx / 8) & 1) /* MIMO */
4380 idx += (int32_t)le32toh(uc->atten[grp][c]);
4381
4382 if (cmd.band == 0)
4383 idx += 9; /* 5GHz */
4384 if (ridx == IWN_RIDX_MAX)
4385 idx += 5; /* CCK */
4386
4387 /* Make sure idx stays in a valid range. */
4388 if (idx < 0)
4389 idx = 0;
4390 else if (idx > IWN4965_MAX_PWR_INDEX)
4391 idx = IWN4965_MAX_PWR_INDEX;
4392
4393 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
4394 "%s: Tx chain %d, rate idx %d: power=%d\n",
4395 __func__, c, ridx, idx);
4396 cmd.power[ridx].rf_gain[c] = rf_gain[idx];
4397 cmd.power[ridx].dsp_gain[c] = dsp_gain[idx];
4398 }
4399 }
4400
4401 DPRINTF(sc, IWN_DEBUG_CALIBRATE | IWN_DEBUG_TXPOW,
4402 "%s: set tx power for chan %d\n", __func__, chan);
4403 return iwn_cmd(sc, IWN_CMD_TXPOWER, &cmd, sizeof cmd, async);
4404
4405#undef interpolate
4406#undef fdivround
4407}
4408
4409static int
4410iwn5000_set_txpower(struct iwn_softc *sc, struct ieee80211_channel *ch,
4411 int async)
4412{
4413 struct iwn5000_cmd_txpower cmd;
4414
4415 /*
4416 * TX power calibration is handled automatically by the firmware
4417 * for 5000 Series.
4418 */
4419 memset(&cmd, 0, sizeof cmd);
4420 cmd.global_limit = 2 * IWN5000_TXPOWER_MAX_DBM; /* 16 dBm */
4421 cmd.flags = IWN5000_TXPOWER_NO_CLOSED;
4422 cmd.srv_limit = IWN5000_TXPOWER_AUTO;
4423 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: setting TX power\n", __func__);
4424 return iwn_cmd(sc, IWN_CMD_TXPOWER_DBM, &cmd, sizeof cmd, async);
4425}
4426
4427/*
4428 * Retrieve the maximum RSSI (in dBm) among receivers.
4429 */
4430static int
4431iwn4965_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat)
4432{
4433 struct iwn4965_rx_phystat *phy = (void *)stat->phybuf;
4434 uint8_t mask, agc;
4435 int rssi;
4436
4437 mask = (le16toh(phy->antenna) >> 4) & IWN_ANT_ABC;
4438 agc = (le16toh(phy->agc) >> 7) & 0x7f;
4439
4440 rssi = 0;
4441 if (mask & IWN_ANT_A)
4442 rssi = MAX(rssi, phy->rssi[0]);
4443 if (mask & IWN_ANT_B)
4444 rssi = MAX(rssi, phy->rssi[2]);
4445 if (mask & IWN_ANT_C)
4446 rssi = MAX(rssi, phy->rssi[4]);
4447
4448 DPRINTF(sc, IWN_DEBUG_RECV,
4449 "%s: agc %d mask 0x%x rssi %d %d %d result %d\n", __func__, agc,
4450 mask, phy->rssi[0], phy->rssi[2], phy->rssi[4],
4451 rssi - agc - IWN_RSSI_TO_DBM);
4452 return rssi - agc - IWN_RSSI_TO_DBM;
4453}
4454
4455static int
4456iwn5000_get_rssi(struct iwn_softc *sc, struct iwn_rx_stat *stat)
4457{
4458 struct iwn5000_rx_phystat *phy = (void *)stat->phybuf;
4459 uint8_t agc;
4460 int rssi;
4461
4462 agc = (le32toh(phy->agc) >> 9) & 0x7f;
4463
4464 rssi = MAX(le16toh(phy->rssi[0]) & 0xff,
4465 le16toh(phy->rssi[1]) & 0xff);
4466 rssi = MAX(le16toh(phy->rssi[2]) & 0xff, rssi);
4467
4468 DPRINTF(sc, IWN_DEBUG_RECV,
4469 "%s: agc %d rssi %d %d %d result %d\n", __func__, agc,
4470 phy->rssi[0], phy->rssi[1], phy->rssi[2],
4471 rssi - agc - IWN_RSSI_TO_DBM);
4472 return rssi - agc - IWN_RSSI_TO_DBM;
4473}
4474
4475/*
4476 * Retrieve the average noise (in dBm) among receivers.
4477 */
4478static int
4479iwn_get_noise(const struct iwn_rx_general_stats *stats)
4480{
4481 int i, total, nbant, noise;
4482
4483 total = nbant = 0;
4484 for (i = 0; i < 3; i++) {
4485 if ((noise = le32toh(stats->noise[i]) & 0xff) == 0)
4486 continue;
4487 total += noise;
4488 nbant++;
4489 }
4490 /* There should be at least one antenna but check anyway. */
4491 return (nbant == 0) ? -127 : (total / nbant) - 107;
4492}
4493
4494/*
4495 * Compute temperature (in degC) from last received statistics.
4496 */
4497static int
4498iwn4965_get_temperature(struct iwn_softc *sc)
4499{
4500 struct iwn_ucode_info *uc = &sc->ucode_info;
4501 int32_t r1, r2, r3, r4, temp;
4502
4503 r1 = le32toh(uc->temp[0].chan20MHz);
4504 r2 = le32toh(uc->temp[1].chan20MHz);
4505 r3 = le32toh(uc->temp[2].chan20MHz);
4506 r4 = le32toh(sc->rawtemp);
4507
4508 if (r1 == r3) /* Prevents division by 0 (should not happen). */
4509 return 0;
4510
4511 /* Sign-extend 23-bit R4 value to 32-bit. */
4512 r4 = ((r4 & 0xffffff) ^ 0x800000) - 0x800000;
4513 /* Compute temperature in Kelvin. */
4514 temp = (259 * (r4 - r2)) / (r3 - r1);
4515 temp = (temp * 97) / 100 + 8;
4516
4517 DPRINTF(sc, IWN_DEBUG_ANY, "temperature %dK/%dC\n", temp,
4518 IWN_KTOC(temp));
4519 return IWN_KTOC(temp);
4520}
4521
4522static int
4523iwn5000_get_temperature(struct iwn_softc *sc)
4524{
4525 int32_t temp;
4526
4527 /*
4528 * Temperature is not used by the driver for 5000 Series because
4529 * TX power calibration is handled by firmware.
4530 */
4531 temp = le32toh(sc->rawtemp);
4532 if (sc->hw_type == IWN_HW_REV_TYPE_5150) {
4533 temp = (temp / -5) + sc->temp_off;
4534 temp = IWN_KTOC(temp);
4535 }
4536 return temp;
4537}
4538
4539/*
4540 * Initialize sensitivity calibration state machine.
4541 */
4542static int
4543iwn_init_sensitivity(struct iwn_softc *sc)
4544{
4545 struct iwn_ops *ops = &sc->ops;
4546 struct iwn_calib_state *calib = &sc->calib;
4547 uint32_t flags;
4548 int error;
4549
4550 /* Reset calibration state machine. */
4551 memset(calib, 0, sizeof (*calib));
4552 calib->state = IWN_CALIB_STATE_INIT;
4553 calib->cck_state = IWN_CCK_STATE_HIFA;
4554 /* Set initial correlation values. */
4555 calib->ofdm_x1 = sc->limits->min_ofdm_x1;
4556 calib->ofdm_mrc_x1 = sc->limits->min_ofdm_mrc_x1;
4557 calib->ofdm_x4 = sc->limits->min_ofdm_x4;
4558 calib->ofdm_mrc_x4 = sc->limits->min_ofdm_mrc_x4;
4559 calib->cck_x4 = 125;
4560 calib->cck_mrc_x4 = sc->limits->min_cck_mrc_x4;
4561 calib->energy_cck = sc->limits->energy_cck;
4562
4563 /* Write initial sensitivity. */
4564 if ((error = iwn_send_sensitivity(sc)) != 0)
4565 return error;
4566
4567 /* Write initial gains. */
4568 if ((error = ops->init_gains(sc)) != 0)
4569 return error;
4570
4571 /* Request statistics at each beacon interval. */
4572 flags = 0;
4573 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending request for statistics\n",
4574 __func__);
4575 return iwn_cmd(sc, IWN_CMD_GET_STATISTICS, &flags, sizeof flags, 1);
4576}
4577
4578/*
4579 * Collect noise and RSSI statistics for the first 20 beacons received
4580 * after association and use them to determine connected antennas and
4581 * to set differential gains.
4582 */
4583static void
4584iwn_collect_noise(struct iwn_softc *sc,
4585 const struct iwn_rx_general_stats *stats)
4586{
4587 struct iwn_ops *ops = &sc->ops;
4588 struct iwn_calib_state *calib = &sc->calib;
4589 struct ifnet *ifp = sc->sc_ifp;
4590 struct ieee80211com *ic = ifp->if_l2com;
4591 uint32_t val;
4592 int i;
4593
4594 /* Accumulate RSSI and noise for all 3 antennas. */
4595 for (i = 0; i < 3; i++) {
4596 calib->rssi[i] += le32toh(stats->rssi[i]) & 0xff;
4597 calib->noise[i] += le32toh(stats->noise[i]) & 0xff;
4598 }
4599 /* NB: We update differential gains only once after 20 beacons. */
4600 if (++calib->nbeacons < 20)
4601 return;
4602
4603 /* Determine highest average RSSI. */
4604 val = MAX(calib->rssi[0], calib->rssi[1]);
4605 val = MAX(calib->rssi[2], val);
4606
4607 /* Determine which antennas are connected. */
4608 sc->chainmask = sc->rxchainmask;
4609 for (i = 0; i < 3; i++)
4610 if (val - calib->rssi[i] > 15 * 20)
4611 sc->chainmask &= ~(1 << i);
4612 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4613 "%s: RX chains mask: theoretical=0x%x, actual=0x%x\n",
4614 __func__, sc->rxchainmask, sc->chainmask);
4615
4616 /* If none of the TX antennas are connected, keep at least one. */
4617 if ((sc->chainmask & sc->txchainmask) == 0)
4618 sc->chainmask |= IWN_LSB(sc->txchainmask);
4619
4620 (void)ops->set_gains(sc);
4621 calib->state = IWN_CALIB_STATE_RUN;
4622
4623#ifdef notyet
4624 /* XXX Disable RX chains with no antennas connected. */
4625 sc->rxon.rxchain = htole16(IWN_RXCHAIN_SEL(sc->chainmask));
4626 (void)iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1);
4627#endif
4628
4629 /* Enable power-saving mode if requested by user. */
4630 if (ic->ic_flags & IEEE80211_F_PMGTON)
4631 (void)iwn_set_pslevel(sc, 0, 3, 1);
4632}
4633
4634static int
4635iwn4965_init_gains(struct iwn_softc *sc)
4636{
4637 struct iwn_phy_calib_gain cmd;
4638
4639 memset(&cmd, 0, sizeof cmd);
4640 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN;
4641 /* Differential gains initially set to 0 for all 3 antennas. */
4642 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4643 "%s: setting initial differential gains\n", __func__);
4644 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1);
4645}
4646
4647static int
4648iwn5000_init_gains(struct iwn_softc *sc)
4649{
4650 struct iwn_phy_calib cmd;
4651
4652 memset(&cmd, 0, sizeof cmd);
4653 cmd.code = sc->reset_noise_gain;
4654 cmd.ngroups = 1;
4655 cmd.isvalid = 1;
4656 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4657 "%s: setting initial differential gains\n", __func__);
4658 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1);
4659}
4660
4661static int
4662iwn4965_set_gains(struct iwn_softc *sc)
4663{
4664 struct iwn_calib_state *calib = &sc->calib;
4665 struct iwn_phy_calib_gain cmd;
4666 int i, delta, noise;
4667
4668 /* Get minimal noise among connected antennas. */
4669 noise = INT_MAX; /* NB: There's at least one antenna. */
4670 for (i = 0; i < 3; i++)
4671 if (sc->chainmask & (1 << i))
4672 noise = MIN(calib->noise[i], noise);
4673
4674 memset(&cmd, 0, sizeof cmd);
4675 cmd.code = IWN4965_PHY_CALIB_DIFF_GAIN;
4676 /* Set differential gains for connected antennas. */
4677 for (i = 0; i < 3; i++) {
4678 if (sc->chainmask & (1 << i)) {
4679 /* Compute attenuation (in unit of 1.5dB). */
4680 delta = (noise - (int32_t)calib->noise[i]) / 30;
4681 /* NB: delta <= 0 */
4682 /* Limit to [-4.5dB,0]. */
4683 cmd.gain[i] = MIN(abs(delta), 3);
4684 if (delta < 0)
4685 cmd.gain[i] |= 1 << 2; /* sign bit */
4686 }
4687 }
4688 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4689 "setting differential gains Ant A/B/C: %x/%x/%x (%x)\n",
4690 cmd.gain[0], cmd.gain[1], cmd.gain[2], sc->chainmask);
4691 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1);
4692}
4693
4694static int
4695iwn5000_set_gains(struct iwn_softc *sc)
4696{
4697 struct iwn_calib_state *calib = &sc->calib;
4698 struct iwn_phy_calib_gain cmd;
4699 int i, ant, div, delta;
4700
4701 /* We collected 20 beacons and !=6050 need a 1.5 factor. */
4702 div = (sc->hw_type == IWN_HW_REV_TYPE_6050) ? 20 : 30;
4703
4704 memset(&cmd, 0, sizeof cmd);
4705 cmd.code = sc->noise_gain;
4706 cmd.ngroups = 1;
4707 cmd.isvalid = 1;
4708 /* Get first available RX antenna as referential. */
4709 ant = IWN_LSB(sc->rxchainmask);
4710 /* Set differential gains for other antennas. */
4711 for (i = ant + 1; i < 3; i++) {
4712 if (sc->chainmask & (1 << i)) {
4713 /* The delta is relative to antenna "ant". */
4714 delta = ((int32_t)calib->noise[ant] -
4715 (int32_t)calib->noise[i]) / div;
4716 /* Limit to [-4.5dB,+4.5dB]. */
4717 cmd.gain[i - 1] = MIN(abs(delta), 3);
4718 if (delta < 0)
4719 cmd.gain[i - 1] |= 1 << 2; /* sign bit */
4720 }
4721 }
4722 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4723 "setting differential gains Ant B/C: %x/%x (%x)\n",
4724 cmd.gain[0], cmd.gain[1], sc->chainmask);
4725 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 1);
4726}
4727
4728/*
4729 * Tune RF RX sensitivity based on the number of false alarms detected
4730 * during the last beacon period.
4731 */
4732static void
4733iwn_tune_sensitivity(struct iwn_softc *sc, const struct iwn_rx_stats *stats)
4734{
4735#define inc(val, inc, max) \
4736 if ((val) < (max)) { \
4737 if ((val) < (max) - (inc)) \
4738 (val) += (inc); \
4739 else \
4740 (val) = (max); \
4741 needs_update = 1; \
4742 }
4743#define dec(val, dec, min) \
4744 if ((val) > (min)) { \
4745 if ((val) > (min) + (dec)) \
4746 (val) -= (dec); \
4747 else \
4748 (val) = (min); \
4749 needs_update = 1; \
4750 }
4751
4752 const struct iwn_sensitivity_limits *limits = sc->limits;
4753 struct iwn_calib_state *calib = &sc->calib;
4754 uint32_t val, rxena, fa;
4755 uint32_t energy[3], energy_min;
4756 uint8_t noise[3], noise_ref;
4757 int i, needs_update = 0;
4758
4759 /* Check that we've been enabled long enough. */
4760 if ((rxena = le32toh(stats->general.load)) == 0)
4761 return;
4762
4763 /* Compute number of false alarms since last call for OFDM. */
4764 fa = le32toh(stats->ofdm.bad_plcp) - calib->bad_plcp_ofdm;
4765 fa += le32toh(stats->ofdm.fa) - calib->fa_ofdm;
4766 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */
4767
4768 /* Save counters values for next call. */
4769 calib->bad_plcp_ofdm = le32toh(stats->ofdm.bad_plcp);
4770 calib->fa_ofdm = le32toh(stats->ofdm.fa);
4771
4772 if (fa > 50 * rxena) {
4773 /* High false alarm count, decrease sensitivity. */
4774 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4775 "%s: OFDM high false alarm count: %u\n", __func__, fa);
4776 inc(calib->ofdm_x1, 1, limits->max_ofdm_x1);
4777 inc(calib->ofdm_mrc_x1, 1, limits->max_ofdm_mrc_x1);
4778 inc(calib->ofdm_x4, 1, limits->max_ofdm_x4);
4779 inc(calib->ofdm_mrc_x4, 1, limits->max_ofdm_mrc_x4);
4780
4781 } else if (fa < 5 * rxena) {
4782 /* Low false alarm count, increase sensitivity. */
4783 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4784 "%s: OFDM low false alarm count: %u\n", __func__, fa);
4785 dec(calib->ofdm_x1, 1, limits->min_ofdm_x1);
4786 dec(calib->ofdm_mrc_x1, 1, limits->min_ofdm_mrc_x1);
4787 dec(calib->ofdm_x4, 1, limits->min_ofdm_x4);
4788 dec(calib->ofdm_mrc_x4, 1, limits->min_ofdm_mrc_x4);
4789 }
4790
4791 /* Compute maximum noise among 3 receivers. */
4792 for (i = 0; i < 3; i++)
4793 noise[i] = (le32toh(stats->general.noise[i]) >> 8) & 0xff;
4794 val = MAX(noise[0], noise[1]);
4795 val = MAX(noise[2], val);
4796 /* Insert it into our samples table. */
4797 calib->noise_samples[calib->cur_noise_sample] = val;
4798 calib->cur_noise_sample = (calib->cur_noise_sample + 1) % 20;
4799
4800 /* Compute maximum noise among last 20 samples. */
4801 noise_ref = calib->noise_samples[0];
4802 for (i = 1; i < 20; i++)
4803 noise_ref = MAX(noise_ref, calib->noise_samples[i]);
4804
4805 /* Compute maximum energy among 3 receivers. */
4806 for (i = 0; i < 3; i++)
4807 energy[i] = le32toh(stats->general.energy[i]);
4808 val = MIN(energy[0], energy[1]);
4809 val = MIN(energy[2], val);
4810 /* Insert it into our samples table. */
4811 calib->energy_samples[calib->cur_energy_sample] = val;
4812 calib->cur_energy_sample = (calib->cur_energy_sample + 1) % 10;
4813
4814 /* Compute minimum energy among last 10 samples. */
4815 energy_min = calib->energy_samples[0];
4816 for (i = 1; i < 10; i++)
4817 energy_min = MAX(energy_min, calib->energy_samples[i]);
4818 energy_min += 6;
4819
4820 /* Compute number of false alarms since last call for CCK. */
4821 fa = le32toh(stats->cck.bad_plcp) - calib->bad_plcp_cck;
4822 fa += le32toh(stats->cck.fa) - calib->fa_cck;
4823 fa *= 200 * IEEE80211_DUR_TU; /* 200TU */
4824
4825 /* Save counters values for next call. */
4826 calib->bad_plcp_cck = le32toh(stats->cck.bad_plcp);
4827 calib->fa_cck = le32toh(stats->cck.fa);
4828
4829 if (fa > 50 * rxena) {
4830 /* High false alarm count, decrease sensitivity. */
4831 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4832 "%s: CCK high false alarm count: %u\n", __func__, fa);
4833 calib->cck_state = IWN_CCK_STATE_HIFA;
4834 calib->low_fa = 0;
4835
4836 if (calib->cck_x4 > 160) {
4837 calib->noise_ref = noise_ref;
4838 if (calib->energy_cck > 2)
4839 dec(calib->energy_cck, 2, energy_min);
4840 }
4841 if (calib->cck_x4 < 160) {
4842 calib->cck_x4 = 161;
4843 needs_update = 1;
4844 } else
4845 inc(calib->cck_x4, 3, limits->max_cck_x4);
4846
4847 inc(calib->cck_mrc_x4, 3, limits->max_cck_mrc_x4);
4848
4849 } else if (fa < 5 * rxena) {
4850 /* Low false alarm count, increase sensitivity. */
4851 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4852 "%s: CCK low false alarm count: %u\n", __func__, fa);
4853 calib->cck_state = IWN_CCK_STATE_LOFA;
4854 calib->low_fa++;
4855
4856 if (calib->cck_state != IWN_CCK_STATE_INIT &&
4857 (((int32_t)calib->noise_ref - (int32_t)noise_ref) > 2 ||
4858 calib->low_fa > 100)) {
4859 inc(calib->energy_cck, 2, limits->min_energy_cck);
4860 dec(calib->cck_x4, 3, limits->min_cck_x4);
4861 dec(calib->cck_mrc_x4, 3, limits->min_cck_mrc_x4);
4862 }
4863 } else {
4864 /* Not worth to increase or decrease sensitivity. */
4865 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4866 "%s: CCK normal false alarm count: %u\n", __func__, fa);
4867 calib->low_fa = 0;
4868 calib->noise_ref = noise_ref;
4869
4870 if (calib->cck_state == IWN_CCK_STATE_HIFA) {
4871 /* Previous interval had many false alarms. */
4872 dec(calib->energy_cck, 8, energy_min);
4873 }
4874 calib->cck_state = IWN_CCK_STATE_INIT;
4875 }
4876
4877 if (needs_update)
4878 (void)iwn_send_sensitivity(sc);
4879#undef dec
4880#undef inc
4881}
4882
4883static int
4884iwn_send_sensitivity(struct iwn_softc *sc)
4885{
4886 struct iwn_calib_state *calib = &sc->calib;
4887 struct iwn_enhanced_sensitivity_cmd cmd;
4888 int len;
4889
4890 memset(&cmd, 0, sizeof cmd);
4891 len = sizeof (struct iwn_sensitivity_cmd);
4892 cmd.which = IWN_SENSITIVITY_WORKTBL;
4893 /* OFDM modulation. */
4894 cmd.corr_ofdm_x1 = htole16(calib->ofdm_x1);
4895 cmd.corr_ofdm_mrc_x1 = htole16(calib->ofdm_mrc_x1);
4896 cmd.corr_ofdm_x4 = htole16(calib->ofdm_x4);
4897 cmd.corr_ofdm_mrc_x4 = htole16(calib->ofdm_mrc_x4);
4898 cmd.energy_ofdm = htole16(sc->limits->energy_ofdm);
4899 cmd.energy_ofdm_th = htole16(62);
4900 /* CCK modulation. */
4901 cmd.corr_cck_x4 = htole16(calib->cck_x4);
4902 cmd.corr_cck_mrc_x4 = htole16(calib->cck_mrc_x4);
4903 cmd.energy_cck = htole16(calib->energy_cck);
4904 /* Barker modulation: use default values. */
4905 cmd.corr_barker = htole16(190);
4906 cmd.corr_barker_mrc = htole16(390);
4907
4908 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
4909 "%s: set sensitivity %d/%d/%d/%d/%d/%d/%d\n", __func__,
4910 calib->ofdm_x1, calib->ofdm_mrc_x1, calib->ofdm_x4,
4911 calib->ofdm_mrc_x4, calib->cck_x4,
4912 calib->cck_mrc_x4, calib->energy_cck);
4913
4914 if (!(sc->sc_flags & IWN_FLAG_ENH_SENS))
4915 goto send;
4916 /* Enhanced sensitivity settings. */
4917 len = sizeof (struct iwn_enhanced_sensitivity_cmd);
4918 cmd.ofdm_det_slope_mrc = htole16(668);
4919 cmd.ofdm_det_icept_mrc = htole16(4);
4920 cmd.ofdm_det_slope = htole16(486);
4921 cmd.ofdm_det_icept = htole16(37);
4922 cmd.cck_det_slope_mrc = htole16(853);
4923 cmd.cck_det_icept_mrc = htole16(4);
4924 cmd.cck_det_slope = htole16(476);
4925 cmd.cck_det_icept = htole16(99);
4926send:
4927 return iwn_cmd(sc, IWN_CMD_SET_SENSITIVITY, &cmd, len, 1);
4928}
4929
4930/*
4931 * Set STA mode power saving level (between 0 and 5).
4932 * Level 0 is CAM (Continuously Aware Mode), 5 is for maximum power saving.
4933 */
4934static int
4935iwn_set_pslevel(struct iwn_softc *sc, int dtim, int level, int async)
4936{
4937 struct iwn_pmgt_cmd cmd;
4938 const struct iwn_pmgt *pmgt;
4939 uint32_t max, skip_dtim;
4940 uint32_t reg;
4941 int i;
4942
4943 /* Select which PS parameters to use. */
4944 if (dtim <= 2)
4945 pmgt = &iwn_pmgt[0][level];
4946 else if (dtim <= 10)
4947 pmgt = &iwn_pmgt[1][level];
4948 else
4949 pmgt = &iwn_pmgt[2][level];
4950
4951 memset(&cmd, 0, sizeof cmd);
4952 if (level != 0) /* not CAM */
4953 cmd.flags |= htole16(IWN_PS_ALLOW_SLEEP);
4954 if (level == 5)
4955 cmd.flags |= htole16(IWN_PS_FAST_PD);
4956 /* Retrieve PCIe Active State Power Management (ASPM). */
4957 reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + 0x10, 1);
4958 if (!(reg & 0x1)) /* L0s Entry disabled. */
4959 cmd.flags |= htole16(IWN_PS_PCI_PMGT);
4960 cmd.rxtimeout = htole32(pmgt->rxtimeout * 1024);
4961 cmd.txtimeout = htole32(pmgt->txtimeout * 1024);
4962
4963 if (dtim == 0) {
4964 dtim = 1;
4965 skip_dtim = 0;
4966 } else
4967 skip_dtim = pmgt->skip_dtim;
4968 if (skip_dtim != 0) {
4969 cmd.flags |= htole16(IWN_PS_SLEEP_OVER_DTIM);
4970 max = pmgt->intval[4];
4971 if (max == (uint32_t)-1)
4972 max = dtim * (skip_dtim + 1);
4973 else if (max > dtim)
4974 max = (max / dtim) * dtim;
4975 } else
4976 max = dtim;
4977 for (i = 0; i < 5; i++)
4978 cmd.intval[i] = htole32(MIN(max, pmgt->intval[i]));
4979
4980 DPRINTF(sc, IWN_DEBUG_RESET, "setting power saving level to %d\n",
4981 level);
4982 return iwn_cmd(sc, IWN_CMD_SET_POWER_MODE, &cmd, sizeof cmd, async);
4983}
4984
4985static int
4986iwn_send_btcoex(struct iwn_softc *sc)
4987{
4988 struct iwn_bluetooth cmd;
4989
4990 memset(&cmd, 0, sizeof cmd);
4991 cmd.flags = IWN_BT_COEX_CHAN_ANN | IWN_BT_COEX_BT_PRIO;
4992 cmd.lead_time = IWN_BT_LEAD_TIME_DEF;
4993 cmd.max_kill = IWN_BT_MAX_KILL_DEF;
4994 DPRINTF(sc, IWN_DEBUG_RESET, "%s: configuring bluetooth coexistence\n",
4995 __func__);
4996 return iwn_cmd(sc, IWN_CMD_BT_COEX, &cmd, sizeof(cmd), 0);
4997}
4998
4999static int
5000iwn_send_advanced_btcoex(struct iwn_softc *sc)
5001{
5002 static const uint32_t btcoex_3wire[12] = {
5003 0xaaaaaaaa, 0xaaaaaaaa, 0xaeaaaaaa, 0xaaaaaaaa,
5004 0xcc00ff28, 0x0000aaaa, 0xcc00aaaa, 0x0000aaaa,
5005 0xc0004000, 0x00004000, 0xf0005000, 0xf0005000,
5006 };
5007 struct iwn6000_btcoex_config btconfig;
5008 struct iwn_btcoex_priotable btprio;
5009 struct iwn_btcoex_prot btprot;
5010 int error, i;
5011
5012 memset(&btconfig, 0, sizeof btconfig);
5013 btconfig.flags = 145;
5014 btconfig.max_kill = 5;
5015 btconfig.bt3_t7_timer = 1;
5016 btconfig.kill_ack = htole32(0xffff0000);
5017 btconfig.kill_cts = htole32(0xffff0000);
5018 btconfig.sample_time = 2;
5019 btconfig.bt3_t2_timer = 0xc;
5020 for (i = 0; i < 12; i++)
5021 btconfig.lookup_table[i] = htole32(btcoex_3wire[i]);
5022 btconfig.valid = htole16(0xff);
5023 btconfig.prio_boost = 0xf0;
5024 DPRINTF(sc, IWN_DEBUG_RESET,
5025 "%s: configuring advanced bluetooth coexistence\n", __func__);
5026 error = iwn_cmd(sc, IWN_CMD_BT_COEX, &btconfig, sizeof(btconfig), 1);
5027 if (error != 0)
5028 return error;
5029
5030 memset(&btprio, 0, sizeof btprio);
5031 btprio.calib_init1 = 0x6;
5032 btprio.calib_init2 = 0x7;
5033 btprio.calib_periodic_low1 = 0x2;
5034 btprio.calib_periodic_low2 = 0x3;
5035 btprio.calib_periodic_high1 = 0x4;
5036 btprio.calib_periodic_high2 = 0x5;
5037 btprio.dtim = 0x6;
5038 btprio.scan52 = 0x8;
5039 btprio.scan24 = 0xa;
5040 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PRIOTABLE, &btprio, sizeof(btprio),
5041 1);
5042 if (error != 0)
5043 return error;
5044
5045 /* Force BT state machine change. */
5046 memset(&btprot, 0, sizeof btprio);
5047 btprot.open = 1;
5048 btprot.type = 1;
5049 error = iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1);
5050 if (error != 0)
5051 return error;
5052 btprot.open = 0;
5053 return iwn_cmd(sc, IWN_CMD_BT_COEX_PROT, &btprot, sizeof(btprot), 1);
5054}
5055
5056static int
5057iwn5000_runtime_calib(struct iwn_softc *sc)
5058{
5059 struct iwn5000_calib_config cmd;
5060
5061 memset(&cmd, 0, sizeof cmd);
5062 cmd.ucode.once.enable = 0xffffffff;
5063 cmd.ucode.once.start = IWN5000_CALIB_DC;
5064 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
5065 "%s: configuring runtime calibration\n", __func__);
5066 return iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof(cmd), 0);
5067}
5068
5069static int
5070iwn_config(struct iwn_softc *sc)
5071{
5072 struct iwn_ops *ops = &sc->ops;
5073 struct ifnet *ifp = sc->sc_ifp;
5074 struct ieee80211com *ic = ifp->if_l2com;
5075 uint32_t txmask;
5076 uint16_t rxchain;
5077 int error;
5078
5079 if (sc->hw_type == IWN_HW_REV_TYPE_6005) {
5080 /* Set radio temperature sensor offset. */
5081 error = iwn5000_temp_offset_calib(sc);
5082 if (error != 0) {
5083 device_printf(sc->sc_dev,
5084 "%s: could not set temperature offset\n", __func__);
5085 return error;
5086 }
5087 }
5088
5089 if (sc->hw_type == IWN_HW_REV_TYPE_6050) {
5090 /* Configure runtime DC calibration. */
5091 error = iwn5000_runtime_calib(sc);
5092 if (error != 0) {
5093 device_printf(sc->sc_dev,
5094 "%s: could not configure runtime calibration\n",
5095 __func__);
5096 return error;
5097 }
5098 }
5099
5100 /* Configure valid TX chains for >=5000 Series. */
5101 if (sc->hw_type != IWN_HW_REV_TYPE_4965) {
5102 txmask = htole32(sc->txchainmask);
5103 DPRINTF(sc, IWN_DEBUG_RESET,
5104 "%s: configuring valid TX chains 0x%x\n", __func__, txmask);
5105 error = iwn_cmd(sc, IWN5000_CMD_TX_ANT_CONFIG, &txmask,
5106 sizeof txmask, 0);
5107 if (error != 0) {
5108 device_printf(sc->sc_dev,
5109 "%s: could not configure valid TX chains, "
5110 "error %d\n", __func__, error);
5111 return error;
5112 }
5113 }
5114
5115 /* Configure bluetooth coexistence. */
5116 if (sc->sc_flags & IWN_FLAG_ADV_BTCOEX)
5117 error = iwn_send_advanced_btcoex(sc);
5118 else
5119 error = iwn_send_btcoex(sc);
5120 if (error != 0) {
5121 device_printf(sc->sc_dev,
5122 "%s: could not configure bluetooth coexistence, error %d\n",
5123 __func__, error);
5124 return error;
5125 }
5126
5127 /* Set mode, channel, RX filter and enable RX. */
5128 memset(&sc->rxon, 0, sizeof (struct iwn_rxon));
5129 IEEE80211_ADDR_COPY(sc->rxon.myaddr, IF_LLADDR(ifp));
5130 IEEE80211_ADDR_COPY(sc->rxon.wlap, IF_LLADDR(ifp));
5131 sc->rxon.chan = ieee80211_chan2ieee(ic, ic->ic_curchan);
5132 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF);
5133 if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan))
5134 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ);
5135 switch (ic->ic_opmode) {
5136 case IEEE80211_M_STA:
5137 sc->rxon.mode = IWN_MODE_STA;
5138 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST);
5139 break;
5140 case IEEE80211_M_MONITOR:
5141 sc->rxon.mode = IWN_MODE_MONITOR;
5142 sc->rxon.filter = htole32(IWN_FILTER_MULTICAST |
5143 IWN_FILTER_CTL | IWN_FILTER_PROMISC);
5144 break;
5145 default:
5146 /* Should not get there. */
5147 break;
5148 }
5149 sc->rxon.cck_mask = 0x0f; /* not yet negotiated */
5150 sc->rxon.ofdm_mask = 0xff; /* not yet negotiated */
5151 sc->rxon.ht_single_mask = 0xff;
5152 sc->rxon.ht_dual_mask = 0xff;
5153 sc->rxon.ht_triple_mask = 0xff;
5154 rxchain =
5155 IWN_RXCHAIN_VALID(sc->rxchainmask) |
5156 IWN_RXCHAIN_MIMO_COUNT(2) |
5157 IWN_RXCHAIN_IDLE_COUNT(2);
5158 sc->rxon.rxchain = htole16(rxchain);
5159 DPRINTF(sc, IWN_DEBUG_RESET, "%s: setting configuration\n", __func__);
5160 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 0);
5161 if (error != 0) {
5162 device_printf(sc->sc_dev, "%s: RXON command failed\n",
5163 __func__);
5164 return error;
5165 }
5166
5167 if ((error = iwn_add_broadcast_node(sc, 0)) != 0) {
5168 device_printf(sc->sc_dev, "%s: could not add broadcast node\n",
5169 __func__);
5170 return error;
5171 }
5172
5173 /* Configuration has changed, set TX power accordingly. */
5174 if ((error = ops->set_txpower(sc, ic->ic_curchan, 0)) != 0) {
5175 device_printf(sc->sc_dev, "%s: could not set TX power\n",
5176 __func__);
5177 return error;
5178 }
5179
5180 if ((error = iwn_set_critical_temp(sc)) != 0) {
5181 device_printf(sc->sc_dev,
5182 "%s: could not set critical temperature\n", __func__);
5183 return error;
5184 }
5185
5186 /* Set power saving level to CAM during initialization. */
5187 if ((error = iwn_set_pslevel(sc, 0, 0, 0)) != 0) {
5188 device_printf(sc->sc_dev,
5189 "%s: could not set power saving level\n", __func__);
5190 return error;
5191 }
5192 return 0;
5193}
5194
5195/*
5196 * Add an ssid element to a frame.
5197 */
5198static uint8_t *
5199ieee80211_add_ssid(uint8_t *frm, const uint8_t *ssid, u_int len)
5200{
5201 *frm++ = IEEE80211_ELEMID_SSID;
5202 *frm++ = len;
5203 memcpy(frm, ssid, len);
5204 return frm + len;
5205}
5206
5207static int
5208iwn_scan(struct iwn_softc *sc)
5209{
5210 struct ifnet *ifp = sc->sc_ifp;
5211 struct ieee80211com *ic = ifp->if_l2com;
5212 struct ieee80211_scan_state *ss = ic->ic_scan; /*XXX*/
5213 struct ieee80211_node *ni = ss->ss_vap->iv_bss;
5214 struct iwn_scan_hdr *hdr;
5215 struct iwn_cmd_data *tx;
5216 struct iwn_scan_essid *essid;
5217 struct iwn_scan_chan *chan;
5218 struct ieee80211_frame *wh;
5219 struct ieee80211_rateset *rs;
5220 struct ieee80211_channel *c;
5221 uint8_t *buf, *frm;
5222 uint16_t rxchain;
5223 uint8_t txant;
5224 int buflen, error;
5225
5226 buf = malloc(IWN_SCAN_MAXSZ, M_DEVBUF, M_NOWAIT | M_ZERO);
5227 if (buf == NULL) {
5228 device_printf(sc->sc_dev,
5229 "%s: could not allocate buffer for scan command\n",
5230 __func__);
5231 return ENOMEM;
5232 }
5233 hdr = (struct iwn_scan_hdr *)buf;
5234 /*
5235 * Move to the next channel if no frames are received within 10ms
5236 * after sending the probe request.
5237 */
5238 hdr->quiet_time = htole16(10); /* timeout in milliseconds */
5239 hdr->quiet_threshold = htole16(1); /* min # of packets */
5240
5241 /* Select antennas for scanning. */
5242 rxchain =
5243 IWN_RXCHAIN_VALID(sc->rxchainmask) |
5244 IWN_RXCHAIN_FORCE_MIMO_SEL(sc->rxchainmask) |
5245 IWN_RXCHAIN_DRIVER_FORCE;
5246 if (IEEE80211_IS_CHAN_A(ic->ic_curchan) &&
5247 sc->hw_type == IWN_HW_REV_TYPE_4965) {
5248 /* Ant A must be avoided in 5GHz because of an HW bug. */
5249 rxchain |= IWN_RXCHAIN_FORCE_SEL(IWN_ANT_B);
5250 } else /* Use all available RX antennas. */
5251 rxchain |= IWN_RXCHAIN_FORCE_SEL(sc->rxchainmask);
5252 hdr->rxchain = htole16(rxchain);
5253 hdr->filter = htole32(IWN_FILTER_MULTICAST | IWN_FILTER_BEACON);
5254
5255 tx = (struct iwn_cmd_data *)(hdr + 1);
5256 tx->flags = htole32(IWN_TX_AUTO_SEQ);
5257 tx->id = sc->broadcast_id;
5258 tx->lifetime = htole32(IWN_LIFETIME_INFINITE);
5259
5260 if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) {
5261 /* Send probe requests at 6Mbps. */
5262 tx->rate = htole32(0xd);
5263 rs = &ic->ic_sup_rates[IEEE80211_MODE_11A];
5264 } else {
5265 hdr->flags = htole32(IWN_RXON_24GHZ | IWN_RXON_AUTO);
5266 if (sc->hw_type == IWN_HW_REV_TYPE_4965 &&
5267 sc->rxon.associd && sc->rxon.chan > 14)
5268 tx->rate = htole32(0xd);
5269 else {
5270 /* Send probe requests at 1Mbps. */
5271 tx->rate = htole32(10 | IWN_RFLAG_CCK);
5272 }
5273 rs = &ic->ic_sup_rates[IEEE80211_MODE_11G];
5274 }
5275 /* Use the first valid TX antenna. */
5276 txant = IWN_LSB(sc->txchainmask);
5277 tx->rate |= htole32(IWN_RFLAG_ANT(txant));
5278
5279 essid = (struct iwn_scan_essid *)(tx + 1);
5280 if (ss->ss_ssid[0].len != 0) {
5281 essid[0].id = IEEE80211_ELEMID_SSID;
5282 essid[0].len = ss->ss_ssid[0].len;
5283 memcpy(essid[0].data, ss->ss_ssid[0].ssid, ss->ss_ssid[0].len);
5284 }
5285 /*
5286 * Build a probe request frame. Most of the following code is a
5287 * copy & paste of what is done in net80211.
5288 */
5289 wh = (struct ieee80211_frame *)(essid + 20);
5290 wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_MGT |
5291 IEEE80211_FC0_SUBTYPE_PROBE_REQ;
5292 wh->i_fc[1] = IEEE80211_FC1_DIR_NODS;
5293 IEEE80211_ADDR_COPY(wh->i_addr1, ifp->if_broadcastaddr);
5294 IEEE80211_ADDR_COPY(wh->i_addr2, IF_LLADDR(ifp));
5295 IEEE80211_ADDR_COPY(wh->i_addr3, ifp->if_broadcastaddr);
5296 *(uint16_t *)&wh->i_dur[0] = 0; /* filled by HW */
5297 *(uint16_t *)&wh->i_seq[0] = 0; /* filled by HW */
5298
5299 frm = (uint8_t *)(wh + 1);
5300 frm = ieee80211_add_ssid(frm, NULL, 0);
5301 frm = ieee80211_add_rates(frm, rs);
5302 if (rs->rs_nrates > IEEE80211_RATE_SIZE)
5303 frm = ieee80211_add_xrates(frm, rs);
5304 if (ic->ic_htcaps & IEEE80211_HTC_HT)
5305 frm = ieee80211_add_htcap(frm, ni);
5306
5307 /* Set length of probe request. */
5308 tx->len = htole16(frm - (uint8_t *)wh);
5309
5310 c = ic->ic_curchan;
5311 chan = (struct iwn_scan_chan *)frm;
5312 chan->chan = htole16(ieee80211_chan2ieee(ic, c));
5313 chan->flags = 0;
5314 if (ss->ss_nssid > 0)
5315 chan->flags |= htole32(IWN_CHAN_NPBREQS(1));
5316 chan->dsp_gain = 0x6e;
5317 if (IEEE80211_IS_CHAN_5GHZ(c) &&
5318 !(c->ic_flags & IEEE80211_CHAN_PASSIVE)) {
5319 chan->rf_gain = 0x3b;
5320 chan->active = htole16(24);
5321 chan->passive = htole16(110);
5322 chan->flags |= htole32(IWN_CHAN_ACTIVE);
5323 } else if (IEEE80211_IS_CHAN_5GHZ(c)) {
5324 chan->rf_gain = 0x3b;
5325 chan->active = htole16(24);
5326 if (sc->rxon.associd)
5327 chan->passive = htole16(78);
5328 else
5329 chan->passive = htole16(110);
5330 hdr->crc_threshold = 0xffff;
5331 } else if (!(c->ic_flags & IEEE80211_CHAN_PASSIVE)) {
5332 chan->rf_gain = 0x28;
5333 chan->active = htole16(36);
5334 chan->passive = htole16(120);
5335 chan->flags |= htole32(IWN_CHAN_ACTIVE);
5336 } else {
5337 chan->rf_gain = 0x28;
5338 chan->active = htole16(36);
5339 if (sc->rxon.associd)
5340 chan->passive = htole16(88);
5341 else
5342 chan->passive = htole16(120);
5343 hdr->crc_threshold = 0xffff;
5344 }
5345
5346 DPRINTF(sc, IWN_DEBUG_STATE,
5347 "%s: chan %u flags 0x%x rf_gain 0x%x "
5348 "dsp_gain 0x%x active 0x%x passive 0x%x\n", __func__,
5349 chan->chan, chan->flags, chan->rf_gain, chan->dsp_gain,
5350 chan->active, chan->passive);
5351
5352 hdr->nchan++;
5353 chan++;
5354 buflen = (uint8_t *)chan - buf;
5355 hdr->len = htole16(buflen);
5356
5357 DPRINTF(sc, IWN_DEBUG_STATE, "sending scan command nchan=%d\n",
5358 hdr->nchan);
5359 error = iwn_cmd(sc, IWN_CMD_SCAN, buf, buflen, 1);
5360 free(buf, M_DEVBUF);
5361 return error;
5362}
5363
5364static int
5365iwn_auth(struct iwn_softc *sc, struct ieee80211vap *vap)
5366{
5367 struct iwn_ops *ops = &sc->ops;
5368 struct ifnet *ifp = sc->sc_ifp;
5369 struct ieee80211com *ic = ifp->if_l2com;
5370 struct ieee80211_node *ni = vap->iv_bss;
5371 int error;
5372
5373 /* Update adapter configuration. */
5374 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid);
5375 sc->rxon.chan = ieee80211_chan2ieee(ic, ni->ni_chan);
5376 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF);
5377 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan))
5378 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ);
5379 if (ic->ic_flags & IEEE80211_F_SHSLOT)
5380 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT);
5381 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
5382 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE);
5383 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) {
5384 sc->rxon.cck_mask = 0;
5385 sc->rxon.ofdm_mask = 0x15;
5386 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) {
5387 sc->rxon.cck_mask = 0x03;
5388 sc->rxon.ofdm_mask = 0;
5389 } else {
5390 /* Assume 802.11b/g. */
5391 sc->rxon.cck_mask = 0x0f;
5392 sc->rxon.ofdm_mask = 0x15;
5393 }
5394 DPRINTF(sc, IWN_DEBUG_STATE, "rxon chan %d flags %x cck %x ofdm %x\n",
5395 sc->rxon.chan, sc->rxon.flags, sc->rxon.cck_mask,
5396 sc->rxon.ofdm_mask);
5397 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1);
5398 if (error != 0) {
5399 device_printf(sc->sc_dev, "%s: RXON command failed, error %d\n",
5400 __func__, error);
5401 return error;
5402 }
5403
5404 /* Configuration has changed, set TX power accordingly. */
5405 if ((error = ops->set_txpower(sc, ni->ni_chan, 1)) != 0) {
5406 device_printf(sc->sc_dev,
5407 "%s: could not set TX power, error %d\n", __func__, error);
5408 return error;
5409 }
5410 /*
5411 * Reconfiguring RXON clears the firmware nodes table so we must
5412 * add the broadcast node again.
5413 */
5414 if ((error = iwn_add_broadcast_node(sc, 1)) != 0) {
5415 device_printf(sc->sc_dev,
5416 "%s: could not add broadcast node, error %d\n", __func__,
5417 error);
5418 return error;
5419 }
5420 return 0;
5421}
5422
5423static int
5424iwn_run(struct iwn_softc *sc, struct ieee80211vap *vap)
5425{
5426 struct iwn_ops *ops = &sc->ops;
5427 struct ifnet *ifp = sc->sc_ifp;
5428 struct ieee80211com *ic = ifp->if_l2com;
5429 struct ieee80211_node *ni = vap->iv_bss;
5430 struct iwn_node_info node;
5431 uint32_t htflags = 0;
5432 int error;
5433
5434 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
5435 /* Link LED blinks while monitoring. */
5436 iwn_set_led(sc, IWN_LED_LINK, 5, 5);
5437 return 0;
5438 }
5439 if ((error = iwn_set_timing(sc, ni)) != 0) {
5440 device_printf(sc->sc_dev,
5441 "%s: could not set timing, error %d\n", __func__, error);
5442 return error;
5443 }
5444
5445 /* Update adapter configuration. */
5446 IEEE80211_ADDR_COPY(sc->rxon.bssid, ni->ni_bssid);
5447 sc->rxon.associd = htole16(IEEE80211_AID(ni->ni_associd));
5448 sc->rxon.chan = ieee80211_chan2ieee(ic, ni->ni_chan);
5449 sc->rxon.flags = htole32(IWN_RXON_TSF | IWN_RXON_CTS_TO_SELF);
5450 if (IEEE80211_IS_CHAN_2GHZ(ni->ni_chan))
5451 sc->rxon.flags |= htole32(IWN_RXON_AUTO | IWN_RXON_24GHZ);
5452 if (ic->ic_flags & IEEE80211_F_SHSLOT)
5453 sc->rxon.flags |= htole32(IWN_RXON_SHSLOT);
5454 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE)
5455 sc->rxon.flags |= htole32(IWN_RXON_SHPREAMBLE);
5456 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) {
5457 sc->rxon.cck_mask = 0;
5458 sc->rxon.ofdm_mask = 0x15;
5459 } else if (IEEE80211_IS_CHAN_B(ni->ni_chan)) {
5460 sc->rxon.cck_mask = 0x03;
5461 sc->rxon.ofdm_mask = 0;
5462 } else {
5463 /* Assume 802.11b/g. */
5464 sc->rxon.cck_mask = 0x0f;
5465 sc->rxon.ofdm_mask = 0x15;
5466 }
5467 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) {
5468 htflags |= IWN_RXON_HT_PROTMODE(ic->ic_curhtprotmode);
5469 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan)) {
5470 switch (ic->ic_curhtprotmode) {
5471 case IEEE80211_HTINFO_OPMODE_HT20PR:
5472 htflags |= IWN_RXON_HT_MODEPURE40;
5473 break;
5474 default:
5475 htflags |= IWN_RXON_HT_MODEMIXED;
5476 break;
5477 }
5478 }
5479 if (IEEE80211_IS_CHAN_HT40D(ni->ni_chan))
5480 htflags |= IWN_RXON_HT_HT40MINUS;
5481 }
5482 sc->rxon.flags |= htole32(htflags);
5483 sc->rxon.filter |= htole32(IWN_FILTER_BSS);
5484 DPRINTF(sc, IWN_DEBUG_STATE, "rxon chan %d flags %x\n",
5485 sc->rxon.chan, sc->rxon.flags);
5486 error = iwn_cmd(sc, IWN_CMD_RXON, &sc->rxon, sc->rxonsz, 1);
5487 if (error != 0) {
5488 device_printf(sc->sc_dev,
5489 "%s: could not update configuration, error %d\n", __func__,
5490 error);
5491 return error;
5492 }
5493
5494 /* Configuration has changed, set TX power accordingly. */
5495 if ((error = ops->set_txpower(sc, ni->ni_chan, 1)) != 0) {
5496 device_printf(sc->sc_dev,
5497 "%s: could not set TX power, error %d\n", __func__, error);
5498 return error;
5499 }
5500
5501 /* Fake a join to initialize the TX rate. */
5502 ((struct iwn_node *)ni)->id = IWN_ID_BSS;
5503 iwn_newassoc(ni, 1);
5504
5505 /* Add BSS node. */
5506 memset(&node, 0, sizeof node);
5507 IEEE80211_ADDR_COPY(node.macaddr, ni->ni_macaddr);
5508 node.id = IWN_ID_BSS;
5509 if (IEEE80211_IS_CHAN_HT(ni->ni_chan)) {
5510 switch (ni->ni_htcap & IEEE80211_HTCAP_SMPS) {
5511 case IEEE80211_HTCAP_SMPS_ENA:
5512 node.htflags |= htole32(IWN_SMPS_MIMO_DIS);
5513 break;
5514 case IEEE80211_HTCAP_SMPS_DYNAMIC:
5515 node.htflags |= htole32(IWN_SMPS_MIMO_PROT);
5516 break;
5517 }
5518 node.htflags |= htole32(IWN_AMDPU_SIZE_FACTOR(3) |
5519 IWN_AMDPU_DENSITY(5)); /* 4us */
5520 if (IEEE80211_IS_CHAN_HT40(ni->ni_chan))
5521 node.htflags |= htole32(IWN_NODE_HT40);
5522 }
5523 DPRINTF(sc, IWN_DEBUG_STATE, "%s: adding BSS node\n", __func__);
5524 error = ops->add_node(sc, &node, 1);
5525 if (error != 0) {
5526 device_printf(sc->sc_dev,
5527 "%s: could not add BSS node, error %d\n", __func__, error);
5528 return error;
5529 }
5530 DPRINTF(sc, IWN_DEBUG_STATE, "%s: setting link quality for node %d\n",
5531 __func__, node.id);
5532 if ((error = iwn_set_link_quality(sc, ni)) != 0) {
5533 device_printf(sc->sc_dev,
5534 "%s: could not setup link quality for node %d, error %d\n",
5535 __func__, node.id, error);
5536 return error;
5537 }
5538
5539 if ((error = iwn_init_sensitivity(sc)) != 0) {
5540 device_printf(sc->sc_dev,
5541 "%s: could not set sensitivity, error %d\n", __func__,
5542 error);
5543 return error;
5544 }
5545 /* Start periodic calibration timer. */
5546 sc->calib.state = IWN_CALIB_STATE_ASSOC;
5547 sc->calib_cnt = 0;
5548 callout_reset(&sc->calib_to, msecs_to_ticks(500), iwn_calib_timeout,
5549 sc);
5550
5551 /* Link LED always on while associated. */
5552 iwn_set_led(sc, IWN_LED_LINK, 0, 1);
5553 return 0;
5554}
5555
5556/*
5557 * This function is called by upper layer when an ADDBA request is received
5558 * from another STA and before the ADDBA response is sent.
5559 */
5560static int
5561iwn_ampdu_rx_start(struct ieee80211_node *ni, struct ieee80211_rx_ampdu *rap,
5562 int baparamset, int batimeout, int baseqctl)
5563{
5564#define MS(_v, _f) (((_v) & _f) >> _f##_S)
5565 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc;
5566 struct iwn_ops *ops = &sc->ops;
5567 struct iwn_node *wn = (void *)ni;
5568 struct iwn_node_info node;
5569 uint16_t ssn;
5570 uint8_t tid;
5571 int error;
5572
5573 tid = MS(le16toh(baparamset), IEEE80211_BAPS_TID);
5574 ssn = MS(le16toh(baseqctl), IEEE80211_BASEQ_START);
5575
5576 memset(&node, 0, sizeof node);
5577 node.id = wn->id;
5578 node.control = IWN_NODE_UPDATE;
5579 node.flags = IWN_FLAG_SET_ADDBA;
5580 node.addba_tid = tid;
5581 node.addba_ssn = htole16(ssn);
5582 DPRINTF(sc, IWN_DEBUG_RECV, "ADDBA RA=%d TID=%d SSN=%d\n",
5583 wn->id, tid, ssn);
5584 error = ops->add_node(sc, &node, 1);
5585 if (error != 0)
5586 return error;
5587 return sc->sc_ampdu_rx_start(ni, rap, baparamset, batimeout, baseqctl);
5588#undef MS
5589}
5590
5591/*
5592 * This function is called by upper layer on teardown of an HT-immediate
5593 * Block Ack agreement (eg. uppon receipt of a DELBA frame).
5594 */
5595static void
5596iwn_ampdu_rx_stop(struct ieee80211_node *ni, struct ieee80211_rx_ampdu *rap)
5597{
5598 struct ieee80211com *ic = ni->ni_ic;
5599 struct iwn_softc *sc = ic->ic_ifp->if_softc;
5600 struct iwn_ops *ops = &sc->ops;
5601 struct iwn_node *wn = (void *)ni;
5602 struct iwn_node_info node;
5603 uint8_t tid;
5604
5605 /* XXX: tid as an argument */
5606 for (tid = 0; tid < WME_NUM_TID; tid++) {
5607 if (&ni->ni_rx_ampdu[tid] == rap)
5608 break;
5609 }
5610
5611 memset(&node, 0, sizeof node);
5612 node.id = wn->id;
5613 node.control = IWN_NODE_UPDATE;
5614 node.flags = IWN_FLAG_SET_DELBA;
5615 node.delba_tid = tid;
5616 DPRINTF(sc, IWN_DEBUG_RECV, "DELBA RA=%d TID=%d\n", wn->id, tid);
5617 (void)ops->add_node(sc, &node, 1);
5618 sc->sc_ampdu_rx_stop(ni, rap);
5619}
5620
5621static int
5622iwn_addba_request(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap,
5623 int dialogtoken, int baparamset, int batimeout)
5624{
5625 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc;
5626 int qid;
5627
5628 for (qid = sc->firstaggqueue; qid < sc->ntxqs; qid++) {
5629 if (sc->qid2tap[qid] == NULL)
5630 break;
5631 }
5632 if (qid == sc->ntxqs) {
5633 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: not free aggregation queue\n",
5634 __func__);
5635 return 0;
5636 }
5637 tap->txa_private = malloc(sizeof(int), M_DEVBUF, M_NOWAIT);
5638 if (tap->txa_private == NULL) {
5639 device_printf(sc->sc_dev,
5640 "%s: failed to alloc TX aggregation structure\n", __func__);
5641 return 0;
5642 }
5643 sc->qid2tap[qid] = tap;
5644 *(int *)tap->txa_private = qid;
5645 return sc->sc_addba_request(ni, tap, dialogtoken, baparamset,
5646 batimeout);
5647}
5648
5649static int
5650iwn_addba_response(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap,
5651 int code, int baparamset, int batimeout)
5652{
5653 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc;
5654 int qid = *(int *)tap->txa_private;
5655 uint8_t tid = tap->txa_tid;
5656 int ret;
5657
5658 if (code == IEEE80211_STATUS_SUCCESS) {
5659 ni->ni_txseqs[tid] = tap->txa_start & 0xfff;
5660 ret = iwn_ampdu_tx_start(ni->ni_ic, ni, tid);
5661 if (ret != 1)
5662 return ret;
5663 } else {
5664 sc->qid2tap[qid] = NULL;
5665 free(tap->txa_private, M_DEVBUF);
5666 tap->txa_private = NULL;
5667 }
5668 return sc->sc_addba_response(ni, tap, code, baparamset, batimeout);
5669}
5670
5671/*
5672 * This function is called by upper layer when an ADDBA response is received
5673 * from another STA.
5674 */
5675static int
5676iwn_ampdu_tx_start(struct ieee80211com *ic, struct ieee80211_node *ni,
5677 uint8_t tid)
5678{
5679 struct ieee80211_tx_ampdu *tap = &ni->ni_tx_ampdu[tid];
5680 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc;
5681 struct iwn_ops *ops = &sc->ops;
5682 struct iwn_node *wn = (void *)ni;
5683 struct iwn_node_info node;
5684 int error, qid;
5685
5686 /* Enable TX for the specified RA/TID. */
5687 wn->disable_tid &= ~(1 << tid);
5688 memset(&node, 0, sizeof node);
5689 node.id = wn->id;
5690 node.control = IWN_NODE_UPDATE;
5691 node.flags = IWN_FLAG_SET_DISABLE_TID;
5692 node.disable_tid = htole16(wn->disable_tid);
5693 error = ops->add_node(sc, &node, 1);
5694 if (error != 0)
5695 return 0;
5696
5697 if ((error = iwn_nic_lock(sc)) != 0)
5698 return 0;
5699 qid = *(int *)tap->txa_private;
5700 DPRINTF(sc, IWN_DEBUG_XMIT, "%s: ra=%d tid=%d ssn=%d qid=%d\n",
5701 __func__, wn->id, tid, tap->txa_start, qid);
5702 ops->ampdu_tx_start(sc, ni, qid, tid, tap->txa_start & 0xfff);
5703 iwn_nic_unlock(sc);
5704
5705 iwn_set_link_quality(sc, ni);
5706 return 1;
5707}
5708
5709static void
5710iwn_ampdu_tx_stop(struct ieee80211_node *ni, struct ieee80211_tx_ampdu *tap)
5711{
5712 struct iwn_softc *sc = ni->ni_ic->ic_ifp->if_softc;
5713 struct iwn_ops *ops = &sc->ops;
5714 uint8_t tid = tap->txa_tid;
5715 int qid;
5716
5717 sc->sc_addba_stop(ni, tap);
5718
5719 if (tap->txa_private == NULL)
5720 return;
5721
5722 qid = *(int *)tap->txa_private;
5723 if (sc->txq[qid].queued != 0)
5724 return;
5725 if (iwn_nic_lock(sc) != 0)
5726 return;
5727 ops->ampdu_tx_stop(sc, qid, tid, tap->txa_start & 0xfff);
5728 iwn_nic_unlock(sc);
5729 sc->qid2tap[qid] = NULL;
5730 free(tap->txa_private, M_DEVBUF);
5731 tap->txa_private = NULL;
5732}
5733
5734static void
5735iwn4965_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni,
5736 int qid, uint8_t tid, uint16_t ssn)
5737{
5738 struct iwn_node *wn = (void *)ni;
5739
5740 /* Stop TX scheduler while we're changing its configuration. */
5741 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid),
5742 IWN4965_TXQ_STATUS_CHGACT);
5743
5744 /* Assign RA/TID translation to the queue. */
5745 iwn_mem_write_2(sc, sc->sched_base + IWN4965_SCHED_TRANS_TBL(qid),
5746 wn->id << 4 | tid);
5747
5748 /* Enable chain-building mode for the queue. */
5749 iwn_prph_setbits(sc, IWN4965_SCHED_QCHAIN_SEL, 1 << qid);
5750
5751 /* Set starting sequence number from the ADDBA request. */
5752 sc->txq[qid].cur = sc->txq[qid].read = (ssn & 0xff);
5753 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff));
5754 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn);
5755
5756 /* Set scheduler window size. */
5757 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid),
5758 IWN_SCHED_WINSZ);
5759 /* Set scheduler frame limit. */
5760 iwn_mem_write(sc, sc->sched_base + IWN4965_SCHED_QUEUE_OFFSET(qid) + 4,
5761 IWN_SCHED_LIMIT << 16);
5762
5763 /* Enable interrupts for the queue. */
5764 iwn_prph_setbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid);
5765
5766 /* Mark the queue as active. */
5767 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid),
5768 IWN4965_TXQ_STATUS_ACTIVE | IWN4965_TXQ_STATUS_AGGR_ENA |
5769 iwn_tid2fifo[tid] << 1);
5770}
5771
5772static void
5773iwn4965_ampdu_tx_stop(struct iwn_softc *sc, int qid, uint8_t tid, uint16_t ssn)
5774{
5775 /* Stop TX scheduler while we're changing its configuration. */
5776 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid),
5777 IWN4965_TXQ_STATUS_CHGACT);
5778
5779 /* Set starting sequence number from the ADDBA request. */
5780 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff));
5781 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), ssn);
5782
5783 /* Disable interrupts for the queue. */
5784 iwn_prph_clrbits(sc, IWN4965_SCHED_INTR_MASK, 1 << qid);
5785
5786 /* Mark the queue as inactive. */
5787 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid),
5788 IWN4965_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid] << 1);
5789}
5790
5791static void
5792iwn5000_ampdu_tx_start(struct iwn_softc *sc, struct ieee80211_node *ni,
5793 int qid, uint8_t tid, uint16_t ssn)
5794{
5795 struct iwn_node *wn = (void *)ni;
5796
5797 /* Stop TX scheduler while we're changing its configuration. */
5798 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid),
5799 IWN5000_TXQ_STATUS_CHGACT);
5800
5801 /* Assign RA/TID translation to the queue. */
5802 iwn_mem_write_2(sc, sc->sched_base + IWN5000_SCHED_TRANS_TBL(qid),
5803 wn->id << 4 | tid);
5804
5805 /* Enable chain-building mode for the queue. */
5806 iwn_prph_setbits(sc, IWN5000_SCHED_QCHAIN_SEL, 1 << qid);
5807
5808 /* Enable aggregation for the queue. */
5809 iwn_prph_setbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid);
5810
5811 /* Set starting sequence number from the ADDBA request. */
5812 sc->txq[qid].cur = sc->txq[qid].read = (ssn & 0xff);
5813 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff));
5814 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn);
5815
5816 /* Set scheduler window size and frame limit. */
5817 iwn_mem_write(sc, sc->sched_base + IWN5000_SCHED_QUEUE_OFFSET(qid) + 4,
5818 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ);
5819
5820 /* Enable interrupts for the queue. */
5821 iwn_prph_setbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid);
5822
5823 /* Mark the queue as active. */
5824 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid),
5825 IWN5000_TXQ_STATUS_ACTIVE | iwn_tid2fifo[tid]);
5826}
5827
5828static void
5829iwn5000_ampdu_tx_stop(struct iwn_softc *sc, int qid, uint8_t tid, uint16_t ssn)
5830{
5831 /* Stop TX scheduler while we're changing its configuration. */
5832 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid),
5833 IWN5000_TXQ_STATUS_CHGACT);
5834
5835 /* Disable aggregation for the queue. */
5836 iwn_prph_clrbits(sc, IWN5000_SCHED_AGGR_SEL, 1 << qid);
5837
5838 /* Set starting sequence number from the ADDBA request. */
5839 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | (ssn & 0xff));
5840 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), ssn);
5841
5842 /* Disable interrupts for the queue. */
5843 iwn_prph_clrbits(sc, IWN5000_SCHED_INTR_MASK, 1 << qid);
5844
5845 /* Mark the queue as inactive. */
5846 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid),
5847 IWN5000_TXQ_STATUS_INACTIVE | iwn_tid2fifo[tid]);
5848}
5849
5850/*
5851 * Query calibration tables from the initialization firmware. We do this
5852 * only once at first boot. Called from a process context.
5853 */
5854static int
5855iwn5000_query_calibration(struct iwn_softc *sc)
5856{
5857 struct iwn5000_calib_config cmd;
5858 int error;
5859
5860 memset(&cmd, 0, sizeof cmd);
5861 cmd.ucode.once.enable = 0xffffffff;
5862 cmd.ucode.once.start = 0xffffffff;
5863 cmd.ucode.once.send = 0xffffffff;
5864 cmd.ucode.flags = 0xffffffff;
5865 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: sending calibration query\n",
5866 __func__);
5867 error = iwn_cmd(sc, IWN5000_CMD_CALIB_CONFIG, &cmd, sizeof cmd, 0);
5868 if (error != 0)
5869 return error;
5870
5871 /* Wait at most two seconds for calibration to complete. */
5872 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE))
5873 error = msleep(sc, &sc->sc_mtx, PCATCH, "iwncal", 2 * hz);
5874 return error;
5875}
5876
5877/*
5878 * Send calibration results to the runtime firmware. These results were
5879 * obtained on first boot from the initialization firmware.
5880 */
5881static int
5882iwn5000_send_calibration(struct iwn_softc *sc)
5883{
5884 int idx, error;
5885
5886 for (idx = 0; idx < 5; idx++) {
5887 if (sc->calibcmd[idx].buf == NULL)
5888 continue; /* No results available. */
5889 DPRINTF(sc, IWN_DEBUG_CALIBRATE,
5890 "send calibration result idx=%d len=%d\n", idx,
5891 sc->calibcmd[idx].len);
5892 error = iwn_cmd(sc, IWN_CMD_PHY_CALIB, sc->calibcmd[idx].buf,
5893 sc->calibcmd[idx].len, 0);
5894 if (error != 0) {
5895 device_printf(sc->sc_dev,
5896 "%s: could not send calibration result, error %d\n",
5897 __func__, error);
5898 return error;
5899 }
5900 }
5901 return 0;
5902}
5903
5904static int
5905iwn5000_send_wimax_coex(struct iwn_softc *sc)
5906{
5907 struct iwn5000_wimax_coex wimax;
5908
5909#ifdef notyet
5910 if (sc->hw_type == IWN_HW_REV_TYPE_6050) {
5911 /* Enable WiMAX coexistence for combo adapters. */
5912 wimax.flags =
5913 IWN_WIMAX_COEX_ASSOC_WA_UNMASK |
5914 IWN_WIMAX_COEX_UNASSOC_WA_UNMASK |
5915 IWN_WIMAX_COEX_STA_TABLE_VALID |
5916 IWN_WIMAX_COEX_ENABLE;
5917 memcpy(wimax.events, iwn6050_wimax_events,
5918 sizeof iwn6050_wimax_events);
5919 } else
5920#endif
5921 {
5922 /* Disable WiMAX coexistence. */
5923 wimax.flags = 0;
5924 memset(wimax.events, 0, sizeof wimax.events);
5925 }
5926 DPRINTF(sc, IWN_DEBUG_RESET, "%s: Configuring WiMAX coexistence\n",
5927 __func__);
5928 return iwn_cmd(sc, IWN5000_CMD_WIMAX_COEX, &wimax, sizeof wimax, 0);
5929}
5930
5931static int
5932iwn5000_crystal_calib(struct iwn_softc *sc)
5933{
5934 struct iwn5000_phy_calib_crystal cmd;
5935
5936 memset(&cmd, 0, sizeof cmd);
5937 cmd.code = IWN5000_PHY_CALIB_CRYSTAL;
5938 cmd.ngroups = 1;
5939 cmd.isvalid = 1;
5940 cmd.cap_pin[0] = le32toh(sc->eeprom_crystal) & 0xff;
5941 cmd.cap_pin[1] = (le32toh(sc->eeprom_crystal) >> 16) & 0xff;
5942 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "sending crystal calibration %d, %d\n",
5943 cmd.cap_pin[0], cmd.cap_pin[1]);
5944 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0);
5945}
5946
5947static int
5948iwn5000_temp_offset_calib(struct iwn_softc *sc)
5949{
5950 struct iwn5000_phy_calib_temp_offset cmd;
5951
5952 memset(&cmd, 0, sizeof cmd);
5953 cmd.code = IWN5000_PHY_CALIB_TEMP_OFFSET;
5954 cmd.ngroups = 1;
5955 cmd.isvalid = 1;
5956 if (sc->eeprom_temp != 0)
5957 cmd.offset = htole16(sc->eeprom_temp);
5958 else
5959 cmd.offset = htole16(IWN_DEFAULT_TEMP_OFFSET);
5960 DPRINTF(sc, IWN_DEBUG_CALIBRATE, "setting radio sensor offset to %d\n",
5961 le16toh(cmd.offset));
5962 return iwn_cmd(sc, IWN_CMD_PHY_CALIB, &cmd, sizeof cmd, 0);
5963}
5964
5965/*
5966 * This function is called after the runtime firmware notifies us of its
5967 * readiness (called in a process context).
5968 */
5969static int
5970iwn4965_post_alive(struct iwn_softc *sc)
5971{
5972 int error, qid;
5973
5974 if ((error = iwn_nic_lock(sc)) != 0)
5975 return error;
5976
5977 /* Clear TX scheduler state in SRAM. */
5978 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR);
5979 iwn_mem_set_region_4(sc, sc->sched_base + IWN4965_SCHED_CTX_OFF, 0,
5980 IWN4965_SCHED_CTX_LEN / sizeof (uint32_t));
5981
5982 /* Set physical address of TX scheduler rings (1KB aligned). */
5983 iwn_prph_write(sc, IWN4965_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10);
5984
5985 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY);
5986
5987 /* Disable chain mode for all our 16 queues. */
5988 iwn_prph_write(sc, IWN4965_SCHED_QCHAIN_SEL, 0);
5989
5990 for (qid = 0; qid < IWN4965_NTXQUEUES; qid++) {
5991 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_RDPTR(qid), 0);
5992 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0);
5993
5994 /* Set scheduler window size. */
5995 iwn_mem_write(sc, sc->sched_base +
5996 IWN4965_SCHED_QUEUE_OFFSET(qid), IWN_SCHED_WINSZ);
5997 /* Set scheduler frame limit. */
5998 iwn_mem_write(sc, sc->sched_base +
5999 IWN4965_SCHED_QUEUE_OFFSET(qid) + 4,
6000 IWN_SCHED_LIMIT << 16);
6001 }
6002
6003 /* Enable interrupts for all our 16 queues. */
6004 iwn_prph_write(sc, IWN4965_SCHED_INTR_MASK, 0xffff);
6005 /* Identify TX FIFO rings (0-7). */
6006 iwn_prph_write(sc, IWN4965_SCHED_TXFACT, 0xff);
6007
6008 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */
6009 for (qid = 0; qid < 7; qid++) {
6010 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 };
6011 iwn_prph_write(sc, IWN4965_SCHED_QUEUE_STATUS(qid),
6012 IWN4965_TXQ_STATUS_ACTIVE | qid2fifo[qid] << 1);
6013 }
6014 iwn_nic_unlock(sc);
6015 return 0;
6016}
6017
6018/*
6019 * This function is called after the initialization or runtime firmware
6020 * notifies us of its readiness (called in a process context).
6021 */
6022static int
6023iwn5000_post_alive(struct iwn_softc *sc)
6024{
6025 int error, qid;
6026
6027 /* Switch to using ICT interrupt mode. */
6028 iwn5000_ict_reset(sc);
6029
6030 if ((error = iwn_nic_lock(sc)) != 0)
6031 return error;
6032
6033 /* Clear TX scheduler state in SRAM. */
6034 sc->sched_base = iwn_prph_read(sc, IWN_SCHED_SRAM_ADDR);
6035 iwn_mem_set_region_4(sc, sc->sched_base + IWN5000_SCHED_CTX_OFF, 0,
6036 IWN5000_SCHED_CTX_LEN / sizeof (uint32_t));
6037
6038 /* Set physical address of TX scheduler rings (1KB aligned). */
6039 iwn_prph_write(sc, IWN5000_SCHED_DRAM_ADDR, sc->sched_dma.paddr >> 10);
6040
6041 IWN_SETBITS(sc, IWN_FH_TX_CHICKEN, IWN_FH_TX_CHICKEN_SCHED_RETRY);
6042
6043 /* Enable chain mode for all queues, except command queue. */
6044 iwn_prph_write(sc, IWN5000_SCHED_QCHAIN_SEL, 0xfffef);
6045 iwn_prph_write(sc, IWN5000_SCHED_AGGR_SEL, 0);
6046
6047 for (qid = 0; qid < IWN5000_NTXQUEUES; qid++) {
6048 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_RDPTR(qid), 0);
6049 IWN_WRITE(sc, IWN_HBUS_TARG_WRPTR, qid << 8 | 0);
6050
6051 iwn_mem_write(sc, sc->sched_base +
6052 IWN5000_SCHED_QUEUE_OFFSET(qid), 0);
6053 /* Set scheduler window size and frame limit. */
6054 iwn_mem_write(sc, sc->sched_base +
6055 IWN5000_SCHED_QUEUE_OFFSET(qid) + 4,
6056 IWN_SCHED_LIMIT << 16 | IWN_SCHED_WINSZ);
6057 }
6058
6059 /* Enable interrupts for all our 20 queues. */
6060 iwn_prph_write(sc, IWN5000_SCHED_INTR_MASK, 0xfffff);
6061 /* Identify TX FIFO rings (0-7). */
6062 iwn_prph_write(sc, IWN5000_SCHED_TXFACT, 0xff);
6063
6064 /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */
6065 for (qid = 0; qid < 7; qid++) {
6066 static uint8_t qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 };
6067 iwn_prph_write(sc, IWN5000_SCHED_QUEUE_STATUS(qid),
6068 IWN5000_TXQ_STATUS_ACTIVE | qid2fifo[qid]);
6069 }
6070 iwn_nic_unlock(sc);
6071
6072 /* Configure WiMAX coexistence for combo adapters. */
6073 error = iwn5000_send_wimax_coex(sc);
6074 if (error != 0) {
6075 device_printf(sc->sc_dev,
6076 "%s: could not configure WiMAX coexistence, error %d\n",
6077 __func__, error);
6078 return error;
6079 }
6080 if (sc->hw_type != IWN_HW_REV_TYPE_5150) {
6081 /* Perform crystal calibration. */
6082 error = iwn5000_crystal_calib(sc);
6083 if (error != 0) {
6084 device_printf(sc->sc_dev,
6085 "%s: crystal calibration failed, error %d\n",
6086 __func__, error);
6087 return error;
6088 }
6089 }
6090 if (!(sc->sc_flags & IWN_FLAG_CALIB_DONE)) {
6091 /* Query calibration from the initialization firmware. */
6092 if ((error = iwn5000_query_calibration(sc)) != 0) {
6093 device_printf(sc->sc_dev,
6094 "%s: could not query calibration, error %d\n",
6095 __func__, error);
6096 return error;
6097 }
6098 /*
6099 * We have the calibration results now, reboot with the
6100 * runtime firmware (call ourselves recursively!)
6101 */
6102 iwn_hw_stop(sc);
6103 error = iwn_hw_init(sc);
6104 } else {
6105 /* Send calibration results to runtime firmware. */
6106 error = iwn5000_send_calibration(sc);
6107 }
6108 return error;
6109}
6110
6111/*
6112 * The firmware boot code is small and is intended to be copied directly into
6113 * the NIC internal memory (no DMA transfer).
6114 */
6115static int
6116iwn4965_load_bootcode(struct iwn_softc *sc, const uint8_t *ucode, int size)
6117{
6118 int error, ntries;
6119
6120 size /= sizeof (uint32_t);
6121
6122 if ((error = iwn_nic_lock(sc)) != 0)
6123 return error;
6124
6125 /* Copy microcode image into NIC memory. */
6126 iwn_prph_write_region_4(sc, IWN_BSM_SRAM_BASE,
6127 (const uint32_t *)ucode, size);
6128
6129 iwn_prph_write(sc, IWN_BSM_WR_MEM_SRC, 0);
6130 iwn_prph_write(sc, IWN_BSM_WR_MEM_DST, IWN_FW_TEXT_BASE);
6131 iwn_prph_write(sc, IWN_BSM_WR_DWCOUNT, size);
6132
6133 /* Start boot load now. */
6134 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START);
6135
6136 /* Wait for transfer to complete. */
6137 for (ntries = 0; ntries < 1000; ntries++) {
6138 if (!(iwn_prph_read(sc, IWN_BSM_WR_CTRL) &
6139 IWN_BSM_WR_CTRL_START))
6140 break;
6141 DELAY(10);
6142 }
6143 if (ntries == 1000) {
6144 device_printf(sc->sc_dev, "%s: could not load boot firmware\n",
6145 __func__);
6146 iwn_nic_unlock(sc);
6147 return ETIMEDOUT;
6148 }
6149
6150 /* Enable boot after power up. */
6151 iwn_prph_write(sc, IWN_BSM_WR_CTRL, IWN_BSM_WR_CTRL_START_EN);
6152
6153 iwn_nic_unlock(sc);
6154 return 0;
6155}
6156
6157static int
6158iwn4965_load_firmware(struct iwn_softc *sc)
6159{
6160 struct iwn_fw_info *fw = &sc->fw;
6161 struct iwn_dma_info *dma = &sc->fw_dma;
6162 int error;
6163
6164 /* Copy initialization sections into pre-allocated DMA-safe memory. */
6165 memcpy(dma->vaddr, fw->init.data, fw->init.datasz);
6166 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE);
6167 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ,
6168 fw->init.text, fw->init.textsz);
6169 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE);
6170
6171 /* Tell adapter where to find initialization sections. */
6172 if ((error = iwn_nic_lock(sc)) != 0)
6173 return error;
6174 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4);
6175 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->init.datasz);
6176 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR,
6177 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4);
6178 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE, fw->init.textsz);
6179 iwn_nic_unlock(sc);
6180
6181 /* Load firmware boot code. */
6182 error = iwn4965_load_bootcode(sc, fw->boot.text, fw->boot.textsz);
6183 if (error != 0) {
6184 device_printf(sc->sc_dev, "%s: could not load boot firmware\n",
6185 __func__);
6186 return error;
6187 }
6188 /* Now press "execute". */
6189 IWN_WRITE(sc, IWN_RESET, 0);
6190
6191 /* Wait at most one second for first alive notification. */
6192 if ((error = msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", hz)) != 0) {
6193 device_printf(sc->sc_dev,
6194 "%s: timeout waiting for adapter to initialize, error %d\n",
6195 __func__, error);
6196 return error;
6197 }
6198
6199 /* Retrieve current temperature for initial TX power calibration. */
6200 sc->rawtemp = sc->ucode_info.temp[3].chan20MHz;
6201 sc->temp = iwn4965_get_temperature(sc);
6202
6203 /* Copy runtime sections into pre-allocated DMA-safe memory. */
6204 memcpy(dma->vaddr, fw->main.data, fw->main.datasz);
6205 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE);
6206 memcpy(dma->vaddr + IWN4965_FW_DATA_MAXSZ,
6207 fw->main.text, fw->main.textsz);
6208 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE);
6209
6210 /* Tell adapter where to find runtime sections. */
6211 if ((error = iwn_nic_lock(sc)) != 0)
6212 return error;
6213 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_ADDR, dma->paddr >> 4);
6214 iwn_prph_write(sc, IWN_BSM_DRAM_DATA_SIZE, fw->main.datasz);
6215 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_ADDR,
6216 (dma->paddr + IWN4965_FW_DATA_MAXSZ) >> 4);
6217 iwn_prph_write(sc, IWN_BSM_DRAM_TEXT_SIZE,
6218 IWN_FW_UPDATED | fw->main.textsz);
6219 iwn_nic_unlock(sc);
6220
6221 return 0;
6222}
6223
6224static int
6225iwn5000_load_firmware_section(struct iwn_softc *sc, uint32_t dst,
6226 const uint8_t *section, int size)
6227{
6228 struct iwn_dma_info *dma = &sc->fw_dma;
6229 int error;
6230
6231 /* Copy firmware section into pre-allocated DMA-safe memory. */
6232 memcpy(dma->vaddr, section, size);
6233 bus_dmamap_sync(dma->tag, dma->map, BUS_DMASYNC_PREWRITE);
6234
6235 if ((error = iwn_nic_lock(sc)) != 0)
6236 return error;
6237
6238 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL),
6239 IWN_FH_TX_CONFIG_DMA_PAUSE);
6240
6241 IWN_WRITE(sc, IWN_FH_SRAM_ADDR(IWN_SRVC_DMACHNL), dst);
6242 IWN_WRITE(sc, IWN_FH_TFBD_CTRL0(IWN_SRVC_DMACHNL),
6243 IWN_LOADDR(dma->paddr));
6244 IWN_WRITE(sc, IWN_FH_TFBD_CTRL1(IWN_SRVC_DMACHNL),
6245 IWN_HIADDR(dma->paddr) << 28 | size);
6246 IWN_WRITE(sc, IWN_FH_TXBUF_STATUS(IWN_SRVC_DMACHNL),
6247 IWN_FH_TXBUF_STATUS_TBNUM(1) |
6248 IWN_FH_TXBUF_STATUS_TBIDX(1) |
6249 IWN_FH_TXBUF_STATUS_TFBD_VALID);
6250
6251 /* Kick Flow Handler to start DMA transfer. */
6252 IWN_WRITE(sc, IWN_FH_TX_CONFIG(IWN_SRVC_DMACHNL),
6253 IWN_FH_TX_CONFIG_DMA_ENA | IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD);
6254
6255 iwn_nic_unlock(sc);
6256
6257 /* Wait at most five seconds for FH DMA transfer to complete. */
6258 return msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", 5 * hz);
6259}
6260
6261static int
6262iwn5000_load_firmware(struct iwn_softc *sc)
6263{
6264 struct iwn_fw_part *fw;
6265 int error;
6266
6267 /* Load the initialization firmware on first boot only. */
6268 fw = (sc->sc_flags & IWN_FLAG_CALIB_DONE) ?
6269 &sc->fw.main : &sc->fw.init;
6270
6271 error = iwn5000_load_firmware_section(sc, IWN_FW_TEXT_BASE,
6272 fw->text, fw->textsz);
6273 if (error != 0) {
6274 device_printf(sc->sc_dev,
6275 "%s: could not load firmware %s section, error %d\n",
6276 __func__, ".text", error);
6277 return error;
6278 }
6279 error = iwn5000_load_firmware_section(sc, IWN_FW_DATA_BASE,
6280 fw->data, fw->datasz);
6281 if (error != 0) {
6282 device_printf(sc->sc_dev,
6283 "%s: could not load firmware %s section, error %d\n",
6284 __func__, ".data", error);
6285 return error;
6286 }
6287
6288 /* Now press "execute". */
6289 IWN_WRITE(sc, IWN_RESET, 0);
6290 return 0;
6291}
6292
6293/*
6294 * Extract text and data sections from a legacy firmware image.
6295 */
6296static int
6297iwn_read_firmware_leg(struct iwn_softc *sc, struct iwn_fw_info *fw)
6298{
6299 const uint32_t *ptr;
6300 size_t hdrlen = 24;
6301 uint32_t rev;
6302
6303 ptr = (const uint32_t *)fw->data;
6304 rev = le32toh(*ptr++);
6305
6306 /* Check firmware API version. */
6307 if (IWN_FW_API(rev) <= 1) {
6308 device_printf(sc->sc_dev,
6309 "%s: bad firmware, need API version >=2\n", __func__);
6310 return EINVAL;
6311 }
6312 if (IWN_FW_API(rev) >= 3) {
6313 /* Skip build number (version 2 header). */
6314 hdrlen += 4;
6315 ptr++;
6316 }
6317 if (fw->size < hdrlen) {
6318 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n",
6319 __func__, fw->size);
6320 return EINVAL;
6321 }
6322 fw->main.textsz = le32toh(*ptr++);
6323 fw->main.datasz = le32toh(*ptr++);
6324 fw->init.textsz = le32toh(*ptr++);
6325 fw->init.datasz = le32toh(*ptr++);
6326 fw->boot.textsz = le32toh(*ptr++);
6327
6328 /* Check that all firmware sections fit. */
6329 if (fw->size < hdrlen + fw->main.textsz + fw->main.datasz +
6330 fw->init.textsz + fw->init.datasz + fw->boot.textsz) {
6331 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n",
6332 __func__, fw->size);
6333 return EINVAL;
6334 }
6335
6336 /* Get pointers to firmware sections. */
6337 fw->main.text = (const uint8_t *)ptr;
6338 fw->main.data = fw->main.text + fw->main.textsz;
6339 fw->init.text = fw->main.data + fw->main.datasz;
6340 fw->init.data = fw->init.text + fw->init.textsz;
6341 fw->boot.text = fw->init.data + fw->init.datasz;
6342 return 0;
6343}
6344
6345/*
6346 * Extract text and data sections from a TLV firmware image.
6347 */
6348static int
6349iwn_read_firmware_tlv(struct iwn_softc *sc, struct iwn_fw_info *fw,
6350 uint16_t alt)
6351{
6352 const struct iwn_fw_tlv_hdr *hdr;
6353 const struct iwn_fw_tlv *tlv;
6354 const uint8_t *ptr, *end;
6355 uint64_t altmask;
6356 uint32_t len, tmp;
6357
6358 if (fw->size < sizeof (*hdr)) {
6359 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n",
6360 __func__, fw->size);
6361 return EINVAL;
6362 }
6363 hdr = (const struct iwn_fw_tlv_hdr *)fw->data;
6364 if (hdr->signature != htole32(IWN_FW_SIGNATURE)) {
6365 device_printf(sc->sc_dev, "%s: bad firmware signature 0x%08x\n",
6366 __func__, le32toh(hdr->signature));
6367 return EINVAL;
6368 }
6369 DPRINTF(sc, IWN_DEBUG_RESET, "FW: \"%.64s\", build 0x%x\n", hdr->descr,
6370 le32toh(hdr->build));
6371
6372 /*
6373 * Select the closest supported alternative that is less than
6374 * or equal to the specified one.
6375 */
6376 altmask = le64toh(hdr->altmask);
6377 while (alt > 0 && !(altmask & (1ULL << alt)))
6378 alt--; /* Downgrade. */
6379 DPRINTF(sc, IWN_DEBUG_RESET, "using alternative %d\n", alt);
6380
6381 ptr = (const uint8_t *)(hdr + 1);
6382 end = (const uint8_t *)(fw->data + fw->size);
6383
6384 /* Parse type-length-value fields. */
6385 while (ptr + sizeof (*tlv) <= end) {
6386 tlv = (const struct iwn_fw_tlv *)ptr;
6387 len = le32toh(tlv->len);
6388
6389 ptr += sizeof (*tlv);
6390 if (ptr + len > end) {
6391 device_printf(sc->sc_dev,
6392 "%s: firmware too short: %zu bytes\n", __func__,
6393 fw->size);
6394 return EINVAL;
6395 }
6396 /* Skip other alternatives. */
6397 if (tlv->alt != 0 && tlv->alt != htole16(alt))
6398 goto next;
6399
6400 switch (le16toh(tlv->type)) {
6401 case IWN_FW_TLV_MAIN_TEXT:
6402 fw->main.text = ptr;
6403 fw->main.textsz = len;
6404 break;
6405 case IWN_FW_TLV_MAIN_DATA:
6406 fw->main.data = ptr;
6407 fw->main.datasz = len;
6408 break;
6409 case IWN_FW_TLV_INIT_TEXT:
6410 fw->init.text = ptr;
6411 fw->init.textsz = len;
6412 break;
6413 case IWN_FW_TLV_INIT_DATA:
6414 fw->init.data = ptr;
6415 fw->init.datasz = len;
6416 break;
6417 case IWN_FW_TLV_BOOT_TEXT:
6418 fw->boot.text = ptr;
6419 fw->boot.textsz = len;
6420 break;
6421 case IWN_FW_TLV_ENH_SENS:
6422 if (!len)
6423 sc->sc_flags |= IWN_FLAG_ENH_SENS;
6424 break;
6425 case IWN_FW_TLV_PHY_CALIB:
6426 tmp = htole32(*ptr);
6427 if (tmp < 253) {
6428 sc->reset_noise_gain = tmp;
6429 sc->noise_gain = tmp + 1;
6430 }
6431 break;
6432 default:
6433 DPRINTF(sc, IWN_DEBUG_RESET,
6434 "TLV type %d not handled\n", le16toh(tlv->type));
6435 break;
6436 }
6437 next: /* TLV fields are 32-bit aligned. */
6438 ptr += (len + 3) & ~3;
6439 }
6440 return 0;
6441}
6442
6443static int
6444iwn_read_firmware(struct iwn_softc *sc)
6445{
6446 struct iwn_fw_info *fw = &sc->fw;
6447 int error;
6448
6449 IWN_UNLOCK(sc);
6450
6451 memset(fw, 0, sizeof (*fw));
6452
6453 /* Read firmware image from filesystem. */
6454 sc->fw_fp = firmware_get(sc->fwname);
6455 if (sc->fw_fp == NULL) {
6456 device_printf(sc->sc_dev, "%s: could not read firmware %s\n",
6457 __func__, sc->fwname);
6458 IWN_LOCK(sc);
6459 return EINVAL;
6460 }
6461 IWN_LOCK(sc);
6462
6463 fw->size = sc->fw_fp->datasize;
6464 fw->data = (const uint8_t *)sc->fw_fp->data;
6465 if (fw->size < sizeof (uint32_t)) {
6466 device_printf(sc->sc_dev, "%s: firmware too short: %zu bytes\n",
6467 __func__, fw->size);
6468 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD);
6469 sc->fw_fp = NULL;
6470 return EINVAL;
6471 }
6472
6473 /* Retrieve text and data sections. */
6474 if (*(const uint32_t *)fw->data != 0) /* Legacy image. */
6475 error = iwn_read_firmware_leg(sc, fw);
6476 else
6477 error = iwn_read_firmware_tlv(sc, fw, 1);
6478 if (error != 0) {
6479 device_printf(sc->sc_dev,
6480 "%s: could not read firmware sections, error %d\n",
6481 __func__, error);
6482 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD);
6483 sc->fw_fp = NULL;
6484 return error;
6485 }
6486
6487 /* Make sure text and data sections fit in hardware memory. */
6488 if (fw->main.textsz > sc->fw_text_maxsz ||
6489 fw->main.datasz > sc->fw_data_maxsz ||
6490 fw->init.textsz > sc->fw_text_maxsz ||
6491 fw->init.datasz > sc->fw_data_maxsz ||
6492 fw->boot.textsz > IWN_FW_BOOT_TEXT_MAXSZ ||
6493 (fw->boot.textsz & 3) != 0) {
6494 device_printf(sc->sc_dev, "%s: firmware sections too large\n",
6495 __func__);
6496 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD);
6497 sc->fw_fp = NULL;
6498 return EINVAL;
6499 }
6500
6501 /* We can proceed with loading the firmware. */
6502 return 0;
6503}
6504
6505static int
6506iwn_clock_wait(struct iwn_softc *sc)
6507{
6508 int ntries;
6509
6510 /* Set "initialization complete" bit. */
6511 IWN_SETBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE);
6512
6513 /* Wait for clock stabilization. */
6514 for (ntries = 0; ntries < 2500; ntries++) {
6515 if (IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_MAC_CLOCK_READY)
6516 return 0;
6517 DELAY(10);
6518 }
6519 device_printf(sc->sc_dev,
6520 "%s: timeout waiting for clock stabilization\n", __func__);
6521 return ETIMEDOUT;
6522}
6523
6524static int
6525iwn_apm_init(struct iwn_softc *sc)
6526{
6527 uint32_t reg;
6528 int error;
6529
6530 /* Disable L0s exit timer (NMI bug workaround). */
6531 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_DIS_L0S_TIMER);
6532 /* Don't wait for ICH L0s (ICH bug workaround). */
6533 IWN_SETBITS(sc, IWN_GIO_CHICKEN, IWN_GIO_CHICKEN_L1A_NO_L0S_RX);
6534
6535 /* Set FH wait threshold to max (HW bug under stress workaround). */
6536 IWN_SETBITS(sc, IWN_DBG_HPET_MEM, 0xffff0000);
6537
6538 /* Enable HAP INTA to move adapter from L1a to L0s. */
6539 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_HAP_WAKE_L1A);
6540
6541 /* Retrieve PCIe Active State Power Management (ASPM). */
6542 reg = pci_read_config(sc->sc_dev, sc->sc_cap_off + 0x10, 1);
6543 /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */
6544 if (reg & 0x02) /* L1 Entry enabled. */
6545 IWN_SETBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA);
6546 else
6547 IWN_CLRBITS(sc, IWN_GIO, IWN_GIO_L0S_ENA);
6548
6549 if (sc->hw_type != IWN_HW_REV_TYPE_4965 &&
6550 sc->hw_type <= IWN_HW_REV_TYPE_1000)
6551 IWN_SETBITS(sc, IWN_ANA_PLL, IWN_ANA_PLL_INIT);
6552
6553 /* Wait for clock stabilization before accessing prph. */
6554 if ((error = iwn_clock_wait(sc)) != 0)
6555 return error;
6556
6557 if ((error = iwn_nic_lock(sc)) != 0)
6558 return error;
6559 if (sc->hw_type == IWN_HW_REV_TYPE_4965) {
6560 /* Enable DMA and BSM (Bootstrap State Machine). */
6561 iwn_prph_write(sc, IWN_APMG_CLK_EN,
6562 IWN_APMG_CLK_CTRL_DMA_CLK_RQT |
6563 IWN_APMG_CLK_CTRL_BSM_CLK_RQT);
6564 } else {
6565 /* Enable DMA. */
6566 iwn_prph_write(sc, IWN_APMG_CLK_EN,
6567 IWN_APMG_CLK_CTRL_DMA_CLK_RQT);
6568 }
6569 DELAY(20);
6570 /* Disable L1-Active. */
6571 iwn_prph_setbits(sc, IWN_APMG_PCI_STT, IWN_APMG_PCI_STT_L1A_DIS);
6572 iwn_nic_unlock(sc);
6573
6574 return 0;
6575}
6576
6577static void
6578iwn_apm_stop_master(struct iwn_softc *sc)
6579{
6580 int ntries;
6581
6582 /* Stop busmaster DMA activity. */
6583 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_STOP_MASTER);
6584 for (ntries = 0; ntries < 100; ntries++) {
6585 if (IWN_READ(sc, IWN_RESET) & IWN_RESET_MASTER_DISABLED)
6586 return;
6587 DELAY(10);
6588 }
6589 device_printf(sc->sc_dev, "%s: timeout waiting for master\n", __func__);
6590}
6591
6592static void
6593iwn_apm_stop(struct iwn_softc *sc)
6594{
6595 iwn_apm_stop_master(sc);
6596
6597 /* Reset the entire device. */
6598 IWN_SETBITS(sc, IWN_RESET, IWN_RESET_SW);
6599 DELAY(10);
6600 /* Clear "initialization complete" bit. */
6601 IWN_CLRBITS(sc, IWN_GP_CNTRL, IWN_GP_CNTRL_INIT_DONE);
6602}
6603
6604static int
6605iwn4965_nic_config(struct iwn_softc *sc)
6606{
6607 if (IWN_RFCFG_TYPE(sc->rfcfg) == 1) {
6608 /*
6609 * I don't believe this to be correct but this is what the
6610 * vendor driver is doing. Probably the bits should not be
6611 * shifted in IWN_RFCFG_*.
6612 */
6613 IWN_SETBITS(sc, IWN_HW_IF_CONFIG,
6614 IWN_RFCFG_TYPE(sc->rfcfg) |
6615 IWN_RFCFG_STEP(sc->rfcfg) |
6616 IWN_RFCFG_DASH(sc->rfcfg));
6617 }
6618 IWN_SETBITS(sc, IWN_HW_IF_CONFIG,
6619 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI);
6620 return 0;
6621}
6622
6623static int
6624iwn5000_nic_config(struct iwn_softc *sc)
6625{
6626 uint32_t tmp;
6627 int error;
6628
6629 if (IWN_RFCFG_TYPE(sc->rfcfg) < 3) {
6630 IWN_SETBITS(sc, IWN_HW_IF_CONFIG,
6631 IWN_RFCFG_TYPE(sc->rfcfg) |
6632 IWN_RFCFG_STEP(sc->rfcfg) |
6633 IWN_RFCFG_DASH(sc->rfcfg));
6634 }
6635 IWN_SETBITS(sc, IWN_HW_IF_CONFIG,
6636 IWN_HW_IF_CONFIG_RADIO_SI | IWN_HW_IF_CONFIG_MAC_SI);
6637
6638 if ((error = iwn_nic_lock(sc)) != 0)
6639 return error;
6640 iwn_prph_setbits(sc, IWN_APMG_PS, IWN_APMG_PS_EARLY_PWROFF_DIS);
6641
6642 if (sc->hw_type == IWN_HW_REV_TYPE_1000) {
6643 /*
6644 * Select first Switching Voltage Regulator (1.32V) to
6645 * solve a stability issue related to noisy DC2DC line
6646 * in the silicon of 1000 Series.
6647 */
6648 tmp = iwn_prph_read(sc, IWN_APMG_DIGITAL_SVR);
6649 tmp &= ~IWN_APMG_DIGITAL_SVR_VOLTAGE_MASK;
6650 tmp |= IWN_APMG_DIGITAL_SVR_VOLTAGE_1_32;
6651 iwn_prph_write(sc, IWN_APMG_DIGITAL_SVR, tmp);
6652 }
6653 iwn_nic_unlock(sc);
6654
6655 if (sc->sc_flags & IWN_FLAG_INTERNAL_PA) {
6656 /* Use internal power amplifier only. */
6657 IWN_WRITE(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_RADIO_2X2_IPA);
6658 }
6659 if ((sc->hw_type == IWN_HW_REV_TYPE_6050 ||
6660 sc->hw_type == IWN_HW_REV_TYPE_6005) && sc->calib_ver >= 6) {
6661 /* Indicate that ROM calibration version is >=6. */
6662 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_CALIB_VER6);
6663 }
6664 if (sc->hw_type == IWN_HW_REV_TYPE_6005)
6665 IWN_SETBITS(sc, IWN_GP_DRIVER, IWN_GP_DRIVER_6050_1X2);
6666 return 0;
6667}
6668
6669/*
6670 * Take NIC ownership over Intel Active Management Technology (AMT).
6671 */
6672static int
6673iwn_hw_prepare(struct iwn_softc *sc)
6674{
6675 int ntries;
6676
6677 /* Check if hardware is ready. */
6678 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY);
6679 for (ntries = 0; ntries < 5; ntries++) {
6680 if (IWN_READ(sc, IWN_HW_IF_CONFIG) &
6681 IWN_HW_IF_CONFIG_NIC_READY)
6682 return 0;
6683 DELAY(10);
6684 }
6685
6686 /* Hardware not ready, force into ready state. */
6687 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_PREPARE);
6688 for (ntries = 0; ntries < 15000; ntries++) {
6689 if (!(IWN_READ(sc, IWN_HW_IF_CONFIG) &
6690 IWN_HW_IF_CONFIG_PREPARE_DONE))
6691 break;
6692 DELAY(10);
6693 }
6694 if (ntries == 15000)
6695 return ETIMEDOUT;
6696
6697 /* Hardware should be ready now. */
6698 IWN_SETBITS(sc, IWN_HW_IF_CONFIG, IWN_HW_IF_CONFIG_NIC_READY);
6699 for (ntries = 0; ntries < 5; ntries++) {
6700 if (IWN_READ(sc, IWN_HW_IF_CONFIG) &
6701 IWN_HW_IF_CONFIG_NIC_READY)
6702 return 0;
6703 DELAY(10);
6704 }
6705 return ETIMEDOUT;
6706}
6707
6708static int
6709iwn_hw_init(struct iwn_softc *sc)
6710{
6711 struct iwn_ops *ops = &sc->ops;
6712 int error, chnl, qid;
6713
6714 /* Clear pending interrupts. */
6715 IWN_WRITE(sc, IWN_INT, 0xffffffff);
6716
6717 if ((error = iwn_apm_init(sc)) != 0) {
6718 device_printf(sc->sc_dev,
6719 "%s: could not power ON adapter, error %d\n", __func__,
6720 error);
6721 return error;
6722 }
6723
6724 /* Select VMAIN power source. */
6725 if ((error = iwn_nic_lock(sc)) != 0)
6726 return error;
6727 iwn_prph_clrbits(sc, IWN_APMG_PS, IWN_APMG_PS_PWR_SRC_MASK);
6728 iwn_nic_unlock(sc);
6729
6730 /* Perform adapter-specific initialization. */
6731 if ((error = ops->nic_config(sc)) != 0)
6732 return error;
6733
6734 /* Initialize RX ring. */
6735 if ((error = iwn_nic_lock(sc)) != 0)
6736 return error;
6737 IWN_WRITE(sc, IWN_FH_RX_CONFIG, 0);
6738 IWN_WRITE(sc, IWN_FH_RX_WPTR, 0);
6739 /* Set physical address of RX ring (256-byte aligned). */
6740 IWN_WRITE(sc, IWN_FH_RX_BASE, sc->rxq.desc_dma.paddr >> 8);
6741 /* Set physical address of RX status (16-byte aligned). */
6742 IWN_WRITE(sc, IWN_FH_STATUS_WPTR, sc->rxq.stat_dma.paddr >> 4);
6743 /* Enable RX. */
6744 IWN_WRITE(sc, IWN_FH_RX_CONFIG,
6745 IWN_FH_RX_CONFIG_ENA |
6746 IWN_FH_RX_CONFIG_IGN_RXF_EMPTY | /* HW bug workaround */
6747 IWN_FH_RX_CONFIG_IRQ_DST_HOST |
6748 IWN_FH_RX_CONFIG_SINGLE_FRAME |
6749 IWN_FH_RX_CONFIG_RB_TIMEOUT(0) |
6750 IWN_FH_RX_CONFIG_NRBD(IWN_RX_RING_COUNT_LOG));
6751 iwn_nic_unlock(sc);
6752 IWN_WRITE(sc, IWN_FH_RX_WPTR, (IWN_RX_RING_COUNT - 1) & ~7);
6753
6754 if ((error = iwn_nic_lock(sc)) != 0)
6755 return error;
6756
6757 /* Initialize TX scheduler. */
6758 iwn_prph_write(sc, sc->sched_txfact_addr, 0);
6759
6760 /* Set physical address of "keep warm" page (16-byte aligned). */
6761 IWN_WRITE(sc, IWN_FH_KW_ADDR, sc->kw_dma.paddr >> 4);
6762
6763 /* Initialize TX rings. */
6764 for (qid = 0; qid < sc->ntxqs; qid++) {
6765 struct iwn_tx_ring *txq = &sc->txq[qid];
6766
6767 /* Set physical address of TX ring (256-byte aligned). */
6768 IWN_WRITE(sc, IWN_FH_CBBC_QUEUE(qid),
6769 txq->desc_dma.paddr >> 8);
6770 }
6771 iwn_nic_unlock(sc);
6772
6773 /* Enable DMA channels. */
6774 for (chnl = 0; chnl < sc->ndmachnls; chnl++) {
6775 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl),
6776 IWN_FH_TX_CONFIG_DMA_ENA |
6777 IWN_FH_TX_CONFIG_DMA_CREDIT_ENA);
6778 }
6779
6780 /* Clear "radio off" and "commands blocked" bits. */
6781 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL);
6782 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_CMD_BLOCKED);
6783
6784 /* Clear pending interrupts. */
6785 IWN_WRITE(sc, IWN_INT, 0xffffffff);
6786 /* Enable interrupt coalescing. */
6787 IWN_WRITE(sc, IWN_INT_COALESCING, 512 / 8);
6788 /* Enable interrupts. */
6789 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
6790
6791 /* _Really_ make sure "radio off" bit is cleared! */
6792 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL);
6793 IWN_WRITE(sc, IWN_UCODE_GP1_CLR, IWN_UCODE_GP1_RFKILL);
6794
6795 /* Enable shadow registers. */
6796 if (sc->hw_type >= IWN_HW_REV_TYPE_6000)
6797 IWN_SETBITS(sc, IWN_SHADOW_REG_CTRL, 0x800fffff);
6798
6799 if ((error = ops->load_firmware(sc)) != 0) {
6800 device_printf(sc->sc_dev,
6801 "%s: could not load firmware, error %d\n", __func__,
6802 error);
6803 return error;
6804 }
6805 /* Wait at most one second for firmware alive notification. */
6806 if ((error = msleep(sc, &sc->sc_mtx, PCATCH, "iwninit", hz)) != 0) {
6807 device_printf(sc->sc_dev,
6808 "%s: timeout waiting for adapter to initialize, error %d\n",
6809 __func__, error);
6810 return error;
6811 }
6812 /* Do post-firmware initialization. */
6813 return ops->post_alive(sc);
6814}
6815
6816static void
6817iwn_hw_stop(struct iwn_softc *sc)
6818{
6819 int chnl, qid, ntries;
6820
6821 IWN_WRITE(sc, IWN_RESET, IWN_RESET_NEVO);
6822
6823 /* Disable interrupts. */
6824 IWN_WRITE(sc, IWN_INT_MASK, 0);
6825 IWN_WRITE(sc, IWN_INT, 0xffffffff);
6826 IWN_WRITE(sc, IWN_FH_INT, 0xffffffff);
6827 sc->sc_flags &= ~IWN_FLAG_USE_ICT;
6828
6829 /* Make sure we no longer hold the NIC lock. */
6830 iwn_nic_unlock(sc);
6831
6832 /* Stop TX scheduler. */
6833 iwn_prph_write(sc, sc->sched_txfact_addr, 0);
6834
6835 /* Stop all DMA channels. */
6836 if (iwn_nic_lock(sc) == 0) {
6837 for (chnl = 0; chnl < sc->ndmachnls; chnl++) {
6838 IWN_WRITE(sc, IWN_FH_TX_CONFIG(chnl), 0);
6839 for (ntries = 0; ntries < 200; ntries++) {
6840 if (IWN_READ(sc, IWN_FH_TX_STATUS) &
6841 IWN_FH_TX_STATUS_IDLE(chnl))
6842 break;
6843 DELAY(10);
6844 }
6845 }
6846 iwn_nic_unlock(sc);
6847 }
6848
6849 /* Stop RX ring. */
6850 iwn_reset_rx_ring(sc, &sc->rxq);
6851
6852 /* Reset all TX rings. */
6853 for (qid = 0; qid < sc->ntxqs; qid++)
6854 iwn_reset_tx_ring(sc, &sc->txq[qid]);
6855
6856 if (iwn_nic_lock(sc) == 0) {
6857 iwn_prph_write(sc, IWN_APMG_CLK_DIS,
6858 IWN_APMG_CLK_CTRL_DMA_CLK_RQT);
6859 iwn_nic_unlock(sc);
6860 }
6861 DELAY(5);
6862 /* Power OFF adapter. */
6863 iwn_apm_stop(sc);
6864}
6865
6866static void
6867iwn_radio_on(void *arg0, int pending)
6868{
6869 struct iwn_softc *sc = arg0;
6870 struct ifnet *ifp = sc->sc_ifp;
6871 struct ieee80211com *ic = ifp->if_l2com;
6872 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
6873
6874 if (vap != NULL) {
6875 iwn_init(sc);
6876 ieee80211_init(vap);
6877 }
6878}
6879
6880static void
6881iwn_radio_off(void *arg0, int pending)
6882{
6883 struct iwn_softc *sc = arg0;
6884 struct ifnet *ifp = sc->sc_ifp;
6885 struct ieee80211com *ic = ifp->if_l2com;
6886 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
6887
6888 iwn_stop(sc);
6889 if (vap != NULL)
6890 ieee80211_stop(vap);
6891
6892 /* Enable interrupts to get RF toggle notification. */
6893 IWN_LOCK(sc);
6894 IWN_WRITE(sc, IWN_INT, 0xffffffff);
6895 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
6896 IWN_UNLOCK(sc);
6897}
6898
6899static void
6900iwn_init_locked(struct iwn_softc *sc)
6901{
6902 struct ifnet *ifp = sc->sc_ifp;
6903 int error;
6904
6905 IWN_LOCK_ASSERT(sc);
6906
6907 if ((error = iwn_hw_prepare(sc)) != 0) {
6908 device_printf(sc->sc_dev, "%s: hardware not ready, error %d\n",
6909 __func__, error);
6910 goto fail;
6911 }
6912
6913 /* Initialize interrupt mask to default value. */
6914 sc->int_mask = IWN_INT_MASK_DEF;
6915 sc->sc_flags &= ~IWN_FLAG_USE_ICT;
6916
6917 /* Check that the radio is not disabled by hardware switch. */
6918 if (!(IWN_READ(sc, IWN_GP_CNTRL) & IWN_GP_CNTRL_RFKILL)) {
6919 device_printf(sc->sc_dev,
6920 "radio is disabled by hardware switch\n");
6921 /* Enable interrupts to get RF toggle notifications. */
6922 IWN_WRITE(sc, IWN_INT, 0xffffffff);
6923 IWN_WRITE(sc, IWN_INT_MASK, sc->int_mask);
6924 return;
6925 }
6926
6927 /* Read firmware images from the filesystem. */
6928 if ((error = iwn_read_firmware(sc)) != 0) {
6929 device_printf(sc->sc_dev,
6930 "%s: could not read firmware, error %d\n", __func__,
6931 error);
6932 goto fail;
6933 }
6934
6935 /* Initialize hardware and upload firmware. */
6936 error = iwn_hw_init(sc);
6937 firmware_put(sc->fw_fp, FIRMWARE_UNLOAD);
6938 sc->fw_fp = NULL;
6939 if (error != 0) {
6940 device_printf(sc->sc_dev,
6941 "%s: could not initialize hardware, error %d\n", __func__,
6942 error);
6943 goto fail;
6944 }
6945
6946 /* Configure adapter now that it is ready. */
6947 if ((error = iwn_config(sc)) != 0) {
6948 device_printf(sc->sc_dev,
6949 "%s: could not configure device, error %d\n", __func__,
6950 error);
6951 goto fail;
6952 }
6953
6954 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
6955 ifp->if_drv_flags |= IFF_DRV_RUNNING;
6956
6957 callout_reset(&sc->watchdog_to, hz, iwn_watchdog, sc);
6958 return;
6959
6960fail: iwn_stop_locked(sc);
6961}
6962
6963static void
6964iwn_init(void *arg)
6965{
6966 struct iwn_softc *sc = arg;
6967 struct ifnet *ifp = sc->sc_ifp;
6968 struct ieee80211com *ic = ifp->if_l2com;
6969
6970 IWN_LOCK(sc);
6971 iwn_init_locked(sc);
6972 IWN_UNLOCK(sc);
6973
6974 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
6975 ieee80211_start_all(ic);
6976}
6977
6978static void
6979iwn_stop_locked(struct iwn_softc *sc)
6980{
6981 struct ifnet *ifp = sc->sc_ifp;
6982
6983 IWN_LOCK_ASSERT(sc);
6984
6985 sc->sc_tx_timer = 0;
6986 callout_stop(&sc->watchdog_to);
6987 callout_stop(&sc->calib_to);
6988 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
6989
6990 /* Power OFF hardware. */
6991 iwn_hw_stop(sc);
6992}
6993
6994static void
6995iwn_stop(struct iwn_softc *sc)
6996{
6997 IWN_LOCK(sc);
6998 iwn_stop_locked(sc);
6999 IWN_UNLOCK(sc);
7000}
7001
7002/*
7003 * Callback from net80211 to start a scan.
7004 */
7005static void
7006iwn_scan_start(struct ieee80211com *ic)
7007{
7008 struct ifnet *ifp = ic->ic_ifp;
7009 struct iwn_softc *sc = ifp->if_softc;
7010
7011 IWN_LOCK(sc);
7012 /* make the link LED blink while we're scanning */
7013 iwn_set_led(sc, IWN_LED_LINK, 20, 2);
7014 IWN_UNLOCK(sc);
7015}
7016
7017/*
7018 * Callback from net80211 to terminate a scan.
7019 */
7020static void
7021iwn_scan_end(struct ieee80211com *ic)
7022{
7023 struct ifnet *ifp = ic->ic_ifp;
7024 struct iwn_softc *sc = ifp->if_softc;
7025 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps);
7026
7027 IWN_LOCK(sc);
7028 if (vap->iv_state == IEEE80211_S_RUN) {
7029 /* Set link LED to ON status if we are associated */
7030 iwn_set_led(sc, IWN_LED_LINK, 0, 1);
7031 }
7032 IWN_UNLOCK(sc);
7033}
7034
7035/*
7036 * Callback from net80211 to force a channel change.
7037 */
7038static void
7039iwn_set_channel(struct ieee80211com *ic)
7040{
7041 const struct ieee80211_channel *c = ic->ic_curchan;
7042 struct ifnet *ifp = ic->ic_ifp;
7043 struct iwn_softc *sc = ifp->if_softc;
7044 int error;
7045
7046 IWN_LOCK(sc);
7047 sc->sc_rxtap.wr_chan_freq = htole16(c->ic_freq);
7048 sc->sc_rxtap.wr_chan_flags = htole16(c->ic_flags);
7049 sc->sc_txtap.wt_chan_freq = htole16(c->ic_freq);
7050 sc->sc_txtap.wt_chan_flags = htole16(c->ic_flags);
7051
7052 /*
7053 * Only need to set the channel in Monitor mode. AP scanning and auth
7054 * are already taken care of by their respective firmware commands.
7055 */
7056 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
7057 error = iwn_config(sc);
7058 if (error != 0)
7059 device_printf(sc->sc_dev,
7060 "%s: error %d settting channel\n", __func__, error);
7061 }
7062 IWN_UNLOCK(sc);
7063}
7064
7065/*
7066 * Callback from net80211 to start scanning of the current channel.
7067 */
7068static void
7069iwn_scan_curchan(struct ieee80211_scan_state *ss, unsigned long maxdwell)
7070{
7071 struct ieee80211vap *vap = ss->ss_vap;
7072 struct iwn_softc *sc = vap->iv_ic->ic_ifp->if_softc;
7073 int error;
7074
7075 IWN_LOCK(sc);
7076 error = iwn_scan(sc);
7077 IWN_UNLOCK(sc);
7078 if (error != 0)
7079 ieee80211_cancel_scan(vap);
7080}
7081
7082/*
7083 * Callback from net80211 to handle the minimum dwell time being met.
7084 * The intent is to terminate the scan but we just let the firmware
7085 * notify us when it's finished as we have no safe way to abort it.
7086 */
7087static void
7088iwn_scan_mindwell(struct ieee80211_scan_state *ss)
7089{
7090 /* NB: don't try to abort scan; wait for firmware to finish */
7091}
7092
7093static void
7094iwn_hw_reset(void *arg0, int pending)
7095{
7096 struct iwn_softc *sc = arg0;
7097 struct ifnet *ifp = sc->sc_ifp;
7098 struct ieee80211com *ic = ifp->if_l2com;
7099
7100 iwn_stop(sc);
7101 iwn_init(sc);
7102 ieee80211_notify_radio(ic, 1);
7103}