r300.c (254885) | r300.c (255573) |
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1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation --- 13 unchanged lines hidden (view full) --- 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29#include <sys/cdefs.h> | 1/* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation --- 13 unchanged lines hidden (view full) --- 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29#include <sys/cdefs.h> |
30__FBSDID("$FreeBSD: head/sys/dev/drm2/radeon/r300.c 254885 2013-08-25 19:37:15Z dumbbell $"); | 30__FBSDID("$FreeBSD: head/sys/dev/drm2/radeon/r300.c 255573 2013-09-14 17:24:41Z dumbbell $"); |
31 32#include <dev/drm2/drmP.h> 33#include <dev/drm2/drm.h> 34#include <dev/drm2/drm_crtc_helper.h> 35#include "radeon_reg.h" 36#include "radeon.h" 37#include "radeon_asic.h" 38#include <dev/drm2/radeon/radeon_drm.h> --- 357 unchanged lines hidden (view full) --- 396 /* stop CP */ 397 WREG32(RADEON_CP_CSQ_CNTL, 0); 398 tmp = RREG32(RADEON_CP_RB_CNTL); 399 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 400 WREG32(RADEON_CP_RB_RPTR_WR, 0); 401 WREG32(RADEON_CP_RB_WPTR, 0); 402 WREG32(RADEON_CP_RB_CNTL, tmp); 403 /* save PCI state */ | 31 32#include <dev/drm2/drmP.h> 33#include <dev/drm2/drm.h> 34#include <dev/drm2/drm_crtc_helper.h> 35#include "radeon_reg.h" 36#include "radeon.h" 37#include "radeon_asic.h" 38#include <dev/drm2/radeon/radeon_drm.h> --- 357 unchanged lines hidden (view full) --- 396 /* stop CP */ 397 WREG32(RADEON_CP_CSQ_CNTL, 0); 398 tmp = RREG32(RADEON_CP_RB_CNTL); 399 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); 400 WREG32(RADEON_CP_RB_RPTR_WR, 0); 401 WREG32(RADEON_CP_RB_WPTR, 0); 402 WREG32(RADEON_CP_RB_CNTL, tmp); 403 /* save PCI state */ |
404 pci_save_state(rdev->dev); | 404 pci_save_state(device_get_parent(rdev->dev)); |
405 /* disable bus mastering */ 406 r100_bm_disable(rdev); 407 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | 408 S_0000F0_SOFT_RESET_GA(1)); 409 RREG32(R_0000F0_RBBM_SOFT_RESET); 410 DRM_MDELAY(500); 411 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 412 DRM_MDELAY(1); --- 7 unchanged lines hidden (view full) --- 420 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); 421 RREG32(R_0000F0_RBBM_SOFT_RESET); 422 DRM_MDELAY(500); 423 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 424 DRM_MDELAY(1); 425 status = RREG32(R_000E40_RBBM_STATUS); 426 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 427 /* restore PCI & busmastering */ | 405 /* disable bus mastering */ 406 r100_bm_disable(rdev); 407 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | 408 S_0000F0_SOFT_RESET_GA(1)); 409 RREG32(R_0000F0_RBBM_SOFT_RESET); 410 DRM_MDELAY(500); 411 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 412 DRM_MDELAY(1); --- 7 unchanged lines hidden (view full) --- 420 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); 421 RREG32(R_0000F0_RBBM_SOFT_RESET); 422 DRM_MDELAY(500); 423 WREG32(R_0000F0_RBBM_SOFT_RESET, 0); 424 DRM_MDELAY(1); 425 status = RREG32(R_000E40_RBBM_STATUS); 426 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); 427 /* restore PCI & busmastering */ |
428 pci_restore_state(rdev->dev); | 428 pci_restore_state(device_get_parent(rdev->dev)); |
429 r100_enable_bm(rdev); 430 /* Check if GPU is idle */ 431 if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { 432 dev_err(rdev->dev, "failed to reset GPU\n"); 433 ret = -1; 434 } else 435 dev_info(rdev->dev, "GPU reset succeed\n"); 436 r100_mc_resume(rdev, &save); --- 1130 unchanged lines hidden --- | 429 r100_enable_bm(rdev); 430 /* Check if GPU is idle */ 431 if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) { 432 dev_err(rdev->dev, "failed to reset GPU\n"); 433 ret = -1; 434 } else 435 dev_info(rdev->dev, "GPU reset succeed\n"); 436 r100_mc_resume(rdev, &save); --- 1130 unchanged lines hidden --- |