1/* $FreeBSD: head/sys/dev/drm/i915_drm.h 145132 2005-04-16 03:44:47Z anholt $ */
| 1/*-
2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
|
2
| 26
|
| 27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/sys/dev/drm/i915_drm.h 152909 2005-11-28 23:13:57Z anholt $");
29
|
3#ifndef _I915_DRM_H_
4#define _I915_DRM_H_
5
6/* Please note that modifications to all structs defined here are
7 * subject to backwards-compatibility constraints.
8 */
9
| 30#ifndef _I915_DRM_H_
31#define _I915_DRM_H_
32
33/* Please note that modifications to all structs defined here are
34 * subject to backwards-compatibility constraints.
35 */
36
|
10#include "drm.h"
| 37#include "dev/drm/drm.h"
|
11
12/* Each region is a minimum of 16k, and there are at most 255 of them.
13 */
14#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
15 * of chars for next/prev indices */
16#define I915_LOG_MIN_TEX_REGION_SIZE 14
17
18typedef struct _drm_i915_init {
19 enum {
20 I915_INIT_DMA = 0x01,
21 I915_CLEANUP_DMA = 0x02,
22 I915_RESUME_DMA = 0x03
23 } func;
24 unsigned int mmio_offset;
25 int sarea_priv_offset;
26 unsigned int ring_start;
27 unsigned int ring_end;
28 unsigned int ring_size;
29 unsigned int front_offset;
30 unsigned int back_offset;
31 unsigned int depth_offset;
32 unsigned int w;
33 unsigned int h;
34 unsigned int pitch;
35 unsigned int pitch_bits;
36 unsigned int back_pitch;
37 unsigned int depth_pitch;
38 unsigned int cpp;
39 unsigned int chipset;
40} drm_i915_init_t;
41
42typedef struct _drm_i915_sarea {
43 drm_tex_region_t texList[I915_NR_TEX_REGIONS + 1];
44 int last_upload; /* last time texture was uploaded */
45 int last_enqueue; /* last time a buffer was enqueued */
46 int last_dispatch; /* age of the most recently dispatched buffer */
47 int ctxOwner; /* last context to upload state */
48 int texAge;
49 int pf_enabled; /* is pageflipping allowed? */
50 int pf_active;
51 int pf_current_page; /* which buffer is being displayed? */
52 int perf_boxes; /* performance boxes to be displayed */
53} drm_i915_sarea_t;
54
55/* Flags for perf_boxes
56 */
57#define I915_BOX_RING_EMPTY 0x1
58#define I915_BOX_FLIP 0x2
59#define I915_BOX_WAIT 0x4
60#define I915_BOX_TEXTURE_LOAD 0x8
61#define I915_BOX_LOST_CONTEXT 0x10
62
63/* I915 specific ioctls
64 * The device specific ioctl range is 0x40 to 0x79.
65 */
66#define DRM_I915_INIT 0x00
67#define DRM_I915_FLUSH 0x01
68#define DRM_I915_FLIP 0x02
69#define DRM_I915_BATCHBUFFER 0x03
70#define DRM_I915_IRQ_EMIT 0x04
71#define DRM_I915_IRQ_WAIT 0x05
72#define DRM_I915_GETPARAM 0x06
73#define DRM_I915_SETPARAM 0x07
74#define DRM_I915_ALLOC 0x08
75#define DRM_I915_FREE 0x09
76#define DRM_I915_INIT_HEAP 0x0a
77#define DRM_I915_CMDBUFFER 0x0b
78
79#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
80#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
81#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
82#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
83#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
84#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
85#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
86#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
87#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
88#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
89#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
90#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
91
92/* Allow drivers to submit batchbuffers directly to hardware, relying
93 * on the security mechanisms provided by hardware.
94 */
95typedef struct _drm_i915_batchbuffer {
96 int start; /* agp offset */
97 int used; /* nr bytes in use */
98 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
99 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
100 int num_cliprects; /* mulitpass with multiple cliprects? */
101 drm_clip_rect_t __user *cliprects; /* pointer to userspace cliprects */
102} drm_i915_batchbuffer_t;
103
104/* As above, but pass a pointer to userspace buffer which can be
105 * validated by the kernel prior to sending to hardware.
106 */
107typedef struct _drm_i915_cmdbuffer {
108 char __user *buf; /* pointer to userspace command buffer */
109 int sz; /* nr bytes in buf */
110 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
111 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
112 int num_cliprects; /* mulitpass with multiple cliprects? */
113 drm_clip_rect_t __user *cliprects; /* pointer to userspace cliprects */
114} drm_i915_cmdbuffer_t;
115
116/* Userspace can request & wait on irq's:
117 */
118typedef struct drm_i915_irq_emit {
119 int __user *irq_seq;
120} drm_i915_irq_emit_t;
121
122typedef struct drm_i915_irq_wait {
123 int irq_seq;
124} drm_i915_irq_wait_t;
125
126/* Ioctl to query kernel params:
127 */
128#define I915_PARAM_IRQ_ACTIVE 1
129#define I915_PARAM_ALLOW_BATCHBUFFER 2
130
131typedef struct drm_i915_getparam {
132 int param;
133 int __user *value;
134} drm_i915_getparam_t;
135
136/* Ioctl to set kernel params:
137 */
138#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
139#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
140#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
141
142typedef struct drm_i915_setparam {
143 int param;
144 int value;
145} drm_i915_setparam_t;
146
147/* A memory manager for regions of shared memory:
148 */
149#define I915_MEM_REGION_AGP 1
150
151typedef struct drm_i915_mem_alloc {
152 int region;
153 int alignment;
154 int size;
155 int __user *region_offset; /* offset from start of fb or agp */
156} drm_i915_mem_alloc_t;
157
158typedef struct drm_i915_mem_free {
159 int region;
160 int region_offset;
161} drm_i915_mem_free_t;
162
163typedef struct drm_i915_mem_init_heap {
164 int region;
165 int size;
166 int start;
167} drm_i915_mem_init_heap_t;
168
169#endif /* _I915_DRM_H_ */
| 38
39/* Each region is a minimum of 16k, and there are at most 255 of them.
40 */
41#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
42 * of chars for next/prev indices */
43#define I915_LOG_MIN_TEX_REGION_SIZE 14
44
45typedef struct _drm_i915_init {
46 enum {
47 I915_INIT_DMA = 0x01,
48 I915_CLEANUP_DMA = 0x02,
49 I915_RESUME_DMA = 0x03
50 } func;
51 unsigned int mmio_offset;
52 int sarea_priv_offset;
53 unsigned int ring_start;
54 unsigned int ring_end;
55 unsigned int ring_size;
56 unsigned int front_offset;
57 unsigned int back_offset;
58 unsigned int depth_offset;
59 unsigned int w;
60 unsigned int h;
61 unsigned int pitch;
62 unsigned int pitch_bits;
63 unsigned int back_pitch;
64 unsigned int depth_pitch;
65 unsigned int cpp;
66 unsigned int chipset;
67} drm_i915_init_t;
68
69typedef struct _drm_i915_sarea {
70 drm_tex_region_t texList[I915_NR_TEX_REGIONS + 1];
71 int last_upload; /* last time texture was uploaded */
72 int last_enqueue; /* last time a buffer was enqueued */
73 int last_dispatch; /* age of the most recently dispatched buffer */
74 int ctxOwner; /* last context to upload state */
75 int texAge;
76 int pf_enabled; /* is pageflipping allowed? */
77 int pf_active;
78 int pf_current_page; /* which buffer is being displayed? */
79 int perf_boxes; /* performance boxes to be displayed */
80} drm_i915_sarea_t;
81
82/* Flags for perf_boxes
83 */
84#define I915_BOX_RING_EMPTY 0x1
85#define I915_BOX_FLIP 0x2
86#define I915_BOX_WAIT 0x4
87#define I915_BOX_TEXTURE_LOAD 0x8
88#define I915_BOX_LOST_CONTEXT 0x10
89
90/* I915 specific ioctls
91 * The device specific ioctl range is 0x40 to 0x79.
92 */
93#define DRM_I915_INIT 0x00
94#define DRM_I915_FLUSH 0x01
95#define DRM_I915_FLIP 0x02
96#define DRM_I915_BATCHBUFFER 0x03
97#define DRM_I915_IRQ_EMIT 0x04
98#define DRM_I915_IRQ_WAIT 0x05
99#define DRM_I915_GETPARAM 0x06
100#define DRM_I915_SETPARAM 0x07
101#define DRM_I915_ALLOC 0x08
102#define DRM_I915_FREE 0x09
103#define DRM_I915_INIT_HEAP 0x0a
104#define DRM_I915_CMDBUFFER 0x0b
105
106#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
107#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
108#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
109#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
110#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
111#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
112#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
113#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
114#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
115#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
116#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
117#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
118
119/* Allow drivers to submit batchbuffers directly to hardware, relying
120 * on the security mechanisms provided by hardware.
121 */
122typedef struct _drm_i915_batchbuffer {
123 int start; /* agp offset */
124 int used; /* nr bytes in use */
125 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
126 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
127 int num_cliprects; /* mulitpass with multiple cliprects? */
128 drm_clip_rect_t __user *cliprects; /* pointer to userspace cliprects */
129} drm_i915_batchbuffer_t;
130
131/* As above, but pass a pointer to userspace buffer which can be
132 * validated by the kernel prior to sending to hardware.
133 */
134typedef struct _drm_i915_cmdbuffer {
135 char __user *buf; /* pointer to userspace command buffer */
136 int sz; /* nr bytes in buf */
137 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
138 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
139 int num_cliprects; /* mulitpass with multiple cliprects? */
140 drm_clip_rect_t __user *cliprects; /* pointer to userspace cliprects */
141} drm_i915_cmdbuffer_t;
142
143/* Userspace can request & wait on irq's:
144 */
145typedef struct drm_i915_irq_emit {
146 int __user *irq_seq;
147} drm_i915_irq_emit_t;
148
149typedef struct drm_i915_irq_wait {
150 int irq_seq;
151} drm_i915_irq_wait_t;
152
153/* Ioctl to query kernel params:
154 */
155#define I915_PARAM_IRQ_ACTIVE 1
156#define I915_PARAM_ALLOW_BATCHBUFFER 2
157
158typedef struct drm_i915_getparam {
159 int param;
160 int __user *value;
161} drm_i915_getparam_t;
162
163/* Ioctl to set kernel params:
164 */
165#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
166#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
167#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
168
169typedef struct drm_i915_setparam {
170 int param;
171 int value;
172} drm_i915_setparam_t;
173
174/* A memory manager for regions of shared memory:
175 */
176#define I915_MEM_REGION_AGP 1
177
178typedef struct drm_i915_mem_alloc {
179 int region;
180 int alignment;
181 int size;
182 int __user *region_offset; /* offset from start of fb or agp */
183} drm_i915_mem_alloc_t;
184
185typedef struct drm_i915_mem_free {
186 int region;
187 int region_offset;
188} drm_i915_mem_free_t;
189
190typedef struct drm_i915_mem_init_heap {
191 int region;
192 int size;
193 int start;
194} drm_i915_mem_init_heap_t;
195
196#endif /* _I915_DRM_H_ */
|