1/*
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 * $FreeBSD: head/sys/dev/bge/if_bgereg.h 119047 2003-08-17 19:14:02Z ps $
34 */
35
36/*
37 * BCM570x memory map. The internal memory layout varies somewhat
38 * depending on whether or not we have external SSRAM attached.
39 * The BCM5700 can have up to 16MB of external memory. The BCM5701
40 * is apparently not designed to use external SSRAM. The mappings
41 * up to the first 4 send rings are the same for both internal and
42 * external memory configurations. Note that mini RX ring space is
43 * only available with external SSRAM configurations, which means
44 * the mini RX ring is not supported on the BCM5701.
45 *
46 * The NIC's memory can be accessed by the host in one of 3 ways:
47 *
48 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA
49 * registers in PCI config space can be used to read any 32-bit
50 * address within the NIC's memory.
51 *
52 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config
53 * space can be used in conjunction with the memory window in the
54 * device register space at offset 0x8000 to read any 32K chunk
55 * of NIC memory.
56 *
57 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is
58 * set, the device I/O mapping consumes 32MB of host address space,
59 * allowing all of the registers and internal NIC memory to be
60 * accessed directly. NIC memory addresses are offset by 0x01000000.
61 * Flat mode consumes so much host address space that it is not
62 * recommended.
63 */
64#define BGE_PAGE_ZERO 0x00000000
65#define BGE_PAGE_ZERO_END 0x000000FF
66#define BGE_SEND_RING_RCB 0x00000100
67#define BGE_SEND_RING_RCB_END 0x000001FF
68#define BGE_RX_RETURN_RING_RCB 0x00000200
69#define BGE_RX_RETURN_RING_RCB_END 0x000002FF
70#define BGE_STATS_BLOCK 0x00000300
71#define BGE_STATS_BLOCK_END 0x00000AFF
72#define BGE_STATUS_BLOCK 0x00000B00
73#define BGE_STATUS_BLOCK_END 0x00000B4F
74#define BGE_SOFTWARE_GENCOMM 0x00000B50
75#define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54
76#define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58
77#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF
78#define BGE_UNMAPPED 0x00001000
79#define BGE_UNMAPPED_END 0x00001FFF
80#define BGE_DMA_DESCRIPTORS 0x00002000
81#define BGE_DMA_DESCRIPTORS_END 0x00003FFF
82#define BGE_SEND_RING_1_TO_4 0x00004000
83#define BGE_SEND_RING_1_TO_4_END 0x00005FFF
84
85/* Mappings for internal memory configuration */
86#define BGE_STD_RX_RINGS 0x00006000
87#define BGE_STD_RX_RINGS_END 0x00006FFF
88#define BGE_JUMBO_RX_RINGS 0x00007000
89#define BGE_JUMBO_RX_RINGS_END 0x00007FFF
90#define BGE_BUFFPOOL_1 0x00008000
91#define BGE_BUFFPOOL_1_END 0x0000FFFF
92#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */
93#define BGE_BUFFPOOL_2_END 0x00017FFF
94#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */
95#define BGE_BUFFPOOL_3_END 0x0001FFFF
96
97/* Mappings for external SSRAM configurations */
98#define BGE_SEND_RING_5_TO_6 0x00006000
99#define BGE_SEND_RING_5_TO_6_END 0x00006FFF
100#define BGE_SEND_RING_7_TO_8 0x00007000
101#define BGE_SEND_RING_7_TO_8_END 0x00007FFF
102#define BGE_SEND_RING_9_TO_16 0x00008000
103#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF
104#define BGE_EXT_STD_RX_RINGS 0x0000C000
105#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF
106#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000
107#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF
108#define BGE_MINI_RX_RINGS 0x0000E000
109#define BGE_MINI_RX_RINGS_END 0x0000FFFF
110#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */
111#define BGE_AVAIL_REGION1_END 0x00017FFF
112#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */
113#define BGE_AVAIL_REGION2_END 0x0001FFFF
114#define BGE_EXT_SSRAM 0x00020000
115#define BGE_EXT_SSRAM_END 0x000FFFFF
116
117
118/*
119 * BCM570x register offsets. These are memory mapped registers
120 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros.
121 * Each register must be accessed using 32 bit operations.
122 *
123 * All registers are accessed through a 32K shared memory block.
124 * The first group of registers are actually copies of the PCI
125 * configuration space registers.
126 */
127
128/*
129 * PCI registers defined in the PCI 2.2 spec.
130 */
131#define BGE_PCI_VID 0x00
132#define BGE_PCI_DID 0x02
133#define BGE_PCI_CMD 0x04
134#define BGE_PCI_STS 0x06
135#define BGE_PCI_REV 0x08
136#define BGE_PCI_CLASS 0x09
137#define BGE_PCI_CACHESZ 0x0C
138#define BGE_PCI_LATTIMER 0x0D
139#define BGE_PCI_HDRTYPE 0x0E
140#define BGE_PCI_BIST 0x0F
141#define BGE_PCI_BAR0 0x10
142#define BGE_PCI_BAR1 0x14
143#define BGE_PCI_SUBSYS 0x2C
144#define BGE_PCI_SUBVID 0x2E
145#define BGE_PCI_ROMBASE 0x30
146#define BGE_PCI_CAPPTR 0x34
147#define BGE_PCI_INTLINE 0x3C
148#define BGE_PCI_INTPIN 0x3D
149#define BGE_PCI_MINGNT 0x3E
150#define BGE_PCI_MAXLAT 0x3F
151#define BGE_PCI_PCIXCAP 0x40
152#define BGE_PCI_NEXTPTR_PM 0x41
153#define BGE_PCI_PCIX_CMD 0x42
154#define BGE_PCI_PCIX_STS 0x44
155#define BGE_PCI_PWRMGMT_CAPID 0x48
156#define BGE_PCI_NEXTPTR_VPD 0x49
157#define BGE_PCI_PWRMGMT_CAPS 0x4A
158#define BGE_PCI_PWRMGMT_CMD 0x4C
159#define BGE_PCI_PWRMGMT_STS 0x4D
160#define BGE_PCI_PWRMGMT_DATA 0x4F
161#define BGE_PCI_VPD_CAPID 0x50
162#define BGE_PCI_NEXTPTR_MSI 0x51
163#define BGE_PCI_VPD_ADDR 0x52
164#define BGE_PCI_VPD_DATA 0x54
165#define BGE_PCI_MSI_CAPID 0x58
166#define BGE_PCI_NEXTPTR_NONE 0x59
167#define BGE_PCI_MSI_CTL 0x5A
168#define BGE_PCI_MSI_ADDR_HI 0x5C
169#define BGE_PCI_MSI_ADDR_LO 0x60
170#define BGE_PCI_MSI_DATA 0x64
171
172/*
173 * PCI registers specific to the BCM570x family.
174 */
175#define BGE_PCI_MISC_CTL 0x68
176#define BGE_PCI_DMA_RW_CTL 0x6C
177#define BGE_PCI_PCISTATE 0x70
178#define BGE_PCI_CLKCTL 0x74
179#define BGE_PCI_REG_BASEADDR 0x78
180#define BGE_PCI_MEMWIN_BASEADDR 0x7C
181#define BGE_PCI_REG_DATA 0x80
182#define BGE_PCI_MEMWIN_DATA 0x84
183#define BGE_PCI_MODECTL 0x88
184#define BGE_PCI_MISC_CFG 0x8C
185#define BGE_PCI_MISC_LOCALCTL 0x90
186#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98
187#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C
188#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0
189#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4
190#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8
191#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC
192#define BGE_PCI_ISR_MBX_HI 0xB0
193#define BGE_PCI_ISR_MBX_LO 0xB4
194
195/* PCI Misc. Host control register */
196#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001
197#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002
198#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004
199#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008
200#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010
201#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020
202#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040
203#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080
204#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000
205
206#define BGE_BIGENDIAN_INIT \
207 (BGE_PCIMISCCTL_ENDIAN_BYTESWAP| \
208 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_CLEAR_INTA| \
209 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR)
210
211#define BGE_LITTLEENDIAN_INIT \
212 (BGE_PCIMISCCTL_CLEAR_INTA|BGE_PCIMISCCTL_MASK_PCI_INTR| \
213 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_INDIRECT_ACCESS)
214
215#define BGE_CHIPID_TIGON_I 0x40000000
216#define BGE_CHIPID_TIGON_II 0x60000000
217#define BGE_CHIPID_BCM5700_B0 0x71000000
218#define BGE_CHIPID_BCM5700_B1 0x71020000
219#define BGE_CHIPID_BCM5700_B2 0x71030000
220#define BGE_CHIPID_BCM5700_ALTIMA 0x71040000
221#define BGE_CHIPID_BCM5700_C0 0x72000000
222#define BGE_CHIPID_BCM5701_A0 0x00000000 /* grrrr */
223#define BGE_CHIPID_BCM5701_B0 0x01000000
224#define BGE_CHIPID_BCM5701_B2 0x01020000
225#define BGE_CHIPID_BCM5701_B5 0x01050000
226#define BGE_CHIPID_BCM5703_A0 0x10000000
227#define BGE_CHIPID_BCM5703_A1 0x10010000
228#define BGE_CHIPID_BCM5703_A2 0x10020000
229#define BGE_CHIPID_BCM5704_A0 0x20000000
230#define BGE_CHIPID_BCM5704_A1 0x20010000
231#define BGE_CHIPID_BCM5704_A2 0x20020000
232#define BGE_CHIPID_BCM5705_A0 0x30000000
233#define BGE_CHIPID_BCM5705_A1 0x30010000
234#define BGE_CHIPID_BCM5705_A2 0x30020000
235#define BGE_CHIPID_BCM5705_A3 0x30030000
236
237/* shorthand one */
238#define BGE_ASICREV(x) ((x) >> 28)
239#define BGE_ASICREV_BCM5700 0x07
240#define BGE_ASICREV_BCM5701 0x00
241#define BGE_ASICREV_BCM5703 0x01
242#define BGE_ASICREV_BCM5704 0x02
243#define BGE_ASICREV_BCM5705 0x03
244
245/* chip revisions */
246#define BGE_CHIPREV(x) ((x) >> 24)
247#define BGE_CHIPREV_5700_AX 0x70
248#define BGE_CHIPREV_5700_BX 0x71
249#define BGE_CHIPREV_5700_CX 0x72
250#define BGE_CHIPREV_5701_AX 0x00
251
252/* PCI DMA Read/Write Control register */
253#define BGE_PCIDMARWCTL_MINDMA 0x000000FF
254#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700
255#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800
256#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x00004000
257#define BGE_PCIDMARWCTL_RD_WAT 0x00070000
258# define BGE_PCIDMARWCTL_RD_WAT_SHIFT 16
259#define BGE_PCIDMARWCTL_WR_WAT 0x00380000
260# define BGE_PCIDMARWCTL_WR_WAT_SHIFT 19
261#define BGE_PCIDMARWCTL_USE_MRM 0x00400000
262#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000
263#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000
264# define BGE_PCIDMA_RWCTL_PCI_RD_CMD_SHIFT 24
265#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000
266# define BGE_PCIDMA_RWCTL_PCI_WR_CMD_SHIFT 28
267
268#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000
269#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100
270#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200
271#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300
272#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400
273#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500
274#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600
275#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700
276
277#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000
278#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800
279#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000
280#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800
281#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000
282#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800
283#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000
284#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800
285
286/*
287 * PCI state register -- note, this register is read only
288 * unless the PCISTATE_WR bit of the PCI Misc. Host Control
289 * register is set.
290 */
291#define BGE_PCISTATE_FORCE_RESET 0x00000001
292#define BGE_PCISTATE_INTR_STATE 0x00000002
293#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */
294#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 33/66, 0 = 66/133 */
295#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */
296#define BGE_PCISTATE_WANT_EXPROM 0x00000020
297#define BGE_PCISTATE_EXPROM_RETRY 0x00000040
298#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100
299#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00
300
301/*
302 * PCI Clock Control register -- note, this register is read only
303 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control
304 * register is set.
305 */
306#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F
307#define BGE_PCICLOCKCTL_M66EN 0x00000080
308#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200
309#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400
310#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800
311#define BGE_PCICLOCKCTL_ALTCLK 0x00001000
312#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000
313#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000
314#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000
315#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000
316
317
318#ifndef PCIM_CMD_MWIEN
319#define PCIM_CMD_MWIEN 0x0010
320#endif
321
322/*
323 * High priority mailbox registers
324 * Each mailbox is 64-bits wide, though we only use the
325 * lower 32 bits. To write a 64-bit value, write the upper 32 bits
326 * first. The NIC will load the mailbox after the lower 32 bit word
327 * has been updated.
328 */
329#define BGE_MBX_IRQ0_HI 0x0200
330#define BGE_MBX_IRQ0_LO 0x0204
331#define BGE_MBX_IRQ1_HI 0x0208
332#define BGE_MBX_IRQ1_LO 0x020C
333#define BGE_MBX_IRQ2_HI 0x0210
334#define BGE_MBX_IRQ2_LO 0x0214
335#define BGE_MBX_IRQ3_HI 0x0218
336#define BGE_MBX_IRQ3_LO 0x021C
337#define BGE_MBX_GEN0_HI 0x0220
338#define BGE_MBX_GEN0_LO 0x0224
339#define BGE_MBX_GEN1_HI 0x0228
340#define BGE_MBX_GEN1_LO 0x022C
341#define BGE_MBX_GEN2_HI 0x0230
342#define BGE_MBX_GEN2_LO 0x0234
343#define BGE_MBX_GEN3_HI 0x0228
344#define BGE_MBX_GEN3_LO 0x022C
345#define BGE_MBX_GEN4_HI 0x0240
346#define BGE_MBX_GEN4_LO 0x0244
347#define BGE_MBX_GEN5_HI 0x0248
348#define BGE_MBX_GEN5_LO 0x024C
349#define BGE_MBX_GEN6_HI 0x0250
350#define BGE_MBX_GEN6_LO 0x0254
351#define BGE_MBX_GEN7_HI 0x0258
352#define BGE_MBX_GEN7_LO 0x025C
353#define BGE_MBX_RELOAD_STATS_HI 0x0260
354#define BGE_MBX_RELOAD_STATS_LO 0x0264
355#define BGE_MBX_RX_STD_PROD_HI 0x0268
356#define BGE_MBX_RX_STD_PROD_LO 0x026C
357#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270
358#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274
359#define BGE_MBX_RX_MINI_PROD_HI 0x0278
360#define BGE_MBX_RX_MINI_PROD_LO 0x027C
361#define BGE_MBX_RX_CONS0_HI 0x0280
362#define BGE_MBX_RX_CONS0_LO 0x0284
363#define BGE_MBX_RX_CONS1_HI 0x0288
364#define BGE_MBX_RX_CONS1_LO 0x028C
365#define BGE_MBX_RX_CONS2_HI 0x0290
366#define BGE_MBX_RX_CONS2_LO 0x0294
367#define BGE_MBX_RX_CONS3_HI 0x0298
368#define BGE_MBX_RX_CONS3_LO 0x029C
369#define BGE_MBX_RX_CONS4_HI 0x02A0
370#define BGE_MBX_RX_CONS4_LO 0x02A4
371#define BGE_MBX_RX_CONS5_HI 0x02A8
372#define BGE_MBX_RX_CONS5_LO 0x02AC
373#define BGE_MBX_RX_CONS6_HI 0x02B0
374#define BGE_MBX_RX_CONS6_LO 0x02B4
375#define BGE_MBX_RX_CONS7_HI 0x02B8
376#define BGE_MBX_RX_CONS7_LO 0x02BC
377#define BGE_MBX_RX_CONS8_HI 0x02C0
378#define BGE_MBX_RX_CONS8_LO 0x02C4
379#define BGE_MBX_RX_CONS9_HI 0x02C8
380#define BGE_MBX_RX_CONS9_LO 0x02CC
381#define BGE_MBX_RX_CONS10_HI 0x02D0
382#define BGE_MBX_RX_CONS10_LO 0x02D4
383#define BGE_MBX_RX_CONS11_HI 0x02D8
384#define BGE_MBX_RX_CONS11_LO 0x02DC
385#define BGE_MBX_RX_CONS12_HI 0x02E0
386#define BGE_MBX_RX_CONS12_LO 0x02E4
387#define BGE_MBX_RX_CONS13_HI 0x02E8
388#define BGE_MBX_RX_CONS13_LO 0x02EC
389#define BGE_MBX_RX_CONS14_HI 0x02F0
390#define BGE_MBX_RX_CONS14_LO 0x02F4
391#define BGE_MBX_RX_CONS15_HI 0x02F8
392#define BGE_MBX_RX_CONS15_LO 0x02FC
393#define BGE_MBX_TX_HOST_PROD0_HI 0x0300
394#define BGE_MBX_TX_HOST_PROD0_LO 0x0304
395#define BGE_MBX_TX_HOST_PROD1_HI 0x0308
396#define BGE_MBX_TX_HOST_PROD1_LO 0x030C
397#define BGE_MBX_TX_HOST_PROD2_HI 0x0310
398#define BGE_MBX_TX_HOST_PROD2_LO 0x0314
399#define BGE_MBX_TX_HOST_PROD3_HI 0x0318
400#define BGE_MBX_TX_HOST_PROD3_LO 0x031C
401#define BGE_MBX_TX_HOST_PROD4_HI 0x0320
402#define BGE_MBX_TX_HOST_PROD4_LO 0x0324
403#define BGE_MBX_TX_HOST_PROD5_HI 0x0328
404#define BGE_MBX_TX_HOST_PROD5_LO 0x032C
405#define BGE_MBX_TX_HOST_PROD6_HI 0x0330
406#define BGE_MBX_TX_HOST_PROD6_LO 0x0334
407#define BGE_MBX_TX_HOST_PROD7_HI 0x0338
408#define BGE_MBX_TX_HOST_PROD7_LO 0x033C
409#define BGE_MBX_TX_HOST_PROD8_HI 0x0340
410#define BGE_MBX_TX_HOST_PROD8_LO 0x0344
411#define BGE_MBX_TX_HOST_PROD9_HI 0x0348
412#define BGE_MBX_TX_HOST_PROD9_LO 0x034C
413#define BGE_MBX_TX_HOST_PROD10_HI 0x0350
414#define BGE_MBX_TX_HOST_PROD10_LO 0x0354
415#define BGE_MBX_TX_HOST_PROD11_HI 0x0358
416#define BGE_MBX_TX_HOST_PROD11_LO 0x035C
417#define BGE_MBX_TX_HOST_PROD12_HI 0x0360
418#define BGE_MBX_TX_HOST_PROD12_LO 0x0364
419#define BGE_MBX_TX_HOST_PROD13_HI 0x0368
420#define BGE_MBX_TX_HOST_PROD13_LO 0x036C
421#define BGE_MBX_TX_HOST_PROD14_HI 0x0370
422#define BGE_MBX_TX_HOST_PROD14_LO 0x0374
423#define BGE_MBX_TX_HOST_PROD15_HI 0x0378
424#define BGE_MBX_TX_HOST_PROD15_LO 0x037C
425#define BGE_MBX_TX_NIC_PROD0_HI 0x0380
426#define BGE_MBX_TX_NIC_PROD0_LO 0x0384
427#define BGE_MBX_TX_NIC_PROD1_HI 0x0388
428#define BGE_MBX_TX_NIC_PROD1_LO 0x038C
429#define BGE_MBX_TX_NIC_PROD2_HI 0x0390
430#define BGE_MBX_TX_NIC_PROD2_LO 0x0394
431#define BGE_MBX_TX_NIC_PROD3_HI 0x0398
432#define BGE_MBX_TX_NIC_PROD3_LO 0x039C
433#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0
434#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4
435#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8
436#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC
437#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0
438#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4
439#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8
440#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC
441#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0
442#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4
443#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8
444#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC
445#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0
446#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4
447#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8
448#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC
449#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0
450#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4
451#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8
452#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC
453#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0
454#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4
455#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8
456#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC
457
458#define BGE_TX_RINGS_MAX 4
459#define BGE_TX_RINGS_EXTSSRAM_MAX 16
460#define BGE_RX_RINGS_MAX 16
461
462/* Ethernet MAC control registers */
463#define BGE_MAC_MODE 0x0400
464#define BGE_MAC_STS 0x0404
465#define BGE_MAC_EVT_ENB 0x0408
466#define BGE_MAC_LED_CTL 0x040C
467#define BGE_MAC_ADDR1_LO 0x0410
468#define BGE_MAC_ADDR1_HI 0x0414
469#define BGE_MAC_ADDR2_LO 0x0418
470#define BGE_MAC_ADDR2_HI 0x041C
471#define BGE_MAC_ADDR3_LO 0x0420
472#define BGE_MAC_ADDR3_HI 0x0424
473#define BGE_MAC_ADDR4_LO 0x0428
474#define BGE_MAC_ADDR4_HI 0x042C
475#define BGE_WOL_PATPTR 0x0430
476#define BGE_WOL_PATCFG 0x0434
477#define BGE_TX_RANDOM_BACKOFF 0x0438
478#define BGE_RX_MTU 0x043C
479#define BGE_GBIT_PCS_TEST 0x0440
480#define BGE_TX_TBI_AUTONEG 0x0444
481#define BGE_RX_TBI_AUTONEG 0x0448
482#define BGE_MI_COMM 0x044C
483#define BGE_MI_STS 0x0450
484#define BGE_MI_MODE 0x0454
485#define BGE_AUTOPOLL_STS 0x0458
486#define BGE_TX_MODE 0x045C
487#define BGE_TX_STS 0x0460
488#define BGE_TX_LENGTHS 0x0464
489#define BGE_RX_MODE 0x0468
490#define BGE_RX_STS 0x046C
491#define BGE_MAR0 0x0470
492#define BGE_MAR1 0x0474
493#define BGE_MAR2 0x0478
494#define BGE_MAR3 0x047C
495#define BGE_RX_BD_RULES_CTL0 0x0480
496#define BGE_RX_BD_RULES_MASKVAL0 0x0484
497#define BGE_RX_BD_RULES_CTL1 0x0488
498#define BGE_RX_BD_RULES_MASKVAL1 0x048C
499#define BGE_RX_BD_RULES_CTL2 0x0490
500#define BGE_RX_BD_RULES_MASKVAL2 0x0494
501#define BGE_RX_BD_RULES_CTL3 0x0498
502#define BGE_RX_BD_RULES_MASKVAL3 0x049C
503#define BGE_RX_BD_RULES_CTL4 0x04A0
504#define BGE_RX_BD_RULES_MASKVAL4 0x04A4
505#define BGE_RX_BD_RULES_CTL5 0x04A8
506#define BGE_RX_BD_RULES_MASKVAL5 0x04AC
507#define BGE_RX_BD_RULES_CTL6 0x04B0
508#define BGE_RX_BD_RULES_MASKVAL6 0x04B4
509#define BGE_RX_BD_RULES_CTL7 0x04B8
510#define BGE_RX_BD_RULES_MASKVAL7 0x04BC
511#define BGE_RX_BD_RULES_CTL8 0x04C0
512#define BGE_RX_BD_RULES_MASKVAL8 0x04C4
513#define BGE_RX_BD_RULES_CTL9 0x04C8
514#define BGE_RX_BD_RULES_MASKVAL9 0x04CC
515#define BGE_RX_BD_RULES_CTL10 0x04D0
516#define BGE_RX_BD_RULES_MASKVAL10 0x04D4
517#define BGE_RX_BD_RULES_CTL11 0x04D8
518#define BGE_RX_BD_RULES_MASKVAL11 0x04DC
519#define BGE_RX_BD_RULES_CTL12 0x04E0
520#define BGE_RX_BD_RULES_MASKVAL12 0x04E4
521#define BGE_RX_BD_RULES_CTL13 0x04E8
522#define BGE_RX_BD_RULES_MASKVAL13 0x04EC
523#define BGE_RX_BD_RULES_CTL14 0x04F0
524#define BGE_RX_BD_RULES_MASKVAL14 0x04F4
525#define BGE_RX_BD_RULES_CTL15 0x04F8
526#define BGE_RX_BD_RULES_MASKVAL15 0x04FC
527#define BGE_RX_RULES_CFG 0x0500
528#define BGE_RX_STATS 0x0800
529#define BGE_TX_STATS 0x0880
530
531/* Ethernet MAC Mode register */
532#define BGE_MACMODE_RESET 0x00000001
533#define BGE_MACMODE_HALF_DUPLEX 0x00000002
534#define BGE_MACMODE_PORTMODE 0x0000000C
535#define BGE_MACMODE_LOOPBACK 0x00000010
536#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080
537#define BGE_MACMODE_TX_BURST_ENB 0x00000100
538#define BGE_MACMODE_MAX_DEFER 0x00000200
539#define BGE_MACMODE_LINK_POLARITY 0x00000400
540#define BGE_MACMODE_RX_STATS_ENB 0x00000800
541#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000
542#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000
543#define BGE_MACMODE_TX_STATS_ENB 0x00004000
544#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000
545#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000
546#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000
547#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000
548#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000
549#define BGE_MACMODE_MIP_ENB 0x00100000
550#define BGE_MACMODE_TXDMA_ENB 0x00200000
551#define BGE_MACMODE_RXDMA_ENB 0x00400000
552#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000
553
554#define BGE_PORTMODE_NONE 0x00000000
555#define BGE_PORTMODE_MII 0x00000004
556#define BGE_PORTMODE_GMII 0x00000008
557#define BGE_PORTMODE_TBI 0x0000000C
558
559/* MAC Status register */
560#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001
561#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002
562#define BGE_MACSTAT_RX_CFG 0x00000004
563#define BGE_MACSTAT_CFG_CHANGED 0x00000008
564#define BGE_MACSTAT_SYNC_CHANGED 0x00000010
565#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400
566#define BGE_MACSTAT_LINK_CHANGED 0x00001000
567#define BGE_MACSTAT_MI_COMPLETE 0x00400000
568#define BGE_MACSTAT_MI_INTERRUPT 0x00800000
569#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000
570#define BGE_MACSTAT_ODI_ERROR 0x02000000
571#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000
572#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000
573
574/* MAC Event Enable Register */
575#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400
576#define BGE_EVTENB_LINK_CHANGED 0x00001000
577#define BGE_EVTENB_MI_COMPLETE 0x00400000
578#define BGE_EVTENB_MI_INTERRUPT 0x00800000
579#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000
580#define BGE_EVTENB_ODI_ERROR 0x02000000
581#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000
582#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000
583
584/* LED Control Register */
585#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001
586#define BGE_LEDCTL_1000MBPS_LED 0x00000002
587#define BGE_LEDCTL_100MBPS_LED 0x00000004
588#define BGE_LEDCTL_10MBPS_LED 0x00000008
589#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010
590#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020
591#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040
592#define BGE_LEDCTL_1000MBPS_STS 0x00000080
593#define BGE_LEDCTL_100MBPS_STS 0x00000100
594#define BGE_LEDCTL_10MBPS_STS 0x00000200
595#define BGE_LEDCTL_TRADLED_STS 0x00000400
596#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000
597#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000
598
599/* TX backoff seed register */
600#define BGE_TX_BACKOFF_SEED_MASK 0x3F
601
602/* Autopoll status register */
603#define BGE_AUTOPOLLSTS_ERROR 0x00000001
604
605/* Transmit MAC mode register */
606#define BGE_TXMODE_RESET 0x00000001
607#define BGE_TXMODE_ENABLE 0x00000002
608#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010
609#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020
610#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040
611
612/* Transmit MAC status register */
613#define BGE_TXSTAT_RX_XOFFED 0x00000001
614#define BGE_TXSTAT_SENT_XOFF 0x00000002
615#define BGE_TXSTAT_SENT_XON 0x00000004
616#define BGE_TXSTAT_LINK_UP 0x00000008
617#define BGE_TXSTAT_ODI_UFLOW 0x00000010
618#define BGE_TXSTAT_ODI_OFLOW 0x00000020
619
620/* Transmit MAC lengths register */
621#define BGE_TXLEN_SLOTTIME 0x000000FF
622#define BGE_TXLEN_IPG 0x00000F00
623#define BGE_TXLEN_CRS 0x00003000
624
625/* Receive MAC mode register */
626#define BGE_RXMODE_RESET 0x00000001
627#define BGE_RXMODE_ENABLE 0x00000002
628#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004
629#define BGE_RXMODE_RX_GIANTS 0x00000020
630#define BGE_RXMODE_RX_RUNTS 0x00000040
631#define BGE_RXMODE_8022_LENCHECK 0x00000080
632#define BGE_RXMODE_RX_PROMISC 0x00000100
633#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200
634#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400
635
636/* Receive MAC status register */
637#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001
638#define BGE_RXSTAT_RCVD_XOFF 0x00000002
639#define BGE_RXSTAT_RCVD_XON 0x00000004
640
641/* Receive Rules Control register */
642#define BGE_RXRULECTL_OFFSET 0x000000FF
643#define BGE_RXRULECTL_CLASS 0x00001F00
644#define BGE_RXRULECTL_HDRTYPE 0x0000E000
645#define BGE_RXRULECTL_COMPARE_OP 0x00030000
646#define BGE_RXRULECTL_MAP 0x01000000
647#define BGE_RXRULECTL_DISCARD 0x02000000
648#define BGE_RXRULECTL_MASK 0x04000000
649#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000
650#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000
651#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000
652#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000
653
654/* Receive Rules Mask register */
655#define BGE_RXRULEMASK_VALUE 0x0000FFFF
656#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000
657
658/* MI communication register */
659#define BGE_MICOMM_DATA 0x0000FFFF
660#define BGE_MICOMM_REG 0x001F0000
661#define BGE_MICOMM_PHY 0x03E00000
662#define BGE_MICOMM_CMD 0x0C000000
663#define BGE_MICOMM_READFAIL 0x10000000
664#define BGE_MICOMM_BUSY 0x20000000
665
666#define BGE_MIREG(x) ((x & 0x1F) << 16)
667#define BGE_MIPHY(x) ((x & 0x1F) << 21)
668#define BGE_MICMD_WRITE 0x04000000
669#define BGE_MICMD_READ 0x08000000
670
671/* MI status register */
672#define BGE_MISTS_LINK 0x00000001
673#define BGE_MISTS_10MBPS 0x00000002
674
675#define BGE_MIMODE_SHORTPREAMBLE 0x00000002
676#define BGE_MIMODE_AUTOPOLL 0x00000010
677#define BGE_MIMODE_CLKCNT 0x001F0000
678
679
680/*
681 * Send data initiator control registers.
682 */
683#define BGE_SDI_MODE 0x0C00
684#define BGE_SDI_STATUS 0x0C04
685#define BGE_SDI_STATS_CTL 0x0C08
686#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C
687#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10
688#define BGE_LOCSTATS_COS0 0x0C80
689#define BGE_LOCSTATS_COS1 0x0C84
690#define BGE_LOCSTATS_COS2 0x0C88
691#define BGE_LOCSTATS_COS3 0x0C8C
692#define BGE_LOCSTATS_COS4 0x0C90
693#define BGE_LOCSTATS_COS5 0x0C84
694#define BGE_LOCSTATS_COS6 0x0C98
695#define BGE_LOCSTATS_COS7 0x0C9C
696#define BGE_LOCSTATS_COS8 0x0CA0
697#define BGE_LOCSTATS_COS9 0x0CA4
698#define BGE_LOCSTATS_COS10 0x0CA8
699#define BGE_LOCSTATS_COS11 0x0CAC
700#define BGE_LOCSTATS_COS12 0x0CB0
701#define BGE_LOCSTATS_COS13 0x0CB4
702#define BGE_LOCSTATS_COS14 0x0CB8
703#define BGE_LOCSTATS_COS15 0x0CBC
704#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0
705#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4
706#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8
707#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC
708#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0
709#define BGE_LOCSTATS_IRQS 0x0CD4
710#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8
711#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC
712
713/* Send Data Initiator mode register */
714#define BGE_SDIMODE_RESET 0x00000001
715#define BGE_SDIMODE_ENABLE 0x00000002
716#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004
717
718/* Send Data Initiator stats register */
719#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004
720
721/* Send Data Initiator stats control register */
722#define BGE_SDISTATSCTL_ENABLE 0x00000001
723#define BGE_SDISTATSCTL_FASTER 0x00000002
724#define BGE_SDISTATSCTL_CLEAR 0x00000004
725#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008
726#define BGE_SDISTATSCTL_FORCEZERO 0x00000010
727
728/*
729 * Send Data Completion Control registers
730 */
731#define BGE_SDC_MODE 0x1000
732#define BGE_SDC_STATUS 0x1004
733
734/* Send Data completion mode register */
735#define BGE_SDCMODE_RESET 0x00000001
736#define BGE_SDCMODE_ENABLE 0x00000002
737#define BGE_SDCMODE_ATTN 0x00000004
738
739/* Send Data completion status register */
740#define BGE_SDCSTAT_ATTN 0x00000004
741
742/*
743 * Send BD Ring Selector Control registers
744 */
745#define BGE_SRS_MODE 0x1400
746#define BGE_SRS_STATUS 0x1404
747#define BGE_SRS_HWDIAG 0x1408
748#define BGE_SRS_LOC_NIC_CONS0 0x1440
749#define BGE_SRS_LOC_NIC_CONS1 0x1444
750#define BGE_SRS_LOC_NIC_CONS2 0x1448
751#define BGE_SRS_LOC_NIC_CONS3 0x144C
752#define BGE_SRS_LOC_NIC_CONS4 0x1450
753#define BGE_SRS_LOC_NIC_CONS5 0x1454
754#define BGE_SRS_LOC_NIC_CONS6 0x1458
755#define BGE_SRS_LOC_NIC_CONS7 0x145C
756#define BGE_SRS_LOC_NIC_CONS8 0x1460
757#define BGE_SRS_LOC_NIC_CONS9 0x1464
758#define BGE_SRS_LOC_NIC_CONS10 0x1468
759#define BGE_SRS_LOC_NIC_CONS11 0x146C
760#define BGE_SRS_LOC_NIC_CONS12 0x1470
761#define BGE_SRS_LOC_NIC_CONS13 0x1474
762#define BGE_SRS_LOC_NIC_CONS14 0x1478
763#define BGE_SRS_LOC_NIC_CONS15 0x147C
764
765/* Send BD Ring Selector Mode register */
766#define BGE_SRSMODE_RESET 0x00000001
767#define BGE_SRSMODE_ENABLE 0x00000002
768#define BGE_SRSMODE_ATTN 0x00000004
769
770/* Send BD Ring Selector Status register */
771#define BGE_SRSSTAT_ERROR 0x00000004
772
773/* Send BD Ring Selector HW Diagnostics register */
774#define BGE_SRSHWDIAG_STATE 0x0000000F
775#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0
776#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00
777#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000
778
779/*
780 * Send BD Initiator Selector Control registers
781 */
782#define BGE_SBDI_MODE 0x1800
783#define BGE_SBDI_STATUS 0x1804
784#define BGE_SBDI_LOC_NIC_PROD0 0x1808
785#define BGE_SBDI_LOC_NIC_PROD1 0x180C
786#define BGE_SBDI_LOC_NIC_PROD2 0x1810
787#define BGE_SBDI_LOC_NIC_PROD3 0x1814
788#define BGE_SBDI_LOC_NIC_PROD4 0x1818
789#define BGE_SBDI_LOC_NIC_PROD5 0x181C
790#define BGE_SBDI_LOC_NIC_PROD6 0x1820
791#define BGE_SBDI_LOC_NIC_PROD7 0x1824
792#define BGE_SBDI_LOC_NIC_PROD8 0x1828
793#define BGE_SBDI_LOC_NIC_PROD9 0x182C
794#define BGE_SBDI_LOC_NIC_PROD10 0x1830
795#define BGE_SBDI_LOC_NIC_PROD11 0x1834
796#define BGE_SBDI_LOC_NIC_PROD12 0x1838
797#define BGE_SBDI_LOC_NIC_PROD13 0x183C
798#define BGE_SBDI_LOC_NIC_PROD14 0x1840
799#define BGE_SBDI_LOC_NIC_PROD15 0x1844
800
801/* Send BD Initiator Mode register */
802#define BGE_SBDIMODE_RESET 0x00000001
803#define BGE_SBDIMODE_ENABLE 0x00000002
804#define BGE_SBDIMODE_ATTN 0x00000004
805
806/* Send BD Initiator Status register */
807#define BGE_SBDISTAT_ERROR 0x00000004
808
809/*
810 * Send BD Completion Control registers
811 */
812#define BGE_SBDC_MODE 0x1C00
813#define BGE_SBDC_STATUS 0x1C04
814
815/* Send BD Completion Control Mode register */
816#define BGE_SBDCMODE_RESET 0x00000001
817#define BGE_SBDCMODE_ENABLE 0x00000002
818#define BGE_SBDCMODE_ATTN 0x00000004
819
820/* Send BD Completion Control Status register */
821#define BGE_SBDCSTAT_ATTN 0x00000004
822
823/*
824 * Receive List Placement Control registers
825 */
826#define BGE_RXLP_MODE 0x2000
827#define BGE_RXLP_STATUS 0x2004
828#define BGE_RXLP_SEL_LIST_LOCK 0x2008
829#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C
830#define BGE_RXLP_CFG 0x2010
831#define BGE_RXLP_STATS_CTL 0x2014
832#define BGE_RXLP_STATS_ENABLE_MASK 0x2018
833#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C
834#define BGE_RXLP_HEAD0 0x2100
835#define BGE_RXLP_TAIL0 0x2104
836#define BGE_RXLP_COUNT0 0x2108
837#define BGE_RXLP_HEAD1 0x2110
838#define BGE_RXLP_TAIL1 0x2114
839#define BGE_RXLP_COUNT1 0x2118
840#define BGE_RXLP_HEAD2 0x2120
841#define BGE_RXLP_TAIL2 0x2124
842#define BGE_RXLP_COUNT2 0x2128
843#define BGE_RXLP_HEAD3 0x2130
844#define BGE_RXLP_TAIL3 0x2134
845#define BGE_RXLP_COUNT3 0x2138
846#define BGE_RXLP_HEAD4 0x2140
847#define BGE_RXLP_TAIL4 0x2144
848#define BGE_RXLP_COUNT4 0x2148
849#define BGE_RXLP_HEAD5 0x2150
850#define BGE_RXLP_TAIL5 0x2154
851#define BGE_RXLP_COUNT5 0x2158
852#define BGE_RXLP_HEAD6 0x2160
853#define BGE_RXLP_TAIL6 0x2164
854#define BGE_RXLP_COUNT6 0x2168
855#define BGE_RXLP_HEAD7 0x2170
856#define BGE_RXLP_TAIL7 0x2174
857#define BGE_RXLP_COUNT7 0x2178
858#define BGE_RXLP_HEAD8 0x2180
859#define BGE_RXLP_TAIL8 0x2184
860#define BGE_RXLP_COUNT8 0x2188
861#define BGE_RXLP_HEAD9 0x2190
862#define BGE_RXLP_TAIL9 0x2194
863#define BGE_RXLP_COUNT9 0x2198
864#define BGE_RXLP_HEAD10 0x21A0
865#define BGE_RXLP_TAIL10 0x21A4
866#define BGE_RXLP_COUNT10 0x21A8
867#define BGE_RXLP_HEAD11 0x21B0
868#define BGE_RXLP_TAIL11 0x21B4
869#define BGE_RXLP_COUNT11 0x21B8
870#define BGE_RXLP_HEAD12 0x21C0
871#define BGE_RXLP_TAIL12 0x21C4
872#define BGE_RXLP_COUNT12 0x21C8
873#define BGE_RXLP_HEAD13 0x21D0
874#define BGE_RXLP_TAIL13 0x21D4
875#define BGE_RXLP_COUNT13 0x21D8
876#define BGE_RXLP_HEAD14 0x21E0
877#define BGE_RXLP_TAIL14 0x21E4
878#define BGE_RXLP_COUNT14 0x21E8
879#define BGE_RXLP_HEAD15 0x21F0
880#define BGE_RXLP_TAIL15 0x21F4
881#define BGE_RXLP_COUNT15 0x21F8
882#define BGE_RXLP_LOCSTAT_COS0 0x2200
883#define BGE_RXLP_LOCSTAT_COS1 0x2204
884#define BGE_RXLP_LOCSTAT_COS2 0x2208
885#define BGE_RXLP_LOCSTAT_COS3 0x220C
886#define BGE_RXLP_LOCSTAT_COS4 0x2210
887#define BGE_RXLP_LOCSTAT_COS5 0x2214
888#define BGE_RXLP_LOCSTAT_COS6 0x2218
889#define BGE_RXLP_LOCSTAT_COS7 0x221C
890#define BGE_RXLP_LOCSTAT_COS8 0x2220
891#define BGE_RXLP_LOCSTAT_COS9 0x2224
892#define BGE_RXLP_LOCSTAT_COS10 0x2228
893#define BGE_RXLP_LOCSTAT_COS11 0x222C
894#define BGE_RXLP_LOCSTAT_COS12 0x2230
895#define BGE_RXLP_LOCSTAT_COS13 0x2234
896#define BGE_RXLP_LOCSTAT_COS14 0x2238
897#define BGE_RXLP_LOCSTAT_COS15 0x223C
898#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240
899#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244
900#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248
901#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C
902#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250
903#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254
904#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258
905
906
907/* Receive List Placement mode register */
908#define BGE_RXLPMODE_RESET 0x00000001
909#define BGE_RXLPMODE_ENABLE 0x00000002
910#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004
911#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008
912#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010
913
914/* Receive List Placement Status register */
915#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004
916#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008
917#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010
918
919/*
920 * Receive Data and Receive BD Initiator Control Registers
921 */
922#define BGE_RDBDI_MODE 0x2400
923#define BGE_RDBDI_STATUS 0x2404
924#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440
925#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444
926#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448
927#define BGE_RX_JUMBO_RCB_NICADDR 0x244C
928#define BGE_RX_STD_RCB_HADDR_HI 0x2450
929#define BGE_RX_STD_RCB_HADDR_LO 0x2454
930#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458
931#define BGE_RX_STD_RCB_NICADDR 0x245C
932#define BGE_RX_MINI_RCB_HADDR_HI 0x2460
933#define BGE_RX_MINI_RCB_HADDR_LO 0x2464
934#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468
935#define BGE_RX_MINI_RCB_NICADDR 0x246C
936#define BGE_RDBDI_JUMBO_RX_CONS 0x2470
937#define BGE_RDBDI_STD_RX_CONS 0x2474
938#define BGE_RDBDI_MINI_RX_CONS 0x2478
939#define BGE_RDBDI_RETURN_PROD0 0x2480
940#define BGE_RDBDI_RETURN_PROD1 0x2484
941#define BGE_RDBDI_RETURN_PROD2 0x2488
942#define BGE_RDBDI_RETURN_PROD3 0x248C
943#define BGE_RDBDI_RETURN_PROD4 0x2490
944#define BGE_RDBDI_RETURN_PROD5 0x2494
945#define BGE_RDBDI_RETURN_PROD6 0x2498
946#define BGE_RDBDI_RETURN_PROD7 0x249C
947#define BGE_RDBDI_RETURN_PROD8 0x24A0
948#define BGE_RDBDI_RETURN_PROD9 0x24A4
949#define BGE_RDBDI_RETURN_PROD10 0x24A8
950#define BGE_RDBDI_RETURN_PROD11 0x24AC
951#define BGE_RDBDI_RETURN_PROD12 0x24B0
952#define BGE_RDBDI_RETURN_PROD13 0x24B4
953#define BGE_RDBDI_RETURN_PROD14 0x24B8
954#define BGE_RDBDI_RETURN_PROD15 0x24BC
955#define BGE_RDBDI_HWDIAG 0x24C0
956
957
958/* Receive Data and Receive BD Initiator Mode register */
959#define BGE_RDBDIMODE_RESET 0x00000001
960#define BGE_RDBDIMODE_ENABLE 0x00000002
961#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004
962#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008
963#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010
964
965/* Receive Data and Receive BD Initiator Status register */
966#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004
967#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008
968#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010
969
970
971/*
972 * Receive Data Completion Control registers
973 */
974#define BGE_RDC_MODE 0x2800
975
976/* Receive Data Completion Mode register */
977#define BGE_RDCMODE_RESET 0x00000001
978#define BGE_RDCMODE_ENABLE 0x00000002
979#define BGE_RDCMODE_ATTN 0x00000004
980
981/*
982 * Receive BD Initiator Control registers
983 */
984#define BGE_RBDI_MODE 0x2C00
985#define BGE_RBDI_STATUS 0x2C04
986#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08
987#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C
988#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10
989#define BGE_RBDI_MINI_REPL_THRESH 0x2C14
990#define BGE_RBDI_STD_REPL_THRESH 0x2C18
991#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C
992
993/* Receive BD Initiator Mode register */
994#define BGE_RBDIMODE_RESET 0x00000001
995#define BGE_RBDIMODE_ENABLE 0x00000002
996#define BGE_RBDIMODE_ATTN 0x00000004
997
998/* Receive BD Initiator Status register */
999#define BGE_RBDISTAT_ATTN 0x00000004
1000
1001/*
1002 * Receive BD Completion Control registers
1003 */
1004#define BGE_RBDC_MODE 0x3000
1005#define BGE_RBDC_STATUS 0x3004
1006#define BGE_RBDC_JUMBO_BD_PROD 0x3008
1007#define BGE_RBDC_STD_BD_PROD 0x300C
1008#define BGE_RBDC_MINI_BD_PROD 0x3010
1009
1010/* Receive BD completion mode register */
1011#define BGE_RBDCMODE_RESET 0x00000001
1012#define BGE_RBDCMODE_ENABLE 0x00000002
1013#define BGE_RBDCMODE_ATTN 0x00000004
1014
1015/* Receive BD completion status register */
1016#define BGE_RBDCSTAT_ERROR 0x00000004
1017
1018/*
1019 * Receive List Selector Control registers
1020 */
1021#define BGE_RXLS_MODE 0x3400
1022#define BGE_RXLS_STATUS 0x3404
1023
1024/* Receive List Selector Mode register */
1025#define BGE_RXLSMODE_RESET 0x00000001
1026#define BGE_RXLSMODE_ENABLE 0x00000002
1027#define BGE_RXLSMODE_ATTN 0x00000004
1028
1029/* Receive List Selector Status register */
1030#define BGE_RXLSSTAT_ERROR 0x00000004
1031
1032/*
1033 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs)
1034 */
1035#define BGE_MBCF_MODE 0x3800
1036#define BGE_MBCF_STATUS 0x3804
1037
1038/* Mbuf Cluster Free mode register */
1039#define BGE_MBCFMODE_RESET 0x00000001
1040#define BGE_MBCFMODE_ENABLE 0x00000002
1041#define BGE_MBCFMODE_ATTN 0x00000004
1042
1043/* Mbuf Cluster Free status register */
1044#define BGE_MBCFSTAT_ERROR 0x00000004
1045
1046/*
1047 * Host Coalescing Control registers
1048 */
1049#define BGE_HCC_MODE 0x3C00
1050#define BGE_HCC_STATUS 0x3C04
1051#define BGE_HCC_RX_COAL_TICKS 0x3C08
1052#define BGE_HCC_TX_COAL_TICKS 0x3C0C
1053#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10
1054#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14
1055#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */
1056#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */
1057#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */
1058#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */
1059#define BGE_HCC_STATS_TICKS 0x3C28
1060#define BGE_HCC_STATS_ADDR_HI 0x3C30
1061#define BGE_HCC_STATS_ADDR_LO 0x3C34
1062#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38
1063#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C
1064#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */
1065#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */
1066#define BGE_FLOW_ATTN 0x3C48
1067#define BGE_HCC_JUMBO_BD_CONS 0x3C50
1068#define BGE_HCC_STD_BD_CONS 0x3C54
1069#define BGE_HCC_MINI_BD_CONS 0x3C58
1070#define BGE_HCC_RX_RETURN_PROD0 0x3C80
1071#define BGE_HCC_RX_RETURN_PROD1 0x3C84
1072#define BGE_HCC_RX_RETURN_PROD2 0x3C88
1073#define BGE_HCC_RX_RETURN_PROD3 0x3C8C
1074#define BGE_HCC_RX_RETURN_PROD4 0x3C90
1075#define BGE_HCC_RX_RETURN_PROD5 0x3C94
1076#define BGE_HCC_RX_RETURN_PROD6 0x3C98
1077#define BGE_HCC_RX_RETURN_PROD7 0x3C9C
1078#define BGE_HCC_RX_RETURN_PROD8 0x3CA0
1079#define BGE_HCC_RX_RETURN_PROD9 0x3CA4
1080#define BGE_HCC_RX_RETURN_PROD10 0x3CA8
1081#define BGE_HCC_RX_RETURN_PROD11 0x3CAC
1082#define BGE_HCC_RX_RETURN_PROD12 0x3CB0
1083#define BGE_HCC_RX_RETURN_PROD13 0x3CB4
1084#define BGE_HCC_RX_RETURN_PROD14 0x3CB8
1085#define BGE_HCC_RX_RETURN_PROD15 0x3CBC
1086#define BGE_HCC_TX_BD_CONS0 0x3CC0
1087#define BGE_HCC_TX_BD_CONS1 0x3CC4
1088#define BGE_HCC_TX_BD_CONS2 0x3CC8
1089#define BGE_HCC_TX_BD_CONS3 0x3CCC
1090#define BGE_HCC_TX_BD_CONS4 0x3CD0
1091#define BGE_HCC_TX_BD_CONS5 0x3CD4
1092#define BGE_HCC_TX_BD_CONS6 0x3CD8
1093#define BGE_HCC_TX_BD_CONS7 0x3CDC
1094#define BGE_HCC_TX_BD_CONS8 0x3CE0
1095#define BGE_HCC_TX_BD_CONS9 0x3CE4
1096#define BGE_HCC_TX_BD_CONS10 0x3CE8
1097#define BGE_HCC_TX_BD_CONS11 0x3CEC
1098#define BGE_HCC_TX_BD_CONS12 0x3CF0
1099#define BGE_HCC_TX_BD_CONS13 0x3CF4
1100#define BGE_HCC_TX_BD_CONS14 0x3CF8
1101#define BGE_HCC_TX_BD_CONS15 0x3CFC
1102
1103
1104/* Host coalescing mode register */
1105#define BGE_HCCMODE_RESET 0x00000001
1106#define BGE_HCCMODE_ENABLE 0x00000002
1107#define BGE_HCCMODE_ATTN 0x00000004
1108#define BGE_HCCMODE_COAL_NOW 0x00000008
1109#define BGE_HCCMODE_MSI_BITS 0x0x000070
1110#define BGE_HCCMODE_STATBLK_SIZE 0x00000180
1111
1112#define BGE_STATBLKSZ_FULL 0x00000000
1113#define BGE_STATBLKSZ_64BYTE 0x00000080
1114#define BGE_STATBLKSZ_32BYTE 0x00000100
1115
1116/* Host coalescing status register */
1117#define BGE_HCCSTAT_ERROR 0x00000004
1118
1119/* Flow attention register */
1120#define BGE_FLOWATTN_MB_LOWAT 0x00000040
1121#define BGE_FLOWATTN_MEMARB 0x00000080
1122#define BGE_FLOWATTN_HOSTCOAL 0x00008000
1123#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000
1124#define BGE_FLOWATTN_RCB_INVAL 0x00020000
1125#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000
1126#define BGE_FLOWATTN_RDBDI 0x00080000
1127#define BGE_FLOWATTN_RXLS 0x00100000
1128#define BGE_FLOWATTN_RXLP 0x00200000
1129#define BGE_FLOWATTN_RBDC 0x00400000
1130#define BGE_FLOWATTN_RBDI 0x00800000
1131#define BGE_FLOWATTN_SDC 0x08000000
1132#define BGE_FLOWATTN_SDI 0x10000000
1133#define BGE_FLOWATTN_SRS 0x20000000
1134#define BGE_FLOWATTN_SBDC 0x40000000
1135#define BGE_FLOWATTN_SBDI 0x80000000
1136
1137/*
1138 * Memory arbiter registers
1139 */
1140#define BGE_MARB_MODE 0x4000
1141#define BGE_MARB_STATUS 0x4004
1142#define BGE_MARB_TRAPADDR_HI 0x4008
1143#define BGE_MARB_TRAPADDR_LO 0x400C
1144
1145/* Memory arbiter mode register */
1146#define BGE_MARBMODE_RESET 0x00000001
1147#define BGE_MARBMODE_ENABLE 0x00000002
1148#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004
1149#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008
1150#define BGE_MARBMODE_DMAW1_TRAP 0x00000010
1151#define BGE_MARBMODE_DMAR1_TRAP 0x00000020
1152#define BGE_MARBMODE_RXRISC_TRAP 0x00000040
1153#define BGE_MARBMODE_TXRISC_TRAP 0x00000080
1154#define BGE_MARBMODE_PCI_TRAP 0x00000100
1155#define BGE_MARBMODE_DMAR2_TRAP 0x00000200
1156#define BGE_MARBMODE_RXQ_TRAP 0x00000400
1157#define BGE_MARBMODE_RXDI1_TRAP 0x00000800
1158#define BGE_MARBMODE_RXDI2_TRAP 0x00001000
1159#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000
1160#define BGE_MARBMODE_HCOAL_TRAP 0x00004000
1161#define BGE_MARBMODE_MBUF_TRAP 0x00008000
1162#define BGE_MARBMODE_TXDI_TRAP 0x00010000
1163#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000
1164#define BGE_MARBMODE_TXBD_TRAP 0x00040000
1165#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000
1166#define BGE_MARBMODE_DMAW2_TRAP 0x00100000
1167#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000
1168#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000
1169#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000
1170#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000
1171#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000
1172
1173/* Memory arbiter status register */
1174#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004
1175#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008
1176#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010
1177#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020
1178#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040
1179#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080
1180#define BGE_MARBSTAT_PCI_TRAP 0x00000100
1181#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200
1182#define BGE_MARBSTAT_RXQ_TRAP 0x00000400
1183#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800
1184#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000
1185#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000
1186#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000
1187#define BGE_MARBSTAT_MBUF_TRAP 0x00008000
1188#define BGE_MARBSTAT_TXDI_TRAP 0x00010000
1189#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000
1190#define BGE_MARBSTAT_TXBD_TRAP 0x00040000
1191#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000
1192#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000
1193#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000
1194#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000
1195#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000
1196#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000
1197#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000
1198
1199/*
1200 * Buffer manager control registers
1201 */
1202#define BGE_BMAN_MODE 0x4400
1203#define BGE_BMAN_STATUS 0x4404
1204#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408
1205#define BGE_BMAN_MBUFPOOL_LEN 0x440C
1206#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410
1207#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414
1208#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418
1209#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C
1210#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420
1211#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424
1212#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428
1213#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C
1214#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430
1215#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434
1216#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438
1217#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C
1218#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440
1219#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444
1220#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448
1221#define BGE_BMAN_HWDIAG_1 0x444C
1222#define BGE_BMAN_HWDIAG_2 0x4450
1223#define BGE_BMAN_HWDIAG_3 0x4454
1224
1225/* Buffer manager mode register */
1226#define BGE_BMANMODE_RESET 0x00000001
1227#define BGE_BMANMODE_ENABLE 0x00000002
1228#define BGE_BMANMODE_ATTN 0x00000004
1229#define BGE_BMANMODE_TESTMODE 0x00000008
1230#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010
1231
1232/* Buffer manager status register */
1233#define BGE_BMANSTAT_ERRO 0x00000004
1234#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010
1235
1236
1237/*
1238 * Read DMA Control registers
1239 */
1240#define BGE_RDMA_MODE 0x4800
1241#define BGE_RDMA_STATUS 0x4804
1242
1243/* Read DMA mode register */
1244#define BGE_RDMAMODE_RESET 0x00000001
1245#define BGE_RDMAMODE_ENABLE 0x00000002
1246#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004
1247#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008
1248#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010
1249#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020
1250#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040
1251#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080
1252#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100
1253#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200
1254#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC
1255
1256/* Read DMA status register */
1257#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004
1258#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008
1259#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010
1260#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020
1261#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040
1262#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080
1263#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100
1264#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200
1265
1266/*
1267 * Write DMA control registers
1268 */
1269#define BGE_WDMA_MODE 0x4C00
1270#define BGE_WDMA_STATUS 0x4C04
1271
1272/* Write DMA mode register */
1273#define BGE_WDMAMODE_RESET 0x00000001
1274#define BGE_WDMAMODE_ENABLE 0x00000002
1275#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004
1276#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008
1277#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010
1278#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020
1279#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040
1280#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080
1281#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100
1282#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200
1283#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC
1284
1285/* Write DMA status register */
1286#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004
1287#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008
1288#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010
1289#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020
1290#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040
1291#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080
1292#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100
1293#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200
1294
1295
1296/*
1297 * RX CPU registers
1298 */
1299#define BGE_RXCPU_MODE 0x5000
1300#define BGE_RXCPU_STATUS 0x5004
1301#define BGE_RXCPU_PC 0x501C
1302
1303/* RX CPU mode register */
1304#define BGE_RXCPUMODE_RESET 0x00000001
1305#define BGE_RXCPUMODE_SINGLESTEP 0x00000002
1306#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004
1307#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008
1308#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010
1309#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020
1310#define BGE_RXCPUMODE_ROMFAIL 0x00000040
1311#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080
1312#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100
1313#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200
1314#define BGE_RXCPUMODE_HALTCPU 0x00000400
1315#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800
1316#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000
1317#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000
1318
1319/* RX CPU status register */
1320#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001
1321#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002
1322#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004
1323#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008
1324#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010
1325#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020
1326#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040
1327#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080
1328#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100
1329#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200
1330#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000
1331#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000
1332#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000
1333#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000
1334#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000
1335#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000
1336#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000
1337
1338
1339/*
1340 * TX CPU registers
1341 */
1342#define BGE_TXCPU_MODE 0x5400
1343#define BGE_TXCPU_STATUS 0x5404
1344#define BGE_TXCPU_PC 0x541C
1345
1346/* TX CPU mode register */
1347#define BGE_TXCPUMODE_RESET 0x00000001
1348#define BGE_TXCPUMODE_SINGLESTEP 0x00000002
1349#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004
1350#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008
1351#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010
1352#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020
1353#define BGE_TXCPUMODE_ROMFAIL 0x00000040
1354#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080
1355#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100
1356#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200
1357#define BGE_TXCPUMODE_HALTCPU 0x00000400
1358#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800
1359#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000
1360
1361/* TX CPU status register */
1362#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001
1363#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002
1364#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004
1365#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008
1366#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010
1367#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020
1368#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040
1369#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080
1370#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100
1371#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200
1372#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000
1373#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000
1374#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000
1375#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000
1376#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000
1377#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000
1378#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000
1379
1380
1381/*
1382 * Low priority mailbox registers
1383 */
1384#define BGE_LPMBX_IRQ0_HI 0x5800
1385#define BGE_LPMBX_IRQ0_LO 0x5804
1386#define BGE_LPMBX_IRQ1_HI 0x5808
1387#define BGE_LPMBX_IRQ1_LO 0x580C
1388#define BGE_LPMBX_IRQ2_HI 0x5810
1389#define BGE_LPMBX_IRQ2_LO 0x5814
1390#define BGE_LPMBX_IRQ3_HI 0x5818
1391#define BGE_LPMBX_IRQ3_LO 0x581C
1392#define BGE_LPMBX_GEN0_HI 0x5820
1393#define BGE_LPMBX_GEN0_LO 0x5824
1394#define BGE_LPMBX_GEN1_HI 0x5828
1395#define BGE_LPMBX_GEN1_LO 0x582C
1396#define BGE_LPMBX_GEN2_HI 0x5830
1397#define BGE_LPMBX_GEN2_LO 0x5834
1398#define BGE_LPMBX_GEN3_HI 0x5828
1399#define BGE_LPMBX_GEN3_LO 0x582C
1400#define BGE_LPMBX_GEN4_HI 0x5840
1401#define BGE_LPMBX_GEN4_LO 0x5844
1402#define BGE_LPMBX_GEN5_HI 0x5848
1403#define BGE_LPMBX_GEN5_LO 0x584C
1404#define BGE_LPMBX_GEN6_HI 0x5850
1405#define BGE_LPMBX_GEN6_LO 0x5854
1406#define BGE_LPMBX_GEN7_HI 0x5858
1407#define BGE_LPMBX_GEN7_LO 0x585C
1408#define BGE_LPMBX_RELOAD_STATS_HI 0x5860
1409#define BGE_LPMBX_RELOAD_STATS_LO 0x5864
1410#define BGE_LPMBX_RX_STD_PROD_HI 0x5868
1411#define BGE_LPMBX_RX_STD_PROD_LO 0x586C
1412#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870
1413#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874
1414#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878
1415#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C
1416#define BGE_LPMBX_RX_CONS0_HI 0x5880
1417#define BGE_LPMBX_RX_CONS0_LO 0x5884
1418#define BGE_LPMBX_RX_CONS1_HI 0x5888
1419#define BGE_LPMBX_RX_CONS1_LO 0x588C
1420#define BGE_LPMBX_RX_CONS2_HI 0x5890
1421#define BGE_LPMBX_RX_CONS2_LO 0x5894
1422#define BGE_LPMBX_RX_CONS3_HI 0x5898
1423#define BGE_LPMBX_RX_CONS3_LO 0x589C
1424#define BGE_LPMBX_RX_CONS4_HI 0x58A0
1425#define BGE_LPMBX_RX_CONS4_LO 0x58A4
1426#define BGE_LPMBX_RX_CONS5_HI 0x58A8
1427#define BGE_LPMBX_RX_CONS5_LO 0x58AC
1428#define BGE_LPMBX_RX_CONS6_HI 0x58B0
1429#define BGE_LPMBX_RX_CONS6_LO 0x58B4
1430#define BGE_LPMBX_RX_CONS7_HI 0x58B8
1431#define BGE_LPMBX_RX_CONS7_LO 0x58BC
1432#define BGE_LPMBX_RX_CONS8_HI 0x58C0
1433#define BGE_LPMBX_RX_CONS8_LO 0x58C4
1434#define BGE_LPMBX_RX_CONS9_HI 0x58C8
1435#define BGE_LPMBX_RX_CONS9_LO 0x58CC
1436#define BGE_LPMBX_RX_CONS10_HI 0x58D0
1437#define BGE_LPMBX_RX_CONS10_LO 0x58D4
1438#define BGE_LPMBX_RX_CONS11_HI 0x58D8
1439#define BGE_LPMBX_RX_CONS11_LO 0x58DC
1440#define BGE_LPMBX_RX_CONS12_HI 0x58E0
1441#define BGE_LPMBX_RX_CONS12_LO 0x58E4
1442#define BGE_LPMBX_RX_CONS13_HI 0x58E8
1443#define BGE_LPMBX_RX_CONS13_LO 0x58EC
1444#define BGE_LPMBX_RX_CONS14_HI 0x58F0
1445#define BGE_LPMBX_RX_CONS14_LO 0x58F4
1446#define BGE_LPMBX_RX_CONS15_HI 0x58F8
1447#define BGE_LPMBX_RX_CONS15_LO 0x58FC
1448#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900
1449#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904
1450#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908
1451#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C
1452#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910
1453#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914
1454#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918
1455#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C
1456#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920
1457#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924
1458#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928
1459#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C
1460#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930
1461#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934
1462#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938
1463#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C
1464#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940
1465#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944
1466#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948
1467#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C
1468#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950
1469#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954
1470#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958
1471#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C
1472#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960
1473#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964
1474#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968
1475#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C
1476#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970
1477#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974
1478#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978
1479#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C
1480#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980
1481#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984
1482#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988
1483#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C
1484#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990
1485#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994
1486#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998
1487#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C
1488#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0
1489#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4
1490#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8
1491#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC
1492#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0
1493#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4
1494#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8
1495#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC
1496#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0
1497#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4
1498#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8
1499#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC
1500#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0
1501#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4
1502#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8
1503#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC
1504#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0
1505#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4
1506#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8
1507#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC
1508#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0
1509#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4
1510#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8
1511#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC
1512
1513/*
1514 * Flow throw Queue reset register
1515 */
1516#define BGE_FTQ_RESET 0x5C00
1517
1518#define BGE_FTQRESET_DMAREAD 0x00000002
1519#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004
1520#define BGE_FTQRESET_DMADONE 0x00000010
1521#define BGE_FTQRESET_SBDC 0x00000020
1522#define BGE_FTQRESET_SDI 0x00000040
1523#define BGE_FTQRESET_WDMA 0x00000080
1524#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100
1525#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200
1526#define BGE_FTQRESET_SDC 0x00000400
1527#define BGE_FTQRESET_HCC 0x00000800
1528#define BGE_FTQRESET_TXFIFO 0x00001000
1529#define BGE_FTQRESET_MBC 0x00002000
1530#define BGE_FTQRESET_RBDC 0x00004000
1531#define BGE_FTQRESET_RXLP 0x00008000
1532#define BGE_FTQRESET_RDBDI 0x00010000
1533#define BGE_FTQRESET_RDC 0x00020000
1534#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000
1535
1536/*
1537 * Message Signaled Interrupt registers
1538 */
1539#define BGE_MSI_MODE 0x6000
1540#define BGE_MSI_STATUS 0x6004
1541#define BGE_MSI_FIFOACCESS 0x6008
1542
1543/* MSI mode register */
1544#define BGE_MSIMODE_RESET 0x00000001
1545#define BGE_MSIMODE_ENABLE 0x00000002
1546#define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004
1547#define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008
1548#define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010
1549#define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020
1550#define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040
1551
1552/* MSI status register */
1553#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004
1554#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008
1555#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010
1556#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020
1557#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040
1558
1559
1560/*
1561 * DMA Completion registers
1562 */
1563#define BGE_DMAC_MODE 0x6400
1564
1565/* DMA Completion mode register */
1566#define BGE_DMACMODE_RESET 0x00000001
1567#define BGE_DMACMODE_ENABLE 0x00000002
1568
1569
1570/*
1571 * General control registers.
1572 */
1573#define BGE_MODE_CTL 0x6800
1574#define BGE_MISC_CFG 0x6804
1575#define BGE_MISC_LOCAL_CTL 0x6808
1576#define BGE_EE_ADDR 0x6838
1577#define BGE_EE_DATA 0x683C
1578#define BGE_EE_CTL 0x6840
1579#define BGE_MDI_CTL 0x6844
1580#define BGE_EE_DELAY 0x6848
1581
1582/* Mode control register */
1583#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001
1584#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002
1585#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004
1586#define BGE_MODECTL_BYTESWAP_DATA 0x00000010
1587#define BGE_MODECTL_WORDSWAP_DATA 0x00000020
1588#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200
1589#define BGE_MODECTL_NO_RX_CRC 0x00000400
1590#define BGE_MODECTL_RX_BADFRAMES 0x00000800
1591#define BGE_MODECTL_NO_TX_INTR 0x00002000
1592#define BGE_MODECTL_NO_RX_INTR 0x00004000
1593#define BGE_MODECTL_FORCE_PCI32 0x00008000
1594#define BGE_MODECTL_STACKUP 0x00010000
1595#define BGE_MODECTL_HOST_SEND_BDS 0x00020000
1596#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000
1597#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000
1598#define BGE_MODECTL_TX_ATTN_INTR 0x01000000
1599#define BGE_MODECTL_RX_ATTN_INTR 0x02000000
1600#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000
1601#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000
1602#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000
1603#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000
1604#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000
1605
1606/* Misc. config register */
1607#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001
1608#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE
1609
1610#define BGE_32BITTIME_66MHZ (0x41 << 1)
1611
1612/* Misc. Local Control */
1613#define BGE_MLC_INTR_STATE 0x00000001
1614#define BGE_MLC_INTR_CLR 0x00000002
1615#define BGE_MLC_INTR_SET 0x00000004
1616#define BGE_MLC_INTR_ONATTN 0x00000008
1617#define BGE_MLC_MISCIO_IN0 0x00000100
1618#define BGE_MLC_MISCIO_IN1 0x00000200
1619#define BGE_MLC_MISCIO_IN2 0x00000400
1620#define BGE_MLC_MISCIO_OUTEN0 0x00000800
1621#define BGE_MLC_MISCIO_OUTEN1 0x00001000
1622#define BGE_MLC_MISCIO_OUTEN2 0x00002000
1623#define BGE_MLC_MISCIO_OUT0 0x00004000
1624#define BGE_MLC_MISCIO_OUT1 0x00008000
1625#define BGE_MLC_MISCIO_OUT2 0x00010000
1626#define BGE_MLC_EXTRAM_ENB 0x00020000
1627#define BGE_MLC_SRAM_SIZE 0x001C0000
1628#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */
1629#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */
1630#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000
1631#define BGE_MLC_AUTO_EEPROM 0x01000000
1632
1633#define BGE_SSRAMSIZE_256KB 0x00000000
1634#define BGE_SSRAMSIZE_512KB 0x00040000
1635#define BGE_SSRAMSIZE_1MB 0x00080000
1636#define BGE_SSRAMSIZE_2MB 0x000C0000
1637#define BGE_SSRAMSIZE_4MB 0x00100000
1638#define BGE_SSRAMSIZE_8MB 0x00140000
1639#define BGE_SSRAMSIZE_16M 0x00180000
1640
1641/* EEPROM address register */
1642#define BGE_EEADDR_ADDRESS 0x0000FFFC
1643#define BGE_EEADDR_HALFCLK 0x01FF0000
1644#define BGE_EEADDR_START 0x02000000
1645#define BGE_EEADDR_DEVID 0x1C000000
1646#define BGE_EEADDR_RESET 0x20000000
1647#define BGE_EEADDR_DONE 0x40000000
1648#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */
1649
1650#define BGE_EEDEVID(x) ((x & 7) << 26)
1651#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16)
1652#define BGE_HALFCLK_384SCL 0x60
1653#define BGE_EE_READCMD \
1654 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \
1655 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE)
1656#define BGE_EE_WRCMD \
1657 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \
1658 BGE_EEADDR_START|BGE_EEADDR_DONE)
1659
1660/* EEPROM Control register */
1661#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001
1662#define BGE_EECTL_CLKOUT 0x00000002
1663#define BGE_EECTL_CLKIN 0x00000004
1664#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008
1665#define BGE_EECTL_DATAOUT 0x00000010
1666#define BGE_EECTL_DATAIN 0x00000020
1667
1668/* MDI (MII/GMII) access register */
1669#define BGE_MDI_DATA 0x00000001
1670#define BGE_MDI_DIR 0x00000002
1671#define BGE_MDI_SEL 0x00000004
1672#define BGE_MDI_CLK 0x00000008
1673
1674#define BGE_MEMWIN_START 0x00008000
1675#define BGE_MEMWIN_END 0x0000FFFF
1676
1677
1678#define BGE_MEMWIN_READ(sc, x, val) \
1679 do { \
1680 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \
1681 (0xFFFF0000 & x), 4); \
1682 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \
1683 } while(0)
1684
1685#define BGE_MEMWIN_WRITE(sc, x, val) \
1686 do { \
1687 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \
1688 (0xFFFF0000 & x), 4); \
1689 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \
1690 } while(0)
1691
1692/*
1693 * This magic number is used to prevent PXE restart when we
1694 * issue a software reset. We write this magic number to the
1695 * firmware mailbox at 0xB50 in order to prevent the PXE boot
1696 * code from running.
1697 */
1698#define BGE_MAGIC_NUMBER 0x4B657654
1699
1700typedef struct {
1701 u_int32_t bge_addr_hi;
1702 u_int32_t bge_addr_lo;
1703} bge_hostaddr;
1704
1705#define BGE_HOSTADDR(x, y) \
1706 do { \
1707 (x).bge_addr_lo = ((u_int64_t) (y) & 0xffffffff); \
1708 (x).bge_addr_hi = ((u_int64_t) (y) >> 32); \
1709 } while(0)
1710
1711#define BGE_ADDR_LO(y) \
1712 ((u_int64_t) (y) & 0xFFFFFFFF)
1713#define BGE_ADDR_HI(y) \
1714 ((u_int64_t) (y) >> 32)
1715
1716/* Ring control block structure */
1717struct bge_rcb {
1718 bge_hostaddr bge_hostaddr;
1719 u_int32_t bge_maxlen_flags;
1720 u_int32_t bge_nicaddr;
1721};
1722#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags))
1723
1724#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001
1725#define BGE_RCB_FLAG_RING_DISABLED 0x0002
1726
1727struct bge_tx_bd {
1728 bge_hostaddr bge_addr;
1729 u_int16_t bge_flags;
1730 u_int16_t bge_len;
1731 u_int16_t bge_vlan_tag;
1732 u_int16_t bge_rsvd;
1733};
1734
1735#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001
1736#define BGE_TXBDFLAG_IP_CSUM 0x0002
1737#define BGE_TXBDFLAG_END 0x0004
1738#define BGE_TXBDFLAG_IP_FRAG 0x0008
1739#define BGE_TXBDFLAG_IP_FRAG_END 0x0010
1740#define BGE_TXBDFLAG_VLAN_TAG 0x0040
1741#define BGE_TXBDFLAG_COAL_NOW 0x0080
1742#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100
1743#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200
1744#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000
1745#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000
1746#define BGE_TXBDFLAG_NO_CRC 0x8000
1747
1748#define BGE_NIC_TXRING_ADDR(ringno, size) \
1749 BGE_SEND_RING_1_TO_4 + \
1750 ((ringno * sizeof(struct bge_tx_bd) * size) / 4)
1751
1752struct bge_rx_bd {
1753 bge_hostaddr bge_addr;
1754 u_int16_t bge_len;
1755 u_int16_t bge_idx;
1756 u_int16_t bge_flags;
1757 u_int16_t bge_type;
1758 u_int16_t bge_tcp_udp_csum;
1759 u_int16_t bge_ip_csum;
1760 u_int16_t bge_vlan_tag;
1761 u_int16_t bge_error_flag;
1762 u_int32_t bge_rsvd;
1763 u_int32_t bge_opaque;
1764};
1765
1766#define BGE_RXBDFLAG_END 0x0004
1767#define BGE_RXBDFLAG_JUMBO_RING 0x0020
1768#define BGE_RXBDFLAG_VLAN_TAG 0x0040
1769#define BGE_RXBDFLAG_ERROR 0x0400
1770#define BGE_RXBDFLAG_MINI_RING 0x0800
1771#define BGE_RXBDFLAG_IP_CSUM 0x1000
1772#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000
1773#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000
1774
1775#define BGE_RXERRFLAG_BAD_CRC 0x0001
1776#define BGE_RXERRFLAG_COLL_DETECT 0x0002
1777#define BGE_RXERRFLAG_LINK_LOST 0x0004
1778#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008
1779#define BGE_RXERRFLAG_MAC_ABORT 0x0010
1780#define BGE_RXERRFLAG_RUNT 0x0020
1781#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040
1782#define BGE_RXERRFLAG_GIANT 0x0080
1783
1784struct bge_sts_idx {
1785 u_int16_t bge_rx_prod_idx;
1786 u_int16_t bge_tx_cons_idx;
1787};
1788
1789struct bge_status_block {
1790 u_int32_t bge_status;
1791 u_int32_t bge_rsvd0;
1792 u_int16_t bge_rx_jumbo_cons_idx;
1793 u_int16_t bge_rx_std_cons_idx;
1794 u_int16_t bge_rx_mini_cons_idx;
1795 u_int16_t bge_rsvd1;
1796 struct bge_sts_idx bge_idx[16];
1797};
1798
1799#define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx
1800#define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx
1801
1802#define BGE_STATFLAG_UPDATED 0x00000001
1803#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002
1804#define BGE_STATFLAG_ERROR 0x00000004
1805
1806
1807/*
1808 * Broadcom Vendor ID
1809 * (Note: the BCM570x still defaults to the Alteon PCI vendor ID
1810 * even though they're now manufactured by Broadcom)
1811 */
1812#define BCOM_VENDORID 0x14E4
1813#define BCOM_DEVICEID_BCM5700 0x1644
1814#define BCOM_DEVICEID_BCM5701 0x1645
1815#define BCOM_DEVICEID_BCM5702 0x16A6
1816#define BCOM_DEVICEID_BCM5702X 0x16C6
1817#define BCOM_DEVICEID_BCM5703 0x16A7
1818#define BCOM_DEVICEID_BCM5703X 0x16C7
1819#define BCOM_DEVICEID_BCM5704C 0x1648
1820#define BCOM_DEVICEID_BCM5704S 0x16A8
1821#define BCOM_DEVICEID_BCM5705 0x1653
1822#define BCOM_DEVICEID_BCM5705M 0x165D
1823#define BCOM_DEVICEID_BCM5705M_ALT 0x165E
1824#define BCOM_DEVICEID_BCM5782 0x1696
1825#define BCOM_DEVICEID_BCM5901 0x170D
1826#define BCOM_DEVICEID_BCM5901A2 0x170E
1827
1828/*
1829 * Alteon AceNIC PCI vendor/device ID.
1830 */
1831#define ALT_VENDORID 0x12AE
1832#define ALT_DEVICEID_ACENIC 0x0001
1833#define ALT_DEVICEID_ACENIC_COPPER 0x0002
1834#define ALT_DEVICEID_BCM5700 0x0003
1835#define ALT_DEVICEID_BCM5701 0x0004
1836
1837/*
1838 * 3Com 3c985 PCI vendor/device ID.
1839 */
1840#define TC_VENDORID 0x10B7
1841#define TC_DEVICEID_3C985 0x0001
1842#define TC_DEVICEID_3C996 0x0003
1843
1844/*
1845 * SysKonnect PCI vendor ID
1846 */
1847#define SK_VENDORID 0x1148
1848#define SK_DEVICEID_ALTIMA 0x4400
1849#define SK_SUBSYSID_9D21 0x4421
1850#define SK_SUBSYSID_9D41 0x4441
1851
1852/*
1853 * Altima PCI vendor/device ID.
1854 */
1855#define ALTIMA_VENDORID 0x173b
1856#define ALTIMA_DEVICE_AC1000 0x03e8
1857#define ALTIMA_DEVICE_AC9100 0x03ea
1858
1859/*
1860 * Offset of MAC address inside EEPROM.
1861 */
1862#define BGE_EE_MAC_OFFSET 0x7C
1863#define BGE_EE_HWCFG_OFFSET 0xC8
1864
1865#define BGE_HWCFG_VOLTAGE 0x00000003
1866#define BGE_HWCFG_PHYLED_MODE 0x0000000C
1867#define BGE_HWCFG_MEDIA 0x00000030
1868
1869#define BGE_VOLTAGE_1POINT3 0x00000000
1870#define BGE_VOLTAGE_1POINT8 0x00000001
1871
1872#define BGE_PHYLEDMODE_UNSPEC 0x00000000
1873#define BGE_PHYLEDMODE_TRIPLELED 0x00000004
1874#define BGE_PHYLEDMODE_SINGLELED 0x00000008
1875
1876#define BGE_MEDIA_UNSPEC 0x00000000
1877#define BGE_MEDIA_COPPER 0x00000010
1878#define BGE_MEDIA_FIBER 0x00000020
1879
1880#define BGE_PCI_READ_CMD 0x06000000
1881#define BGE_PCI_WRITE_CMD 0x70000000
1882
1883#define BGE_TICKS_PER_SEC 1000000
1884
1885/*
1886 * Ring size constants.
1887 */
1888#define BGE_EVENT_RING_CNT 256
1889#define BGE_CMD_RING_CNT 64
1890#define BGE_STD_RX_RING_CNT 512
1891#define BGE_JUMBO_RX_RING_CNT 256
1892#define BGE_MINI_RX_RING_CNT 1024
1893#define BGE_RETURN_RING_CNT 1024
1894
1895/* 5705 has smaller return ring size */
1896
1897#define BGE_RETURN_RING_CNT_5705 512
1898
1899/*
1900 * Possible TX ring sizes.
1901 */
1902#define BGE_TX_RING_CNT_128 128
1903#define BGE_TX_RING_BASE_128 0x3800
1904
1905#define BGE_TX_RING_CNT_256 256
1906#define BGE_TX_RING_BASE_256 0x3000
1907
1908#define BGE_TX_RING_CNT_512 512
1909#define BGE_TX_RING_BASE_512 0x2000
1910
1911#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512
1912#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512
1913
1914/*
1915 * Tigon III statistics counters.
1916 */
1917/* Statistics maintained MAC Receive block. */
1918struct bge_rx_mac_stats {
1919 bge_hostaddr ifHCInOctets;
1920 bge_hostaddr Reserved1;
1921 bge_hostaddr etherStatsFragments;
1922 bge_hostaddr ifHCInUcastPkts;
1923 bge_hostaddr ifHCInMulticastPkts;
1924 bge_hostaddr ifHCInBroadcastPkts;
1925 bge_hostaddr dot3StatsFCSErrors;
1926 bge_hostaddr dot3StatsAlignmentErrors;
1927 bge_hostaddr xonPauseFramesReceived;
1928 bge_hostaddr xoffPauseFramesReceived;
1929 bge_hostaddr macControlFramesReceived;
1930 bge_hostaddr xoffStateEntered;
1931 bge_hostaddr dot3StatsFramesTooLong;
1932 bge_hostaddr etherStatsJabbers;
1933 bge_hostaddr etherStatsUndersizePkts;
1934 bge_hostaddr inRangeLengthError;
1935 bge_hostaddr outRangeLengthError;
1936 bge_hostaddr etherStatsPkts64Octets;
1937 bge_hostaddr etherStatsPkts65Octetsto127Octets;
1938 bge_hostaddr etherStatsPkts128Octetsto255Octets;
1939 bge_hostaddr etherStatsPkts256Octetsto511Octets;
1940 bge_hostaddr etherStatsPkts512Octetsto1023Octets;
1941 bge_hostaddr etherStatsPkts1024Octetsto1522Octets;
1942 bge_hostaddr etherStatsPkts1523Octetsto2047Octets;
1943 bge_hostaddr etherStatsPkts2048Octetsto4095Octets;
1944 bge_hostaddr etherStatsPkts4096Octetsto8191Octets;
1945 bge_hostaddr etherStatsPkts8192Octetsto9022Octets;
1946};
1947
1948
1949/* Statistics maintained MAC Transmit block. */
1950struct bge_tx_mac_stats {
1951 bge_hostaddr ifHCOutOctets;
1952 bge_hostaddr Reserved2;
1953 bge_hostaddr etherStatsCollisions;
1954 bge_hostaddr outXonSent;
1955 bge_hostaddr outXoffSent;
1956 bge_hostaddr flowControlDone;
1957 bge_hostaddr dot3StatsInternalMacTransmitErrors;
1958 bge_hostaddr dot3StatsSingleCollisionFrames;
1959 bge_hostaddr dot3StatsMultipleCollisionFrames;
1960 bge_hostaddr dot3StatsDeferredTransmissions;
1961 bge_hostaddr Reserved3;
1962 bge_hostaddr dot3StatsExcessiveCollisions;
1963 bge_hostaddr dot3StatsLateCollisions;
1964 bge_hostaddr dot3Collided2Times;
1965 bge_hostaddr dot3Collided3Times;
1966 bge_hostaddr dot3Collided4Times;
1967 bge_hostaddr dot3Collided5Times;
1968 bge_hostaddr dot3Collided6Times;
1969 bge_hostaddr dot3Collided7Times;
1970 bge_hostaddr dot3Collided8Times;
1971 bge_hostaddr dot3Collided9Times;
1972 bge_hostaddr dot3Collided10Times;
1973 bge_hostaddr dot3Collided11Times;
1974 bge_hostaddr dot3Collided12Times;
1975 bge_hostaddr dot3Collided13Times;
1976 bge_hostaddr dot3Collided14Times;
1977 bge_hostaddr dot3Collided15Times;
1978 bge_hostaddr ifHCOutUcastPkts;
1979 bge_hostaddr ifHCOutMulticastPkts;
1980 bge_hostaddr ifHCOutBroadcastPkts;
1981 bge_hostaddr dot3StatsCarrierSenseErrors;
1982 bge_hostaddr ifOutDiscards;
1983 bge_hostaddr ifOutErrors;
1984};
1985
1986/* Stats counters access through registers */
1987struct bge_mac_stats_regs {
1988 u_int32_t ifHCOutOctets;
1989 u_int32_t Reserved0;
1990 u_int32_t etherStatsCollisions;
1991 u_int32_t outXonSent;
1992 u_int32_t outXoffSent;
1993 u_int32_t Reserved1;
1994 u_int32_t dot3StatsInternalMacTransmitErrors;
1995 u_int32_t dot3StatsSingleCollisionFrames;
1996 u_int32_t dot3StatsMultipleCollisionFrames;
1997 u_int32_t dot3StatsDeferredTransmissions;
1998 u_int32_t Reserved2;
1999 u_int32_t dot3StatsExcessiveCollisions;
2000 u_int32_t dot3StatsLateCollisions;
2001 u_int32_t Reserved3[14];
2002 u_int32_t ifHCOutUcastPkts;
2003 u_int32_t ifHCOutMulticastPkts;
2004 u_int32_t ifHCOutBroadcastPkts;
2005 u_int32_t Reserved4[2];
2006 u_int32_t ifHCInOctets;
2007 u_int32_t Reserved5;
2008 u_int32_t etherStatsFragments;
2009 u_int32_t ifHCInUcastPkts;
2010 u_int32_t ifHCInMulticastPkts;
2011 u_int32_t ifHCInBroadcastPkts;
2012 u_int32_t dot3StatsFCSErrors;
2013 u_int32_t dot3StatsAlignmentErrors;
2014 u_int32_t xonPauseFramesReceived;
2015 u_int32_t xoffPauseFramesReceived;
2016 u_int32_t macControlFramesReceived;
2017 u_int32_t xoffStateEntered;
2018 u_int32_t dot3StatsFramesTooLong;
2019 u_int32_t etherStatsJabbers;
2020 u_int32_t etherStatsUndersizePkts;
2021};
2022
2023struct bge_stats {
2024 u_int8_t Reserved0[256];
2025
2026 /* Statistics maintained by Receive MAC. */
2027 struct bge_rx_mac_stats rxstats;
2028
2029 bge_hostaddr Unused1[37];
2030
2031 /* Statistics maintained by Transmit MAC. */
2032 struct bge_tx_mac_stats txstats;
2033
2034 bge_hostaddr Unused2[31];
2035
2036 /* Statistics maintained by Receive List Placement. */
2037 bge_hostaddr COSIfHCInPkts[16];
2038 bge_hostaddr COSFramesDroppedDueToFilters;
2039 bge_hostaddr nicDmaWriteQueueFull;
2040 bge_hostaddr nicDmaWriteHighPriQueueFull;
2041 bge_hostaddr nicNoMoreRxBDs;
2042 bge_hostaddr ifInDiscards;
2043 bge_hostaddr ifInErrors;
2044 bge_hostaddr nicRecvThresholdHit;
2045
2046 bge_hostaddr Unused3[9];
2047
2048 /* Statistics maintained by Send Data Initiator. */
2049 bge_hostaddr COSIfHCOutPkts[16];
2050 bge_hostaddr nicDmaReadQueueFull;
2051 bge_hostaddr nicDmaReadHighPriQueueFull;
2052 bge_hostaddr nicSendDataCompQueueFull;
2053
2054 /* Statistics maintained by Host Coalescing. */
2055 bge_hostaddr nicRingSetSendProdIndex;
2056 bge_hostaddr nicRingStatusUpdate;
2057 bge_hostaddr nicInterrupts;
2058 bge_hostaddr nicAvoidedInterrupts;
2059 bge_hostaddr nicSendThresholdHit;
2060
2061 u_int8_t Reserved4[320];
2062};
2063
2064/*
2065 * Tigon general information block. This resides in host memory
2066 * and contains the status counters, ring control blocks and
2067 * producer pointers.
2068 */
2069
2070struct bge_gib {
2071 struct bge_stats bge_stats;
2072 struct bge_rcb bge_tx_rcb[16];
2073 struct bge_rcb bge_std_rx_rcb;
2074 struct bge_rcb bge_jumbo_rx_rcb;
2075 struct bge_rcb bge_mini_rx_rcb;
2076 struct bge_rcb bge_return_rcb;
2077};
2078
2079#define BGE_FRAMELEN 1518
2080#define BGE_MAX_FRAMELEN 1536
2081#define BGE_JUMBO_FRAMELEN 9018
2082#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
2083#define BGE_PAGE_SIZE PAGE_SIZE
2084#define BGE_MIN_FRAMELEN 60
2085
2086/*
2087 * Other utility macros.
2088 */
2089#define BGE_INC(x, y) (x) = (x + 1) % y
2090
2091/*
2092 * Vital product data and structures.
2093 */
2094#define BGE_VPD_FLAG 0x8000
2095
2096/* VPD structures */
2097struct vpd_res {
2098 u_int8_t vr_id;
2099 u_int8_t vr_len;
2100 u_int8_t vr_pad;
2101};
2102
2103struct vpd_key {
2104 char vk_key[2];
2105 u_int8_t vk_len;
2106};
2107
2108#define VPD_RES_ID 0x82 /* ID string */
2109#define VPD_RES_READ 0x90 /* start of read only area */
2110#define VPD_RES_WRITE 0x81 /* start of read/write area */
2111#define VPD_RES_END 0x78 /* end tag */
2112
2113
2114/*
2115 * Register access macros. The Tigon always uses memory mapped register
2116 * accesses and all registers must be accessed with 32 bit operations.
2117 */
2118
2119#define CSR_WRITE_4(sc, reg, val) \
2120 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val)
2121
2122#define CSR_READ_4(sc, reg) \
2123 bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg)
2124
2125#define BGE_SETBIT(sc, reg, x) \
2126 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x)))
2127#define BGE_CLRBIT(sc, reg, x) \
2128 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x)))
2129
2130#define PCI_SETBIT(dev, reg, x, s) \
2131 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s)
2132#define PCI_CLRBIT(dev, reg, x, s) \
2133 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s)
2134
2135/*
2136 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS
2137 * values are tuneable. They control the actual amount of buffers
2138 * allocated for the standard, mini and jumbo receive rings.
2139 */
2140
2141#define BGE_SSLOTS 256
2142#define BGE_MSLOTS 256
2143#define BGE_JSLOTS 384
2144
2145#define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN)
2146#define BGE_JLEN (BGE_JRAWLEN + (sizeof(u_int64_t) - \
2147 (BGE_JRAWLEN % sizeof(u_int64_t))))
2148#define BGE_JPAGESZ PAGE_SIZE
2149#define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ)
2150#define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID)
2151
2152/*
2153 * Ring structures. Most of these reside in host memory and we tell
2154 * the NIC where they are via the ring control blocks. The exceptions
2155 * are the tx and command rings, which live in NIC memory and which
2156 * we access via the shared memory window.
2157 */
2158
2159struct bge_ring_data {
2160 struct bge_rx_bd *bge_rx_std_ring;
2161 bus_addr_t bge_rx_std_ring_paddr;
2162 struct bge_rx_bd *bge_rx_jumbo_ring;
2163 bus_addr_t bge_rx_jumbo_ring_paddr;
2164 struct bge_rx_bd *bge_rx_return_ring;
2165 bus_addr_t bge_rx_return_ring_paddr;
2166 struct bge_tx_bd *bge_tx_ring;
2167 bus_addr_t bge_tx_ring_paddr;
2168 struct bge_status_block *bge_status_block;
2169 bus_addr_t bge_status_block_paddr;
2170 struct bge_stats *bge_stats;
2171 bus_addr_t bge_stats_paddr;
2172 void *bge_jumbo_buf;
2173 struct bge_gib bge_info;
2174};
2175
2176#define BGE_STD_RX_RING_SZ \
2177 (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT)
2178#define BGE_JUMBO_RX_RING_SZ \
2179 (sizeof(struct bge_rx_bd) * BGE_JUMBO_RX_RING_CNT)
2180#define BGE_TX_RING_SZ \
2181 (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT)
2182#define BGE_RX_RTN_RING_SZ(x) \
2183 (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt)
2184
2185#define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block)
2186
2187#define BGE_STATS_SZ sizeof (struct bge_stats)
2188
2189/*
2190 * Mbuf pointers. We need these to keep track of the virtual addresses
2191 * of our mbuf chains since we can only convert from physical to virtual,
2192 * not the other way around.
2193 */
2194struct bge_chain_data {
2195 bus_dma_tag_t bge_parent_tag;
2196 bus_dma_tag_t bge_rx_std_ring_tag;
2197 bus_dma_tag_t bge_rx_jumbo_ring_tag;
2198 bus_dma_tag_t bge_rx_return_ring_tag;
2199 bus_dma_tag_t bge_tx_ring_tag;
2200 bus_dma_tag_t bge_status_tag;
2201 bus_dma_tag_t bge_stats_tag;
2202 bus_dma_tag_t bge_jumbo_tag;
2203 bus_dma_tag_t bge_mtag; /* mbuf mapping tag */
2204 bus_dma_tag_t bge_mtag_jumbo; /* mbuf mapping tag */
2205 bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT];
2206 bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT];
2207 bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT];
2208 bus_dmamap_t bge_rx_std_ring_map;
2209 bus_dmamap_t bge_rx_jumbo_ring_map;
2210 bus_dmamap_t bge_tx_ring_map;
2211 bus_dmamap_t bge_rx_return_ring_map;
2212 bus_dmamap_t bge_status_map;
2213 bus_dmamap_t bge_stats_map;
2214 bus_dmamap_t bge_jumbo_map;
2215 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT];
2216 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT];
2217 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT];
2218 /* Stick the jumbo mem management stuff here too. */
2219 caddr_t bge_jslots[BGE_JSLOTS];
2220};
2221
2222struct bge_dmamap_arg {
2223 struct bge_softc *sc;
2224 bus_addr_t bge_busaddr;
2225 u_int16_t bge_flags;
2226 int bge_idx;
2227 int bge_maxsegs;
2228 struct bge_tx_bd *bge_ring;
2229};
2230
2231struct bge_type {
2232 u_int16_t bge_vid;
2233 u_int16_t bge_did;
2234 char *bge_name;
2235};
2236
2237#define BGE_HWREV_TIGON 0x01
2238#define BGE_HWREV_TIGON_II 0x02
2239#define BGE_TIMEOUT 100000
2240#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */
2241
2242struct bge_jpool_entry {
2243 int slot;
2244 SLIST_ENTRY(bge_jpool_entry) jpool_entries;
2245};
2246
2247struct bge_bcom_hack {
2248 int reg;
2249 int val;
2250};
2251
2252struct bge_softc {
2253 struct arpcom arpcom; /* interface info */
2254 device_t bge_dev;
2255 device_t bge_miibus;
2256 bus_space_handle_t bge_bhandle;
2257 vm_offset_t bge_vhandle;
2258 bus_space_tag_t bge_btag;
2259 void *bge_intrhand;
2260 struct resource *bge_irq;
2261 struct resource *bge_res;
2262 struct ifmedia bge_ifmedia; /* TBI media info */
2263 u_int8_t bge_unit; /* interface number */
2264 u_int8_t bge_extram; /* has external SSRAM */
2265 u_int8_t bge_tbi;
2266 u_int8_t bge_rx_alignment_bug;
2267 u_int32_t bge_chipid;
2268 u_int8_t bge_asicrev;
2269 u_int8_t bge_chiprev;
2270 struct bge_ring_data bge_ldata; /* rings */
2271 struct bge_chain_data bge_cdata; /* mbufs */
2272 u_int16_t bge_tx_saved_considx;
2273 u_int16_t bge_rx_saved_considx;
2274 u_int16_t bge_ev_saved_considx;
2275 u_int16_t bge_return_ring_cnt;
2276 u_int16_t bge_std; /* current std ring head */
2277 u_int16_t bge_jumbo; /* current jumo ring head */
2278 SLIST_HEAD(__bge_jfreehead, bge_jpool_entry) bge_jfree_listhead;
2279 SLIST_HEAD(__bge_jinusehead, bge_jpool_entry) bge_jinuse_listhead;
2280 u_int32_t bge_stat_ticks;
2281 u_int32_t bge_rx_coal_ticks;
2282 u_int32_t bge_tx_coal_ticks;
2283 u_int32_t bge_rx_max_coal_bds;
2284 u_int32_t bge_tx_max_coal_bds;
2285 u_int32_t bge_tx_buf_ratio;
2286 int bge_if_flags;
2287 int bge_txcnt;
2288 int bge_link;
2289 struct callout_handle bge_stat_ch;
2290 char *bge_vpd_prodname;
2291 char *bge_vpd_readonly;
2292};