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if_bge.c (135359) if_bge.c (135772)
1/*
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 18 unchanged lines hidden (view full) ---

27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34#include <sys/cdefs.h>
1/*
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 18 unchanged lines hidden (view full) ---

27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34#include <sys/cdefs.h>
35__FBSDID("$FreeBSD: head/sys/dev/bge/if_bge.c 135359 2004-09-17 04:58:17Z wpaul $");
35__FBSDID("$FreeBSD: head/sys/dev/bge/if_bge.c 135772 2004-09-24 22:24:33Z ps $");
36
37/*
38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
39 *
40 * The Broadcom BCM5700 is based on technology originally developed by
41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
42 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external

--- 106 unchanged lines hidden (view full) ---

150 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705,
151 "Broadcom BCM5705 Gigabit Ethernet" },
152 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K,
153 "Broadcom BCM5705K Gigabit Ethernet" },
154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M,
155 "Broadcom BCM5705M Gigabit Ethernet" },
156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT,
157 "Broadcom BCM5705M Gigabit Ethernet" },
36
37/*
38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
39 *
40 * The Broadcom BCM5700 is based on technology originally developed by
41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
42 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external

--- 106 unchanged lines hidden (view full) ---

150 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705,
151 "Broadcom BCM5705 Gigabit Ethernet" },
152 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K,
153 "Broadcom BCM5705K Gigabit Ethernet" },
154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M,
155 "Broadcom BCM5705M Gigabit Ethernet" },
156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT,
157 "Broadcom BCM5705M Gigabit Ethernet" },
158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750,
159 "Broadcom BCM5750 Gigabit Ethernet" },
160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M,
161 "Broadcom BCM5750M Gigabit Ethernet" },
162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751,
163 "Broadcom BCM5751 Gigabit Ethernet" },
158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782,
159 "Broadcom BCM5782 Gigabit Ethernet" },
160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788,
161 "Broadcom BCM5788 Gigabit Ethernet" },
162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901,
163 "Broadcom BCM5901 Fast Ethernet" },
164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2,
165 "Broadcom BCM5901A2 Fast Ethernet" },

--- 1045 unchanged lines hidden (view full) ---

1211 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t))
1212 BGE_MEMWIN_WRITE(sc, i, 0);
1213
1214 for (i = BGE_STATUS_BLOCK;
1215 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t))
1216 BGE_MEMWIN_WRITE(sc, i, 0);
1217
1218 /* Set up the PCI DMA control register. */
164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782,
165 "Broadcom BCM5782 Gigabit Ethernet" },
166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788,
167 "Broadcom BCM5788 Gigabit Ethernet" },
168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901,
169 "Broadcom BCM5901 Fast Ethernet" },
170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2,
171 "Broadcom BCM5901A2 Fast Ethernet" },

--- 1045 unchanged lines hidden (view full) ---

1217 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t))
1218 BGE_MEMWIN_WRITE(sc, i, 0);
1219
1220 for (i = BGE_STATUS_BLOCK;
1221 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t))
1222 BGE_MEMWIN_WRITE(sc, i, 0);
1223
1224 /* Set up the PCI DMA control register. */
1219 if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
1225 if (sc->bge_pcie) {
1226 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1227 (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1228 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1229 } else if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
1220 BGE_PCISTATE_PCI_BUSMODE) {
1221 /* Conventional PCI bus */
1222 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1223 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1224 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1225 (0x0F);
1226 } else {
1227 /* PCI-X bus */

--- 22 unchanged lines hidden (view full) ---

1250 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1251 if (tmp == 0x6 || tmp == 0x7)
1252 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1253 }
1254 }
1255
1256 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1257 sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1230 BGE_PCISTATE_PCI_BUSMODE) {
1231 /* Conventional PCI bus */
1232 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1233 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1234 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1235 (0x0F);
1236 } else {
1237 /* PCI-X bus */

--- 22 unchanged lines hidden (view full) ---

1260 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1261 if (tmp == 0x6 || tmp == 0x7)
1262 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1263 }
1264 }
1265
1266 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1267 sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1258 sc->bge_asicrev == BGE_ASICREV_BCM5705)
1268 sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
1269 sc->bge_asicrev == BGE_ASICREV_BCM5750)
1259 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1260 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1261
1262 /*
1263 * Set up general mode register.
1264 */
1265 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME|
1266 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA|

--- 36 unchanged lines hidden (view full) ---

1303 * we can access the first 32K of internal NIC RAM. This will
1304 * allow us to set up the TX send ring RCBs and the RX return
1305 * ring RCBs, plus other things which live in NIC memory.
1306 */
1307 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1308
1309 /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1310
1270 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1271 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1272
1273 /*
1274 * Set up general mode register.
1275 */
1276 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME|
1277 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA|

--- 36 unchanged lines hidden (view full) ---

1314 * we can access the first 32K of internal NIC RAM. This will
1315 * allow us to set up the TX send ring RCBs and the RX return
1316 * ring RCBs, plus other things which live in NIC memory.
1317 */
1318 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1319
1320 /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1321
1311 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
1322 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 ||
1323 sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1312 /* Configure mbuf memory pool */
1313 if (sc->bge_extram) {
1314 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
1315 BGE_EXT_SSRAM);
1316 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1317 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1318 else
1319 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);

--- 8 unchanged lines hidden (view full) ---

1328
1329 /* Configure DMA resource pool */
1330 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1331 BGE_DMA_DESCRIPTORS);
1332 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1333 }
1334
1335 /* Configure mbuf pool watermarks */
1324 /* Configure mbuf memory pool */
1325 if (sc->bge_extram) {
1326 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
1327 BGE_EXT_SSRAM);
1328 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1329 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1330 else
1331 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);

--- 8 unchanged lines hidden (view full) ---

1340
1341 /* Configure DMA resource pool */
1342 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1343 BGE_DMA_DESCRIPTORS);
1344 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1345 }
1346
1347 /* Configure mbuf pool watermarks */
1336 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) {
1348 if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
1349 sc->bge_asicrev == BGE_ASICREV_BCM5750) {
1337 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1338 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1339 } else {
1340 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1341 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1342 }
1343 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1344
1345 /* Configure DMA resource watermarks */
1346 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1347 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1348
1349 /* Enable buffer manager */
1350 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1351 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1352 } else {
1353 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1354 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1355 }
1356 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1357
1358 /* Configure DMA resource watermarks */
1359 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1360 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1361
1362 /* Enable buffer manager */
1350 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
1363 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 ||
1364 sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1351 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1352 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1353
1354 /* Poll for buffer manager start indication */
1355 for (i = 0; i < BGE_TIMEOUT; i++) {
1356 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1357 break;
1358 DELAY(10);

--- 26 unchanged lines hidden (view full) ---

1385 /* Initialize the standard RX ring control block */
1386 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1387 rcb->bge_hostaddr.bge_addr_lo =
1388 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1389 rcb->bge_hostaddr.bge_addr_hi =
1390 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1391 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1392 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
1365 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1366 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1367
1368 /* Poll for buffer manager start indication */
1369 for (i = 0; i < BGE_TIMEOUT; i++) {
1370 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1371 break;
1372 DELAY(10);

--- 26 unchanged lines hidden (view full) ---

1399 /* Initialize the standard RX ring control block */
1400 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
1401 rcb->bge_hostaddr.bge_addr_lo =
1402 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
1403 rcb->bge_hostaddr.bge_addr_hi =
1404 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
1405 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1406 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
1393 if (sc->bge_asicrev == BGE_ASICREV_BCM5705)
1407 if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
1408 sc->bge_asicrev == BGE_ASICREV_BCM5750)
1394 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1395 else
1396 rcb->bge_maxlen_flags =
1397 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1398 if (sc->bge_extram)
1399 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS;
1400 else
1401 rcb->bge_nicaddr = BGE_STD_RX_RINGS;

--- 5 unchanged lines hidden (view full) ---

1407
1408 /*
1409 * Initialize the jumbo RX ring control block
1410 * We set the 'ring disabled' bit in the flags
1411 * field until we're actually ready to start
1412 * using this ring (i.e. once we set the MTU
1413 * high enough to require it).
1414 */
1409 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1410 else
1411 rcb->bge_maxlen_flags =
1412 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1413 if (sc->bge_extram)
1414 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS;
1415 else
1416 rcb->bge_nicaddr = BGE_STD_RX_RINGS;

--- 5 unchanged lines hidden (view full) ---

1422
1423 /*
1424 * Initialize the jumbo RX ring control block
1425 * We set the 'ring disabled' bit in the flags
1426 * field until we're actually ready to start
1427 * using this ring (i.e. once we set the MTU
1428 * high enough to require it).
1429 */
1415 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
1430 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 ||
1431 sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1416 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1417
1418 rcb->bge_hostaddr.bge_addr_lo =
1419 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1420 rcb->bge_hostaddr.bge_addr_hi =
1421 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1422 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1423 sc->bge_cdata.bge_rx_jumbo_ring_map,

--- 47 unchanged lines hidden (view full) ---

1471 /* Configure TX RCB 0 (we use only the first ring) */
1472 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1473 BGE_SEND_RING_RCB);
1474 vrcb->bge_hostaddr.bge_addr_lo =
1475 htole32(BGE_ADDR_LO(sc->bge_ldata.bge_tx_ring_paddr));
1476 vrcb->bge_hostaddr.bge_addr_hi =
1477 htole32(BGE_ADDR_HI(sc->bge_ldata.bge_tx_ring_paddr));
1478 vrcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT);
1432 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1433
1434 rcb->bge_hostaddr.bge_addr_lo =
1435 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1436 rcb->bge_hostaddr.bge_addr_hi =
1437 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
1438 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1439 sc->bge_cdata.bge_rx_jumbo_ring_map,

--- 47 unchanged lines hidden (view full) ---

1487 /* Configure TX RCB 0 (we use only the first ring) */
1488 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1489 BGE_SEND_RING_RCB);
1490 vrcb->bge_hostaddr.bge_addr_lo =
1491 htole32(BGE_ADDR_LO(sc->bge_ldata.bge_tx_ring_paddr));
1492 vrcb->bge_hostaddr.bge_addr_hi =
1493 htole32(BGE_ADDR_HI(sc->bge_ldata.bge_tx_ring_paddr));
1494 vrcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT);
1479 if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
1495 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 ||
1496 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1480 vrcb->bge_maxlen_flags =
1481 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0);
1482
1483 /* Disable all unused RX return rings */
1484 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1485 BGE_RX_RETURN_RING_RCB);
1486 for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1487 vrcb->bge_hostaddr.bge_addr_hi = 0;

--- 72 unchanged lines hidden (view full) ---

1560 return(ENXIO);
1561 }
1562
1563 /* Set up host coalescing defaults */
1564 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1565 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1566 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1567 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1497 vrcb->bge_maxlen_flags =
1498 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0);
1499
1500 /* Disable all unused RX return rings */
1501 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1502 BGE_RX_RETURN_RING_RCB);
1503 for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1504 vrcb->bge_hostaddr.bge_addr_hi = 0;

--- 72 unchanged lines hidden (view full) ---

1577 return(ENXIO);
1578 }
1579
1580 /* Set up host coalescing defaults */
1581 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1582 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1583 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1584 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1568 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
1585 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 ||
1586 sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1569 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1570 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1571 }
1572 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0);
1573 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
1574
1575 /* Set up address of statistics block */
1587 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1588 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1589 }
1590 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0);
1591 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
1592
1593 /* Set up address of statistics block */
1576 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
1594 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 ||
1595 sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1577 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1578 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1579 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1580 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1581 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1582 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1583 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1584 }

--- 14 unchanged lines hidden (view full) ---

1599 /* Turn on RX BD completion state machine and enable attentions */
1600 CSR_WRITE_4(sc, BGE_RBDC_MODE,
1601 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1602
1603 /* Turn on RX list placement state machine */
1604 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1605
1606 /* Turn on RX list selector state machine. */
1596 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
1597 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
1598 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1599 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
1600 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1601 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1602 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1603 }

--- 14 unchanged lines hidden (view full) ---

1618 /* Turn on RX BD completion state machine and enable attentions */
1619 CSR_WRITE_4(sc, BGE_RBDC_MODE,
1620 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1621
1622 /* Turn on RX list placement state machine */
1623 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1624
1625 /* Turn on RX list selector state machine. */
1607 if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
1626 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 ||
1627 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1608 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1609
1610 /* Turn on DMA, clear stats */
1611 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
1612 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
1613 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
1614 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
1615 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII));

--- 5 unchanged lines hidden (view full) ---

1621 /* Assert GPIO pins for PHY reset */
1622 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1623 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1624 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1625 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1626#endif
1627
1628 /* Turn on DMA completion state machine */
1628 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1629
1630 /* Turn on DMA, clear stats */
1631 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
1632 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
1633 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
1634 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
1635 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII));

--- 5 unchanged lines hidden (view full) ---

1641 /* Assert GPIO pins for PHY reset */
1642 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1643 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1644 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1645 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1646#endif
1647
1648 /* Turn on DMA completion state machine */
1629 if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
1649 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 ||
1650 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1630 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1631
1632 /* Turn on write DMA state machine */
1633 CSR_WRITE_4(sc, BGE_WDMA_MODE,
1634 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS);
1635
1636 /* Turn on read DMA state machine */
1637 CSR_WRITE_4(sc, BGE_RDMA_MODE,

--- 4 unchanged lines hidden (view full) ---

1642
1643 /* Turn on RX BD initiator state machine */
1644 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1645
1646 /* Turn on RX data and RX BD initiator state machine */
1647 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1648
1649 /* Turn on Mbuf cluster free state machine */
1651 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1652
1653 /* Turn on write DMA state machine */
1654 CSR_WRITE_4(sc, BGE_WDMA_MODE,
1655 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS);
1656
1657 /* Turn on read DMA state machine */
1658 CSR_WRITE_4(sc, BGE_RDMA_MODE,

--- 4 unchanged lines hidden (view full) ---

1663
1664 /* Turn on RX BD initiator state machine */
1665 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1666
1667 /* Turn on RX data and RX BD initiator state machine */
1668 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1669
1670 /* Turn on Mbuf cluster free state machine */
1650 if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
1671 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 ||
1672 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1651 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1652
1653 /* Turn on send BD completion state machine */
1654 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1655
1656 /* Turn on send data completion state machine */
1657 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
1658

--- 317 unchanged lines hidden (view full) ---

1976 sc->bge_cdata.bge_rx_std_ring_map, sc->bge_ldata.bge_rx_std_ring,
1977 BGE_STD_RX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
1978
1979 if (error)
1980 return (ENOMEM);
1981
1982 sc->bge_ldata.bge_rx_std_ring_paddr = ctx.bge_busaddr;
1983
1673 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1674
1675 /* Turn on send BD completion state machine */
1676 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1677
1678 /* Turn on send data completion state machine */
1679 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
1680

--- 317 unchanged lines hidden (view full) ---

1998 sc->bge_cdata.bge_rx_std_ring_map, sc->bge_ldata.bge_rx_std_ring,
1999 BGE_STD_RX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
2000
2001 if (error)
2002 return (ENOMEM);
2003
2004 sc->bge_ldata.bge_rx_std_ring_paddr = ctx.bge_busaddr;
2005
1984 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
2006 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 ||
2007 sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1985
1986 /*
1987 * Create tag for jumbo mbufs.
1988 * This is really a bit of a kludge. We allocate a special
1989 * jumbo buffer pool which (thanks to the way our DMA
1990 * memory allocation works) will consist of contiguous
1991 * pages. This means that even though a jumbo buffer might
1992 * be larger than a page size, we don't really need to

--- 263 unchanged lines hidden (view full) ---

2256 error = ENXIO;
2257 goto fail;
2258 }
2259
2260 sc->bge_unit = unit;
2261
2262 BGE_LOCK_INIT(sc, device_get_nameunit(dev));
2263
2008
2009 /*
2010 * Create tag for jumbo mbufs.
2011 * This is really a bit of a kludge. We allocate a special
2012 * jumbo buffer pool which (thanks to the way our DMA
2013 * memory allocation works) will consist of contiguous
2014 * pages. This means that even though a jumbo buffer might
2015 * be larger than a page size, we don't really need to

--- 263 unchanged lines hidden (view full) ---

2279 error = ENXIO;
2280 goto fail;
2281 }
2282
2283 sc->bge_unit = unit;
2284
2285 BGE_LOCK_INIT(sc, device_get_nameunit(dev));
2286
2287 /* Save ASIC rev. */
2288
2289 sc->bge_chipid =
2290 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
2291 BGE_PCIMISCCTL_ASICREV;
2292 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
2293 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
2294
2295 /*
2296 * XXX: Broadcom Linux driver. Not in specs or eratta.
2297 * PCI-Express?
2298 */
2299 if (sc->bge_asicrev == BGE_ASICREV_BCM5750) {
2300 u_int32_t v;
2301
2302 v = pci_read_config(dev, BGE_PCI_MSI_CAPID, 4);
2303 if (((v >> 8) & 0xff) == BGE_PCIE_CAPID_REG) {
2304 v = pci_read_config(dev, BGE_PCIE_CAPID_REG, 4);
2305 if ((v & 0xff) == BGE_PCIE_CAPID)
2306 sc->bge_pcie = 1;
2307 }
2308 }
2309
2264 /* Try to reset the chip. */
2265 bge_reset(sc);
2266
2267 if (bge_chipinit(sc)) {
2268 printf("bge%d: chip initialization failed\n", sc->bge_unit);
2269 bge_release_resources(sc);
2270 error = ENXIO;
2271 goto fail;

--- 14 unchanged lines hidden (view full) ---

2286 } else if (bge_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
2287 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
2288 printf("bge%d: failed to read station address\n", unit);
2289 bge_release_resources(sc);
2290 error = ENXIO;
2291 goto fail;
2292 }
2293
2310 /* Try to reset the chip. */
2311 bge_reset(sc);
2312
2313 if (bge_chipinit(sc)) {
2314 printf("bge%d: chip initialization failed\n", sc->bge_unit);
2315 bge_release_resources(sc);
2316 error = ENXIO;
2317 goto fail;

--- 14 unchanged lines hidden (view full) ---

2332 } else if (bge_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,
2333 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
2334 printf("bge%d: failed to read station address\n", unit);
2335 bge_release_resources(sc);
2336 error = ENXIO;
2337 goto fail;
2338 }
2339
2294 /* Save ASIC rev. */
2295
2296 sc->bge_chipid =
2297 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
2298 BGE_PCIMISCCTL_ASICREV;
2299 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
2300 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
2301
2302 /* 5705 limits RX return ring to 512 entries. */
2340 /* 5705 limits RX return ring to 512 entries. */
2303 if (sc->bge_asicrev == BGE_ASICREV_BCM5705)
2341 if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
2342 sc->bge_asicrev == BGE_ASICREV_BCM5750)
2304 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
2305 else
2306 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
2307
2308 if (bge_dma_alloc(dev)) {
2309 printf ("bge%d: failed to allocate DMA resources\n",
2310 sc->bge_unit);
2311 bge_release_resources(sc);
2312 error = ENXIO;
2313 goto fail;
2314 }
2315
2316 /*
2317 * Try to allocate memory for jumbo buffers.
2318 * The 5705 does not appear to support jumbo frames.
2319 */
2343 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
2344 else
2345 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
2346
2347 if (bge_dma_alloc(dev)) {
2348 printf ("bge%d: failed to allocate DMA resources\n",
2349 sc->bge_unit);
2350 bge_release_resources(sc);
2351 error = ENXIO;
2352 goto fail;
2353 }
2354
2355 /*
2356 * Try to allocate memory for jumbo buffers.
2357 * The 5705 does not appear to support jumbo frames.
2358 */
2320 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
2359 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 ||
2360 sc->bge_asicrev != BGE_ASICREV_BCM5750) {
2321 if (bge_alloc_jumbo_mem(sc)) {
2322 printf("bge%d: jumbo buffer allocation "
2323 "failed\n", sc->bge_unit);
2324 bge_release_resources(sc);
2325 error = ENXIO;
2326 goto fail;
2327 }
2328 }

--- 131 unchanged lines hidden (view full) ---

2460 if (sc->bge_tbi) {
2461 ifmedia_removeall(&sc->bge_ifmedia);
2462 } else {
2463 bus_generic_detach(dev);
2464 device_delete_child(dev, sc->bge_miibus);
2465 }
2466
2467 bge_release_resources(sc);
2361 if (bge_alloc_jumbo_mem(sc)) {
2362 printf("bge%d: jumbo buffer allocation "
2363 "failed\n", sc->bge_unit);
2364 bge_release_resources(sc);
2365 error = ENXIO;
2366 goto fail;
2367 }
2368 }

--- 131 unchanged lines hidden (view full) ---

2500 if (sc->bge_tbi) {
2501 ifmedia_removeall(&sc->bge_ifmedia);
2502 } else {
2503 bus_generic_detach(dev);
2504 device_delete_child(dev, sc->bge_miibus);
2505 }
2506
2507 bge_release_resources(sc);
2468 if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
2508 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 ||
2509 sc->bge_asicrev != BGE_ASICREV_BCM5750)
2469 bge_free_jumbo_mem(sc);
2470
2471 return(0);
2472}
2473
2474static void
2475bge_release_resources(sc)
2476 struct bge_softc *sc;

--- 26 unchanged lines hidden (view full) ---

2503 return;
2504}
2505
2506static void
2507bge_reset(sc)
2508 struct bge_softc *sc;
2509{
2510 device_t dev;
2510 bge_free_jumbo_mem(sc);
2511
2512 return(0);
2513}
2514
2515static void
2516bge_release_resources(sc)
2517 struct bge_softc *sc;

--- 26 unchanged lines hidden (view full) ---

2544 return;
2545}
2546
2547static void
2548bge_reset(sc)
2549 struct bge_softc *sc;
2550{
2551 device_t dev;
2511 u_int32_t cachesize, command, pcistate;
2552 u_int32_t cachesize, command, pcistate, reset;
2512 int i, val = 0;
2513
2514 dev = sc->bge_dev;
2515
2516 /* Save some important PCI state. */
2517 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2518 command = pci_read_config(dev, BGE_PCI_CMD, 4);
2519 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2520
2521 pci_write_config(dev, BGE_PCI_MISC_CTL,
2522 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2523 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2524
2553 int i, val = 0;
2554
2555 dev = sc->bge_dev;
2556
2557 /* Save some important PCI state. */
2558 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2559 command = pci_read_config(dev, BGE_PCI_CMD, 4);
2560 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2561
2562 pci_write_config(dev, BGE_PCI_MISC_CTL,
2563 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2564 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2565
2566 reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2567
2568 /* XXX: Broadcom Linux driver. */
2569 if (sc->bge_pcie) {
2570 if (CSR_READ_4(sc, 0x7e2c) == 0x60) /* PCIE 1.0 */
2571 CSR_WRITE_4(sc, 0x7e2c, 0x20);
2572 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2573 /* Prevent PCIE link training during global reset */
2574 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
2575 reset |= (1<<29);
2576 }
2577 }
2578
2525 /* Issue global reset */
2579 /* Issue global reset */
2526 bge_writereg_ind(sc, BGE_MISC_CFG,
2527 BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1));
2580 bge_writereg_ind(sc, BGE_MISC_CFG, reset);
2528
2529 DELAY(1000);
2530
2581
2582 DELAY(1000);
2583
2584 /* XXX: Broadcom Linux driver. */
2585 if (sc->bge_pcie) {
2586 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
2587 uint32_t v;
2588
2589 DELAY(500000); /* wait for link training to complete */
2590 v = pci_read_config(dev, 0xc4, 4);
2591 pci_write_config(dev, 0xc4, v | (1<<15), 4);
2592 }
2593 /* Set PCIE max payload size and clear error status. */
2594 pci_write_config(dev, 0xd8, 0xf5000, 4);
2595 }
2596
2531 /* Reset some of the PCI state that got zapped by reset */
2532 pci_write_config(dev, BGE_PCI_MISC_CTL,
2533 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2534 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2535 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2536 pci_write_config(dev, BGE_PCI_CMD, command, 4);
2537 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1));
2538
2539 /* Enable memory arbiter. */
2597 /* Reset some of the PCI state that got zapped by reset */
2598 pci_write_config(dev, BGE_PCI_MISC_CTL,
2599 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2600 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2601 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2602 pci_write_config(dev, BGE_PCI_CMD, command, 4);
2603 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1));
2604
2605 /* Enable memory arbiter. */
2540 if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
2606 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 ||
2607 sc->bge_asicrev != BGE_ASICREV_BCM5750)
2541 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2542
2543 /*
2544 * Prevent PXE restart: write a magic number to the
2545 * general communications memory at 0xB50.
2546 */
2547 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2548 /*

--- 41 unchanged lines hidden (view full) ---

2590 */
2591 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && sc->bge_tbi) {
2592 uint32_t serdescfg;
2593 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2594 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2595 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2596 }
2597
2608 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2609
2610 /*
2611 * Prevent PXE restart: write a magic number to the
2612 * general communications memory at 0xB50.
2613 */
2614 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
2615 /*

--- 41 unchanged lines hidden (view full) ---

2657 */
2658 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && sc->bge_tbi) {
2659 uint32_t serdescfg;
2660 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
2661 serdescfg = (serdescfg & ~0xFFF) | 0x880;
2662 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
2663 }
2664
2665 /* XXX: Broadcom Linux driver. */
2666 if (sc->bge_pcie && sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
2667 uint32_t v;
2668
2669 v = CSR_READ_4(sc, 0x7c00);
2670 CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
2671 }
2598 DELAY(10000);
2599
2600 return;
2601}
2602
2603/*
2604 * Frame reception handling. This is called if there's a frame
2605 * on the receive return list.

--- 13 unchanged lines hidden (view full) ---

2619 BGE_LOCK_ASSERT(sc);
2620
2621 ifp = &sc->arpcom.ac_if;
2622
2623 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
2624 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTWRITE);
2625 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2626 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTREAD);
2672 DELAY(10000);
2673
2674 return;
2675}
2676
2677/*
2678 * Frame reception handling. This is called if there's a frame
2679 * on the receive return list.

--- 13 unchanged lines hidden (view full) ---

2693 BGE_LOCK_ASSERT(sc);
2694
2695 ifp = &sc->arpcom.ac_if;
2696
2697 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
2698 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTWRITE);
2699 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2700 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTREAD);
2627 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
2701 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 ||
2702 sc->bge_asicrev != BGE_ASICREV_BCM5750) {
2628 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2629 sc->bge_cdata.bge_rx_jumbo_ring_map,
2630 BUS_DMASYNC_POSTREAD);
2631 }
2632
2633 while(sc->bge_rx_saved_considx !=
2634 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) {
2635 struct bge_rx_bd *cur_rx;

--- 99 unchanged lines hidden (view full) ---

2735 BGE_LOCK(sc);
2736 }
2737
2738 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
2739 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREWRITE);
2740 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2741 sc->bge_cdata.bge_rx_std_ring_map,
2742 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_PREWRITE);
2703 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2704 sc->bge_cdata.bge_rx_jumbo_ring_map,
2705 BUS_DMASYNC_POSTREAD);
2706 }
2707
2708 while(sc->bge_rx_saved_considx !=
2709 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) {
2710 struct bge_rx_bd *cur_rx;

--- 99 unchanged lines hidden (view full) ---

2810 BGE_LOCK(sc);
2811 }
2812
2813 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
2814 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREWRITE);
2815 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2816 sc->bge_cdata.bge_rx_std_ring_map,
2817 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_PREWRITE);
2743 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
2818 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 ||
2819 sc->bge_asicrev != BGE_ASICREV_BCM5750) {
2744 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2745 sc->bge_cdata.bge_rx_jumbo_ring_map,
2746 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
2747 }
2748
2749 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2750 if (stdcnt)
2751 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);

--- 169 unchanged lines hidden (view full) ---

2921 struct mii_data *mii = NULL;
2922 struct ifmedia *ifm = NULL;
2923 struct ifnet *ifp;
2924
2925 ifp = &sc->arpcom.ac_if;
2926
2927 BGE_LOCK_ASSERT(sc);
2928
2820 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2821 sc->bge_cdata.bge_rx_jumbo_ring_map,
2822 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
2823 }
2824
2825 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2826 if (stdcnt)
2827 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);

--- 169 unchanged lines hidden (view full) ---

2997 struct mii_data *mii = NULL;
2998 struct ifmedia *ifm = NULL;
2999 struct ifnet *ifp;
3000
3001 ifp = &sc->arpcom.ac_if;
3002
3003 BGE_LOCK_ASSERT(sc);
3004
2929 if (sc->bge_asicrev == BGE_ASICREV_BCM5705)
3005 if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
3006 sc->bge_asicrev == BGE_ASICREV_BCM5750)
2930 bge_stats_update_regs(sc);
2931 else
2932 bge_stats_update(sc);
2933 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
2934 if (sc->bge_link)
2935 return;
2936
2937 if (sc->bge_tbi) {

--- 495 unchanged lines hidden (view full) ---

3433 struct bge_softc *sc = ifp->if_softc;
3434 struct ifreq *ifr = (struct ifreq *) data;
3435 int mask, error = 0;
3436 struct mii_data *mii;
3437
3438 switch(command) {
3439 case SIOCSIFMTU:
3440 /* Disallow jumbo frames on 5705. */
3007 bge_stats_update_regs(sc);
3008 else
3009 bge_stats_update(sc);
3010 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
3011 if (sc->bge_link)
3012 return;
3013
3014 if (sc->bge_tbi) {

--- 495 unchanged lines hidden (view full) ---

3510 struct bge_softc *sc = ifp->if_softc;
3511 struct ifreq *ifr = (struct ifreq *) data;
3512 int mask, error = 0;
3513 struct mii_data *mii;
3514
3515 switch(command) {
3516 case SIOCSIFMTU:
3517 /* Disallow jumbo frames on 5705. */
3441 if ((sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
3518 if (((sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
3519 sc->bge_asicrev == BGE_ASICREV_BCM5750) &&
3442 ifr->ifr_mtu > ETHERMTU) || ifr->ifr_mtu > BGE_JUMBO_MTU)
3443 error = EINVAL;
3444 else {
3445 ifp->if_mtu = ifr->ifr_mtu;
3446 ifp->if_flags &= ~IFF_RUNNING;
3447 bge_init(sc);
3448 }
3449 break;

--- 110 unchanged lines hidden (view full) ---

3560 callout_stop(&sc->bge_stat_ch);
3561
3562 /*
3563 * Disable all of the receiver blocks
3564 */
3565 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3566 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3567 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3520 ifr->ifr_mtu > ETHERMTU) || ifr->ifr_mtu > BGE_JUMBO_MTU)
3521 error = EINVAL;
3522 else {
3523 ifp->if_mtu = ifr->ifr_mtu;
3524 ifp->if_flags &= ~IFF_RUNNING;
3525 bge_init(sc);
3526 }
3527 break;

--- 110 unchanged lines hidden (view full) ---

3638 callout_stop(&sc->bge_stat_ch);
3639
3640 /*
3641 * Disable all of the receiver blocks
3642 */
3643 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
3644 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
3645 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
3568 if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
3646 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 ||
3647 sc->bge_asicrev != BGE_ASICREV_BCM5750)
3569 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
3570 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3571 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3572 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3573
3574 /*
3575 * Disable all of the transmit blocks
3576 */
3577 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3578 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3579 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3580 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3581 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3648 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
3649 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
3650 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
3651 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
3652
3653 /*
3654 * Disable all of the transmit blocks
3655 */
3656 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
3657 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
3658 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
3659 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
3660 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
3582 if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
3661 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 ||
3662 sc->bge_asicrev != BGE_ASICREV_BCM5750)
3583 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
3584 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3585
3586 /*
3587 * Shut down all of the memory managers and related
3588 * state machines.
3589 */
3590 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3591 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3663 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
3664 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
3665
3666 /*
3667 * Shut down all of the memory managers and related
3668 * state machines.
3669 */
3670 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
3671 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
3592 if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
3672 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 ||
3673 sc->bge_asicrev != BGE_ASICREV_BCM5750)
3593 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
3594 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3595 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3674 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
3675 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
3676 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
3596 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) {
3677 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 ||
3678 sc->bge_asicrev != BGE_ASICREV_BCM5750) {
3597 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
3598 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3599 }
3600
3601 /* Disable host interrupts. */
3602 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
3603 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
3604
3605 /*
3606 * Tell firmware we're shutting down.
3607 */
3608 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3609
3610 /* Free the RX lists. */
3611 bge_free_rx_ring_std(sc);
3612
3613 /* Free jumbo RX list. */
3679 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
3680 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
3681 }
3682
3683 /* Disable host interrupts. */
3684 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
3685 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
3686
3687 /*
3688 * Tell firmware we're shutting down.
3689 */
3690 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3691
3692 /* Free the RX lists. */
3693 bge_free_rx_ring_std(sc);
3694
3695 /* Free jumbo RX list. */
3614 if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
3696 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 ||
3697 sc->bge_asicrev != BGE_ASICREV_BCM5750)
3615 bge_free_rx_ring_jumbo(sc);
3616
3617 /* Free TX buffers. */
3618 bge_free_tx_ring(sc);
3619
3620 /*
3621 * Isolate/power down the PHY, but leave the media selection
3622 * unchanged so that things will be put back to normal when

--- 41 unchanged lines hidden --- 		3698 bge_free_rx_ring_jumbo(sc);
3699
3700 /* Free TX buffers. */
3701 bge_free_tx_ring(sc);
3702
3703 /*
3704 * Isolate/power down the PHY, but leave the media selection
3705 * unchanged so that things will be put back to normal when

--- 41 unchanged lines hidden ---