18 */
19#include "opt_ah.h"
20
21#include "ah.h"
22#include "ah_internal.h"
23#include "ah_devid.h"
24
25#include "ah_eeprom_v4k.h" /* XXX for tx/rx gain */
26
27#include "ar9002/ar9280.h"
28#include "ar9002/ar9285.h"
29#include "ar5416/ar5416reg.h"
30#include "ar5416/ar5416phy.h"
31
32#include "ar9002/ar9285.ini"
33#include "ar9002/ar9285v2.ini"
34#include "ar9002/ar9280v2.ini" /* XXX ini for tx/rx gain */
35
36#include "ar9002/ar9285_cal.h"
37#include "ar9002/ar9285_phy.h"
38#include "ar9002/ar9285_diversity.h"
39
40static const HAL_PERCAL_DATA ar9280_iq_cal = { /* single sample */
41 .calName = "IQ", .calType = IQ_MISMATCH_CAL,
42 .calNumSamples = MIN_CAL_SAMPLES,
43 .calCountMax = PER_MAX_LOG_COUNT,
44 .calCollect = ar5416IQCalCollect,
45 .calPostProc = ar5416IQCalibration
46};
47static const HAL_PERCAL_DATA ar9280_adc_gain_cal = { /* single sample */
48 .calName = "ADC Gain", .calType = ADC_GAIN_CAL,
49 .calNumSamples = MIN_CAL_SAMPLES,
50 .calCountMax = PER_MIN_LOG_COUNT,
51 .calCollect = ar5416AdcGainCalCollect,
52 .calPostProc = ar5416AdcGainCalibration
53};
54static const HAL_PERCAL_DATA ar9280_adc_dc_cal = { /* single sample */
55 .calName = "ADC DC", .calType = ADC_DC_CAL,
56 .calNumSamples = MIN_CAL_SAMPLES,
57 .calCountMax = PER_MIN_LOG_COUNT,
58 .calCollect = ar5416AdcDcCalCollect,
59 .calPostProc = ar5416AdcDcCalibration
60};
61static const HAL_PERCAL_DATA ar9280_adc_init_dc_cal = {
62 .calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL,
63 .calNumSamples = MIN_CAL_SAMPLES,
64 .calCountMax = INIT_LOG_COUNT,
65 .calCollect = ar5416AdcDcCalCollect,
66 .calPostProc = ar5416AdcDcCalibration
67};
68
69static void ar9285ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore,
70 HAL_BOOL power_off);
71static void ar9285DisablePCIE(struct ath_hal *ah);
72static HAL_BOOL ar9285FillCapabilityInfo(struct ath_hal *ah);
73static void ar9285WriteIni(struct ath_hal *ah,
74 const struct ieee80211_channel *chan);
75
76static void
77ar9285AniSetup(struct ath_hal *ah)
78{
79 /*
80 * These are the parameters from the AR5416 ANI code;
81 * they likely need quite a bit of adjustment for the
82 * AR9285.
83 */
84 static const struct ar5212AniParams aniparams = {
85 .maxNoiseImmunityLevel = 4, /* levels 0..4 */
86 .totalSizeDesired = { -55, -55, -55, -55, -62 },
87 .coarseHigh = { -14, -14, -14, -14, -12 },
88 .coarseLow = { -64, -64, -64, -64, -70 },
89 .firpwr = { -78, -78, -78, -78, -80 },
| 18 */
19#include "opt_ah.h"
20
21#include "ah.h"
22#include "ah_internal.h"
23#include "ah_devid.h"
24
25#include "ah_eeprom_v4k.h" /* XXX for tx/rx gain */
26
27#include "ar9002/ar9280.h"
28#include "ar9002/ar9285.h"
29#include "ar5416/ar5416reg.h"
30#include "ar5416/ar5416phy.h"
31
32#include "ar9002/ar9285.ini"
33#include "ar9002/ar9285v2.ini"
34#include "ar9002/ar9280v2.ini" /* XXX ini for tx/rx gain */
35
36#include "ar9002/ar9285_cal.h"
37#include "ar9002/ar9285_phy.h"
38#include "ar9002/ar9285_diversity.h"
39
40static const HAL_PERCAL_DATA ar9280_iq_cal = { /* single sample */
41 .calName = "IQ", .calType = IQ_MISMATCH_CAL,
42 .calNumSamples = MIN_CAL_SAMPLES,
43 .calCountMax = PER_MAX_LOG_COUNT,
44 .calCollect = ar5416IQCalCollect,
45 .calPostProc = ar5416IQCalibration
46};
47static const HAL_PERCAL_DATA ar9280_adc_gain_cal = { /* single sample */
48 .calName = "ADC Gain", .calType = ADC_GAIN_CAL,
49 .calNumSamples = MIN_CAL_SAMPLES,
50 .calCountMax = PER_MIN_LOG_COUNT,
51 .calCollect = ar5416AdcGainCalCollect,
52 .calPostProc = ar5416AdcGainCalibration
53};
54static const HAL_PERCAL_DATA ar9280_adc_dc_cal = { /* single sample */
55 .calName = "ADC DC", .calType = ADC_DC_CAL,
56 .calNumSamples = MIN_CAL_SAMPLES,
57 .calCountMax = PER_MIN_LOG_COUNT,
58 .calCollect = ar5416AdcDcCalCollect,
59 .calPostProc = ar5416AdcDcCalibration
60};
61static const HAL_PERCAL_DATA ar9280_adc_init_dc_cal = {
62 .calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL,
63 .calNumSamples = MIN_CAL_SAMPLES,
64 .calCountMax = INIT_LOG_COUNT,
65 .calCollect = ar5416AdcDcCalCollect,
66 .calPostProc = ar5416AdcDcCalibration
67};
68
69static void ar9285ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore,
70 HAL_BOOL power_off);
71static void ar9285DisablePCIE(struct ath_hal *ah);
72static HAL_BOOL ar9285FillCapabilityInfo(struct ath_hal *ah);
73static void ar9285WriteIni(struct ath_hal *ah,
74 const struct ieee80211_channel *chan);
75
76static void
77ar9285AniSetup(struct ath_hal *ah)
78{
79 /*
80 * These are the parameters from the AR5416 ANI code;
81 * they likely need quite a bit of adjustment for the
82 * AR9285.
83 */
84 static const struct ar5212AniParams aniparams = {
85 .maxNoiseImmunityLevel = 4, /* levels 0..4 */
86 .totalSizeDesired = { -55, -55, -55, -55, -62 },
87 .coarseHigh = { -14, -14, -14, -14, -12 },
88 .coarseLow = { -64, -64, -64, -64, -70 },
89 .firpwr = { -78, -78, -78, -78, -80 },
|
92 .maxFirstepLevel = 2, /* levels 0..2 */
93 .firstep = { 0, 4, 8 },
94 .ofdmTrigHigh = 500,
95 .ofdmTrigLow = 200,
96 .cckTrigHigh = 200,
97 .cckTrigLow = 100,
98 .rssiThrHigh = 40,
99 .rssiThrLow = 7,
100 .period = 100,
101 };
102 /* NB: disable ANI noise immmunity for reliable RIFS rx */
103 AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL);
104
105 ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE);
106}
107
108/*
109 * Attach for an AR9285 part.
110 */
111static struct ath_hal *
112ar9285Attach(uint16_t devid, HAL_SOFTC sc,
113 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata,
114 HAL_STATUS *status)
115{
116 struct ath_hal_9285 *ahp9285;
117 struct ath_hal_5212 *ahp;
118 struct ath_hal *ah;
119 uint32_t val;
120 HAL_STATUS ecode;
121 HAL_BOOL rfStatus;
122
123 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
124 __func__, sc, (void*) st, (void*) sh);
125
126 /* NB: memory is returned zero'd */
127 ahp9285 = ath_hal_malloc(sizeof (struct ath_hal_9285));
128 if (ahp9285 == AH_NULL) {
129 HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
130 "%s: cannot allocate memory for state block\n", __func__);
131 *status = HAL_ENOMEM;
132 return AH_NULL;
133 }
134 ahp = AH5212(ahp9285);
135 ah = &ahp->ah_priv.h;
136
137 ar5416InitState(AH5416(ah), devid, sc, st, sh, status);
138
139 /*
140 * Use the "local" EEPROM data given to us by the higher layers.
141 * This is a private copy out of system flash. The Linux ath9k
142 * commit for the initial AR9130 support mentions MMIO flash
143 * access is "unreliable." -adrian
144 */
145 if (eepromdata != AH_NULL) {
146 AH_PRIVATE(ah)->ah_eepromRead = ath_hal_EepromDataRead;
147 AH_PRIVATE(ah)->ah_eepromWrite = NULL;
148 ah->ah_eepromdata = eepromdata;
149 }
150
151 /* XXX override with 9285 specific state */
152 /* override 5416 methods for our needs */
153 AH5416(ah)->ah_initPLL = ar9280InitPLL;
154
155 ah->ah_setAntennaSwitch = ar9285SetAntennaSwitch;
156 ah->ah_configPCIE = ar9285ConfigPCIE;
157 ah->ah_disablePCIE = ar9285DisablePCIE;
158 ah->ah_setTxPower = ar9285SetTransmitPower;
159 ah->ah_setBoardValues = ar9285SetBoardValues;
160
161 AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal;
162 AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal;
163 AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal;
164 AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal;
165 AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
166
167 AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate;
168 AH5416(ah)->ah_writeIni = ar9285WriteIni;
169 AH5416(ah)->ah_rx_chainmask = AR9285_DEFAULT_RXCHAINMASK;
170 AH5416(ah)->ah_tx_chainmask = AR9285_DEFAULT_TXCHAINMASK;
171
172 ahp->ah_maxTxTrigLev = MAX_TX_FIFO_THRESHOLD >> 1;
173
174 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {
175 /* reset chip */
176 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n",
177 __func__);
178 ecode = HAL_EIO;
179 goto bad;
180 }
181
182 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
183 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n",
184 __func__);
185 ecode = HAL_EIO;
186 goto bad;
187 }
188 /* Read Revisions from Chips before taking out of reset */
189 val = OS_REG_READ(ah, AR_SREV);
190 HALDEBUG(ah, HAL_DEBUG_ATTACH,
191 "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n",
192 __func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION),
193 MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION));
194 /* NB: include chip type to differentiate from pre-Sowl versions */
195 AH_PRIVATE(ah)->ah_macVersion =
196 (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S;
197 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION);
198 AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0;
199
200 /* setup common ini data; rf backends handle remainder */
201 if (AR_SREV_KITE_12_OR_LATER(ah)) {
202 HAL_INI_INIT(&ahp->ah_ini_modes, ar9285Modes_v2, 6);
203 HAL_INI_INIT(&ahp->ah_ini_common, ar9285Common_v2, 2);
204 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
205 ar9285PciePhy_clkreq_always_on_L1_v2, 2);
206 } else {
207 HAL_INI_INIT(&ahp->ah_ini_modes, ar9285Modes, 6);
208 HAL_INI_INIT(&ahp->ah_ini_common, ar9285Common, 2);
209 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
210 ar9285PciePhy_clkreq_always_on_L1, 2);
211 }
212 ar5416AttachPCIE(ah);
213
214 /* Attach methods that require MAC version/revision info */
215 if (AR_SREV_KITE_12_OR_LATER(ah))
216 AH5416(ah)->ah_cal_initcal = ar9285InitCalHardware;
217 if (AR_SREV_KITE_11_OR_LATER(ah))
218 AH5416(ah)->ah_cal_pacal = ar9002_hw_pa_cal;
219
220 ecode = ath_hal_v4kEepromAttach(ah);
221 if (ecode != HAL_OK)
222 goto bad;
223
224 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */
225 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n",
226 __func__);
227 ecode = HAL_EIO;
228 goto bad;
229 }
230
231 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
232
233 if (!ar5212ChipTest(ah)) {
234 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
235 __func__);
236 ecode = HAL_ESELFTEST;
237 goto bad;
238 }
239
240 /*
241 * Set correct Baseband to analog shift
242 * setting to access analog chips.
243 */
244 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
245
246 /* Read Radio Chip Rev Extract */
247 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah);
248 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
249 case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */
250 case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */
251 break;
252 default:
253 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
254 AH_PRIVATE(ah)->ah_analog5GhzRev =
255 AR_RAD5133_SREV_MAJOR;
256 break;
257 }
258#ifdef AH_DEBUG
259 HALDEBUG(ah, HAL_DEBUG_ANY,
260 "%s: 5G Radio Chip Rev 0x%02X is not supported by "
261 "this driver\n", __func__,
262 AH_PRIVATE(ah)->ah_analog5GhzRev);
263 ecode = HAL_ENOTSUPP;
264 goto bad;
265#endif
266 }
267 rfStatus = ar9285RfAttach(ah, &ecode);
268 if (!rfStatus) {
269 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
270 __func__, ecode);
271 goto bad;
272 }
273
274 HAL_INI_INIT(&ahp9285->ah_ini_rxgain, ar9280Modes_original_rxgain_v2,
275 6);
276
277 if (AR_SREV_9285E_20(ah))
278 ath_hal_printf(ah, "[ath] AR9285E_20 detected; using XE TX gain tables\n");
279
280 /* setup txgain table */
281 switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) {
282 case AR5416_EEP_TXGAIN_HIGH_POWER:
283 if (AR_SREV_9285E_20(ah))
284 HAL_INI_INIT(&ahp9285->ah_ini_txgain,
285 ar9285Modes_XE2_0_high_power, 6);
286 else
287 HAL_INI_INIT(&ahp9285->ah_ini_txgain,
288 ar9285Modes_high_power_tx_gain_v2, 6);
289 break;
290 case AR5416_EEP_TXGAIN_ORIG:
291 if (AR_SREV_9285E_20(ah))
292 HAL_INI_INIT(&ahp9285->ah_ini_txgain,
293 ar9285Modes_XE2_0_normal_power, 6);
294 else
295 HAL_INI_INIT(&ahp9285->ah_ini_txgain,
296 ar9285Modes_original_tx_gain_v2, 6);
297 break;
298 default:
299 HALASSERT(AH_FALSE);
300 goto bad; /* XXX ? try to continue */
301 }
302
303 /*
304 * Got everything we need now to setup the capabilities.
305 */
306 if (!ar9285FillCapabilityInfo(ah)) {
307 ecode = HAL_EEREAD;
308 goto bad;
309 }
310
311 /* Print out whether the EEPROM settings enable AR9285 diversity */
312 if (ar9285_check_div_comb(ah)) {
313 ath_hal_printf(ah, "[ath] Enabling diversity for Kite\n");
314 ah->ah_rxAntCombDiversity = ar9285_ant_comb_scan;
315 }
316
317 /* Disable 11n for the AR2427 */
318 if (devid == AR2427_DEVID_PCIE)
319 AH_PRIVATE(ah)->ah_caps.halHTSupport = AH_FALSE;
320
321 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
322 if (ecode != HAL_OK) {
323 HALDEBUG(ah, HAL_DEBUG_ANY,
324 "%s: error getting mac address from EEPROM\n", __func__);
325 goto bad;
326 }
327 /* XXX How about the serial number ? */
328 /* Read Reg Domain */
329 AH_PRIVATE(ah)->ah_currentRD =
330 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL);
331 /*
332 * For Kite and later chipsets, the following bits are not
333 * programmed in EEPROM and so are set as enabled always.
334 */
335 AH_PRIVATE(ah)->ah_currentRDext = AR9285_RDEXT_DEFAULT;
336
337 /*
338 * ah_miscMode is populated by ar5416FillCapabilityInfo()
339 * starting from griffin. Set here to make sure that
340 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is
341 * placed into hardware.
342 */
343 if (ahp->ah_miscMode != 0)
344 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode);
345
346 ar9285AniSetup(ah); /* Anti Noise Immunity */
347
348 /* Setup noise floor min/max/nominal values */
349 AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ;
350 AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ;
351 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9285_2GHZ;
352 /* XXX no 5ghz values? */
353
354 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
355
356 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
357
358 return ah;
359bad:
360 if (ah != AH_NULL)
361 ah->ah_detach(ah);
362 if (status)
363 *status = ecode;
364 return AH_NULL;
365}
366
367static void
368ar9285ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off)
369{
370 uint32_t val;
371
372 /*
373 * This workaround needs some integration work with the HAL
374 * config parameters and the if_ath_pci.c glue.
375 * Specifically, read the value of the PCI register 0x70c
376 * (4 byte PCI config space register) and store it in ath_hal_war70c.
377 * Then if it's non-zero, the below WAR would override register
378 * 0x570c upon suspend/resume.
379 */
380#if 0
381 if (AR_SREV_9285E_20(ah)) {
382 val = AH_PRIVATE(ah)->ah_config.ath_hal_war70c;
383 if (val) {
384 val &= 0xffff00ff;
385 val |= 0x6f00;
386 OS_REG_WRITE(ah, 0x570c, val);
387 }
388 }
389#endif
390
391 if (AH_PRIVATE(ah)->ah_ispcie && !restore) {
392 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);
393 OS_DELAY(1000);
394 }
395
396 /*
397 * Set PCIe workaround bits
398 *
399 * NOTE:
400 *
401 * In Merlin and Kite, bit 14 in WA register (disable L1) should only
402 * be set when device enters D3 and be cleared when device comes back
403 * to D0.
404 */
405 if (power_off) { /* Power-off */
406 OS_REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
407
408 val = OS_REG_READ(ah, AR_WA);
409
410 /*
411 * Disable bit 6 and 7 before entering D3 to prevent
412 * system hang.
413 */
414 val &= ~(AR_WA_BIT6 | AR_WA_BIT7);
415
416 /*
417 * See above: set AR_WA_D3_L1_DISABLE when entering D3 state.
418 *
419 * XXX The reference HAL does it this way - it only sets
420 * AR_WA_D3_L1_DISABLE if it's set in AR9280_WA_DEFAULT,
421 * which it (currently) isn't. So the following statement
422 * is currently a NOP.
423 */
424 if (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)
425 val |= AR_WA_D3_L1_DISABLE;
426
427 if (AR_SREV_9285E_20(ah))
428 val |= AR_WA_BIT23;
429
430 OS_REG_WRITE(ah, AR_WA, val);
431 } else { /* Power-on */
432 val = AR9285_WA_DEFAULT;
433 /*
434 * See note above: make sure L1_DISABLE is not set.
435 */
436 val &= (~AR_WA_D3_L1_DISABLE);
437
438 /* Software workaroud for ASPM system hang. */
439 val |= (AR_WA_BIT6 | AR_WA_BIT7);
440
441 if (AR_SREV_9285E_20(ah))
442 val |= AR_WA_BIT23;
443
444 OS_REG_WRITE(ah, AR_WA, val);
445
446 /* set bit 19 to allow forcing of pcie core into L1 state */
447 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
448 }
449}
450
451static void
452ar9285DisablePCIE(struct ath_hal *ah)
453{
454}
455
456static void
457ar9285WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan)
458{
459 u_int modesIndex, freqIndex;
460 int regWrites = 0;
461
462 /* Setup the indices for the next set of register array writes */
463 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */
464 freqIndex = 2;
465 if (IEEE80211_IS_CHAN_HT40(chan))
466 modesIndex = 3;
467 else if (IEEE80211_IS_CHAN_108G(chan))
468 modesIndex = 5;
469 else
470 modesIndex = 4;
471
472 /* Set correct Baseband to analog shift setting to access analog chips. */
473 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
474 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
475 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes,
476 modesIndex, regWrites);
477 if (AR_SREV_KITE_12_OR_LATER(ah)) {
478 regWrites = ath_hal_ini_write(ah, &AH9285(ah)->ah_ini_txgain,
479 modesIndex, regWrites);
480 }
481 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common,
482 1, regWrites);
483}
484
485/*
486 * Fill all software cached or static hardware state information.
487 * Return failure if capabilities are to come from EEPROM and
488 * cannot be read.
489 */
490static HAL_BOOL
491ar9285FillCapabilityInfo(struct ath_hal *ah)
492{
493 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
494
495 if (!ar5416FillCapabilityInfo(ah))
496 return AH_FALSE;
497 pCap->halNumGpioPins = 12;
498 pCap->halWowSupport = AH_TRUE;
499 pCap->halWowMatchPatternExact = AH_TRUE;
500#if 0
501 pCap->halWowMatchPatternDword = AH_TRUE;
502#endif
503 /* AR9285 has 2 antennas but is a 1x1 stream device */
504 pCap->halTxStreams = 1;
505 pCap->halRxStreams = 1;
506
507 if (ar9285_check_div_comb(ah))
508 pCap->halAntDivCombSupport = AH_TRUE;
509
510 pCap->halCSTSupport = AH_TRUE;
511 pCap->halRifsRxSupport = AH_TRUE;
512 pCap->halRifsTxSupport = AH_TRUE;
513 pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */
514 pCap->halExtChanDfsSupport = AH_TRUE;
515 pCap->halUseCombinedRadarRssi = AH_TRUE;
516#if 0
517 /* XXX bluetooth */
518 pCap->halBtCoexSupport = AH_TRUE;
519#endif
520 pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */
521 pCap->hal4kbSplitTransSupport = AH_FALSE;
522 /* Disable this so Block-ACK works correctly */
523 pCap->halHasRxSelfLinkedTail = AH_FALSE;
524 pCap->halMbssidAggrSupport = AH_TRUE;
525 pCap->hal4AddrAggrSupport = AH_TRUE;
526
527 if (AR_SREV_KITE_12_OR_LATER(ah))
528 pCap->halPSPollBroken = AH_FALSE;
529
530 /* Only RX STBC supported */
531 pCap->halRxStbcSupport = 1;
532 pCap->halTxStbcSupport = 0;
533
534 return AH_TRUE;
535}
536
537static const char*
538ar9285Probe(uint16_t vendorid, uint16_t devid)
539{
540 if (vendorid == ATHEROS_VENDOR_ID && devid == AR9285_DEVID_PCIE)
541 return "Atheros 9285";
542 if (vendorid == ATHEROS_VENDOR_ID && (devid == AR2427_DEVID_PCIE))
543 return "Atheros 2427";
544
545 return AH_NULL;
546}
547AH_CHIP(AR9285, ar9285Probe, ar9285Attach);
| 92 .maxFirstepLevel = 2, /* levels 0..2 */
93 .firstep = { 0, 4, 8 },
94 .ofdmTrigHigh = 500,
95 .ofdmTrigLow = 200,
96 .cckTrigHigh = 200,
97 .cckTrigLow = 100,
98 .rssiThrHigh = 40,
99 .rssiThrLow = 7,
100 .period = 100,
101 };
102 /* NB: disable ANI noise immmunity for reliable RIFS rx */
103 AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL);
104
105 ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE);
106}
107
108/*
109 * Attach for an AR9285 part.
110 */
111static struct ath_hal *
112ar9285Attach(uint16_t devid, HAL_SOFTC sc,
113 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata,
114 HAL_STATUS *status)
115{
116 struct ath_hal_9285 *ahp9285;
117 struct ath_hal_5212 *ahp;
118 struct ath_hal *ah;
119 uint32_t val;
120 HAL_STATUS ecode;
121 HAL_BOOL rfStatus;
122
123 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
124 __func__, sc, (void*) st, (void*) sh);
125
126 /* NB: memory is returned zero'd */
127 ahp9285 = ath_hal_malloc(sizeof (struct ath_hal_9285));
128 if (ahp9285 == AH_NULL) {
129 HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
130 "%s: cannot allocate memory for state block\n", __func__);
131 *status = HAL_ENOMEM;
132 return AH_NULL;
133 }
134 ahp = AH5212(ahp9285);
135 ah = &ahp->ah_priv.h;
136
137 ar5416InitState(AH5416(ah), devid, sc, st, sh, status);
138
139 /*
140 * Use the "local" EEPROM data given to us by the higher layers.
141 * This is a private copy out of system flash. The Linux ath9k
142 * commit for the initial AR9130 support mentions MMIO flash
143 * access is "unreliable." -adrian
144 */
145 if (eepromdata != AH_NULL) {
146 AH_PRIVATE(ah)->ah_eepromRead = ath_hal_EepromDataRead;
147 AH_PRIVATE(ah)->ah_eepromWrite = NULL;
148 ah->ah_eepromdata = eepromdata;
149 }
150
151 /* XXX override with 9285 specific state */
152 /* override 5416 methods for our needs */
153 AH5416(ah)->ah_initPLL = ar9280InitPLL;
154
155 ah->ah_setAntennaSwitch = ar9285SetAntennaSwitch;
156 ah->ah_configPCIE = ar9285ConfigPCIE;
157 ah->ah_disablePCIE = ar9285DisablePCIE;
158 ah->ah_setTxPower = ar9285SetTransmitPower;
159 ah->ah_setBoardValues = ar9285SetBoardValues;
160
161 AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal;
162 AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal;
163 AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal;
164 AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal;
165 AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
166
167 AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate;
168 AH5416(ah)->ah_writeIni = ar9285WriteIni;
169 AH5416(ah)->ah_rx_chainmask = AR9285_DEFAULT_RXCHAINMASK;
170 AH5416(ah)->ah_tx_chainmask = AR9285_DEFAULT_TXCHAINMASK;
171
172 ahp->ah_maxTxTrigLev = MAX_TX_FIFO_THRESHOLD >> 1;
173
174 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {
175 /* reset chip */
176 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n",
177 __func__);
178 ecode = HAL_EIO;
179 goto bad;
180 }
181
182 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
183 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n",
184 __func__);
185 ecode = HAL_EIO;
186 goto bad;
187 }
188 /* Read Revisions from Chips before taking out of reset */
189 val = OS_REG_READ(ah, AR_SREV);
190 HALDEBUG(ah, HAL_DEBUG_ATTACH,
191 "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n",
192 __func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION),
193 MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION));
194 /* NB: include chip type to differentiate from pre-Sowl versions */
195 AH_PRIVATE(ah)->ah_macVersion =
196 (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S;
197 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION);
198 AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0;
199
200 /* setup common ini data; rf backends handle remainder */
201 if (AR_SREV_KITE_12_OR_LATER(ah)) {
202 HAL_INI_INIT(&ahp->ah_ini_modes, ar9285Modes_v2, 6);
203 HAL_INI_INIT(&ahp->ah_ini_common, ar9285Common_v2, 2);
204 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
205 ar9285PciePhy_clkreq_always_on_L1_v2, 2);
206 } else {
207 HAL_INI_INIT(&ahp->ah_ini_modes, ar9285Modes, 6);
208 HAL_INI_INIT(&ahp->ah_ini_common, ar9285Common, 2);
209 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
210 ar9285PciePhy_clkreq_always_on_L1, 2);
211 }
212 ar5416AttachPCIE(ah);
213
214 /* Attach methods that require MAC version/revision info */
215 if (AR_SREV_KITE_12_OR_LATER(ah))
216 AH5416(ah)->ah_cal_initcal = ar9285InitCalHardware;
217 if (AR_SREV_KITE_11_OR_LATER(ah))
218 AH5416(ah)->ah_cal_pacal = ar9002_hw_pa_cal;
219
220 ecode = ath_hal_v4kEepromAttach(ah);
221 if (ecode != HAL_OK)
222 goto bad;
223
224 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */
225 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n",
226 __func__);
227 ecode = HAL_EIO;
228 goto bad;
229 }
230
231 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
232
233 if (!ar5212ChipTest(ah)) {
234 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
235 __func__);
236 ecode = HAL_ESELFTEST;
237 goto bad;
238 }
239
240 /*
241 * Set correct Baseband to analog shift
242 * setting to access analog chips.
243 */
244 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
245
246 /* Read Radio Chip Rev Extract */
247 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah);
248 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
249 case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */
250 case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */
251 break;
252 default:
253 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
254 AH_PRIVATE(ah)->ah_analog5GhzRev =
255 AR_RAD5133_SREV_MAJOR;
256 break;
257 }
258#ifdef AH_DEBUG
259 HALDEBUG(ah, HAL_DEBUG_ANY,
260 "%s: 5G Radio Chip Rev 0x%02X is not supported by "
261 "this driver\n", __func__,
262 AH_PRIVATE(ah)->ah_analog5GhzRev);
263 ecode = HAL_ENOTSUPP;
264 goto bad;
265#endif
266 }
267 rfStatus = ar9285RfAttach(ah, &ecode);
268 if (!rfStatus) {
269 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
270 __func__, ecode);
271 goto bad;
272 }
273
274 HAL_INI_INIT(&ahp9285->ah_ini_rxgain, ar9280Modes_original_rxgain_v2,
275 6);
276
277 if (AR_SREV_9285E_20(ah))
278 ath_hal_printf(ah, "[ath] AR9285E_20 detected; using XE TX gain tables\n");
279
280 /* setup txgain table */
281 switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) {
282 case AR5416_EEP_TXGAIN_HIGH_POWER:
283 if (AR_SREV_9285E_20(ah))
284 HAL_INI_INIT(&ahp9285->ah_ini_txgain,
285 ar9285Modes_XE2_0_high_power, 6);
286 else
287 HAL_INI_INIT(&ahp9285->ah_ini_txgain,
288 ar9285Modes_high_power_tx_gain_v2, 6);
289 break;
290 case AR5416_EEP_TXGAIN_ORIG:
291 if (AR_SREV_9285E_20(ah))
292 HAL_INI_INIT(&ahp9285->ah_ini_txgain,
293 ar9285Modes_XE2_0_normal_power, 6);
294 else
295 HAL_INI_INIT(&ahp9285->ah_ini_txgain,
296 ar9285Modes_original_tx_gain_v2, 6);
297 break;
298 default:
299 HALASSERT(AH_FALSE);
300 goto bad; /* XXX ? try to continue */
301 }
302
303 /*
304 * Got everything we need now to setup the capabilities.
305 */
306 if (!ar9285FillCapabilityInfo(ah)) {
307 ecode = HAL_EEREAD;
308 goto bad;
309 }
310
311 /* Print out whether the EEPROM settings enable AR9285 diversity */
312 if (ar9285_check_div_comb(ah)) {
313 ath_hal_printf(ah, "[ath] Enabling diversity for Kite\n");
314 ah->ah_rxAntCombDiversity = ar9285_ant_comb_scan;
315 }
316
317 /* Disable 11n for the AR2427 */
318 if (devid == AR2427_DEVID_PCIE)
319 AH_PRIVATE(ah)->ah_caps.halHTSupport = AH_FALSE;
320
321 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
322 if (ecode != HAL_OK) {
323 HALDEBUG(ah, HAL_DEBUG_ANY,
324 "%s: error getting mac address from EEPROM\n", __func__);
325 goto bad;
326 }
327 /* XXX How about the serial number ? */
328 /* Read Reg Domain */
329 AH_PRIVATE(ah)->ah_currentRD =
330 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL);
331 /*
332 * For Kite and later chipsets, the following bits are not
333 * programmed in EEPROM and so are set as enabled always.
334 */
335 AH_PRIVATE(ah)->ah_currentRDext = AR9285_RDEXT_DEFAULT;
336
337 /*
338 * ah_miscMode is populated by ar5416FillCapabilityInfo()
339 * starting from griffin. Set here to make sure that
340 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is
341 * placed into hardware.
342 */
343 if (ahp->ah_miscMode != 0)
344 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode);
345
346 ar9285AniSetup(ah); /* Anti Noise Immunity */
347
348 /* Setup noise floor min/max/nominal values */
349 AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ;
350 AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ;
351 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9285_2GHZ;
352 /* XXX no 5ghz values? */
353
354 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
355
356 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
357
358 return ah;
359bad:
360 if (ah != AH_NULL)
361 ah->ah_detach(ah);
362 if (status)
363 *status = ecode;
364 return AH_NULL;
365}
366
367static void
368ar9285ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off)
369{
370 uint32_t val;
371
372 /*
373 * This workaround needs some integration work with the HAL
374 * config parameters and the if_ath_pci.c glue.
375 * Specifically, read the value of the PCI register 0x70c
376 * (4 byte PCI config space register) and store it in ath_hal_war70c.
377 * Then if it's non-zero, the below WAR would override register
378 * 0x570c upon suspend/resume.
379 */
380#if 0
381 if (AR_SREV_9285E_20(ah)) {
382 val = AH_PRIVATE(ah)->ah_config.ath_hal_war70c;
383 if (val) {
384 val &= 0xffff00ff;
385 val |= 0x6f00;
386 OS_REG_WRITE(ah, 0x570c, val);
387 }
388 }
389#endif
390
391 if (AH_PRIVATE(ah)->ah_ispcie && !restore) {
392 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);
393 OS_DELAY(1000);
394 }
395
396 /*
397 * Set PCIe workaround bits
398 *
399 * NOTE:
400 *
401 * In Merlin and Kite, bit 14 in WA register (disable L1) should only
402 * be set when device enters D3 and be cleared when device comes back
403 * to D0.
404 */
405 if (power_off) { /* Power-off */
406 OS_REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
407
408 val = OS_REG_READ(ah, AR_WA);
409
410 /*
411 * Disable bit 6 and 7 before entering D3 to prevent
412 * system hang.
413 */
414 val &= ~(AR_WA_BIT6 | AR_WA_BIT7);
415
416 /*
417 * See above: set AR_WA_D3_L1_DISABLE when entering D3 state.
418 *
419 * XXX The reference HAL does it this way - it only sets
420 * AR_WA_D3_L1_DISABLE if it's set in AR9280_WA_DEFAULT,
421 * which it (currently) isn't. So the following statement
422 * is currently a NOP.
423 */
424 if (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)
425 val |= AR_WA_D3_L1_DISABLE;
426
427 if (AR_SREV_9285E_20(ah))
428 val |= AR_WA_BIT23;
429
430 OS_REG_WRITE(ah, AR_WA, val);
431 } else { /* Power-on */
432 val = AR9285_WA_DEFAULT;
433 /*
434 * See note above: make sure L1_DISABLE is not set.
435 */
436 val &= (~AR_WA_D3_L1_DISABLE);
437
438 /* Software workaroud for ASPM system hang. */
439 val |= (AR_WA_BIT6 | AR_WA_BIT7);
440
441 if (AR_SREV_9285E_20(ah))
442 val |= AR_WA_BIT23;
443
444 OS_REG_WRITE(ah, AR_WA, val);
445
446 /* set bit 19 to allow forcing of pcie core into L1 state */
447 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
448 }
449}
450
451static void
452ar9285DisablePCIE(struct ath_hal *ah)
453{
454}
455
456static void
457ar9285WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan)
458{
459 u_int modesIndex, freqIndex;
460 int regWrites = 0;
461
462 /* Setup the indices for the next set of register array writes */
463 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */
464 freqIndex = 2;
465 if (IEEE80211_IS_CHAN_HT40(chan))
466 modesIndex = 3;
467 else if (IEEE80211_IS_CHAN_108G(chan))
468 modesIndex = 5;
469 else
470 modesIndex = 4;
471
472 /* Set correct Baseband to analog shift setting to access analog chips. */
473 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
474 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
475 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes,
476 modesIndex, regWrites);
477 if (AR_SREV_KITE_12_OR_LATER(ah)) {
478 regWrites = ath_hal_ini_write(ah, &AH9285(ah)->ah_ini_txgain,
479 modesIndex, regWrites);
480 }
481 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common,
482 1, regWrites);
483}
484
485/*
486 * Fill all software cached or static hardware state information.
487 * Return failure if capabilities are to come from EEPROM and
488 * cannot be read.
489 */
490static HAL_BOOL
491ar9285FillCapabilityInfo(struct ath_hal *ah)
492{
493 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
494
495 if (!ar5416FillCapabilityInfo(ah))
496 return AH_FALSE;
497 pCap->halNumGpioPins = 12;
498 pCap->halWowSupport = AH_TRUE;
499 pCap->halWowMatchPatternExact = AH_TRUE;
500#if 0
501 pCap->halWowMatchPatternDword = AH_TRUE;
502#endif
503 /* AR9285 has 2 antennas but is a 1x1 stream device */
504 pCap->halTxStreams = 1;
505 pCap->halRxStreams = 1;
506
507 if (ar9285_check_div_comb(ah))
508 pCap->halAntDivCombSupport = AH_TRUE;
509
510 pCap->halCSTSupport = AH_TRUE;
511 pCap->halRifsRxSupport = AH_TRUE;
512 pCap->halRifsTxSupport = AH_TRUE;
513 pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */
514 pCap->halExtChanDfsSupport = AH_TRUE;
515 pCap->halUseCombinedRadarRssi = AH_TRUE;
516#if 0
517 /* XXX bluetooth */
518 pCap->halBtCoexSupport = AH_TRUE;
519#endif
520 pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */
521 pCap->hal4kbSplitTransSupport = AH_FALSE;
522 /* Disable this so Block-ACK works correctly */
523 pCap->halHasRxSelfLinkedTail = AH_FALSE;
524 pCap->halMbssidAggrSupport = AH_TRUE;
525 pCap->hal4AddrAggrSupport = AH_TRUE;
526
527 if (AR_SREV_KITE_12_OR_LATER(ah))
528 pCap->halPSPollBroken = AH_FALSE;
529
530 /* Only RX STBC supported */
531 pCap->halRxStbcSupport = 1;
532 pCap->halTxStbcSupport = 0;
533
534 return AH_TRUE;
535}
536
537static const char*
538ar9285Probe(uint16_t vendorid, uint16_t devid)
539{
540 if (vendorid == ATHEROS_VENDOR_ID && devid == AR9285_DEVID_PCIE)
541 return "Atheros 9285";
542 if (vendorid == ATHEROS_VENDOR_ID && (devid == AR2427_DEVID_PCIE))
543 return "Atheros 2427";
544
545 return AH_NULL;
546}
547AH_CHIP(AR9285, ar9285Probe, ar9285Attach);
|