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ar5413.c (186333) ar5413.c (187831)
1/*
1/*
2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $Id: ar5413.c,v 1.8 2008/11/15 22:15:46 sam Exp $
17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5212/ar5413.c 187831 2009-01-28 18:00:22Z sam $
18 */
19#include "opt_ah.h"
20
21#include "ah.h"
22#include "ah_internal.h"
23
24#include "ah_eeprom_v3.h"
25

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70}
71
72/*
73 * Take the MHz channel value and set the Channel value
74 *
75 * ASSUMES: Writes enabled to analog bus
76 */
77static HAL_BOOL
18 */
19#include "opt_ah.h"
20
21#include "ah.h"
22#include "ah_internal.h"
23
24#include "ah_eeprom_v3.h"
25

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70}
71
72/*
73 * Take the MHz channel value and set the Channel value
74 *
75 * ASSUMES: Writes enabled to analog bus
76 */
77static HAL_BOOL
78ar5413SetChannel(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan)
78ar5413SetChannel(struct ath_hal *ah, const struct ieee80211_channel *chan)
79{
79{
80 uint16_t freq = ath_hal_gethwchannel(ah, chan);
80 uint32_t channelSel = 0;
81 uint32_t bModeSynth = 0;
82 uint32_t aModeRefSel = 0;
83 uint32_t reg32 = 0;
81 uint32_t channelSel = 0;
82 uint32_t bModeSynth = 0;
83 uint32_t aModeRefSel = 0;
84 uint32_t reg32 = 0;
84 uint16_t freq;
85
85
86 OS_MARK(ah, AH_MARK_SETCHANNEL, chan->channel);
86 OS_MARK(ah, AH_MARK_SETCHANNEL, freq);
87
87
88 if (chan->channel < 4800) {
88 if (freq < 4800) {
89 uint32_t txctl;
90
89 uint32_t txctl;
90
91 if (((chan->channel - 2192) % 5) == 0) {
92 channelSel = ((chan->channel - 672) * 2 - 3040)/10;
91 if (((freq - 2192) % 5) == 0) {
92 channelSel = ((freq - 672) * 2 - 3040)/10;
93 bModeSynth = 0;
93 bModeSynth = 0;
94 } else if (((chan->channel - 2224) % 5) == 0) {
95 channelSel = ((chan->channel - 704) * 2 - 3040) / 10;
94 } else if (((freq - 2224) % 5) == 0) {
95 channelSel = ((freq - 704) * 2 - 3040) / 10;
96 bModeSynth = 1;
97 } else {
98 HALDEBUG(ah, HAL_DEBUG_ANY,
99 "%s: invalid channel %u MHz\n",
96 bModeSynth = 1;
97 } else {
98 HALDEBUG(ah, HAL_DEBUG_ANY,
99 "%s: invalid channel %u MHz\n",
100 __func__, chan->channel);
100 __func__, freq);
101 return AH_FALSE;
102 }
103
104 channelSel = (channelSel << 2) & 0xff;
105 channelSel = ath_hal_reverseBits(channelSel, 8);
106
107 txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);
101 return AH_FALSE;
102 }
103
104 channelSel = (channelSel << 2) & 0xff;
105 channelSel = ath_hal_reverseBits(channelSel, 8);
106
107 txctl = OS_REG_READ(ah, AR_PHY_CCK_TX_CTRL);
108 if (chan->channel == 2484) {
108 if (freq == 2484) {
109 /* Enable channel spreading for channel 14 */
110 OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
111 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
112 } else {
113 OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
114 txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
115 }
109 /* Enable channel spreading for channel 14 */
110 OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
111 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
112 } else {
113 OS_REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
114 txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
115 }
116 } else if (((chan->channel % 5) == 2) && (chan->channel <= 5435)) {
117 freq = chan->channel - 2; /* Align to even 5MHz raster */
116 } else if (((freq % 5) == 2) && (freq <= 5435)) {
117 freq = freq - 2; /* Align to even 5MHz raster */
118 channelSel = ath_hal_reverseBits(
119 (uint32_t)(((freq - 4800)*10)/25 + 1), 8);
120 aModeRefSel = ath_hal_reverseBits(0, 2);
118 channelSel = ath_hal_reverseBits(
119 (uint32_t)(((freq - 4800)*10)/25 + 1), 8);
120 aModeRefSel = ath_hal_reverseBits(0, 2);
121 } else if ((chan->channel % 20) == 0 && chan->channel >= 5120) {
121 } else if ((freq % 20) == 0 && freq >= 5120) {
122 channelSel = ath_hal_reverseBits(
122 channelSel = ath_hal_reverseBits(
123 ((chan->channel - 4800) / 20 << 2), 8);
123 ((freq - 4800) / 20 << 2), 8);
124 aModeRefSel = ath_hal_reverseBits(1, 2);
124 aModeRefSel = ath_hal_reverseBits(1, 2);
125 } else if ((chan->channel % 10) == 0) {
125 } else if ((freq % 10) == 0) {
126 channelSel = ath_hal_reverseBits(
126 channelSel = ath_hal_reverseBits(
127 ((chan->channel - 4800) / 10 << 1), 8);
127 ((freq - 4800) / 10 << 1), 8);
128 aModeRefSel = ath_hal_reverseBits(1, 2);
128 aModeRefSel = ath_hal_reverseBits(1, 2);
129 } else if ((chan->channel % 5) == 0) {
129 } else if ((freq % 5) == 0) {
130 channelSel = ath_hal_reverseBits(
130 channelSel = ath_hal_reverseBits(
131 (chan->channel - 4800) / 5, 8);
131 (freq - 4800) / 5, 8);
132 aModeRefSel = ath_hal_reverseBits(1, 2);
133 } else {
134 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel %u MHz\n",
132 aModeRefSel = ath_hal_reverseBits(1, 2);
133 } else {
134 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel %u MHz\n",
135 __func__, chan->channel);
135 __func__, freq);
136 return AH_FALSE;
137 }
138
139 reg32 = (channelSel << 4) | (aModeRefSel << 2) | (bModeSynth << 1) |
140 (1 << 12) | 0x1;
141 OS_REG_WRITE(ah, AR_PHY(0x27), reg32 & 0xff);
142
143 reg32 >>= 8;

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149
150/*
151 * Reads EEPROM header info from device structure and programs
152 * all rf registers
153 *
154 * REQUIRES: Access to the analog rf device
155 */
156static HAL_BOOL
136 return AH_FALSE;
137 }
138
139 reg32 = (channelSel << 4) | (aModeRefSel << 2) | (bModeSynth << 1) |
140 (1 << 12) | 0x1;
141 OS_REG_WRITE(ah, AR_PHY(0x27), reg32 & 0xff);
142
143 reg32 >>= 8;

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149
150/*
151 * Reads EEPROM header info from device structure and programs
152 * all rf registers
153 *
154 * REQUIRES: Access to the analog rf device
155 */
156static HAL_BOOL
157ar5413SetRfRegs(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan, uint16_t modesIndex, uint16_t *rfXpdGain)
157ar5413SetRfRegs(struct ath_hal *ah,
158 const struct ieee80211_channel *chan,
159 uint16_t modesIndex, uint16_t *rfXpdGain)
158{
159#define RF_BANK_SETUP(_priv, _ix, _col) do { \
160 int i; \
161 for (i = 0; i < N(ar5212Bank##_ix##_5413); i++) \
162 (_priv)->Bank##_ix##Data[i] = ar5212Bank##_ix##_5413[i][_col];\
163} while (0)
164 struct ath_hal_5212 *ahp = AH5212(ah);
160{
161#define RF_BANK_SETUP(_priv, _ix, _col) do { \
162 int i; \
163 for (i = 0; i < N(ar5212Bank##_ix##_5413); i++) \
164 (_priv)->Bank##_ix##Data[i] = ar5212Bank##_ix##_5413[i][_col];\
165} while (0)
166 struct ath_hal_5212 *ahp = AH5212(ah);
167 uint16_t freq = ath_hal_gethwchannel(ah, chan);
165 const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
166 uint16_t ob5GHz = 0, db5GHz = 0;
167 uint16_t ob2GHz = 0, db2GHz = 0;
168 struct ar5413State *priv = AR5413(ah);
169 int regWrites = 0;
170
168 const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
169 uint16_t ob5GHz = 0, db5GHz = 0;
170 uint16_t ob2GHz = 0, db2GHz = 0;
171 struct ar5413State *priv = AR5413(ah);
172 int regWrites = 0;
173
171 HALDEBUG(ah, HAL_DEBUG_RFPARAM,
172 "%s: chan 0x%x flag 0x%x modesIndex 0x%x\n",
173 __func__, chan->channel, chan->channelFlags, modesIndex);
174 HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan %u/0x%x modesIndex %u\n",
175 __func__, chan->ic_freq, chan->ic_flags, modesIndex);
174
175 HALASSERT(priv != AH_NULL);
176
177 /* Setup rf parameters */
176
177 HALASSERT(priv != AH_NULL);
178
179 /* Setup rf parameters */
178 switch (chan->channelFlags & CHANNEL_ALL) {
179 case CHANNEL_A:
180 case CHANNEL_T:
181 if (chan->channel > 4000 && chan->channel < 5260) {
180 switch (chan->ic_flags & IEEE80211_CHAN_ALLFULL) {
181 case IEEE80211_CHAN_A:
182 if (freq > 4000 && freq < 5260) {
182 ob5GHz = ee->ee_ob1;
183 db5GHz = ee->ee_db1;
183 ob5GHz = ee->ee_ob1;
184 db5GHz = ee->ee_db1;
184 } else if (chan->channel >= 5260 && chan->channel < 5500) {
185 } else if (freq >= 5260 && freq < 5500) {
185 ob5GHz = ee->ee_ob2;
186 db5GHz = ee->ee_db2;
186 ob5GHz = ee->ee_ob2;
187 db5GHz = ee->ee_db2;
187 } else if (chan->channel >= 5500 && chan->channel < 5725) {
188 } else if (freq >= 5500 && freq < 5725) {
188 ob5GHz = ee->ee_ob3;
189 db5GHz = ee->ee_db3;
189 ob5GHz = ee->ee_ob3;
190 db5GHz = ee->ee_db3;
190 } else if (chan->channel >= 5725) {
191 } else if (freq >= 5725) {
191 ob5GHz = ee->ee_ob4;
192 db5GHz = ee->ee_db4;
193 } else {
194 /* XXX else */
195 }
196 break;
192 ob5GHz = ee->ee_ob4;
193 db5GHz = ee->ee_db4;
194 } else {
195 /* XXX else */
196 }
197 break;
197 case CHANNEL_B:
198 case IEEE80211_CHAN_B:
198 ob2GHz = ee->ee_obFor24;
199 db2GHz = ee->ee_dbFor24;
200 break;
199 ob2GHz = ee->ee_obFor24;
200 db2GHz = ee->ee_dbFor24;
201 break;
201 case CHANNEL_G:
202 case CHANNEL_108G:
202 case IEEE80211_CHAN_G:
203 case IEEE80211_CHAN_PUREG: /* NB: really 108G */
203 ob2GHz = ee->ee_obFor24g;
204 db2GHz = ee->ee_dbFor24g;
205 break;
206 default:
207 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
204 ob2GHz = ee->ee_obFor24g;
205 db2GHz = ee->ee_dbFor24g;
206 break;
207 default:
208 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel flags 0x%x\n",
208 __func__, chan->channelFlags);
209 __func__, chan->ic_flags);
209 return AH_FALSE;
210 }
211
212 /* Bank 1 Write */
213 RF_BANK_SETUP(priv, 1, 1);
214
215 /* Bank 2 Write */
216 RF_BANK_SETUP(priv, 2, modesIndex);
217
218 /* Bank 3 Write */
219 RF_BANK_SETUP(priv, 3, modesIndex);
220
221 /* Bank 6 Write */
222 RF_BANK_SETUP(priv, 6, modesIndex);
223
224 /* Only the 5 or 2 GHz OB/DB need to be set for a mode */
210 return AH_FALSE;
211 }
212
213 /* Bank 1 Write */
214 RF_BANK_SETUP(priv, 1, 1);
215
216 /* Bank 2 Write */
217 RF_BANK_SETUP(priv, 2, modesIndex);
218
219 /* Bank 3 Write */
220 RF_BANK_SETUP(priv, 3, modesIndex);
221
222 /* Bank 6 Write */
223 RF_BANK_SETUP(priv, 6, modesIndex);
224
225 /* Only the 5 or 2 GHz OB/DB need to be set for a mode */
225 if (IS_CHAN_2GHZ(chan)) {
226 if (IEEE80211_IS_CHAN_2GHZ(chan)) {
226 ar5212ModifyRfBuffer(priv->Bank6Data, ob2GHz, 3, 241, 0);
227 ar5212ModifyRfBuffer(priv->Bank6Data, db2GHz, 3, 238, 0);
228
229 /* TODO - only for Eagle 1.0 2GHz - remove for production */
230 /* XXX: but without this bit G doesn't work. */
231 ar5212ModifyRfBuffer(priv->Bank6Data, 1 , 1, 291, 2);
232
233 /* Optimum value for rf_pwd_iclobuf2G for PCIe chips only */

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532 return numPdGainsUsed;
533#undef VpdTable_L
534#undef VpdTable_R
535#undef VpdTable_I
536}
537
538static HAL_BOOL
539ar5413SetPowerTable(struct ath_hal *ah,
227 ar5212ModifyRfBuffer(priv->Bank6Data, ob2GHz, 3, 241, 0);
228 ar5212ModifyRfBuffer(priv->Bank6Data, db2GHz, 3, 238, 0);
229
230 /* TODO - only for Eagle 1.0 2GHz - remove for production */
231 /* XXX: but without this bit G doesn't work. */
232 ar5212ModifyRfBuffer(priv->Bank6Data, 1 , 1, 291, 2);
233
234 /* Optimum value for rf_pwd_iclobuf2G for PCIe chips only */

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533 return numPdGainsUsed;
534#undef VpdTable_L
535#undef VpdTable_R
536#undef VpdTable_I
537}
538
539static HAL_BOOL
540ar5413SetPowerTable(struct ath_hal *ah,
540 int16_t *minPower, int16_t *maxPower, HAL_CHANNEL_INTERNAL *chan,
541 int16_t *minPower, int16_t *maxPower,
542 const struct ieee80211_channel *chan,
541 uint16_t *rfXpdGain)
542{
543 struct ath_hal_5212 *ahp = AH5212(ah);
543 uint16_t *rfXpdGain)
544{
545 struct ath_hal_5212 *ahp = AH5212(ah);
546 uint16_t freq = ath_hal_gethwchannel(ah, chan);
544 const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
545 const RAW_DATA_STRUCT_2413 *pRawDataset = AH_NULL;
546 uint16_t pdGainOverlap_t2;
547 int16_t minCalPower5413_t2;
548 uint16_t *pdadcValues = ahp->ah_pcdacTable;
549 uint16_t gainBoundaries[4];
550 uint32_t reg32, regoffset;
551 int i, numPdGainsUsed;
552#ifndef AH_USE_INIPDGAIN
553 uint32_t tpcrg1;
554#endif
555
556 HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan 0x%x flag 0x%x\n",
547 const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
548 const RAW_DATA_STRUCT_2413 *pRawDataset = AH_NULL;
549 uint16_t pdGainOverlap_t2;
550 int16_t minCalPower5413_t2;
551 uint16_t *pdadcValues = ahp->ah_pcdacTable;
552 uint16_t gainBoundaries[4];
553 uint32_t reg32, regoffset;
554 int i, numPdGainsUsed;
555#ifndef AH_USE_INIPDGAIN
556 uint32_t tpcrg1;
557#endif
558
559 HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: chan 0x%x flag 0x%x\n",
557 __func__, chan->channel,chan->channelFlags);
560 __func__, chan->ic_freq, chan->ic_flags);
558
561
559 if (IS_CHAN_G(chan) || IS_CHAN_108G(chan))
562 if (IEEE80211_IS_CHAN_G(chan) || IEEE80211_IS_CHAN_108G(chan))
560 pRawDataset = &ee->ee_rawDataset2413[headerInfo11G];
563 pRawDataset = &ee->ee_rawDataset2413[headerInfo11G];
561 else if (IS_CHAN_B(chan))
564 else if (IEEE80211_IS_CHAN_B(chan))
562 pRawDataset = &ee->ee_rawDataset2413[headerInfo11B];
563 else {
565 pRawDataset = &ee->ee_rawDataset2413[headerInfo11B];
566 else {
564 HALASSERT(IS_CHAN_5GHZ(chan));
567 HALASSERT(IEEE80211_IS_CHAN_5GHZ(chan));
565 pRawDataset = &ee->ee_rawDataset2413[headerInfo11A];
566 }
567
568 pdGainOverlap_t2 = (uint16_t) SM(OS_REG_READ(ah, AR_PHY_TPCRG5),
569 AR_PHY_TPCRG5_PD_GAIN_OVERLAP);
570
571 numPdGainsUsed = ar5413getGainBoundariesAndPdadcsForPowers(ah,
568 pRawDataset = &ee->ee_rawDataset2413[headerInfo11A];
569 }
570
571 pdGainOverlap_t2 = (uint16_t) SM(OS_REG_READ(ah, AR_PHY_TPCRG5),
572 AR_PHY_TPCRG5_PD_GAIN_OVERLAP);
573
574 numPdGainsUsed = ar5413getGainBoundariesAndPdadcsForPowers(ah,
572 chan->channel, pRawDataset, pdGainOverlap_t2,
575 freq, pRawDataset, pdGainOverlap_t2,
573 &minCalPower5413_t2,gainBoundaries, rfXpdGain, pdadcValues);
574 HALASSERT(1 <= numPdGainsUsed && numPdGainsUsed <= 3);
575
576#ifdef AH_USE_INIPDGAIN
577 /*
578 * Use pd_gains curve from eeprom; Atheros always uses
579 * the default curve from the ini file but some vendors
580 * (e.g. Zcomax) want to override this curve and not

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671 Pmax = data->pDataPerPDGain[ii].pwr_t4[numVpd-1];
672 return(Pmax);
673 }
674 }
675 return(Pmax);
676}
677
678static HAL_BOOL
576 &minCalPower5413_t2,gainBoundaries, rfXpdGain, pdadcValues);
577 HALASSERT(1 <= numPdGainsUsed && numPdGainsUsed <= 3);
578
579#ifdef AH_USE_INIPDGAIN
580 /*
581 * Use pd_gains curve from eeprom; Atheros always uses
582 * the default curve from the ini file but some vendors
583 * (e.g. Zcomax) want to override this curve and not

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674 Pmax = data->pDataPerPDGain[ii].pwr_t4[numVpd-1];
675 return(Pmax);
676 }
677 }
678 return(Pmax);
679}
680
681static HAL_BOOL
679ar5413GetChannelMaxMinPower(struct ath_hal *ah, HAL_CHANNEL *chan,
682ar5413GetChannelMaxMinPower(struct ath_hal *ah,
683 const struct ieee80211_channel *chan,
680 int16_t *maxPow, int16_t *minPow)
681{
684 int16_t *maxPow, int16_t *minPow)
685{
686 uint16_t freq = chan->ic_freq; /* NB: never mapped */
682 const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
683 const RAW_DATA_STRUCT_2413 *pRawDataset = AH_NULL;
684 const RAW_DATA_PER_CHANNEL_2413 *data=AH_NULL;
685 uint16_t numChannels;
686 int totalD,totalF, totalMin,last, i;
687
688 *maxPow = 0;
689
687 const HAL_EEPROM *ee = AH_PRIVATE(ah)->ah_eeprom;
688 const RAW_DATA_STRUCT_2413 *pRawDataset = AH_NULL;
689 const RAW_DATA_PER_CHANNEL_2413 *data=AH_NULL;
690 uint16_t numChannels;
691 int totalD,totalF, totalMin,last, i;
692
693 *maxPow = 0;
694
690 if (IS_CHAN_G(chan) || IS_CHAN_108G(chan))
695 if (IEEE80211_IS_CHAN_G(chan) || IEEE80211_IS_CHAN_108G(chan))
691 pRawDataset = &ee->ee_rawDataset2413[headerInfo11G];
696 pRawDataset = &ee->ee_rawDataset2413[headerInfo11G];
692 else if (IS_CHAN_B(chan))
697 else if (IEEE80211_IS_CHAN_B(chan))
693 pRawDataset = &ee->ee_rawDataset2413[headerInfo11B];
694 else {
698 pRawDataset = &ee->ee_rawDataset2413[headerInfo11B];
699 else {
695 HALASSERT(IS_CHAN_5GHZ(chan));
700 HALASSERT(IEEE80211_IS_CHAN_5GHZ(chan));
696 pRawDataset = &ee->ee_rawDataset2413[headerInfo11A];
697 }
698
699 numChannels = pRawDataset->numChannels;
700 data = pRawDataset->pDataPerChannel;
701
702 /* Make sure the channel is in the range of the TP values
703 * (freq piers)
704 */
705 if (numChannels < 1)
706 return(AH_FALSE);
707
701 pRawDataset = &ee->ee_rawDataset2413[headerInfo11A];
702 }
703
704 numChannels = pRawDataset->numChannels;
705 data = pRawDataset->pDataPerChannel;
706
707 /* Make sure the channel is in the range of the TP values
708 * (freq piers)
709 */
710 if (numChannels < 1)
711 return(AH_FALSE);
712
708 if ((chan->channel < data[0].channelValue) ||
709 (chan->channel > data[numChannels-1].channelValue)) {
710 if (chan->channel < data[0].channelValue) {
713 if ((freq < data[0].channelValue) ||
714 (freq > data[numChannels-1].channelValue)) {
715 if (freq < data[0].channelValue) {
711 *maxPow = ar5413GetMaxPower(ah, &data[0]);
712 *minPow = ar5413GetMinPower(ah, &data[0]);
713 return(AH_TRUE);
714 } else {
715 *maxPow = ar5413GetMaxPower(ah, &data[numChannels - 1]);
716 *minPow = ar5413GetMinPower(ah, &data[numChannels - 1]);
717 return(AH_TRUE);
718 }
719 }
720
721 /* Linearly interpolate the power value now */
716 *maxPow = ar5413GetMaxPower(ah, &data[0]);
717 *minPow = ar5413GetMinPower(ah, &data[0]);
718 return(AH_TRUE);
719 } else {
720 *maxPow = ar5413GetMaxPower(ah, &data[numChannels - 1]);
721 *minPow = ar5413GetMinPower(ah, &data[numChannels - 1]);
722 return(AH_TRUE);
723 }
724 }
725
726 /* Linearly interpolate the power value now */
722 for (last=0,i=0; (i<numChannels) && (chan->channel > data[i].channelValue);
727 for (last=0,i=0; (i<numChannels) && (freq > data[i].channelValue);
723 last = i++);
724 totalD = data[i].channelValue - data[last].channelValue;
725 if (totalD > 0) {
726 totalF = ar5413GetMaxPower(ah, &data[i]) - ar5413GetMaxPower(ah, &data[last]);
728 last = i++);
729 totalD = data[i].channelValue - data[last].channelValue;
730 if (totalD > 0) {
731 totalF = ar5413GetMaxPower(ah, &data[i]) - ar5413GetMaxPower(ah, &data[last]);
727 *maxPow = (int8_t) ((totalF*(chan->channel-data[last].channelValue) +
732 *maxPow = (int8_t) ((totalF*(freq-data[last].channelValue) +
728 ar5413GetMaxPower(ah, &data[last])*totalD)/totalD);
729 totalMin = ar5413GetMinPower(ah, &data[i]) - ar5413GetMinPower(ah, &data[last]);
733 ar5413GetMaxPower(ah, &data[last])*totalD)/totalD);
734 totalMin = ar5413GetMinPower(ah, &data[i]) - ar5413GetMinPower(ah, &data[last]);
730 *minPow = (int8_t) ((totalMin*(chan->channel-data[last].channelValue) +
735 *minPow = (int8_t) ((totalMin*(freq-data[last].channelValue) +
731 ar5413GetMinPower(ah, &data[last])*totalD)/totalD);
732 return(AH_TRUE);
733 } else {
736 ar5413GetMinPower(ah, &data[last])*totalD)/totalD);
737 return(AH_TRUE);
738 } else {
734 if (chan->channel == data[i].channelValue) {
739 if (freq == data[i].channelValue) {
735 *maxPow = ar5413GetMaxPower(ah, &data[i]);
736 *minPow = ar5413GetMinPower(ah, &data[i]);
737 return(AH_TRUE);
738 } else
739 return(AH_FALSE);
740 }
741}
742

--- 55 unchanged lines hidden --- 		740 *maxPow = ar5413GetMaxPower(ah, &data[i]);
741 *minPow = ar5413GetMinPower(ah, &data[i]);
742 return(AH_TRUE);
743 } else
744 return(AH_FALSE);
745 }
746}
747

--- 55 unchanged lines hidden ---