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ah.h (190096) ah.h (192396)
1/*
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
1/*
2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 *
17 * $FreeBSD: head/sys/dev/ath/ath_hal/ah.h 190096 2009-03-19 19:29:10Z sam $
17 * $FreeBSD: head/sys/dev/ath/ath_hal/ah.h 192396 2009-05-19 17:30:13Z sam $
18 */
19
20#ifndef _ATH_AH_H_
21#define _ATH_AH_H_
22/*
23 * Atheros Hardware Access Layer
24 *
25 * Clients of the HAL call ath_hal_attach to obtain a reference to an ath_hal

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104 HAL_CAP_INTMIT = 29, /* interference mitigation */
105 HAL_CAP_RXORN_FATAL = 30, /* HAL_INT_RXORN treated as fatal */
106 HAL_CAP_HT = 31, /* hardware can support HT */
107 HAL_CAP_TX_CHAINMASK = 32, /* mask of TX chains supported */
108 HAL_CAP_RX_CHAINMASK = 33, /* mask of RX chains supported */
109 HAL_CAP_RXTSTAMP_PREC = 34, /* rx desc tstamp precision (bits) */
110 HAL_CAP_BB_HANG = 35, /* can baseband hang */
111 HAL_CAP_MAC_HANG = 36, /* can MAC hang */
18 */
19
20#ifndef _ATH_AH_H_
21#define _ATH_AH_H_
22/*
23 * Atheros Hardware Access Layer
24 *
25 * Clients of the HAL call ath_hal_attach to obtain a reference to an ath_hal

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104 HAL_CAP_INTMIT = 29, /* interference mitigation */
105 HAL_CAP_RXORN_FATAL = 30, /* HAL_INT_RXORN treated as fatal */
106 HAL_CAP_HT = 31, /* hardware can support HT */
107 HAL_CAP_TX_CHAINMASK = 32, /* mask of TX chains supported */
108 HAL_CAP_RX_CHAINMASK = 33, /* mask of RX chains supported */
109 HAL_CAP_RXTSTAMP_PREC = 34, /* rx desc tstamp precision (bits) */
110 HAL_CAP_BB_HANG = 35, /* can baseband hang */
111 HAL_CAP_MAC_HANG = 36, /* can MAC hang */
112 HAL_CAP_INTRMASK = 37, /* bitmask of supported interrupts */
112} HAL_CAPABILITY_TYPE;
113
114/*
115 * "States" for setting the LED. These correspond to
116 * the possible 802.11 operational states and there may
117 * be a many-to-one mapping between these states and the
118 * actual hardware state for the LED's (i.e. the hardware
119 * may have fewer states).

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343 | HAL_INT_DTIMSYNC
344 | HAL_INT_CABEND,
345
346 /* Interrupt bits that map directly to ISR/IMR bits */
347 HAL_INT_COMMON = HAL_INT_RXNOFRM
348 | HAL_INT_RXDESC
349 | HAL_INT_RXEOL
350 | HAL_INT_RXORN
113} HAL_CAPABILITY_TYPE;
114
115/*
116 * "States" for setting the LED. These correspond to
117 * the possible 802.11 operational states and there may
118 * be a many-to-one mapping between these states and the
119 * actual hardware state for the LED's (i.e. the hardware
120 * may have fewer states).

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344 | HAL_INT_DTIMSYNC
345 | HAL_INT_CABEND,
346
347 /* Interrupt bits that map directly to ISR/IMR bits */
348 HAL_INT_COMMON = HAL_INT_RXNOFRM
349 | HAL_INT_RXDESC
350 | HAL_INT_RXEOL
351 | HAL_INT_RXORN
351 | HAL_INT_TXURN
352 | HAL_INT_TXDESC
352 | HAL_INT_TXDESC
353 | HAL_INT_TXURN
353 | HAL_INT_MIB
354 | HAL_INT_RXPHY
355 | HAL_INT_RXKCM
356 | HAL_INT_SWBA
357 | HAL_INT_BMISS
358 | HAL_INT_GPIO,
359} HAL_INT;
360

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354 | HAL_INT_MIB
355 | HAL_INT_RXPHY
356 | HAL_INT_RXKCM
357 | HAL_INT_SWBA
358 | HAL_INT_BMISS
359 | HAL_INT_GPIO,
360} HAL_INT;
361

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