29
30#include "opt_ata.h"
31#include <sys/param.h>
32#include <sys/module.h>
33#include <sys/systm.h>
34#include <sys/kernel.h>
35#include <sys/ata.h>
36#include <sys/bus.h>
37#include <sys/endian.h>
38#include <sys/malloc.h>
39#include <sys/lock.h>
40#include <sys/mutex.h>
41#include <sys/sema.h>
42#include <sys/taskqueue.h>
43#include <vm/uma.h>
44#include <machine/stdarg.h>
45#include <machine/resource.h>
46#include <machine/bus.h>
47#include <sys/rman.h>
48#include <dev/pci/pcivar.h>
49#include <dev/pci/pcireg.h>
50#include <dev/ata/ata-all.h>
51#include <dev/ata/ata-pci.h>
52#include <ata_if.h>
53
54/* local prototypes */
55static int ata_cmd_ch_attach(device_t dev);
56static int ata_cmd_status(device_t dev);
57static int ata_cmd_setmode(device_t dev, int target, int mode);
58static int ata_sii_ch_attach(device_t dev);
59static int ata_sii_ch_detach(device_t dev);
60static int ata_sii_status(device_t dev);
61static void ata_sii_reset(device_t dev);
62static int ata_sii_setmode(device_t dev, int target, int mode);
63static int ata_siiprb_ch_attach(device_t dev);
64static int ata_siiprb_ch_detach(device_t dev);
65static int ata_siiprb_status(device_t dev);
66static int ata_siiprb_begin_transaction(struct ata_request *request);
67static int ata_siiprb_end_transaction(struct ata_request *request);
68static int ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result);
69static int ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t result);
70static u_int32_t ata_siiprb_softreset(device_t dev, int port);
71static void ata_siiprb_reset(device_t dev);
72static void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
73static void ata_siiprb_dmainit(device_t dev);
74
75/* misc defines */
76#define SII_MEMIO 1
77#define SII_PRBIO 2
78#define SII_INTR 0x01
79#define SII_SETCLK 0x02
80#define SII_BUG 0x04
81#define SII_4CH 0x08
82
83
84/*
85 * Silicon Image Inc. (SiI) (former CMD) chipset support functions
86 */
87static int
88ata_sii_probe(device_t dev)
89{
90 struct ata_pci_controller *ctlr = device_get_softc(dev);
91 static struct ata_chip_id ids[] =
92 {{ ATA_SII3114, 0x00, SII_MEMIO, SII_4CH, ATA_SA150, "3114" },
93 { ATA_SII3512, 0x02, SII_MEMIO, 0, ATA_SA150, "3512" },
94 { ATA_SII3112, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" },
95 { ATA_SII3112_1, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" },
96 { ATA_SII3512, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3512" },
97 { ATA_SII3112, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" },
98 { ATA_SII3112_1, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" },
99 { ATA_SII3124, 0x00, SII_PRBIO, SII_4CH, ATA_SA300, "3124" },
100 { ATA_SII3132, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" },
101 { ATA_SII3132_1, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" },
102 { ATA_SII3132_2, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" },
103 { ATA_SII0680, 0x00, SII_MEMIO, SII_SETCLK, ATA_UDMA6, "680" },
104 { ATA_CMD649, 0x00, 0, SII_INTR, ATA_UDMA5, "(CMD) 649" },
105 { ATA_CMD648, 0x00, 0, SII_INTR, ATA_UDMA4, "(CMD) 648" },
106 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "(CMD) 646U2" },
107 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "(CMD) 646" },
108 { 0, 0, 0, 0, 0, 0}};
109
110 if (pci_get_vendor(dev) != ATA_SILICON_IMAGE_ID)
111 return ENXIO;
112
113 if (!(ctlr->chip = ata_match_chip(dev, ids)))
114 return ENXIO;
115
116 ata_set_desc(dev);
117 ctlr->chipinit = ata_sii_chipinit;
118 return (BUS_PROBE_DEFAULT);
119}
120
121int
122ata_sii_chipinit(device_t dev)
123{
124 struct ata_pci_controller *ctlr = device_get_softc(dev);
125
126 if (ata_setup_interrupt(dev, ata_generic_intr))
127 return ENXIO;
128
129 switch (ctlr->chip->cfg1) {
130 case SII_PRBIO:
131 ctlr->r_type1 = SYS_RES_MEMORY;
132 ctlr->r_rid1 = PCIR_BAR(0);
133 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
134 &ctlr->r_rid1, RF_ACTIVE)))
135 return ENXIO;
136
137 ctlr->r_rid2 = PCIR_BAR(2);
138 ctlr->r_type2 = SYS_RES_MEMORY;
139 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
140 &ctlr->r_rid2, RF_ACTIVE))){
141 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1);
142 return ENXIO;
143 }
144 ctlr->ch_attach = ata_siiprb_ch_attach;
145 ctlr->ch_detach = ata_siiprb_ch_detach;
146 ctlr->reset = ata_siiprb_reset;
147 ctlr->setmode = ata_sata_setmode;
148 ctlr->getrev = ata_sata_getrev;
149 ctlr->channels = (ctlr->chip->cfg2 == SII_4CH) ? 4 : 2;
150
151 /* reset controller */
152 ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000);
153 DELAY(10000);
154 ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f);
155 break;
156
157 case SII_MEMIO:
158 ctlr->r_type2 = SYS_RES_MEMORY;
159 ctlr->r_rid2 = PCIR_BAR(5);
160 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
161 &ctlr->r_rid2, RF_ACTIVE))){
162 if (ctlr->chip->chipid != ATA_SII0680 ||
163 (pci_read_config(dev, 0x8a, 1) & 1))
164 return ENXIO;
165 }
166
167 if (ctlr->chip->cfg2 & SII_SETCLK) {
168 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
169 pci_write_config(dev, 0x8a,
170 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1);
171 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
172 device_printf(dev, "%s could not set ATA133 clock\n",
173 ctlr->chip->text);
174 }
175
176 /* if we have 4 channels enable the second set */
177 if (ctlr->chip->cfg2 & SII_4CH) {
178 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002);
179 ctlr->channels = 4;
180 }
181
182 /* dont block interrupts from any channel */
183 pci_write_config(dev, 0x48,
184 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4);
185
186 /* enable PCI interrupt as BIOS might not */
187 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1);
188
189 if (ctlr->r_res2) {
190 ctlr->ch_attach = ata_sii_ch_attach;
191 ctlr->ch_detach = ata_sii_ch_detach;
192 }
193
194 if (ctlr->chip->max_dma >= ATA_SA150) {
195 ctlr->reset = ata_sii_reset;
196 ctlr->setmode = ata_sata_setmode;
197 ctlr->getrev = ata_sata_getrev;
198 }
199 else
200 ctlr->setmode = ata_sii_setmode;
201 break;
202
203 default:
204 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) {
205 device_printf(dev, "HW has secondary channel disabled\n");
206 ctlr->channels = 1;
207 }
208
209 /* enable interrupt as BIOS might not */
210 pci_write_config(dev, 0x71, 0x01, 1);
211
212 ctlr->ch_attach = ata_cmd_ch_attach;
213 ctlr->ch_detach = ata_pci_ch_detach;
214 ctlr->setmode = ata_cmd_setmode;
215 break;
216 }
217 return 0;
218}
219
220static int
221ata_cmd_ch_attach(device_t dev)
222{
223 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
224 struct ata_channel *ch = device_get_softc(dev);
225
226 /* setup the usual register normal pci style */
227 if (ata_pci_ch_attach(dev))
228 return ENXIO;
229
230 if (ctlr->chip->cfg2 & SII_INTR)
231 ch->hw.status = ata_cmd_status;
232
233 return 0;
234}
235
236static int
237ata_cmd_status(device_t dev)
238{
239 struct ata_channel *ch = device_get_softc(dev);
240 u_int8_t reg71;
241
242 if (((reg71 = pci_read_config(device_get_parent(dev), 0x71, 1)) &
243 (ch->unit ? 0x08 : 0x04))) {
244 pci_write_config(device_get_parent(dev), 0x71,
245 reg71 & ~(ch->unit ? 0x04 : 0x08), 1);
246 return ata_pci_status(dev);
247 }
248 return 0;
249}
250
251static int
252ata_cmd_setmode(device_t dev, int target, int mode)
253{
254 device_t parent = device_get_parent(dev);
255 struct ata_pci_controller *ctlr = device_get_softc(parent);
256 struct ata_channel *ch = device_get_softc(dev);
257 int devno = (ch->unit << 1) + target;
258 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7);
259 int ureg = ch->unit ? 0x7b : 0x73;
260 int piomode;
261 uint8_t piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f, 0x87, 0x32, 0x3f };
262 uint8_t udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 },
263 { 0x11, 0x42 }, { 0x25, 0x8a },
264 { 0x15, 0x4a }, { 0x05, 0x0a } };
265
266 mode = min(mode, ctlr->chip->max_dma);
267 if (mode >= ATA_UDMA0) {
268 u_int8_t umode = pci_read_config(parent, ureg, 1);
269
270 umode &= ~(target == 0 ? 0x35 : 0xca);
271 umode |= udmatimings[mode & ATA_MODE_MASK][target];
272 pci_write_config(parent, ureg, umode, 1);
273 piomode = ATA_PIO4;
274 } else {
275 pci_write_config(parent, ureg,
276 pci_read_config(parent, ureg, 1) &
277 ~(target == 0 ? 0x35 : 0xca), 1);
278 piomode = mode;
279 }
280 pci_write_config(parent, treg, piotimings[ata_mode2idx(piomode)], 1);
281 return (mode);
282}
283
284static int
285ata_sii_ch_attach(device_t dev)
286{
287 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
288 struct ata_channel *ch = device_get_softc(dev);
289 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
290 int i;
291
292 ata_pci_dmainit(dev);
293
294 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
295 ch->r_io[i].res = ctlr->r_res2;
296 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8);
297 }
298 ch->r_io[ATA_CONTROL].res = ctlr->r_res2;
299 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8);
300 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
301 ata_default_registers(dev);
302
303 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2;
304 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8);
305 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2;
306 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8);
307 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2;
308 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8);
309
310 if (ctlr->chip->max_dma >= ATA_SA150) {
311 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
312 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8);
313 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
314 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8);
315 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
316 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8);
317 ch->flags |= ATA_NO_SLAVE;
318 ch->flags |= ATA_SATA;
319 ch->flags |= ATA_KNOWN_PRESENCE;
320
321 /* enable PHY state change interrupt */
322 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16));
323 }
324
325 if (ctlr->chip->cfg2 & SII_BUG) {
326 /* work around errata in early chips */
327 ch->dma.boundary = 8192;
328 ch->dma.segsize = 15 * DEV_BSIZE;
329 }
330
331 ata_pci_hw(dev);
332 ch->hw.status = ata_sii_status;
333 if (ctlr->chip->cfg2 & SII_SETCLK)
334 ch->flags |= ATA_CHECKS_CABLE;
335 return 0;
336}
337
338static int
339ata_sii_ch_detach(device_t dev)
340{
341
342 ata_pci_dmafini(dev);
343 return (0);
344}
345
346static int
347ata_sii_status(device_t dev)
348{
349 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
350 struct ata_channel *ch = device_get_softc(dev);
351 int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8);
352 int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8);
353
354 /* do we have any PHY events ? */
355 if (ctlr->chip->max_dma >= ATA_SA150 &&
356 (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010))
357 ata_sata_phy_check_events(dev);
358
359 if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800)
360 return ata_pci_status(dev);
361 else
362 return 0;
363}
364
365static void
366ata_sii_reset(device_t dev)
367{
368 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
369 struct ata_channel *ch = device_get_softc(dev);
370 int offset = ((ch->unit & 1) << 7) + ((ch->unit & 2) << 8);
371 uint32_t val;
372
373 /* Apply R_ERR on DMA activate FIS errata workaround. */
374 val = ATA_INL(ctlr->r_res2, 0x14c + offset);
375 if ((val & 0x3) == 0x1)
376 ATA_OUTL(ctlr->r_res2, 0x14c + offset, val & ~0x3);
377
378 if (ata_sata_phy_reset(dev, -1, 1))
379 ata_generic_reset(dev);
380 else
381 ch->devices = 0;
382}
383
384static int
385ata_sii_setmode(device_t dev, int target, int mode)
386{
387 device_t parent = device_get_parent(dev);
388 struct ata_pci_controller *ctlr = device_get_softc(parent);
389 struct ata_channel *ch = device_get_softc(dev);
390 int rego = (ch->unit << 4) + (target << 1);
391 int mreg = ch->unit ? 0x84 : 0x80;
392 int mask = 0x03 << (target << 2);
393 int mval = pci_read_config(parent, mreg, 1) & ~mask;
394 int piomode;
395 u_int8_t preg = 0xa4 + rego;
396 u_int8_t dreg = 0xa8 + rego;
397 u_int8_t ureg = 0xac + rego;
398 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
399 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 };
400 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 };
401
402 mode = min(mode, ctlr->chip->max_dma);
403
404 if (ctlr->chip->cfg2 & SII_SETCLK) {
405 if (ata_dma_check_80pin && mode > ATA_UDMA2 &&
406 (pci_read_config(parent, 0x79, 1) &
407 (ch->unit ? 0x02 : 0x01))) {
408 ata_print_cable(dev, "controller");
409 mode = ATA_UDMA2;
410 }
411 }
412 if (mode >= ATA_UDMA0) {
413 pci_write_config(parent, mreg,
414 mval | (0x03 << (target << 2)), 1);
415 pci_write_config(parent, ureg,
416 (pci_read_config(parent, ureg, 1) & ~0x3f) |
417 udmatimings[mode & ATA_MODE_MASK], 1);
418 piomode = ATA_PIO4;
419 } else if (mode >= ATA_WDMA0) {
420 pci_write_config(parent, mreg,
421 mval | (0x02 << (target << 2)), 1);
422 pci_write_config(parent, dreg, dmatimings[mode & ATA_MODE_MASK], 2);
423 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 :
424 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4;
425 } else {
426 pci_write_config(parent, mreg,
427 mval | (0x01 << (target << 2)), 1);
428 piomode = mode;
429 }
430 pci_write_config(parent, preg, piotimings[ata_mode2idx(piomode)], 2);
431 return (mode);
432}
433
434
435struct ata_siiprb_dma_prdentry {
436 u_int64_t addr;
437 u_int32_t count;
438 u_int32_t control;
439} __packed;
440
441#define ATA_SIIPRB_DMA_ENTRIES 129
442struct ata_siiprb_ata_command {
443 struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES];
444} __packed;
445
446struct ata_siiprb_atapi_command {
447 u_int8_t ccb[16];
448 struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES];
449} __packed;
450
451struct ata_siiprb_command {
452 u_int16_t control;
453 u_int16_t protocol_override;
454 u_int32_t transfer_count;
455 u_int8_t fis[24];
456 union {
457 struct ata_siiprb_ata_command ata;
458 struct ata_siiprb_atapi_command atapi;
459 } u;
460} __packed;
461
462static int
463ata_siiprb_ch_attach(device_t dev)
464{
465 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
466 struct ata_channel *ch = device_get_softc(dev);
467 int offset = ch->unit * 0x2000;
468
469 ata_siiprb_dmainit(dev);
470
471 /* set the SATA resources */
472 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
473 ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset;
474 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
475 ch->r_io[ATA_SERROR].offset = 0x1f08 + offset;
476 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
477 ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset;
478 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
479 ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset;
480
481 ch->hw.status = ata_siiprb_status;
482 ch->hw.begin_transaction = ata_siiprb_begin_transaction;
483 ch->hw.end_transaction = ata_siiprb_end_transaction;
484 ch->hw.command = NULL; /* not used here */
485 ch->hw.softreset = ata_siiprb_softreset;
486 ch->hw.pm_read = ata_siiprb_pm_read;
487 ch->hw.pm_write = ata_siiprb_pm_write;
488 ch->flags |= ATA_NO_SLAVE;
489 ch->flags |= ATA_SATA;
490 return 0;
491}
492
493static int
494ata_siiprb_ch_detach(device_t dev)
495{
496
497 ata_dmafini(dev);
498 return 0;
499}
500
501static int
502ata_siiprb_status(device_t dev)
503{
504 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
505 struct ata_channel *ch = device_get_softc(dev);
506 u_int32_t action = ATA_INL(ctlr->r_res1, 0x0044);
507 int offset = ch->unit * 0x2000;
508
509 if (action & (1 << ch->unit)) {
510 u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset);
511
512 /* do we have any PHY events ? */
513 ata_sata_phy_check_events(dev);
514
515 /* clear interrupt(s) */
516 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus);
517
518 /* do we have any device action ? */
519 return (istatus & 0x00000003);
520 }
521 return 0;
522}
523
524static int
525ata_siiprb_begin_transaction(struct ata_request *request)
526{
527 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent));
528 struct ata_channel *ch = device_get_softc(request->parent);
529 struct ata_siiprb_command *prb;
530 struct ata_siiprb_dma_prdentry *prd;
531 int offset = ch->unit * 0x2000;
532 u_int64_t prb_bus;
533
534 /* SOS XXX */
535 if (request->u.ata.command == ATA_DEVICE_RESET) {
536 request->result = 0;
537 return ATA_OP_FINISHED;
538 }
539
540 /* get a piece of the workspace for this request */
541 prb = (struct ata_siiprb_command *)ch->dma.work;
542
543 /* clear the prb structure */
544 bzero(prb, sizeof(struct ata_siiprb_command));
545
546 /* setup the FIS for this request */
547 if (!ata_request2fis_h2d(request, &prb->fis[0])) {
548 device_printf(request->parent, "setting up SATA FIS failed\n");
549 request->result = EIO;
550 return ATA_OP_FINISHED;
551 }
552
553 /* setup transfer type */
554 if (request->flags & ATA_R_ATAPI) {
555 bcopy(request->u.atapi.ccb, prb->u.atapi.ccb, 16);
556 if (request->flags & ATA_R_ATAPI16)
557 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000020);
558 else
559 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000020);
560 if (request->flags & ATA_R_READ)
561 prb->control = htole16(0x0010);
562 if (request->flags & ATA_R_WRITE)
563 prb->control = htole16(0x0020);
564 prd = &prb->u.atapi.prd[0];
565 }
566 else
567 prd = &prb->u.ata.prd[0];
568
569 /* if request moves data setup and load SG list */
570 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
571 if (ch->dma.load(request, prd, NULL)) {
572 device_printf(request->parent, "setting up DMA failed\n");
573 request->result = EIO;
574 return ATA_OP_FINISHED;
575 }
576 }
577
578 /* activate the prb */
579 prb_bus = ch->dma.work_bus;
580 ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus);
581 ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus>>32);
582
583 /* start the timeout */
584 callout_reset(&request->callout, request->timeout * hz,
585 (timeout_t*)ata_timeout, request);
586 return ATA_OP_CONTINUES;
587}
588
589static int
590ata_siiprb_end_transaction(struct ata_request *request)
591{
592 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent));
593 struct ata_channel *ch = device_get_softc(request->parent);
594 struct ata_siiprb_command *prb;
595 int offset = ch->unit * 0x2000;
596 int error, timeout;
597
598 /* kill the timeout */
599 callout_stop(&request->callout);
600
601 prb = (struct ata_siiprb_command *)
602 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
603
604 /* any controller errors flagged ? */
605 if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) {
606 if (bootverbose)
607 printf("ata_siiprb_end_transaction %s error=%08x\n",
608 ata_cmd2str(request), error);
609
610 /* if device error status get details */
611 if (error == 1 || error == 2) {
612 request->status = prb->fis[2];
613 if (request->status & ATA_S_ERROR)
614 request->error = prb->fis[3];
615 }
616
617 /* SOS XXX handle other controller errors here */
618
619 /* initialize port */
620 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000004);
621
622 /* poll for port ready */
623 for (timeout = 0; timeout < 1000; timeout++) {
624 DELAY(1000);
625 if (ATA_INL(ctlr->r_res2, 0x1008 + offset) & 0x00040000)
626 break;
627 }
628 if (bootverbose) {
629 if (timeout >= 1000)
630 device_printf(ch->dev, "port initialize timeout\n");
631 else
632 device_printf(ch->dev, "port initialize time=%dms\n", timeout);
633 }
634 }
635
636 /* on control commands read back registers to the request struct */
637 if (request->flags & ATA_R_CONTROL) {
638 request->u.ata.count = prb->fis[12] | ((u_int16_t)prb->fis[13] << 8);
639 request->u.ata.lba = prb->fis[4] | ((u_int64_t)prb->fis[5] << 8) |
640 ((u_int64_t)prb->fis[6] << 16);
641 if (request->flags & ATA_R_48BIT)
642 request->u.ata.lba |= ((u_int64_t)prb->fis[8] << 24) |
643 ((u_int64_t)prb->fis[9] << 32) |
644 ((u_int64_t)prb->fis[10] << 40);
645 else
646 request->u.ata.lba |= ((u_int64_t)(prb->fis[7] & 0x0f) << 24);
647 }
648
649 /* update progress */
650 if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) {
651 if (request->flags & ATA_R_READ)
| 29
30#include "opt_ata.h"
31#include <sys/param.h>
32#include <sys/module.h>
33#include <sys/systm.h>
34#include <sys/kernel.h>
35#include <sys/ata.h>
36#include <sys/bus.h>
37#include <sys/endian.h>
38#include <sys/malloc.h>
39#include <sys/lock.h>
40#include <sys/mutex.h>
41#include <sys/sema.h>
42#include <sys/taskqueue.h>
43#include <vm/uma.h>
44#include <machine/stdarg.h>
45#include <machine/resource.h>
46#include <machine/bus.h>
47#include <sys/rman.h>
48#include <dev/pci/pcivar.h>
49#include <dev/pci/pcireg.h>
50#include <dev/ata/ata-all.h>
51#include <dev/ata/ata-pci.h>
52#include <ata_if.h>
53
54/* local prototypes */
55static int ata_cmd_ch_attach(device_t dev);
56static int ata_cmd_status(device_t dev);
57static int ata_cmd_setmode(device_t dev, int target, int mode);
58static int ata_sii_ch_attach(device_t dev);
59static int ata_sii_ch_detach(device_t dev);
60static int ata_sii_status(device_t dev);
61static void ata_sii_reset(device_t dev);
62static int ata_sii_setmode(device_t dev, int target, int mode);
63static int ata_siiprb_ch_attach(device_t dev);
64static int ata_siiprb_ch_detach(device_t dev);
65static int ata_siiprb_status(device_t dev);
66static int ata_siiprb_begin_transaction(struct ata_request *request);
67static int ata_siiprb_end_transaction(struct ata_request *request);
68static int ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result);
69static int ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t result);
70static u_int32_t ata_siiprb_softreset(device_t dev, int port);
71static void ata_siiprb_reset(device_t dev);
72static void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
73static void ata_siiprb_dmainit(device_t dev);
74
75/* misc defines */
76#define SII_MEMIO 1
77#define SII_PRBIO 2
78#define SII_INTR 0x01
79#define SII_SETCLK 0x02
80#define SII_BUG 0x04
81#define SII_4CH 0x08
82
83
84/*
85 * Silicon Image Inc. (SiI) (former CMD) chipset support functions
86 */
87static int
88ata_sii_probe(device_t dev)
89{
90 struct ata_pci_controller *ctlr = device_get_softc(dev);
91 static struct ata_chip_id ids[] =
92 {{ ATA_SII3114, 0x00, SII_MEMIO, SII_4CH, ATA_SA150, "3114" },
93 { ATA_SII3512, 0x02, SII_MEMIO, 0, ATA_SA150, "3512" },
94 { ATA_SII3112, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" },
95 { ATA_SII3112_1, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" },
96 { ATA_SII3512, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3512" },
97 { ATA_SII3112, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" },
98 { ATA_SII3112_1, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" },
99 { ATA_SII3124, 0x00, SII_PRBIO, SII_4CH, ATA_SA300, "3124" },
100 { ATA_SII3132, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" },
101 { ATA_SII3132_1, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" },
102 { ATA_SII3132_2, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" },
103 { ATA_SII0680, 0x00, SII_MEMIO, SII_SETCLK, ATA_UDMA6, "680" },
104 { ATA_CMD649, 0x00, 0, SII_INTR, ATA_UDMA5, "(CMD) 649" },
105 { ATA_CMD648, 0x00, 0, SII_INTR, ATA_UDMA4, "(CMD) 648" },
106 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "(CMD) 646U2" },
107 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "(CMD) 646" },
108 { 0, 0, 0, 0, 0, 0}};
109
110 if (pci_get_vendor(dev) != ATA_SILICON_IMAGE_ID)
111 return ENXIO;
112
113 if (!(ctlr->chip = ata_match_chip(dev, ids)))
114 return ENXIO;
115
116 ata_set_desc(dev);
117 ctlr->chipinit = ata_sii_chipinit;
118 return (BUS_PROBE_DEFAULT);
119}
120
121int
122ata_sii_chipinit(device_t dev)
123{
124 struct ata_pci_controller *ctlr = device_get_softc(dev);
125
126 if (ata_setup_interrupt(dev, ata_generic_intr))
127 return ENXIO;
128
129 switch (ctlr->chip->cfg1) {
130 case SII_PRBIO:
131 ctlr->r_type1 = SYS_RES_MEMORY;
132 ctlr->r_rid1 = PCIR_BAR(0);
133 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
134 &ctlr->r_rid1, RF_ACTIVE)))
135 return ENXIO;
136
137 ctlr->r_rid2 = PCIR_BAR(2);
138 ctlr->r_type2 = SYS_RES_MEMORY;
139 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
140 &ctlr->r_rid2, RF_ACTIVE))){
141 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1);
142 return ENXIO;
143 }
144 ctlr->ch_attach = ata_siiprb_ch_attach;
145 ctlr->ch_detach = ata_siiprb_ch_detach;
146 ctlr->reset = ata_siiprb_reset;
147 ctlr->setmode = ata_sata_setmode;
148 ctlr->getrev = ata_sata_getrev;
149 ctlr->channels = (ctlr->chip->cfg2 == SII_4CH) ? 4 : 2;
150
151 /* reset controller */
152 ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000);
153 DELAY(10000);
154 ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f);
155 break;
156
157 case SII_MEMIO:
158 ctlr->r_type2 = SYS_RES_MEMORY;
159 ctlr->r_rid2 = PCIR_BAR(5);
160 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
161 &ctlr->r_rid2, RF_ACTIVE))){
162 if (ctlr->chip->chipid != ATA_SII0680 ||
163 (pci_read_config(dev, 0x8a, 1) & 1))
164 return ENXIO;
165 }
166
167 if (ctlr->chip->cfg2 & SII_SETCLK) {
168 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
169 pci_write_config(dev, 0x8a,
170 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1);
171 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
172 device_printf(dev, "%s could not set ATA133 clock\n",
173 ctlr->chip->text);
174 }
175
176 /* if we have 4 channels enable the second set */
177 if (ctlr->chip->cfg2 & SII_4CH) {
178 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002);
179 ctlr->channels = 4;
180 }
181
182 /* dont block interrupts from any channel */
183 pci_write_config(dev, 0x48,
184 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4);
185
186 /* enable PCI interrupt as BIOS might not */
187 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1);
188
189 if (ctlr->r_res2) {
190 ctlr->ch_attach = ata_sii_ch_attach;
191 ctlr->ch_detach = ata_sii_ch_detach;
192 }
193
194 if (ctlr->chip->max_dma >= ATA_SA150) {
195 ctlr->reset = ata_sii_reset;
196 ctlr->setmode = ata_sata_setmode;
197 ctlr->getrev = ata_sata_getrev;
198 }
199 else
200 ctlr->setmode = ata_sii_setmode;
201 break;
202
203 default:
204 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) {
205 device_printf(dev, "HW has secondary channel disabled\n");
206 ctlr->channels = 1;
207 }
208
209 /* enable interrupt as BIOS might not */
210 pci_write_config(dev, 0x71, 0x01, 1);
211
212 ctlr->ch_attach = ata_cmd_ch_attach;
213 ctlr->ch_detach = ata_pci_ch_detach;
214 ctlr->setmode = ata_cmd_setmode;
215 break;
216 }
217 return 0;
218}
219
220static int
221ata_cmd_ch_attach(device_t dev)
222{
223 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
224 struct ata_channel *ch = device_get_softc(dev);
225
226 /* setup the usual register normal pci style */
227 if (ata_pci_ch_attach(dev))
228 return ENXIO;
229
230 if (ctlr->chip->cfg2 & SII_INTR)
231 ch->hw.status = ata_cmd_status;
232
233 return 0;
234}
235
236static int
237ata_cmd_status(device_t dev)
238{
239 struct ata_channel *ch = device_get_softc(dev);
240 u_int8_t reg71;
241
242 if (((reg71 = pci_read_config(device_get_parent(dev), 0x71, 1)) &
243 (ch->unit ? 0x08 : 0x04))) {
244 pci_write_config(device_get_parent(dev), 0x71,
245 reg71 & ~(ch->unit ? 0x04 : 0x08), 1);
246 return ata_pci_status(dev);
247 }
248 return 0;
249}
250
251static int
252ata_cmd_setmode(device_t dev, int target, int mode)
253{
254 device_t parent = device_get_parent(dev);
255 struct ata_pci_controller *ctlr = device_get_softc(parent);
256 struct ata_channel *ch = device_get_softc(dev);
257 int devno = (ch->unit << 1) + target;
258 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7);
259 int ureg = ch->unit ? 0x7b : 0x73;
260 int piomode;
261 uint8_t piotimings[] = { 0xa9, 0x57, 0x44, 0x32, 0x3f, 0x87, 0x32, 0x3f };
262 uint8_t udmatimings[][2] = { { 0x31, 0xc2 }, { 0x21, 0x82 },
263 { 0x11, 0x42 }, { 0x25, 0x8a },
264 { 0x15, 0x4a }, { 0x05, 0x0a } };
265
266 mode = min(mode, ctlr->chip->max_dma);
267 if (mode >= ATA_UDMA0) {
268 u_int8_t umode = pci_read_config(parent, ureg, 1);
269
270 umode &= ~(target == 0 ? 0x35 : 0xca);
271 umode |= udmatimings[mode & ATA_MODE_MASK][target];
272 pci_write_config(parent, ureg, umode, 1);
273 piomode = ATA_PIO4;
274 } else {
275 pci_write_config(parent, ureg,
276 pci_read_config(parent, ureg, 1) &
277 ~(target == 0 ? 0x35 : 0xca), 1);
278 piomode = mode;
279 }
280 pci_write_config(parent, treg, piotimings[ata_mode2idx(piomode)], 1);
281 return (mode);
282}
283
284static int
285ata_sii_ch_attach(device_t dev)
286{
287 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
288 struct ata_channel *ch = device_get_softc(dev);
289 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
290 int i;
291
292 ata_pci_dmainit(dev);
293
294 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
295 ch->r_io[i].res = ctlr->r_res2;
296 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8);
297 }
298 ch->r_io[ATA_CONTROL].res = ctlr->r_res2;
299 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8);
300 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
301 ata_default_registers(dev);
302
303 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2;
304 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8);
305 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2;
306 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8);
307 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2;
308 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8);
309
310 if (ctlr->chip->max_dma >= ATA_SA150) {
311 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
312 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8);
313 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
314 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8);
315 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
316 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8);
317 ch->flags |= ATA_NO_SLAVE;
318 ch->flags |= ATA_SATA;
319 ch->flags |= ATA_KNOWN_PRESENCE;
320
321 /* enable PHY state change interrupt */
322 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16));
323 }
324
325 if (ctlr->chip->cfg2 & SII_BUG) {
326 /* work around errata in early chips */
327 ch->dma.boundary = 8192;
328 ch->dma.segsize = 15 * DEV_BSIZE;
329 }
330
331 ata_pci_hw(dev);
332 ch->hw.status = ata_sii_status;
333 if (ctlr->chip->cfg2 & SII_SETCLK)
334 ch->flags |= ATA_CHECKS_CABLE;
335 return 0;
336}
337
338static int
339ata_sii_ch_detach(device_t dev)
340{
341
342 ata_pci_dmafini(dev);
343 return (0);
344}
345
346static int
347ata_sii_status(device_t dev)
348{
349 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
350 struct ata_channel *ch = device_get_softc(dev);
351 int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8);
352 int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8);
353
354 /* do we have any PHY events ? */
355 if (ctlr->chip->max_dma >= ATA_SA150 &&
356 (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010))
357 ata_sata_phy_check_events(dev);
358
359 if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800)
360 return ata_pci_status(dev);
361 else
362 return 0;
363}
364
365static void
366ata_sii_reset(device_t dev)
367{
368 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
369 struct ata_channel *ch = device_get_softc(dev);
370 int offset = ((ch->unit & 1) << 7) + ((ch->unit & 2) << 8);
371 uint32_t val;
372
373 /* Apply R_ERR on DMA activate FIS errata workaround. */
374 val = ATA_INL(ctlr->r_res2, 0x14c + offset);
375 if ((val & 0x3) == 0x1)
376 ATA_OUTL(ctlr->r_res2, 0x14c + offset, val & ~0x3);
377
378 if (ata_sata_phy_reset(dev, -1, 1))
379 ata_generic_reset(dev);
380 else
381 ch->devices = 0;
382}
383
384static int
385ata_sii_setmode(device_t dev, int target, int mode)
386{
387 device_t parent = device_get_parent(dev);
388 struct ata_pci_controller *ctlr = device_get_softc(parent);
389 struct ata_channel *ch = device_get_softc(dev);
390 int rego = (ch->unit << 4) + (target << 1);
391 int mreg = ch->unit ? 0x84 : 0x80;
392 int mask = 0x03 << (target << 2);
393 int mval = pci_read_config(parent, mreg, 1) & ~mask;
394 int piomode;
395 u_int8_t preg = 0xa4 + rego;
396 u_int8_t dreg = 0xa8 + rego;
397 u_int8_t ureg = 0xac + rego;
398 u_int16_t piotimings[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
399 u_int16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 };
400 u_int8_t udmatimings[] = { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 };
401
402 mode = min(mode, ctlr->chip->max_dma);
403
404 if (ctlr->chip->cfg2 & SII_SETCLK) {
405 if (ata_dma_check_80pin && mode > ATA_UDMA2 &&
406 (pci_read_config(parent, 0x79, 1) &
407 (ch->unit ? 0x02 : 0x01))) {
408 ata_print_cable(dev, "controller");
409 mode = ATA_UDMA2;
410 }
411 }
412 if (mode >= ATA_UDMA0) {
413 pci_write_config(parent, mreg,
414 mval | (0x03 << (target << 2)), 1);
415 pci_write_config(parent, ureg,
416 (pci_read_config(parent, ureg, 1) & ~0x3f) |
417 udmatimings[mode & ATA_MODE_MASK], 1);
418 piomode = ATA_PIO4;
419 } else if (mode >= ATA_WDMA0) {
420 pci_write_config(parent, mreg,
421 mval | (0x02 << (target << 2)), 1);
422 pci_write_config(parent, dreg, dmatimings[mode & ATA_MODE_MASK], 2);
423 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 :
424 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4;
425 } else {
426 pci_write_config(parent, mreg,
427 mval | (0x01 << (target << 2)), 1);
428 piomode = mode;
429 }
430 pci_write_config(parent, preg, piotimings[ata_mode2idx(piomode)], 2);
431 return (mode);
432}
433
434
435struct ata_siiprb_dma_prdentry {
436 u_int64_t addr;
437 u_int32_t count;
438 u_int32_t control;
439} __packed;
440
441#define ATA_SIIPRB_DMA_ENTRIES 129
442struct ata_siiprb_ata_command {
443 struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES];
444} __packed;
445
446struct ata_siiprb_atapi_command {
447 u_int8_t ccb[16];
448 struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES];
449} __packed;
450
451struct ata_siiprb_command {
452 u_int16_t control;
453 u_int16_t protocol_override;
454 u_int32_t transfer_count;
455 u_int8_t fis[24];
456 union {
457 struct ata_siiprb_ata_command ata;
458 struct ata_siiprb_atapi_command atapi;
459 } u;
460} __packed;
461
462static int
463ata_siiprb_ch_attach(device_t dev)
464{
465 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
466 struct ata_channel *ch = device_get_softc(dev);
467 int offset = ch->unit * 0x2000;
468
469 ata_siiprb_dmainit(dev);
470
471 /* set the SATA resources */
472 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
473 ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset;
474 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
475 ch->r_io[ATA_SERROR].offset = 0x1f08 + offset;
476 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
477 ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset;
478 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
479 ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset;
480
481 ch->hw.status = ata_siiprb_status;
482 ch->hw.begin_transaction = ata_siiprb_begin_transaction;
483 ch->hw.end_transaction = ata_siiprb_end_transaction;
484 ch->hw.command = NULL; /* not used here */
485 ch->hw.softreset = ata_siiprb_softreset;
486 ch->hw.pm_read = ata_siiprb_pm_read;
487 ch->hw.pm_write = ata_siiprb_pm_write;
488 ch->flags |= ATA_NO_SLAVE;
489 ch->flags |= ATA_SATA;
490 return 0;
491}
492
493static int
494ata_siiprb_ch_detach(device_t dev)
495{
496
497 ata_dmafini(dev);
498 return 0;
499}
500
501static int
502ata_siiprb_status(device_t dev)
503{
504 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
505 struct ata_channel *ch = device_get_softc(dev);
506 u_int32_t action = ATA_INL(ctlr->r_res1, 0x0044);
507 int offset = ch->unit * 0x2000;
508
509 if (action & (1 << ch->unit)) {
510 u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset);
511
512 /* do we have any PHY events ? */
513 ata_sata_phy_check_events(dev);
514
515 /* clear interrupt(s) */
516 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus);
517
518 /* do we have any device action ? */
519 return (istatus & 0x00000003);
520 }
521 return 0;
522}
523
524static int
525ata_siiprb_begin_transaction(struct ata_request *request)
526{
527 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent));
528 struct ata_channel *ch = device_get_softc(request->parent);
529 struct ata_siiprb_command *prb;
530 struct ata_siiprb_dma_prdentry *prd;
531 int offset = ch->unit * 0x2000;
532 u_int64_t prb_bus;
533
534 /* SOS XXX */
535 if (request->u.ata.command == ATA_DEVICE_RESET) {
536 request->result = 0;
537 return ATA_OP_FINISHED;
538 }
539
540 /* get a piece of the workspace for this request */
541 prb = (struct ata_siiprb_command *)ch->dma.work;
542
543 /* clear the prb structure */
544 bzero(prb, sizeof(struct ata_siiprb_command));
545
546 /* setup the FIS for this request */
547 if (!ata_request2fis_h2d(request, &prb->fis[0])) {
548 device_printf(request->parent, "setting up SATA FIS failed\n");
549 request->result = EIO;
550 return ATA_OP_FINISHED;
551 }
552
553 /* setup transfer type */
554 if (request->flags & ATA_R_ATAPI) {
555 bcopy(request->u.atapi.ccb, prb->u.atapi.ccb, 16);
556 if (request->flags & ATA_R_ATAPI16)
557 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000020);
558 else
559 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000020);
560 if (request->flags & ATA_R_READ)
561 prb->control = htole16(0x0010);
562 if (request->flags & ATA_R_WRITE)
563 prb->control = htole16(0x0020);
564 prd = &prb->u.atapi.prd[0];
565 }
566 else
567 prd = &prb->u.ata.prd[0];
568
569 /* if request moves data setup and load SG list */
570 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
571 if (ch->dma.load(request, prd, NULL)) {
572 device_printf(request->parent, "setting up DMA failed\n");
573 request->result = EIO;
574 return ATA_OP_FINISHED;
575 }
576 }
577
578 /* activate the prb */
579 prb_bus = ch->dma.work_bus;
580 ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus);
581 ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus>>32);
582
583 /* start the timeout */
584 callout_reset(&request->callout, request->timeout * hz,
585 (timeout_t*)ata_timeout, request);
586 return ATA_OP_CONTINUES;
587}
588
589static int
590ata_siiprb_end_transaction(struct ata_request *request)
591{
592 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent));
593 struct ata_channel *ch = device_get_softc(request->parent);
594 struct ata_siiprb_command *prb;
595 int offset = ch->unit * 0x2000;
596 int error, timeout;
597
598 /* kill the timeout */
599 callout_stop(&request->callout);
600
601 prb = (struct ata_siiprb_command *)
602 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
603
604 /* any controller errors flagged ? */
605 if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) {
606 if (bootverbose)
607 printf("ata_siiprb_end_transaction %s error=%08x\n",
608 ata_cmd2str(request), error);
609
610 /* if device error status get details */
611 if (error == 1 || error == 2) {
612 request->status = prb->fis[2];
613 if (request->status & ATA_S_ERROR)
614 request->error = prb->fis[3];
615 }
616
617 /* SOS XXX handle other controller errors here */
618
619 /* initialize port */
620 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000004);
621
622 /* poll for port ready */
623 for (timeout = 0; timeout < 1000; timeout++) {
624 DELAY(1000);
625 if (ATA_INL(ctlr->r_res2, 0x1008 + offset) & 0x00040000)
626 break;
627 }
628 if (bootverbose) {
629 if (timeout >= 1000)
630 device_printf(ch->dev, "port initialize timeout\n");
631 else
632 device_printf(ch->dev, "port initialize time=%dms\n", timeout);
633 }
634 }
635
636 /* on control commands read back registers to the request struct */
637 if (request->flags & ATA_R_CONTROL) {
638 request->u.ata.count = prb->fis[12] | ((u_int16_t)prb->fis[13] << 8);
639 request->u.ata.lba = prb->fis[4] | ((u_int64_t)prb->fis[5] << 8) |
640 ((u_int64_t)prb->fis[6] << 16);
641 if (request->flags & ATA_R_48BIT)
642 request->u.ata.lba |= ((u_int64_t)prb->fis[8] << 24) |
643 ((u_int64_t)prb->fis[9] << 32) |
644 ((u_int64_t)prb->fis[10] << 40);
645 else
646 request->u.ata.lba |= ((u_int64_t)(prb->fis[7] & 0x0f) << 24);
647 }
648
649 /* update progress */
650 if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) {
651 if (request->flags & ATA_R_READ)
|
653 else
654 request->donecount = request->bytecount;
655 }
656
657 /* release SG list etc */
658 ch->dma.unload(request);
659
660 return ATA_OP_FINISHED;
661}
662
663static int
664ata_siiprb_issue_cmd(device_t dev)
665{
666 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
667 struct ata_channel *ch = device_get_softc(dev);
668 u_int64_t prb_bus = ch->dma.work_bus;
669 u_int32_t status;
670 int offset = ch->unit * 0x2000;
671 int timeout;
672
673 /* issue command to chip */
674 ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus);
675 ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus >> 32);
676
677 /* poll for command finished */
678 for (timeout = 0; timeout < 10000; timeout++) {
679 DELAY(1000);
680 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000)
681 break;
682 }
683 // SOS XXX ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x00010000);
684 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x08ff08ff);
685
686 if (timeout >= 1000)
687 return EIO;
688
689 if (bootverbose)
690 device_printf(dev, "siiprb_issue_cmd time=%dms status=%08x\n",
691 timeout, status);
692 return 0;
693}
694
695static int
696ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result)
697{
698 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
699 struct ata_channel *ch = device_get_softc(dev);
700 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work;
701 int offset = ch->unit * 0x2000;
702
703 bzero(prb, sizeof(struct ata_siiprb_command));
704 prb->fis[0] = 0x27; /* host to device */
705 prb->fis[1] = 0x8f; /* command FIS to PM port */
706 prb->fis[2] = ATA_READ_PM;
707 prb->fis[3] = reg;
708 prb->fis[7] = port;
709 if (ata_siiprb_issue_cmd(dev)) {
710 device_printf(dev, "error reading PM port\n");
711 return EIO;
712 }
713 prb = (struct ata_siiprb_command *)
714 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
715 *result = prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24);
716 return 0;
717}
718
719static int
720ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t value)
721{
722 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
723 struct ata_channel *ch = device_get_softc(dev);
724 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work;
725 int offset = ch->unit * 0x2000;
726
727 bzero(prb, sizeof(struct ata_siiprb_command));
728 prb->fis[0] = 0x27; /* host to device */
729 prb->fis[1] = 0x8f; /* command FIS to PM port */
730 prb->fis[2] = ATA_WRITE_PM;
731 prb->fis[3] = reg;
732 prb->fis[7] = port;
733 prb->fis[12] = value & 0xff;
734 prb->fis[4] = (value >> 8) & 0xff;
735 prb->fis[5] = (value >> 16) & 0xff;
736 prb->fis[6] = (value >> 24) & 0xff;
737 if (ata_siiprb_issue_cmd(dev)) {
738 device_printf(dev, "error writing PM port\n");
739 return ATA_E_ABORT;
740 }
741 prb = (struct ata_siiprb_command *)
742 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
743 return prb->fis[3];
744}
745
746static u_int32_t
747ata_siiprb_softreset(device_t dev, int port)
748{
749 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
750 struct ata_channel *ch = device_get_softc(dev);
751 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work;
752 u_int32_t signature;
753 int offset = ch->unit * 0x2000;
754
755 /* setup the workspace for a soft reset command */
756 bzero(prb, sizeof(struct ata_siiprb_command));
757 prb->control = htole16(0x0080);
758 prb->fis[1] = port & 0x0f;
759
760 /* issue soft reset */
761 if (ata_siiprb_issue_cmd(dev))
762 return -1;
763
764 ata_udelay(150000);
765
766 /* get possible signature */
767 prb = (struct ata_siiprb_command *)
768 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
769 signature=prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24);
770
771 /* clear error bits/interrupt */
772 ATA_IDX_OUTL(ch, ATA_SERROR, 0xffffffff);
773
774 return signature;
775}
776
777static void
778ata_siiprb_reset(device_t dev)
779{
780 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
781 struct ata_channel *ch = device_get_softc(dev);
782 int offset = ch->unit * 0x2000;
783 u_int32_t status, signature;
784 int timeout;
785
786 /* disable interrupts */
787 ATA_OUTL(ctlr->r_res2, 0x1014 + offset, 0x000000ff);
788
789 /* reset channel HW */
790 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001);
791 DELAY(1000);
792 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001);
793 DELAY(10000);
794
795 /* poll for channel ready */
796 for (timeout = 0; timeout < 1000; timeout++) {
797 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00040000)
798 break;
799 DELAY(1000);
800 }
801
802 if (bootverbose) {
803 if (timeout >= 1000)
804 device_printf(dev, "channel HW reset timeout\n");
805 else
806 device_printf(dev, "channel HW reset time=%dms\n", timeout);
807 }
808
809 /* reset phy */
810 if (!ata_sata_phy_reset(dev, -1, 1)) {
811 if (bootverbose)
812 device_printf(dev, "phy reset found no device\n");
813 ch->devices = 0;
814 goto finish;
815 }
816
817 /* issue soft reset */
818 signature = ata_siiprb_softreset(dev, ATA_PM);
819 if (bootverbose)
820 device_printf(dev, "SIGNATURE=%08x\n", signature);
821
822 /* figure out whats there */
823 switch (signature >> 16) {
824 case 0x0000:
825 ch->devices = ATA_ATA_MASTER;
826 break;
827 case 0x9669:
828 ch->devices = ATA_PORTMULTIPLIER;
829 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x2000); /* enable PM support */
830 //SOS XXX need to clear all PM status and interrupts!!!!
831 ata_pm_identify(dev);
832 break;
833 case 0xeb14:
834 ch->devices = ATA_ATAPI_MASTER;
835 break;
836 default:
837 ch->devices = 0;
838 }
839 if (bootverbose)
840 device_printf(dev, "siiprb_reset devices=%08x\n", ch->devices);
841
842finish:
843 /* clear interrupt(s) */
844 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff);
845
846 /* require explicit interrupt ack */
847 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008);
848
849 /* 64bit mode */
850 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400);
851
852 /* enable interrupts wanted */
853 ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff);
854}
855
856static void
857ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
858{
859 struct ata_dmasetprd_args *args = xsc;
860 struct ata_siiprb_dma_prdentry *prd = args->dmatab;
861 int i;
862
863 if ((args->error = error))
864 return;
865
866 for (i = 0; i < nsegs; i++) {
867 prd[i].addr = htole64(segs[i].ds_addr);
868 prd[i].count = htole32(segs[i].ds_len);
869 }
870 prd[i - 1].control = htole32(ATA_DMA_EOT);
871 KASSERT(nsegs <= ATA_SIIPRB_DMA_ENTRIES,("too many DMA segment entries\n"));
872 args->nsegs = nsegs;
873}
874
875static void
876ata_siiprb_dmainit(device_t dev)
877{
878 struct ata_channel *ch = device_get_softc(dev);
879
880 ata_dmainit(dev);
881 /* note start and stop are not used here */
882 ch->dma.setprd = ata_siiprb_dmasetprd;
883 ch->dma.max_address = BUS_SPACE_MAXADDR;
884 ch->dma.max_iosize = (ATA_SIIPRB_DMA_ENTRIES - 1) * PAGE_SIZE;
885}
886
887ATA_DECLARE_DRIVER(ata_sii);
| 653 else
654 request->donecount = request->bytecount;
655 }
656
657 /* release SG list etc */
658 ch->dma.unload(request);
659
660 return ATA_OP_FINISHED;
661}
662
663static int
664ata_siiprb_issue_cmd(device_t dev)
665{
666 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
667 struct ata_channel *ch = device_get_softc(dev);
668 u_int64_t prb_bus = ch->dma.work_bus;
669 u_int32_t status;
670 int offset = ch->unit * 0x2000;
671 int timeout;
672
673 /* issue command to chip */
674 ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus);
675 ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus >> 32);
676
677 /* poll for command finished */
678 for (timeout = 0; timeout < 10000; timeout++) {
679 DELAY(1000);
680 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000)
681 break;
682 }
683 // SOS XXX ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x00010000);
684 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x08ff08ff);
685
686 if (timeout >= 1000)
687 return EIO;
688
689 if (bootverbose)
690 device_printf(dev, "siiprb_issue_cmd time=%dms status=%08x\n",
691 timeout, status);
692 return 0;
693}
694
695static int
696ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result)
697{
698 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
699 struct ata_channel *ch = device_get_softc(dev);
700 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work;
701 int offset = ch->unit * 0x2000;
702
703 bzero(prb, sizeof(struct ata_siiprb_command));
704 prb->fis[0] = 0x27; /* host to device */
705 prb->fis[1] = 0x8f; /* command FIS to PM port */
706 prb->fis[2] = ATA_READ_PM;
707 prb->fis[3] = reg;
708 prb->fis[7] = port;
709 if (ata_siiprb_issue_cmd(dev)) {
710 device_printf(dev, "error reading PM port\n");
711 return EIO;
712 }
713 prb = (struct ata_siiprb_command *)
714 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
715 *result = prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24);
716 return 0;
717}
718
719static int
720ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t value)
721{
722 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
723 struct ata_channel *ch = device_get_softc(dev);
724 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work;
725 int offset = ch->unit * 0x2000;
726
727 bzero(prb, sizeof(struct ata_siiprb_command));
728 prb->fis[0] = 0x27; /* host to device */
729 prb->fis[1] = 0x8f; /* command FIS to PM port */
730 prb->fis[2] = ATA_WRITE_PM;
731 prb->fis[3] = reg;
732 prb->fis[7] = port;
733 prb->fis[12] = value & 0xff;
734 prb->fis[4] = (value >> 8) & 0xff;
735 prb->fis[5] = (value >> 16) & 0xff;
736 prb->fis[6] = (value >> 24) & 0xff;
737 if (ata_siiprb_issue_cmd(dev)) {
738 device_printf(dev, "error writing PM port\n");
739 return ATA_E_ABORT;
740 }
741 prb = (struct ata_siiprb_command *)
742 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
743 return prb->fis[3];
744}
745
746static u_int32_t
747ata_siiprb_softreset(device_t dev, int port)
748{
749 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
750 struct ata_channel *ch = device_get_softc(dev);
751 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work;
752 u_int32_t signature;
753 int offset = ch->unit * 0x2000;
754
755 /* setup the workspace for a soft reset command */
756 bzero(prb, sizeof(struct ata_siiprb_command));
757 prb->control = htole16(0x0080);
758 prb->fis[1] = port & 0x0f;
759
760 /* issue soft reset */
761 if (ata_siiprb_issue_cmd(dev))
762 return -1;
763
764 ata_udelay(150000);
765
766 /* get possible signature */
767 prb = (struct ata_siiprb_command *)
768 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
769 signature=prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24);
770
771 /* clear error bits/interrupt */
772 ATA_IDX_OUTL(ch, ATA_SERROR, 0xffffffff);
773
774 return signature;
775}
776
777static void
778ata_siiprb_reset(device_t dev)
779{
780 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
781 struct ata_channel *ch = device_get_softc(dev);
782 int offset = ch->unit * 0x2000;
783 u_int32_t status, signature;
784 int timeout;
785
786 /* disable interrupts */
787 ATA_OUTL(ctlr->r_res2, 0x1014 + offset, 0x000000ff);
788
789 /* reset channel HW */
790 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001);
791 DELAY(1000);
792 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001);
793 DELAY(10000);
794
795 /* poll for channel ready */
796 for (timeout = 0; timeout < 1000; timeout++) {
797 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00040000)
798 break;
799 DELAY(1000);
800 }
801
802 if (bootverbose) {
803 if (timeout >= 1000)
804 device_printf(dev, "channel HW reset timeout\n");
805 else
806 device_printf(dev, "channel HW reset time=%dms\n", timeout);
807 }
808
809 /* reset phy */
810 if (!ata_sata_phy_reset(dev, -1, 1)) {
811 if (bootverbose)
812 device_printf(dev, "phy reset found no device\n");
813 ch->devices = 0;
814 goto finish;
815 }
816
817 /* issue soft reset */
818 signature = ata_siiprb_softreset(dev, ATA_PM);
819 if (bootverbose)
820 device_printf(dev, "SIGNATURE=%08x\n", signature);
821
822 /* figure out whats there */
823 switch (signature >> 16) {
824 case 0x0000:
825 ch->devices = ATA_ATA_MASTER;
826 break;
827 case 0x9669:
828 ch->devices = ATA_PORTMULTIPLIER;
829 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x2000); /* enable PM support */
830 //SOS XXX need to clear all PM status and interrupts!!!!
831 ata_pm_identify(dev);
832 break;
833 case 0xeb14:
834 ch->devices = ATA_ATAPI_MASTER;
835 break;
836 default:
837 ch->devices = 0;
838 }
839 if (bootverbose)
840 device_printf(dev, "siiprb_reset devices=%08x\n", ch->devices);
841
842finish:
843 /* clear interrupt(s) */
844 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff);
845
846 /* require explicit interrupt ack */
847 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008);
848
849 /* 64bit mode */
850 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400);
851
852 /* enable interrupts wanted */
853 ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff);
854}
855
856static void
857ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
858{
859 struct ata_dmasetprd_args *args = xsc;
860 struct ata_siiprb_dma_prdentry *prd = args->dmatab;
861 int i;
862
863 if ((args->error = error))
864 return;
865
866 for (i = 0; i < nsegs; i++) {
867 prd[i].addr = htole64(segs[i].ds_addr);
868 prd[i].count = htole32(segs[i].ds_len);
869 }
870 prd[i - 1].control = htole32(ATA_DMA_EOT);
871 KASSERT(nsegs <= ATA_SIIPRB_DMA_ENTRIES,("too many DMA segment entries\n"));
872 args->nsegs = nsegs;
873}
874
875static void
876ata_siiprb_dmainit(device_t dev)
877{
878 struct ata_channel *ch = device_get_softc(dev);
879
880 ata_dmainit(dev);
881 /* note start and stop are not used here */
882 ch->dma.setprd = ata_siiprb_dmasetprd;
883 ch->dma.max_address = BUS_SPACE_MAXADDR;
884 ch->dma.max_iosize = (ATA_SIIPRB_DMA_ENTRIES - 1) * PAGE_SIZE;
885}
886
887ATA_DECLARE_DRIVER(ata_sii);
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