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if_alc.c (211052) if_alc.c (211053)
1/*-
2 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28/* Driver for Atheros AR8131/AR8132 PCIe Ethernet. */
29
30#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 14 unchanged lines hidden (view full) ---

23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28/* Driver for Atheros AR8131/AR8132 PCIe Ethernet. */
29
30#include <sys/cdefs.h>
31__FBSDID("$FreeBSD: head/sys/dev/alc/if_alc.c 211052 2010-08-08 00:23:36Z yongari $");
31__FBSDID("$FreeBSD: head/sys/dev/alc/if_alc.c 211053 2010-08-08 00:43:41Z yongari $");
32
33#include <sys/param.h>
34#include <sys/systm.h>
35#include <sys/bus.h>
36#include <sys/endian.h>
37#include <sys/kernel.h>
38#include <sys/lock.h>
39#include <sys/malloc.h>

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564
565static int
566alc_attach(device_t dev)
567{
568 struct alc_softc *sc;
569 struct ifnet *ifp;
570 char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/l1" };
571 uint16_t burst;
32
33#include <sys/param.h>
34#include <sys/systm.h>
35#include <sys/bus.h>
36#include <sys/endian.h>
37#include <sys/kernel.h>
38#include <sys/lock.h>
39#include <sys/malloc.h>

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564
565static int
566alc_attach(device_t dev)
567{
568 struct alc_softc *sc;
569 struct ifnet *ifp;
570 char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/l1" };
571 uint16_t burst;
572 int base, error, i, msic, msixc, pmc, state;
572 int base, error, i, msic, msixc, state;
573 uint32_t cap, ctl, val;
574
575 error = 0;
576 sc = device_get_softc(dev);
577 sc->alc_dev = dev;
578
579 mtx_init(&sc->alc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
580 MTX_DEF);

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595 sc->alc_phyaddr = ALC_PHY_ADDR;
596
597 /* Initialize DMA parameters. */
598 sc->alc_dma_rd_burst = 0;
599 sc->alc_dma_wr_burst = 0;
600 sc->alc_rcb = DMA_CFG_RCB_64;
601 if (pci_find_extcap(dev, PCIY_EXPRESS, &base) == 0) {
602 sc->alc_flags |= ALC_FLAG_PCIE;
573 uint32_t cap, ctl, val;
574
575 error = 0;
576 sc = device_get_softc(dev);
577 sc->alc_dev = dev;
578
579 mtx_init(&sc->alc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
580 MTX_DEF);

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595 sc->alc_phyaddr = ALC_PHY_ADDR;
596
597 /* Initialize DMA parameters. */
598 sc->alc_dma_rd_burst = 0;
599 sc->alc_dma_wr_burst = 0;
600 sc->alc_rcb = DMA_CFG_RCB_64;
601 if (pci_find_extcap(dev, PCIY_EXPRESS, &base) == 0) {
602 sc->alc_flags |= ALC_FLAG_PCIE;
603 sc->alc_expcap = base;
603 burst = CSR_READ_2(sc, base + PCIR_EXPRESS_DEVICE_CTL);
604 sc->alc_dma_rd_burst =
605 (burst & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12;
606 sc->alc_dma_wr_burst = (burst & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5;
607 if (bootverbose) {
608 device_printf(dev, "Read request size : %u bytes.\n",
609 alc_dma_burst[sc->alc_dma_rd_burst]);
610 device_printf(dev, "TLP payload size : %u bytes.\n",

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738 ifp->if_ioctl = alc_ioctl;
739 ifp->if_start = alc_start;
740 ifp->if_init = alc_init;
741 ifp->if_snd.ifq_drv_maxlen = ALC_TX_RING_CNT - 1;
742 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
743 IFQ_SET_READY(&ifp->if_snd);
744 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4;
745 ifp->if_hwassist = ALC_CSUM_FEATURES | CSUM_TSO;
604 burst = CSR_READ_2(sc, base + PCIR_EXPRESS_DEVICE_CTL);
605 sc->alc_dma_rd_burst =
606 (burst & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12;
607 sc->alc_dma_wr_burst = (burst & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5;
608 if (bootverbose) {
609 device_printf(dev, "Read request size : %u bytes.\n",
610 alc_dma_burst[sc->alc_dma_rd_burst]);
611 device_printf(dev, "TLP payload size : %u bytes.\n",

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739 ifp->if_ioctl = alc_ioctl;
740 ifp->if_start = alc_start;
741 ifp->if_init = alc_init;
742 ifp->if_snd.ifq_drv_maxlen = ALC_TX_RING_CNT - 1;
743 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
744 IFQ_SET_READY(&ifp->if_snd);
745 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4;
746 ifp->if_hwassist = ALC_CSUM_FEATURES | CSUM_TSO;
746 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0)
747 if (pci_find_extcap(dev, PCIY_PMG, &base) == 0) {
747 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST;
748 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST;
749 sc->alc_flags |= ALC_FLAG_PM;
750 sc->alc_pmcap = base;
751 }
748 ifp->if_capenable = ifp->if_capabilities;
749
750 /* Set up MII bus. */
751 if ((error = mii_phy_probe(dev, &sc->alc_miibus, alc_mediachange,
752 alc_mediastatus)) != 0) {
753 device_printf(dev, "no PHY found!\n");
754 goto fail;
755 }

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1670}
1671
1672static void
1673alc_setwol(struct alc_softc *sc)
1674{
1675 struct ifnet *ifp;
1676 uint32_t reg, pmcs;
1677 uint16_t pmstat;
752 ifp->if_capenable = ifp->if_capabilities;
753
754 /* Set up MII bus. */
755 if ((error = mii_phy_probe(dev, &sc->alc_miibus, alc_mediachange,
756 alc_mediastatus)) != 0) {
757 device_printf(dev, "no PHY found!\n");
758 goto fail;
759 }

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1674}
1675
1676static void
1677alc_setwol(struct alc_softc *sc)
1678{
1679 struct ifnet *ifp;
1680 uint32_t reg, pmcs;
1681 uint16_t pmstat;
1678 int pmc;
1679
1680 ALC_LOCK_ASSERT(sc);
1681
1682 alc_disable_l0s_l1(sc);
1683 ifp = sc->alc_ifp;
1682
1683 ALC_LOCK_ASSERT(sc);
1684
1685 alc_disable_l0s_l1(sc);
1686 ifp = sc->alc_ifp;
1684 if (pci_find_extcap(sc->alc_dev, PCIY_PMG, &pmc) != 0) {
1687 if ((sc->alc_flags & ALC_FLAG_PM) == 0) {
1685 /* Disable WOL. */
1686 CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
1687 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC);
1688 reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1689 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg);
1690 /* Force PHY power down. */
1691 alc_phy_down(sc);
1692 CSR_WRITE_4(sc, ALC_MASTER_CFG,

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1719 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg);
1720 if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1721 /* WOL disabled, PHY power down. */
1722 alc_phy_down(sc);
1723 CSR_WRITE_4(sc, ALC_MASTER_CFG,
1724 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS);
1725 }
1726 /* Request PME. */
1688 /* Disable WOL. */
1689 CSR_WRITE_4(sc, ALC_WOL_CFG, 0);
1690 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC);
1691 reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1692 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg);
1693 /* Force PHY power down. */
1694 alc_phy_down(sc);
1695 CSR_WRITE_4(sc, ALC_MASTER_CFG,

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1722 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg);
1723 if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1724 /* WOL disabled, PHY power down. */
1725 alc_phy_down(sc);
1726 CSR_WRITE_4(sc, ALC_MASTER_CFG,
1727 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS);
1728 }
1729 /* Request PME. */
1727 pmstat = pci_read_config(sc->alc_dev, pmc + PCIR_POWER_STATUS, 2);
1730 pmstat = pci_read_config(sc->alc_dev,
1731 sc->alc_pmcap + PCIR_POWER_STATUS, 2);
1728 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1729 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1730 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1732 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1733 if ((ifp->if_capenable & IFCAP_WOL) != 0)
1734 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1731 pci_write_config(sc->alc_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1735 pci_write_config(sc->alc_dev,
1736 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2);
1732}
1733
1734static int
1735alc_suspend(device_t dev)
1736{
1737 struct alc_softc *sc;
1738
1739 sc = device_get_softc(dev);

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1746 return (0);
1747}
1748
1749static int
1750alc_resume(device_t dev)
1751{
1752 struct alc_softc *sc;
1753 struct ifnet *ifp;
1737}
1738
1739static int
1740alc_suspend(device_t dev)
1741{
1742 struct alc_softc *sc;
1743
1744 sc = device_get_softc(dev);

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1751 return (0);
1752}
1753
1754static int
1755alc_resume(device_t dev)
1756{
1757 struct alc_softc *sc;
1758 struct ifnet *ifp;
1754 int pmc;
1755 uint16_t pmstat;
1756
1757 sc = device_get_softc(dev);
1758
1759 ALC_LOCK(sc);
1759 uint16_t pmstat;
1760
1761 sc = device_get_softc(dev);
1762
1763 ALC_LOCK(sc);
1760 if (pci_find_extcap(sc->alc_dev, PCIY_PMG, &pmc) == 0) {
1764 if ((sc->alc_flags & ALC_FLAG_PM) != 0) {
1761 /* Disable PME and clear PME status. */
1762 pmstat = pci_read_config(sc->alc_dev,
1765 /* Disable PME and clear PME status. */
1766 pmstat = pci_read_config(sc->alc_dev,
1763 pmc + PCIR_POWER_STATUS, 2);
1767 sc->alc_pmcap + PCIR_POWER_STATUS, 2);
1764 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
1765 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1766 pci_write_config(sc->alc_dev,
1768 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
1769 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1770 pci_write_config(sc->alc_dev,
1767 pmc + PCIR_POWER_STATUS, pmstat, 2);
1771 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2);
1768 }
1769 }
1770 /* Reset PHY. */
1771 alc_phy_reset(sc);
1772 ifp = sc->alc_ifp;
1773 if ((ifp->if_flags & IFF_UP) != 0) {
1774 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1775 alc_init_locked(sc);

--- 1718 unchanged lines hidden --- 		1772 }
1773 }
1774 /* Reset PHY. */
1775 alc_phy_reset(sc);
1776 ifp = sc->alc_ifp;
1777 if ((ifp->if_flags & IFF_UP) != 0) {
1778 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1779 alc_init_locked(sc);

--- 1718 unchanged lines hidden ---