| aic7xxx_inline.h (70807) | aic7xxx_inline.h (71390) |
|---|---|
| 1/* 2 * Inline routines shareable across OS platforms. 3 * 4 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions --- 14 unchanged lines hidden (view full) --- 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * | 1/* 2 * Inline routines shareable across OS platforms. 3 * 4 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000 Justin T. Gibbs. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions --- 14 unchanged lines hidden (view full) --- 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * |
| 31 * $Id: //depot/src/aic7xxx/aic7xxx_inline.h#12 $ | 31 * $Id: //depot/src/aic7xxx/aic7xxx_inline.h#14 $ |
| 32 * | 32 * |
| 33 * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx_inline.h 70807 2001-01-09 00:40:38Z gibbs $ | 33 * $FreeBSD: head/sys/dev/aic7xxx/aic7xxx_inline.h 71390 2001-01-22 21:03:48Z gibbs $ |
| 34 */ 35 36#ifndef _AIC7XXX_INLINE_H_ 37#define _AIC7XXX_INLINE_H_ 38 39/************************* Sequencer Execution Control ************************/ 40static __inline int sequencer_paused(struct ahc_softc *ahc); 41static __inline void ahc_pause_bug_fix(struct ahc_softc *ahc); --- 70 unchanged lines hidden (view full) --- 112 113/* 114 * Block our completion routine from starting the next untagged 115 * transaction for this target or target lun. 116 */ 117static __inline void 118ahc_freeze_untagged_queues(struct ahc_softc *ahc) 119{ | 34 */ 35 36#ifndef _AIC7XXX_INLINE_H_ 37#define _AIC7XXX_INLINE_H_ 38 39/************************* Sequencer Execution Control ************************/ 40static __inline int sequencer_paused(struct ahc_softc *ahc); 41static __inline void ahc_pause_bug_fix(struct ahc_softc *ahc); --- 70 unchanged lines hidden (view full) --- 112 113/* 114 * Block our completion routine from starting the next untagged 115 * transaction for this target or target lun. 116 */ 117static __inline void 118ahc_freeze_untagged_queues(struct ahc_softc *ahc) 119{ |
| 120 if ((ahc->features & AHC_SCB_BTT) == 0) | 120 if ((ahc->flags & AHC_SCB_BTT) == 0) |
| 121 ahc->untagged_queue_lock++; 122} 123 124/* 125 * Allow the next untagged transaction for this target or target lun 126 * to be executed. We use a counting semaphore to allow the lock 127 * to be acquired recursively. Once the count drops to zero, the 128 * transaction queues will be run. 129 */ 130static __inline void 131ahc_release_untagged_queues(struct ahc_softc *ahc) 132{ | 121 ahc->untagged_queue_lock++; 122} 123 124/* 125 * Allow the next untagged transaction for this target or target lun 126 * to be executed. We use a counting semaphore to allow the lock 127 * to be acquired recursively. Once the count drops to zero, the 128 * transaction queues will be run. 129 */ 130static __inline void 131ahc_release_untagged_queues(struct ahc_softc *ahc) 132{ |
| 133 if ((ahc->features & AHC_SCB_BTT) == 0) { | 133 if ((ahc->flags & AHC_SCB_BTT) == 0) { |
| 134 ahc->untagged_queue_lock--; 135 if (ahc->untagged_queue_lock == 0) 136 ahc_run_untagged_queues(ahc); 137 } 138} 139 140/************************** Memory mapping routines ***************************/ 141static __inline struct ahc_dma_seg * --- 281 unchanged lines hidden (view full) --- 423#if AHC_PCI_CONFIG > 0 424 if (ahc->unsolicited_ints > 500 425 && (ahc->chip & AHC_PCI) != 0 426 && (ahc_inb(ahc, ERROR) & PCIERRSTAT) != 0) 427 ahc_pci_intr(ahc); 428#endif 429 } 430 | 134 ahc->untagged_queue_lock--; 135 if (ahc->untagged_queue_lock == 0) 136 ahc_run_untagged_queues(ahc); 137 } 138} 139 140/************************** Memory mapping routines ***************************/ 141static __inline struct ahc_dma_seg * --- 281 unchanged lines hidden (view full) --- 423#if AHC_PCI_CONFIG > 0 424 if (ahc->unsolicited_ints > 500 425 && (ahc->chip & AHC_PCI) != 0 426 && (ahc_inb(ahc, ERROR) & PCIERRSTAT) != 0) 427 ahc_pci_intr(ahc); 428#endif 429 } 430 |
| 431 if (intstat == 0xFF) | 431 if (intstat == 0xFF && (ahc->features & AHC_REMOVABLE) != 0) |
| 432 /* Hot eject */ 433 return; 434 435 if ((intstat & INT_PEND) == 0) { 436 ahc->unsolicited_ints++; 437 return; 438 } 439 ahc->unsolicited_ints = 0; --- 39 unchanged lines hidden --- | 432 /* Hot eject */ 433 return; 434 435 if ((intstat & INT_PEND) == 0) { 436 ahc->unsolicited_ints++; 437 return; 438 } 439 ahc->unsolicited_ints = 0; --- 39 unchanged lines hidden --- |