1/*-
2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org>
3 * Copyright (c) 2009 Alexander Motin <mav@FreeBSD.org>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer,
11 * without modification, immediately at the beginning of the file.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
| 1/*-
2 * Copyright (c) 1998 - 2008 S�ren Schmidt <sos@FreeBSD.org>
3 * Copyright (c) 2009 Alexander Motin <mav@FreeBSD.org>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer,
11 * without modification, immediately at the beginning of the file.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
|
375};
376
377/* structure describing a AHCI controller */
378struct ahci_controller {
379 device_t dev;
380 int r_rid;
381 struct resource *r_mem;
382 struct rman sc_iomem;
383 struct ahci_controller_irq {
384 struct ahci_controller *ctlr;
385 struct resource *r_irq;
386 void *handle;
387 int r_irq_rid;
388 int mode;
389#define AHCI_IRQ_MODE_ALL 0
390#define AHCI_IRQ_MODE_AFTER 1
391#define AHCI_IRQ_MODE_ONE 2
392 } irqs[16];
393 uint32_t caps; /* Controller capabilities */
394 uint32_t caps2; /* Controller capabilities */
395 int quirks;
396 int numirqs;
397 int channels;
398 int ichannels;
399 int ccc; /* CCC timeout */
400 int cccv; /* CCC vector */
401 struct {
402 void (*function)(void *);
403 void *argument;
404 } interrupt[AHCI_MAX_PORTS];
405};
406
407enum ahci_err_type {
408 AHCI_ERR_NONE, /* No error */
409 AHCI_ERR_INVALID, /* Error detected by us before submitting. */
410 AHCI_ERR_INNOCENT, /* Innocent victim. */
411 AHCI_ERR_TFE, /* Task File Error. */
412 AHCI_ERR_SATA, /* SATA error. */
413 AHCI_ERR_TIMEOUT, /* Command execution timeout. */
414 AHCI_ERR_NCQ, /* NCQ command error. CCB should be put on hold
415 * until READ LOG executed to reveal error. */
416};
417
418/* macros to hide busspace uglyness */
419#define ATA_INB(res, offset) \
420 bus_read_1((res), (offset))
421#define ATA_INW(res, offset) \
422 bus_read_2((res), (offset))
423#define ATA_INL(res, offset) \
424 bus_read_4((res), (offset))
425#define ATA_INSW(res, offset, addr, count) \
426 bus_read_multi_2((res), (offset), (addr), (count))
427#define ATA_INSW_STRM(res, offset, addr, count) \
428 bus_read_multi_stream_2((res), (offset), (addr), (count))
429#define ATA_INSL(res, offset, addr, count) \
430 bus_read_multi_4((res), (offset), (addr), (count))
431#define ATA_INSL_STRM(res, offset, addr, count) \
432 bus_read_multi_stream_4((res), (offset), (addr), (count))
433#define ATA_OUTB(res, offset, value) \
434 bus_write_1((res), (offset), (value))
435#define ATA_OUTW(res, offset, value) \
436 bus_write_2((res), (offset), (value))
437#define ATA_OUTL(res, offset, value) \
438 bus_write_4((res), (offset), (value))
439#define ATA_OUTSW(res, offset, addr, count) \
440 bus_write_multi_2((res), (offset), (addr), (count))
441#define ATA_OUTSW_STRM(res, offset, addr, count) \
442 bus_write_multi_stream_2((res), (offset), (addr), (count))
443#define ATA_OUTSL(res, offset, addr, count) \
444 bus_write_multi_4((res), (offset), (addr), (count))
445#define ATA_OUTSL_STRM(res, offset, addr, count) \
446 bus_write_multi_stream_4((res), (offset), (addr), (count))
| 386};
387
388/* structure describing a AHCI controller */
389struct ahci_controller {
390 device_t dev;
391 int r_rid;
392 struct resource *r_mem;
393 struct rman sc_iomem;
394 struct ahci_controller_irq {
395 struct ahci_controller *ctlr;
396 struct resource *r_irq;
397 void *handle;
398 int r_irq_rid;
399 int mode;
400#define AHCI_IRQ_MODE_ALL 0
401#define AHCI_IRQ_MODE_AFTER 1
402#define AHCI_IRQ_MODE_ONE 2
403 } irqs[16];
404 uint32_t caps; /* Controller capabilities */
405 uint32_t caps2; /* Controller capabilities */
406 int quirks;
407 int numirqs;
408 int channels;
409 int ichannels;
410 int ccc; /* CCC timeout */
411 int cccv; /* CCC vector */
412 struct {
413 void (*function)(void *);
414 void *argument;
415 } interrupt[AHCI_MAX_PORTS];
416};
417
418enum ahci_err_type {
419 AHCI_ERR_NONE, /* No error */
420 AHCI_ERR_INVALID, /* Error detected by us before submitting. */
421 AHCI_ERR_INNOCENT, /* Innocent victim. */
422 AHCI_ERR_TFE, /* Task File Error. */
423 AHCI_ERR_SATA, /* SATA error. */
424 AHCI_ERR_TIMEOUT, /* Command execution timeout. */
425 AHCI_ERR_NCQ, /* NCQ command error. CCB should be put on hold
426 * until READ LOG executed to reveal error. */
427};
428
429/* macros to hide busspace uglyness */
430#define ATA_INB(res, offset) \
431 bus_read_1((res), (offset))
432#define ATA_INW(res, offset) \
433 bus_read_2((res), (offset))
434#define ATA_INL(res, offset) \
435 bus_read_4((res), (offset))
436#define ATA_INSW(res, offset, addr, count) \
437 bus_read_multi_2((res), (offset), (addr), (count))
438#define ATA_INSW_STRM(res, offset, addr, count) \
439 bus_read_multi_stream_2((res), (offset), (addr), (count))
440#define ATA_INSL(res, offset, addr, count) \
441 bus_read_multi_4((res), (offset), (addr), (count))
442#define ATA_INSL_STRM(res, offset, addr, count) \
443 bus_read_multi_stream_4((res), (offset), (addr), (count))
444#define ATA_OUTB(res, offset, value) \
445 bus_write_1((res), (offset), (value))
446#define ATA_OUTW(res, offset, value) \
447 bus_write_2((res), (offset), (value))
448#define ATA_OUTL(res, offset, value) \
449 bus_write_4((res), (offset), (value))
450#define ATA_OUTSW(res, offset, addr, count) \
451 bus_write_multi_2((res), (offset), (addr), (count))
452#define ATA_OUTSW_STRM(res, offset, addr, count) \
453 bus_write_multi_stream_2((res), (offset), (addr), (count))
454#define ATA_OUTSL(res, offset, addr, count) \
455 bus_write_multi_4((res), (offset), (addr), (count))
456#define ATA_OUTSL_STRM(res, offset, addr, count) \
457 bus_write_multi_stream_4((res), (offset), (addr), (count))
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