1/*-
2 * Copyright (c) 2000 Doug Rabson
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
| 1/*-
2 * Copyright (c) 2000 Doug Rabson
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
|
27 */
28
29#ifndef _PCI_AGPREG_H_
30#define _PCI_AGPREG_H_
31
32/*
33 * Offsets for various AGP configuration registers.
34 */
35#define AGP_APBASE 0x10
36#define AGP_CAPPTR 0x34
37
38/*
39 * Offsets from the AGP Capability pointer.
40 */
41#define AGP_CAPID 0x0
42#define AGP_CAPID_GET_MAJOR(x) (((x) & 0x00f00000U) >> 20)
43#define AGP_CAPID_GET_MINOR(x) (((x) & 0x000f0000U) >> 16)
44#define AGP_CAPID_GET_NEXT_PTR(x) (((x) & 0x0000ff00U) >> 8)
45#define AGP_CAPID_GET_CAP_ID(x) (((x) & 0x000000ffU) >> 0)
46
47#define AGP_STATUS 0x4
48#define AGP_COMMAND 0x8
49#define AGP_STATUS_AGP3 0x0008
50#define AGP_STATUS_RQ_MASK 0xff000000
51#define AGP_COMMAND_RQ_MASK 0xff000000
52#define AGP_STATUS_ARQSZ_MASK 0xe000
53#define AGP_COMMAND_ARQSZ_MASK 0xe000
54#define AGP_STATUS_CAL_MASK 0x1c00
55#define AGP_COMMAND_CAL_MASK 0x1c00
56#define AGP_STATUS_ISOCH 0x10000
57#define AGP_STATUS_SBA 0x0200
58#define AGP_STATUS_ITA_COH 0x0100
59#define AGP_STATUS_GART64 0x0080
60#define AGP_STATUS_HTRANS 0x0040
61#define AGP_STATUS_64BIT 0x0020
62#define AGP_STATUS_FW 0x0010
63#define AGP_COMMAND_RQ_MASK 0xff000000
64#define AGP_COMMAND_ARQSZ_MASK 0xe000
65#define AGP_COMMAND_CAL_MASK 0x1c00
66#define AGP_COMMAND_SBA 0x0200
67#define AGP_COMMAND_AGP 0x0100
68#define AGP_COMMAND_GART64 0x0080
69#define AGP_COMMAND_64BIT 0x0020
70#define AGP_COMMAND_FW 0x0010
71
72/*
73 * Config offsets for Intel AGP chipsets.
74 */
75#define AGP_INTEL_NBXCFG 0x50
76#define AGP_INTEL_ERRSTS 0x91
77#define AGP_INTEL_AGPCTRL 0xb0
78#define AGP_INTEL_APSIZE 0xb4
79#define AGP_INTEL_ATTBASE 0xb8
80
81/*
82 * Config offsets for Intel i820/i840/i845/i850/i860/i865 AGP chipsets.
83 */
84#define AGP_INTEL_MCHCFG 0x50
85#define AGP_INTEL_I820_RDCR 0x51
86#define AGP_INTEL_I845_MCHCFG 0x51
87#define AGP_INTEL_I8XX_ERRSTS 0xc8
88
89/*
90 * Config offsets for VIA AGP 2.x chipsets.
91 */
92#define AGP_VIA_GARTCTRL 0x80
93#define AGP_VIA_APSIZE 0x84
94#define AGP_VIA_ATTBASE 0x88
95
96/*
97 * Config offsets for VIA AGP 3.0 chipsets.
98 */
99#define AGP3_VIA_GARTCTRL 0x90
100#define AGP3_VIA_APSIZE 0x94
101#define AGP3_VIA_ATTBASE 0x98
102#define AGP_VIA_AGPSEL 0xfd
103
104/*
105 * Config offsets for SiS AGP chipsets.
106 */
107#define AGP_SIS_ATTBASE 0x90
108#define AGP_SIS_WINCTRL 0x94
109#define AGP_SIS_TLBCTRL 0x97
110#define AGP_SIS_TLBFLUSH 0x98
111
112/*
113 * Config offsets for Ali AGP chipsets.
114 */
115#define AGP_ALI_AGPCTRL 0xb8
116#define AGP_ALI_ATTBASE 0xbc
117#define AGP_ALI_TLBCTRL 0xc0
118
119/*
120 * Config offsets for the AMD 751 chipset.
121 */
122#define AGP_AMD751_APBASE 0x10
123#define AGP_AMD751_REGISTERS 0x14
124#define AGP_AMD751_APCTRL 0xac
125#define AGP_AMD751_MODECTRL 0xb0
126#define AGP_AMD751_MODECTRL_SYNEN 0x80
127#define AGP_AMD751_MODECTRL2 0xb2
128#define AGP_AMD751_MODECTRL2_G1LM 0x01
129#define AGP_AMD751_MODECTRL2_GPDCE 0x02
130#define AGP_AMD751_MODECTRL2_NGSE 0x08
131
132/*
133 * Memory mapped register offsets for AMD 751 chipset.
134 */
135#define AGP_AMD751_CAPS 0x00
136#define AGP_AMD751_CAPS_EHI 0x0800
137#define AGP_AMD751_CAPS_P2P 0x0400
138#define AGP_AMD751_CAPS_MPC 0x0200
139#define AGP_AMD751_CAPS_VBE 0x0100
140#define AGP_AMD751_CAPS_REV 0x00ff
141#define AGP_AMD751_STATUS 0x02
142#define AGP_AMD751_STATUS_P2PS 0x0800
143#define AGP_AMD751_STATUS_GCS 0x0400
144#define AGP_AMD751_STATUS_MPS 0x0200
145#define AGP_AMD751_STATUS_VBES 0x0100
146#define AGP_AMD751_STATUS_P2PE 0x0008
147#define AGP_AMD751_STATUS_GCE 0x0004
148#define AGP_AMD751_STATUS_VBEE 0x0001
149#define AGP_AMD751_ATTBASE 0x04
150#define AGP_AMD751_TLBCTRL 0x0c
151
152/*
153 * Config registers for i810 device 0
154 */
155#define AGP_I810_SMRAM 0x70
156#define AGP_I810_SMRAM_GMS 0xc0
157#define AGP_I810_SMRAM_GMS_DISABLED 0x00
158#define AGP_I810_SMRAM_GMS_ENABLED_0 0x40
159#define AGP_I810_SMRAM_GMS_ENABLED_512 0x80
160#define AGP_I810_SMRAM_GMS_ENABLED_1024 0xc0
161#define AGP_I810_MISCC 0x72
162#define AGP_I810_MISCC_WINSIZE 0x0001
163#define AGP_I810_MISCC_WINSIZE_64 0x0000
164#define AGP_I810_MISCC_WINSIZE_32 0x0001
165#define AGP_I810_MISCC_PLCK 0x0008
166#define AGP_I810_MISCC_PLCK_UNLOCKED 0x0000
167#define AGP_I810_MISCC_PLCK_LOCKED 0x0008
168#define AGP_I810_MISCC_WPTC 0x0030
169#define AGP_I810_MISCC_WPTC_NOLIMIT 0x0000
170#define AGP_I810_MISCC_WPTC_62 0x0010
171#define AGP_I810_MISCC_WPTC_50 0x0020
172#define AGP_I810_MISCC_WPTC_37 0x0030
173#define AGP_I810_MISCC_RPTC 0x00c0
174#define AGP_I810_MISCC_RPTC_NOLIMIT 0x0000
175#define AGP_I810_MISCC_RPTC_62 0x0040
176#define AGP_I810_MISCC_RPTC_50 0x0080
177#define AGP_I810_MISCC_RPTC_37 0x00c0
178
179/*
180 * Config registers for i810 device 1
181 */
182#define AGP_I810_GMADR 0x10
183#define AGP_I810_MMADR 0x14
184
185/*
186 * Memory mapped register offsets for i810 chipset.
187 */
188#define AGP_I810_PGTBL_CTL 0x2020
189#define AGP_I810_DRT 0x3000
190#define AGP_I810_DRT_UNPOPULATED 0x00
191#define AGP_I810_DRT_POPULATED 0x01
192#define AGP_I810_GTT 0x10000
193
194/*
195 * Config registers for i830MG device 0
196 */
197#define AGP_I830_GCC1 0x52
198#define AGP_I830_GCC1_DEV2 0x08
199#define AGP_I830_GCC1_DEV2_ENABLED 0x00
200#define AGP_I830_GCC1_DEV2_DISABLED 0x08
201#define AGP_I830_GCC1_GMS 0x70
202#define AGP_I830_GCC1_GMS_STOLEN_512 0x20
203#define AGP_I830_GCC1_GMS_STOLEN_1024 0x30
204#define AGP_I830_GCC1_GMS_STOLEN_8192 0x40
205#define AGP_I830_GCC1_GMASIZE 0x01
206#define AGP_I830_GCC1_GMASIZE_64 0x01
207#define AGP_I830_GCC1_GMASIZE_128 0x00
208
209/*
210 * Config registers for 852GM/855GM/865G device 0
211 */
212#define AGP_I855_GCC1 0x52
213#define AGP_I855_GCC1_DEV2 0x08
214#define AGP_I855_GCC1_DEV2_ENABLED 0x00
215#define AGP_I855_GCC1_DEV2_DISABLED 0x08
216#define AGP_I855_GCC1_GMS 0x70
217#define AGP_I855_GCC1_GMS_STOLEN_0M 0x00
218#define AGP_I855_GCC1_GMS_STOLEN_1M 0x10
219#define AGP_I855_GCC1_GMS_STOLEN_4M 0x20
220#define AGP_I855_GCC1_GMS_STOLEN_8M 0x30
221#define AGP_I855_GCC1_GMS_STOLEN_16M 0x40
222#define AGP_I855_GCC1_GMS_STOLEN_32M 0x50
223
224/*
225 * 852GM/855GM variant identification
226 */
227#define AGP_I85X_CAPID 0x44
228#define AGP_I85X_VARIANT_MASK 0x7
229#define AGP_I85X_VARIANT_SHIFT 5
230#define AGP_I855_GME 0x0
231#define AGP_I855_GM 0x4
232#define AGP_I852_GME 0x2
233#define AGP_I852_GM 0x5
234
235/*
236 * NVIDIA nForce/nForce2 registers
237 */
238#define AGP_NVIDIA_0_APBASE 0x10
239#define AGP_NVIDIA_0_APSIZE 0x80
240#define AGP_NVIDIA_1_WBC 0xf0
241#define AGP_NVIDIA_2_GARTCTRL 0xd0
242#define AGP_NVIDIA_2_APBASE 0xd8
243#define AGP_NVIDIA_2_APLIMIT 0xdc
244#define AGP_NVIDIA_2_ATTBASE(i) (0xe0 + (i) * 4)
245#define AGP_NVIDIA_3_APBASE 0x50
246#define AGP_NVIDIA_3_APLIMIT 0x54
247
248/*
249 * AMD64 GART registers
250 */
251#define AGP_AMD64_APCTRL 0x90
252#define AGP_AMD64_APBASE 0x94
253#define AGP_AMD64_ATTBASE 0x98
254#define AGP_AMD64_CACHECTRL 0x9c
255#define AGP_AMD64_APCTRL_GARTEN 0x00000001
256#define AGP_AMD64_APCTRL_SIZE_MASK 0x0000000e
257#define AGP_AMD64_APCTRL_DISGARTCPU 0x00000010
258#define AGP_AMD64_APCTRL_DISGARTIO 0x00000020
259#define AGP_AMD64_APCTRL_DISWLKPRB 0x00000040
260#define AGP_AMD64_APBASE_MASK 0x00007fff
261#define AGP_AMD64_ATTBASE_MASK 0xfffffff0
262#define AGP_AMD64_CACHECTRL_INVGART 0x00000001
263#define AGP_AMD64_CACHECTRL_PTEERR 0x00000002
264
265/*
| 27 */
28
29#ifndef _PCI_AGPREG_H_
30#define _PCI_AGPREG_H_
31
32/*
33 * Offsets for various AGP configuration registers.
34 */
35#define AGP_APBASE 0x10
36#define AGP_CAPPTR 0x34
37
38/*
39 * Offsets from the AGP Capability pointer.
40 */
41#define AGP_CAPID 0x0
42#define AGP_CAPID_GET_MAJOR(x) (((x) & 0x00f00000U) >> 20)
43#define AGP_CAPID_GET_MINOR(x) (((x) & 0x000f0000U) >> 16)
44#define AGP_CAPID_GET_NEXT_PTR(x) (((x) & 0x0000ff00U) >> 8)
45#define AGP_CAPID_GET_CAP_ID(x) (((x) & 0x000000ffU) >> 0)
46
47#define AGP_STATUS 0x4
48#define AGP_COMMAND 0x8
49#define AGP_STATUS_AGP3 0x0008
50#define AGP_STATUS_RQ_MASK 0xff000000
51#define AGP_COMMAND_RQ_MASK 0xff000000
52#define AGP_STATUS_ARQSZ_MASK 0xe000
53#define AGP_COMMAND_ARQSZ_MASK 0xe000
54#define AGP_STATUS_CAL_MASK 0x1c00
55#define AGP_COMMAND_CAL_MASK 0x1c00
56#define AGP_STATUS_ISOCH 0x10000
57#define AGP_STATUS_SBA 0x0200
58#define AGP_STATUS_ITA_COH 0x0100
59#define AGP_STATUS_GART64 0x0080
60#define AGP_STATUS_HTRANS 0x0040
61#define AGP_STATUS_64BIT 0x0020
62#define AGP_STATUS_FW 0x0010
63#define AGP_COMMAND_RQ_MASK 0xff000000
64#define AGP_COMMAND_ARQSZ_MASK 0xe000
65#define AGP_COMMAND_CAL_MASK 0x1c00
66#define AGP_COMMAND_SBA 0x0200
67#define AGP_COMMAND_AGP 0x0100
68#define AGP_COMMAND_GART64 0x0080
69#define AGP_COMMAND_64BIT 0x0020
70#define AGP_COMMAND_FW 0x0010
71
72/*
73 * Config offsets for Intel AGP chipsets.
74 */
75#define AGP_INTEL_NBXCFG 0x50
76#define AGP_INTEL_ERRSTS 0x91
77#define AGP_INTEL_AGPCTRL 0xb0
78#define AGP_INTEL_APSIZE 0xb4
79#define AGP_INTEL_ATTBASE 0xb8
80
81/*
82 * Config offsets for Intel i820/i840/i845/i850/i860/i865 AGP chipsets.
83 */
84#define AGP_INTEL_MCHCFG 0x50
85#define AGP_INTEL_I820_RDCR 0x51
86#define AGP_INTEL_I845_MCHCFG 0x51
87#define AGP_INTEL_I8XX_ERRSTS 0xc8
88
89/*
90 * Config offsets for VIA AGP 2.x chipsets.
91 */
92#define AGP_VIA_GARTCTRL 0x80
93#define AGP_VIA_APSIZE 0x84
94#define AGP_VIA_ATTBASE 0x88
95
96/*
97 * Config offsets for VIA AGP 3.0 chipsets.
98 */
99#define AGP3_VIA_GARTCTRL 0x90
100#define AGP3_VIA_APSIZE 0x94
101#define AGP3_VIA_ATTBASE 0x98
102#define AGP_VIA_AGPSEL 0xfd
103
104/*
105 * Config offsets for SiS AGP chipsets.
106 */
107#define AGP_SIS_ATTBASE 0x90
108#define AGP_SIS_WINCTRL 0x94
109#define AGP_SIS_TLBCTRL 0x97
110#define AGP_SIS_TLBFLUSH 0x98
111
112/*
113 * Config offsets for Ali AGP chipsets.
114 */
115#define AGP_ALI_AGPCTRL 0xb8
116#define AGP_ALI_ATTBASE 0xbc
117#define AGP_ALI_TLBCTRL 0xc0
118
119/*
120 * Config offsets for the AMD 751 chipset.
121 */
122#define AGP_AMD751_APBASE 0x10
123#define AGP_AMD751_REGISTERS 0x14
124#define AGP_AMD751_APCTRL 0xac
125#define AGP_AMD751_MODECTRL 0xb0
126#define AGP_AMD751_MODECTRL_SYNEN 0x80
127#define AGP_AMD751_MODECTRL2 0xb2
128#define AGP_AMD751_MODECTRL2_G1LM 0x01
129#define AGP_AMD751_MODECTRL2_GPDCE 0x02
130#define AGP_AMD751_MODECTRL2_NGSE 0x08
131
132/*
133 * Memory mapped register offsets for AMD 751 chipset.
134 */
135#define AGP_AMD751_CAPS 0x00
136#define AGP_AMD751_CAPS_EHI 0x0800
137#define AGP_AMD751_CAPS_P2P 0x0400
138#define AGP_AMD751_CAPS_MPC 0x0200
139#define AGP_AMD751_CAPS_VBE 0x0100
140#define AGP_AMD751_CAPS_REV 0x00ff
141#define AGP_AMD751_STATUS 0x02
142#define AGP_AMD751_STATUS_P2PS 0x0800
143#define AGP_AMD751_STATUS_GCS 0x0400
144#define AGP_AMD751_STATUS_MPS 0x0200
145#define AGP_AMD751_STATUS_VBES 0x0100
146#define AGP_AMD751_STATUS_P2PE 0x0008
147#define AGP_AMD751_STATUS_GCE 0x0004
148#define AGP_AMD751_STATUS_VBEE 0x0001
149#define AGP_AMD751_ATTBASE 0x04
150#define AGP_AMD751_TLBCTRL 0x0c
151
152/*
153 * Config registers for i810 device 0
154 */
155#define AGP_I810_SMRAM 0x70
156#define AGP_I810_SMRAM_GMS 0xc0
157#define AGP_I810_SMRAM_GMS_DISABLED 0x00
158#define AGP_I810_SMRAM_GMS_ENABLED_0 0x40
159#define AGP_I810_SMRAM_GMS_ENABLED_512 0x80
160#define AGP_I810_SMRAM_GMS_ENABLED_1024 0xc0
161#define AGP_I810_MISCC 0x72
162#define AGP_I810_MISCC_WINSIZE 0x0001
163#define AGP_I810_MISCC_WINSIZE_64 0x0000
164#define AGP_I810_MISCC_WINSIZE_32 0x0001
165#define AGP_I810_MISCC_PLCK 0x0008
166#define AGP_I810_MISCC_PLCK_UNLOCKED 0x0000
167#define AGP_I810_MISCC_PLCK_LOCKED 0x0008
168#define AGP_I810_MISCC_WPTC 0x0030
169#define AGP_I810_MISCC_WPTC_NOLIMIT 0x0000
170#define AGP_I810_MISCC_WPTC_62 0x0010
171#define AGP_I810_MISCC_WPTC_50 0x0020
172#define AGP_I810_MISCC_WPTC_37 0x0030
173#define AGP_I810_MISCC_RPTC 0x00c0
174#define AGP_I810_MISCC_RPTC_NOLIMIT 0x0000
175#define AGP_I810_MISCC_RPTC_62 0x0040
176#define AGP_I810_MISCC_RPTC_50 0x0080
177#define AGP_I810_MISCC_RPTC_37 0x00c0
178
179/*
180 * Config registers for i810 device 1
181 */
182#define AGP_I810_GMADR 0x10
183#define AGP_I810_MMADR 0x14
184
185/*
186 * Memory mapped register offsets for i810 chipset.
187 */
188#define AGP_I810_PGTBL_CTL 0x2020
189#define AGP_I810_DRT 0x3000
190#define AGP_I810_DRT_UNPOPULATED 0x00
191#define AGP_I810_DRT_POPULATED 0x01
192#define AGP_I810_GTT 0x10000
193
194/*
195 * Config registers for i830MG device 0
196 */
197#define AGP_I830_GCC1 0x52
198#define AGP_I830_GCC1_DEV2 0x08
199#define AGP_I830_GCC1_DEV2_ENABLED 0x00
200#define AGP_I830_GCC1_DEV2_DISABLED 0x08
201#define AGP_I830_GCC1_GMS 0x70
202#define AGP_I830_GCC1_GMS_STOLEN_512 0x20
203#define AGP_I830_GCC1_GMS_STOLEN_1024 0x30
204#define AGP_I830_GCC1_GMS_STOLEN_8192 0x40
205#define AGP_I830_GCC1_GMASIZE 0x01
206#define AGP_I830_GCC1_GMASIZE_64 0x01
207#define AGP_I830_GCC1_GMASIZE_128 0x00
208
209/*
210 * Config registers for 852GM/855GM/865G device 0
211 */
212#define AGP_I855_GCC1 0x52
213#define AGP_I855_GCC1_DEV2 0x08
214#define AGP_I855_GCC1_DEV2_ENABLED 0x00
215#define AGP_I855_GCC1_DEV2_DISABLED 0x08
216#define AGP_I855_GCC1_GMS 0x70
217#define AGP_I855_GCC1_GMS_STOLEN_0M 0x00
218#define AGP_I855_GCC1_GMS_STOLEN_1M 0x10
219#define AGP_I855_GCC1_GMS_STOLEN_4M 0x20
220#define AGP_I855_GCC1_GMS_STOLEN_8M 0x30
221#define AGP_I855_GCC1_GMS_STOLEN_16M 0x40
222#define AGP_I855_GCC1_GMS_STOLEN_32M 0x50
223
224/*
225 * 852GM/855GM variant identification
226 */
227#define AGP_I85X_CAPID 0x44
228#define AGP_I85X_VARIANT_MASK 0x7
229#define AGP_I85X_VARIANT_SHIFT 5
230#define AGP_I855_GME 0x0
231#define AGP_I855_GM 0x4
232#define AGP_I852_GME 0x2
233#define AGP_I852_GM 0x5
234
235/*
236 * NVIDIA nForce/nForce2 registers
237 */
238#define AGP_NVIDIA_0_APBASE 0x10
239#define AGP_NVIDIA_0_APSIZE 0x80
240#define AGP_NVIDIA_1_WBC 0xf0
241#define AGP_NVIDIA_2_GARTCTRL 0xd0
242#define AGP_NVIDIA_2_APBASE 0xd8
243#define AGP_NVIDIA_2_APLIMIT 0xdc
244#define AGP_NVIDIA_2_ATTBASE(i) (0xe0 + (i) * 4)
245#define AGP_NVIDIA_3_APBASE 0x50
246#define AGP_NVIDIA_3_APLIMIT 0x54
247
248/*
249 * AMD64 GART registers
250 */
251#define AGP_AMD64_APCTRL 0x90
252#define AGP_AMD64_APBASE 0x94
253#define AGP_AMD64_ATTBASE 0x98
254#define AGP_AMD64_CACHECTRL 0x9c
255#define AGP_AMD64_APCTRL_GARTEN 0x00000001
256#define AGP_AMD64_APCTRL_SIZE_MASK 0x0000000e
257#define AGP_AMD64_APCTRL_DISGARTCPU 0x00000010
258#define AGP_AMD64_APCTRL_DISGARTIO 0x00000020
259#define AGP_AMD64_APCTRL_DISWLKPRB 0x00000040
260#define AGP_AMD64_APBASE_MASK 0x00007fff
261#define AGP_AMD64_ATTBASE_MASK 0xfffffff0
262#define AGP_AMD64_CACHECTRL_INVGART 0x00000001
263#define AGP_AMD64_CACHECTRL_PTEERR 0x00000002
264
265/*
|
266 * ATI IGP registers
267 */
268#define ATI_GART_MMADDR 0x14
269#define ATI_RS100_APSIZE 0xac
270#define ATI_RS100_IG_AGPMODE 0xb0
271#define ATI_RS300_APSIZE 0xf8
272#define ATI_RS300_IG_AGPMODE 0xfc
273#define ATI_GART_FEATURE_ID 0x00
274#define ATI_GART_BASE 0x04
275#define ATI_GART_CACHE_CNTRL 0x0c
276
277#endif /* !_PCI_AGPREG_H_ */
| 283 * ATI IGP registers
284 */
285#define ATI_GART_MMADDR 0x14
286#define ATI_RS100_APSIZE 0xac
287#define ATI_RS100_IG_AGPMODE 0xb0
288#define ATI_RS300_APSIZE 0xf8
289#define ATI_RS300_IG_AGPMODE 0xfc
290#define ATI_GART_FEATURE_ID 0x00
291#define ATI_GART_BASE 0x04
292#define ATI_GART_CACHE_CNTRL 0x0c
293
294#endif /* !_PCI_AGPREG_H_ */
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