120 desc = agp_nvidia_match(dev); 121 if (desc) { 122 device_set_desc(dev, desc); 123 return (BUS_PROBE_DEFAULT); 124 } 125 return (ENXIO); 126} 127 128static int 129agp_nvidia_attach (device_t dev) 130{ 131 struct agp_nvidia_softc *sc = device_get_softc(dev); 132 struct agp_gatt *gatt; 133 u_int32_t apbase; 134 u_int32_t aplimit; 135 u_int32_t temp; 136 int size; 137 int i; 138 int error; 139 140 switch (pci_get_device(dev)) { 141 case NVIDIA_DEVICEID_NFORCE: 142 sc->wbc_mask = 0x00010000; 143 break; 144 case NVIDIA_DEVICEID_NFORCE2: 145 sc->wbc_mask = 0x80000000; 146 break; 147 default: 148 device_printf(dev, "Bad chip id\n"); 149 return (ENODEV); 150 } 151 152 /* AGP Controller */ 153 sc->dev = dev; 154 155 /* Memory Controller 1 */ 156 sc->mc1_dev = pci_find_bsf(pci_get_bus(dev), 0, 1); 157 if (sc->mc1_dev == NULL) { 158 device_printf(dev, 159 "Unable to find NVIDIA Memory Controller 1.\n"); 160 return (ENODEV); 161 } 162 163 /* Memory Controller 2 */ 164 sc->mc2_dev = pci_find_bsf(pci_get_bus(dev), 0, 2); 165 if (sc->mc2_dev == NULL) { 166 device_printf(dev, 167 "Unable to find NVIDIA Memory Controller 2.\n"); 168 return (ENODEV); 169 } 170 171 /* AGP Host to PCI Bridge */ 172 sc->bdev = pci_find_bsf(pci_get_bus(dev), 30, 0); 173 if (sc->bdev == NULL) { 174 device_printf(dev, 175 "Unable to find NVIDIA AGP Host to PCI Bridge.\n"); 176 return (ENODEV); 177 } 178 179 error = agp_generic_attach(dev); 180 if (error) 181 return (error); 182 183 sc->initial_aperture = AGP_GET_APERTURE(dev); 184 185 for (;;) { 186 gatt = agp_alloc_gatt(dev); 187 if (gatt) 188 break; 189 /* 190 * Probably contigmalloc failure. Try reducing the 191 * aperture so that the gatt size reduces. 192 */ 193 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) 194 goto fail; 195 } 196 sc->gatt = gatt; 197 198 apbase = rman_get_start(sc->agp.as_aperture); 199 aplimit = apbase + AGP_GET_APERTURE(dev) - 1; 200 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_APBASE, apbase, 4); 201 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_APLIMIT, aplimit, 4); 202 pci_write_config(sc->bdev, AGP_NVIDIA_3_APBASE, apbase, 4); 203 pci_write_config(sc->bdev, AGP_NVIDIA_3_APLIMIT, aplimit, 4); 204 205 error = nvidia_init_iorr(apbase, AGP_GET_APERTURE(dev)); 206 if (error) { 207 device_printf(dev, "Failed to setup IORRs\n"); 208 goto fail; 209 } 210 211 /* directory size is 64k */ 212 size = AGP_GET_APERTURE(dev) / 1024 / 1024; 213 sc->num_dirs = size / 64; 214 sc->num_active_entries = (size == 32) ? 16384 : ((size * 1024) / 4); 215 sc->pg_offset = 0; 216 if (sc->num_dirs == 0) { 217 sc->num_dirs = 1; 218 sc->num_active_entries /= (64 / size); 219 sc->pg_offset = (apbase & (64 * 1024 * 1024 - 1) & 220 ~(AGP_GET_APERTURE(dev) - 1)) / PAGE_SIZE; 221 } 222 223 /* (G)ATT Base Address */ 224 for (i = 0; i < 8; i++) { 225 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_ATTBASE(i), 226 (sc->gatt->ag_physical + 227 (i % sc->num_dirs) * 64 * 1024) | 1, 4); 228 } 229 230 /* GTLB Control */ 231 temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4); 232 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, temp | 0x11, 4); 233 234 /* GART Control */ 235 temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4); 236 pci_write_config(sc->dev, AGP_NVIDIA_0_APSIZE, temp | 0x100, 4); 237 238 return (0); 239fail: 240 agp_generic_detach(dev); 241 return (ENOMEM); 242} 243 244static int 245agp_nvidia_detach (device_t dev) 246{ 247 struct agp_nvidia_softc *sc = device_get_softc(dev); 248 u_int32_t temp; 249 250 agp_free_cdev(dev); 251 252 /* GART Control */ 253 temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4); 254 pci_write_config(sc->dev, AGP_NVIDIA_0_APSIZE, temp & ~(0x100), 4); 255 256 /* GTLB Control */ 257 temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4); 258 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, temp & ~(0x11), 4); 259 260 /* Put the aperture back the way it started. */ 261 AGP_SET_APERTURE(dev, sc->initial_aperture); 262 263 /* restore iorr for previous aperture size */ 264 nvidia_init_iorr(rman_get_start(sc->agp.as_aperture), 265 sc->initial_aperture); 266 267 agp_free_gatt(sc->gatt); 268 agp_free_res(dev); 269 270 return (0); 271} 272 273static u_int32_t 274agp_nvidia_get_aperture(device_t dev) 275{ 276 switch (pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1) & 0x0f) { 277 case 0: return (512 * 1024 * 1024); break; 278 case 8: return (256 * 1024 * 1024); break; 279 case 12: return (128 * 1024 * 1024); break; 280 case 14: return (64 * 1024 * 1024); break; 281 case 15: return (32 * 1024 * 1024); break; 282 default: 283 device_printf(dev, "Invalid aperture setting 0x%x\n", 284 pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1)); 285 return 0; 286 } 287} 288 289static int 290agp_nvidia_set_aperture(device_t dev, u_int32_t aperture) 291{ 292 u_int8_t val; 293 u_int8_t key; 294 295 switch (aperture) { 296 case (512 * 1024 * 1024): key = 0; break; 297 case (256 * 1024 * 1024): key = 8; break; 298 case (128 * 1024 * 1024): key = 12; break; 299 case (64 * 1024 * 1024): key = 14; break; 300 case (32 * 1024 * 1024): key = 15; break; 301 default: 302 device_printf(dev, "Invalid aperture size (%dMb)\n", 303 aperture / 1024 / 1024); 304 return (EINVAL); 305 } 306 val = pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1); 307 pci_write_config(dev, AGP_NVIDIA_0_APSIZE, ((val & ~0x0f) | key), 1); 308 309 return (0); 310} 311 312static int 313agp_nvidia_bind_page(device_t dev, vm_offset_t offset, vm_offset_t physical) 314{ 315 struct agp_nvidia_softc *sc = device_get_softc(dev); 316 u_int32_t index; 317 318 if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 319 return (EINVAL); 320 321 index = (sc->pg_offset + offset) >> AGP_PAGE_SHIFT; 322 sc->gatt->ag_virtual[index] = physical | 1; 323 324 return (0); 325} 326 327static int 328agp_nvidia_unbind_page(device_t dev, vm_offset_t offset) 329{ 330 struct agp_nvidia_softc *sc = device_get_softc(dev); 331 u_int32_t index; 332 333 if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 334 return (EINVAL); 335 336 index = (sc->pg_offset + offset) >> AGP_PAGE_SHIFT; 337 sc->gatt->ag_virtual[index] = 0; 338 339 return (0); 340} 341 342static void 343agp_nvidia_flush_tlb (device_t dev) 344{ 345 struct agp_nvidia_softc *sc; 346 u_int32_t wbc_reg, temp; 347 volatile u_int32_t *ag_virtual; 348 int i, pages; 349 350 sc = (struct agp_nvidia_softc *)device_get_softc(dev); 351 352 if (sc->wbc_mask) { 353 wbc_reg = pci_read_config(sc->mc1_dev, AGP_NVIDIA_1_WBC, 4); 354 wbc_reg |= sc->wbc_mask; 355 pci_write_config(sc->mc1_dev, AGP_NVIDIA_1_WBC, wbc_reg, 4); 356 357 /* Wait no more than 3 seconds. */ 358 for (i = 0; i < 3000; i++) { 359 wbc_reg = pci_read_config(sc->mc1_dev, 360 AGP_NVIDIA_1_WBC, 4); 361 if ((sc->wbc_mask & wbc_reg) == 0) 362 break; 363 else 364 DELAY(1000); 365 } 366 if (i == 3000) 367 device_printf(dev, 368 "TLB flush took more than 3 seconds.\n"); 369 } 370 371 ag_virtual = (volatile u_int32_t *)sc->gatt->ag_virtual; 372 373 /* Flush TLB entries. */ 374 pages = sc->gatt->ag_entries * sizeof(u_int32_t) / PAGE_SIZE; 375 for(i = 0; i < pages; i++) 376 temp = ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)]; 377 for(i = 0; i < pages; i++) 378 temp = ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)]; 379} 380 381#define SYSCFG 0xC0010010 382#define IORR_BASE0 0xC0010016 383#define IORR_MASK0 0xC0010017 384#define AMD_K7_NUM_IORR 2 385 386static int 387nvidia_init_iorr(u_int32_t addr, u_int32_t size) 388{ 389 quad_t base, mask, sys; 390 u_int32_t iorr_addr, free_iorr_addr; 391 392 /* Find the iorr that is already used for the addr */ 393 /* If not found, determine the uppermost available iorr */ 394 free_iorr_addr = AMD_K7_NUM_IORR; 395 for(iorr_addr = 0; iorr_addr < AMD_K7_NUM_IORR; iorr_addr++) { 396 base = rdmsr(IORR_BASE0 + 2 * iorr_addr); 397 mask = rdmsr(IORR_MASK0 + 2 * iorr_addr); 398 399 if ((base & 0xfffff000ULL) == (addr & 0xfffff000)) 400 break; 401 402 if ((mask & 0x00000800ULL) == 0) 403 free_iorr_addr = iorr_addr; 404 } 405 406 if (iorr_addr >= AMD_K7_NUM_IORR) { 407 iorr_addr = free_iorr_addr; 408 if (iorr_addr >= AMD_K7_NUM_IORR) 409 return (EINVAL); 410 } 411 412 base = (addr & ~0xfff) | 0x18; 413 mask = (0xfULL << 32) | ((~(size - 1)) & 0xfffff000) | 0x800; 414 wrmsr(IORR_BASE0 + 2 * iorr_addr, base); 415 wrmsr(IORR_MASK0 + 2 * iorr_addr, mask); 416 417 sys = rdmsr(SYSCFG); 418 sys |= 0x00100000ULL; 419 wrmsr(SYSCFG, sys); 420 421 return (0); 422} 423 424static device_method_t agp_nvidia_methods[] = { 425 /* Device interface */ 426 DEVMETHOD(device_probe, agp_nvidia_probe), 427 DEVMETHOD(device_attach, agp_nvidia_attach), 428 DEVMETHOD(device_detach, agp_nvidia_detach), 429 DEVMETHOD(device_shutdown, bus_generic_shutdown), 430 DEVMETHOD(device_suspend, bus_generic_suspend), 431 DEVMETHOD(device_resume, bus_generic_resume), 432 433 /* AGP interface */ 434 DEVMETHOD(agp_get_aperture, agp_nvidia_get_aperture), 435 DEVMETHOD(agp_set_aperture, agp_nvidia_set_aperture), 436 DEVMETHOD(agp_bind_page, agp_nvidia_bind_page), 437 DEVMETHOD(agp_unbind_page, agp_nvidia_unbind_page), 438 DEVMETHOD(agp_flush_tlb, agp_nvidia_flush_tlb), 439 440 DEVMETHOD(agp_enable, agp_generic_enable), 441 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory), 442 DEVMETHOD(agp_free_memory, agp_generic_free_memory), 443 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory), 444 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory), 445 446 { 0, 0 } 447}; 448 449static driver_t agp_nvidia_driver = { 450 "agp", 451 agp_nvidia_methods, 452 sizeof(struct agp_nvidia_softc), 453}; 454 455static devclass_t agp_devclass; 456 457DRIVER_MODULE(agp_nvidia, hostb, agp_nvidia_driver, agp_devclass, 0, 0); 458MODULE_DEPEND(agp_nvidia, agp, 1, 1, 1); 459MODULE_DEPEND(agp_nvidia, pci, 1, 1, 1);
| 122 desc = agp_nvidia_match(dev); 123 if (desc) { 124 device_set_desc(dev, desc); 125 return (BUS_PROBE_DEFAULT); 126 } 127 return (ENXIO); 128} 129 130static int 131agp_nvidia_attach (device_t dev) 132{ 133 struct agp_nvidia_softc *sc = device_get_softc(dev); 134 struct agp_gatt *gatt; 135 u_int32_t apbase; 136 u_int32_t aplimit; 137 u_int32_t temp; 138 int size; 139 int i; 140 int error; 141 142 switch (pci_get_device(dev)) { 143 case NVIDIA_DEVICEID_NFORCE: 144 sc->wbc_mask = 0x00010000; 145 break; 146 case NVIDIA_DEVICEID_NFORCE2: 147 sc->wbc_mask = 0x80000000; 148 break; 149 default: 150 device_printf(dev, "Bad chip id\n"); 151 return (ENODEV); 152 } 153 154 /* AGP Controller */ 155 sc->dev = dev; 156 157 /* Memory Controller 1 */ 158 sc->mc1_dev = pci_find_bsf(pci_get_bus(dev), 0, 1); 159 if (sc->mc1_dev == NULL) { 160 device_printf(dev, 161 "Unable to find NVIDIA Memory Controller 1.\n"); 162 return (ENODEV); 163 } 164 165 /* Memory Controller 2 */ 166 sc->mc2_dev = pci_find_bsf(pci_get_bus(dev), 0, 2); 167 if (sc->mc2_dev == NULL) { 168 device_printf(dev, 169 "Unable to find NVIDIA Memory Controller 2.\n"); 170 return (ENODEV); 171 } 172 173 /* AGP Host to PCI Bridge */ 174 sc->bdev = pci_find_bsf(pci_get_bus(dev), 30, 0); 175 if (sc->bdev == NULL) { 176 device_printf(dev, 177 "Unable to find NVIDIA AGP Host to PCI Bridge.\n"); 178 return (ENODEV); 179 } 180 181 error = agp_generic_attach(dev); 182 if (error) 183 return (error); 184 185 sc->initial_aperture = AGP_GET_APERTURE(dev); 186 187 for (;;) { 188 gatt = agp_alloc_gatt(dev); 189 if (gatt) 190 break; 191 /* 192 * Probably contigmalloc failure. Try reducing the 193 * aperture so that the gatt size reduces. 194 */ 195 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) 196 goto fail; 197 } 198 sc->gatt = gatt; 199 200 apbase = rman_get_start(sc->agp.as_aperture); 201 aplimit = apbase + AGP_GET_APERTURE(dev) - 1; 202 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_APBASE, apbase, 4); 203 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_APLIMIT, aplimit, 4); 204 pci_write_config(sc->bdev, AGP_NVIDIA_3_APBASE, apbase, 4); 205 pci_write_config(sc->bdev, AGP_NVIDIA_3_APLIMIT, aplimit, 4); 206 207 error = nvidia_init_iorr(apbase, AGP_GET_APERTURE(dev)); 208 if (error) { 209 device_printf(dev, "Failed to setup IORRs\n"); 210 goto fail; 211 } 212 213 /* directory size is 64k */ 214 size = AGP_GET_APERTURE(dev) / 1024 / 1024; 215 sc->num_dirs = size / 64; 216 sc->num_active_entries = (size == 32) ? 16384 : ((size * 1024) / 4); 217 sc->pg_offset = 0; 218 if (sc->num_dirs == 0) { 219 sc->num_dirs = 1; 220 sc->num_active_entries /= (64 / size); 221 sc->pg_offset = (apbase & (64 * 1024 * 1024 - 1) & 222 ~(AGP_GET_APERTURE(dev) - 1)) / PAGE_SIZE; 223 } 224 225 /* (G)ATT Base Address */ 226 for (i = 0; i < 8; i++) { 227 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_ATTBASE(i), 228 (sc->gatt->ag_physical + 229 (i % sc->num_dirs) * 64 * 1024) | 1, 4); 230 } 231 232 /* GTLB Control */ 233 temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4); 234 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, temp | 0x11, 4); 235 236 /* GART Control */ 237 temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4); 238 pci_write_config(sc->dev, AGP_NVIDIA_0_APSIZE, temp | 0x100, 4); 239 240 return (0); 241fail: 242 agp_generic_detach(dev); 243 return (ENOMEM); 244} 245 246static int 247agp_nvidia_detach (device_t dev) 248{ 249 struct agp_nvidia_softc *sc = device_get_softc(dev); 250 u_int32_t temp; 251 252 agp_free_cdev(dev); 253 254 /* GART Control */ 255 temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4); 256 pci_write_config(sc->dev, AGP_NVIDIA_0_APSIZE, temp & ~(0x100), 4); 257 258 /* GTLB Control */ 259 temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4); 260 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, temp & ~(0x11), 4); 261 262 /* Put the aperture back the way it started. */ 263 AGP_SET_APERTURE(dev, sc->initial_aperture); 264 265 /* restore iorr for previous aperture size */ 266 nvidia_init_iorr(rman_get_start(sc->agp.as_aperture), 267 sc->initial_aperture); 268 269 agp_free_gatt(sc->gatt); 270 agp_free_res(dev); 271 272 return (0); 273} 274 275static u_int32_t 276agp_nvidia_get_aperture(device_t dev) 277{ 278 switch (pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1) & 0x0f) { 279 case 0: return (512 * 1024 * 1024); break; 280 case 8: return (256 * 1024 * 1024); break; 281 case 12: return (128 * 1024 * 1024); break; 282 case 14: return (64 * 1024 * 1024); break; 283 case 15: return (32 * 1024 * 1024); break; 284 default: 285 device_printf(dev, "Invalid aperture setting 0x%x\n", 286 pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1)); 287 return 0; 288 } 289} 290 291static int 292agp_nvidia_set_aperture(device_t dev, u_int32_t aperture) 293{ 294 u_int8_t val; 295 u_int8_t key; 296 297 switch (aperture) { 298 case (512 * 1024 * 1024): key = 0; break; 299 case (256 * 1024 * 1024): key = 8; break; 300 case (128 * 1024 * 1024): key = 12; break; 301 case (64 * 1024 * 1024): key = 14; break; 302 case (32 * 1024 * 1024): key = 15; break; 303 default: 304 device_printf(dev, "Invalid aperture size (%dMb)\n", 305 aperture / 1024 / 1024); 306 return (EINVAL); 307 } 308 val = pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1); 309 pci_write_config(dev, AGP_NVIDIA_0_APSIZE, ((val & ~0x0f) | key), 1); 310 311 return (0); 312} 313 314static int 315agp_nvidia_bind_page(device_t dev, vm_offset_t offset, vm_offset_t physical) 316{ 317 struct agp_nvidia_softc *sc = device_get_softc(dev); 318 u_int32_t index; 319 320 if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 321 return (EINVAL); 322 323 index = (sc->pg_offset + offset) >> AGP_PAGE_SHIFT; 324 sc->gatt->ag_virtual[index] = physical | 1; 325 326 return (0); 327} 328 329static int 330agp_nvidia_unbind_page(device_t dev, vm_offset_t offset) 331{ 332 struct agp_nvidia_softc *sc = device_get_softc(dev); 333 u_int32_t index; 334 335 if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 336 return (EINVAL); 337 338 index = (sc->pg_offset + offset) >> AGP_PAGE_SHIFT; 339 sc->gatt->ag_virtual[index] = 0; 340 341 return (0); 342} 343 344static void 345agp_nvidia_flush_tlb (device_t dev) 346{ 347 struct agp_nvidia_softc *sc; 348 u_int32_t wbc_reg, temp; 349 volatile u_int32_t *ag_virtual; 350 int i, pages; 351 352 sc = (struct agp_nvidia_softc *)device_get_softc(dev); 353 354 if (sc->wbc_mask) { 355 wbc_reg = pci_read_config(sc->mc1_dev, AGP_NVIDIA_1_WBC, 4); 356 wbc_reg |= sc->wbc_mask; 357 pci_write_config(sc->mc1_dev, AGP_NVIDIA_1_WBC, wbc_reg, 4); 358 359 /* Wait no more than 3 seconds. */ 360 for (i = 0; i < 3000; i++) { 361 wbc_reg = pci_read_config(sc->mc1_dev, 362 AGP_NVIDIA_1_WBC, 4); 363 if ((sc->wbc_mask & wbc_reg) == 0) 364 break; 365 else 366 DELAY(1000); 367 } 368 if (i == 3000) 369 device_printf(dev, 370 "TLB flush took more than 3 seconds.\n"); 371 } 372 373 ag_virtual = (volatile u_int32_t *)sc->gatt->ag_virtual; 374 375 /* Flush TLB entries. */ 376 pages = sc->gatt->ag_entries * sizeof(u_int32_t) / PAGE_SIZE; 377 for(i = 0; i < pages; i++) 378 temp = ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)]; 379 for(i = 0; i < pages; i++) 380 temp = ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)]; 381} 382 383#define SYSCFG 0xC0010010 384#define IORR_BASE0 0xC0010016 385#define IORR_MASK0 0xC0010017 386#define AMD_K7_NUM_IORR 2 387 388static int 389nvidia_init_iorr(u_int32_t addr, u_int32_t size) 390{ 391 quad_t base, mask, sys; 392 u_int32_t iorr_addr, free_iorr_addr; 393 394 /* Find the iorr that is already used for the addr */ 395 /* If not found, determine the uppermost available iorr */ 396 free_iorr_addr = AMD_K7_NUM_IORR; 397 for(iorr_addr = 0; iorr_addr < AMD_K7_NUM_IORR; iorr_addr++) { 398 base = rdmsr(IORR_BASE0 + 2 * iorr_addr); 399 mask = rdmsr(IORR_MASK0 + 2 * iorr_addr); 400 401 if ((base & 0xfffff000ULL) == (addr & 0xfffff000)) 402 break; 403 404 if ((mask & 0x00000800ULL) == 0) 405 free_iorr_addr = iorr_addr; 406 } 407 408 if (iorr_addr >= AMD_K7_NUM_IORR) { 409 iorr_addr = free_iorr_addr; 410 if (iorr_addr >= AMD_K7_NUM_IORR) 411 return (EINVAL); 412 } 413 414 base = (addr & ~0xfff) | 0x18; 415 mask = (0xfULL << 32) | ((~(size - 1)) & 0xfffff000) | 0x800; 416 wrmsr(IORR_BASE0 + 2 * iorr_addr, base); 417 wrmsr(IORR_MASK0 + 2 * iorr_addr, mask); 418 419 sys = rdmsr(SYSCFG); 420 sys |= 0x00100000ULL; 421 wrmsr(SYSCFG, sys); 422 423 return (0); 424} 425 426static device_method_t agp_nvidia_methods[] = { 427 /* Device interface */ 428 DEVMETHOD(device_probe, agp_nvidia_probe), 429 DEVMETHOD(device_attach, agp_nvidia_attach), 430 DEVMETHOD(device_detach, agp_nvidia_detach), 431 DEVMETHOD(device_shutdown, bus_generic_shutdown), 432 DEVMETHOD(device_suspend, bus_generic_suspend), 433 DEVMETHOD(device_resume, bus_generic_resume), 434 435 /* AGP interface */ 436 DEVMETHOD(agp_get_aperture, agp_nvidia_get_aperture), 437 DEVMETHOD(agp_set_aperture, agp_nvidia_set_aperture), 438 DEVMETHOD(agp_bind_page, agp_nvidia_bind_page), 439 DEVMETHOD(agp_unbind_page, agp_nvidia_unbind_page), 440 DEVMETHOD(agp_flush_tlb, agp_nvidia_flush_tlb), 441 442 DEVMETHOD(agp_enable, agp_generic_enable), 443 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory), 444 DEVMETHOD(agp_free_memory, agp_generic_free_memory), 445 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory), 446 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory), 447 448 { 0, 0 } 449}; 450 451static driver_t agp_nvidia_driver = { 452 "agp", 453 agp_nvidia_methods, 454 sizeof(struct agp_nvidia_softc), 455}; 456 457static devclass_t agp_devclass; 458 459DRIVER_MODULE(agp_nvidia, hostb, agp_nvidia_driver, agp_devclass, 0, 0); 460MODULE_DEPEND(agp_nvidia, agp, 1, 1, 1); 461MODULE_DEPEND(agp_nvidia, pci, 1, 1, 1);
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