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agp_nvidia.c (142407) agp_nvidia.c (144517)
1/*-
2 * Copyright (c) 2003 Matthew N. Dodd <winter@jurai.net>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2003 Matthew N. Dodd <winter@jurai.net>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/sys/dev/agp/agp_nvidia.c 142407 2005-02-24 22:33:05Z imp $");
28__FBSDID("$FreeBSD: head/sys/dev/agp/agp_nvidia.c 144517 2005-04-02 01:10:09Z obrien $");
29
30/*
31 * Written using information gleaned from the
32 * NVIDIA nForce/nForce2 AGPGART Linux Kernel Patch.
33 */
34
35#include "opt_bus.h"
36
37#include <sys/param.h>
38#include <sys/systm.h>
39#include <sys/malloc.h>
40#include <sys/kernel.h>
41#include <sys/module.h>
42#include <sys/bus.h>
43#include <sys/lock.h>
44
45#if __FreeBSD_version < 500000
46#include "opt_pci.h"
47#endif
48
49#if __FreeBSD_version > 500000
50#include <sys/mutex.h>
51#include <sys/proc.h>
52#endif
53
54#include <dev/pci/pcivar.h>
55#include <dev/pci/pcireg.h>
56#include <pci/agppriv.h>
57#include <pci/agpreg.h>
58
59#include <vm/vm.h>
60#include <vm/vm_object.h>
61#include <vm/pmap.h>
62
63#include <machine/bus.h>
64#include <machine/resource.h>
65#include <sys/rman.h>
66
67#define NVIDIA_VENDORID 0x10de
68#define NVIDIA_DEVICEID_NFORCE 0x01a4
69#define NVIDIA_DEVICEID_NFORCE2 0x01e0
70
71struct agp_nvidia_softc {
72 struct agp_softc agp;
73 u_int32_t initial_aperture; /* aperture size at startup */
74 struct agp_gatt * gatt;
75
76 device_t dev; /* AGP Controller */
77 device_t mc1_dev; /* Memory Controller */
78 device_t mc2_dev; /* Memory Controller */
79 device_t bdev; /* Bridge */
80
81 u_int32_t wbc_mask;
82 int num_dirs;
83 int num_active_entries;
84 off_t pg_offset;
85};
86
87static const char *agp_nvidia_match(device_t dev);
88static int agp_nvidia_probe(device_t);
89static int agp_nvidia_attach(device_t);
90static int agp_nvidia_detach(device_t);
91static u_int32_t agp_nvidia_get_aperture(device_t);
92static int agp_nvidia_set_aperture(device_t, u_int32_t);
93static int agp_nvidia_bind_page(device_t, int, vm_offset_t);
94static int agp_nvidia_unbind_page(device_t, int);
95
96static int nvidia_init_iorr(u_int32_t, u_int32_t);
97
98static const char *
99agp_nvidia_match (device_t dev)
100{
101 if (pci_get_class(dev) != PCIC_BRIDGE ||
102 pci_get_subclass(dev) != PCIS_BRIDGE_HOST ||
103 pci_get_vendor(dev) != NVIDIA_VENDORID)
104 return (NULL);
105
106 switch (pci_get_device(dev)) {
107 case NVIDIA_DEVICEID_NFORCE:
108 return ("NVIDIA nForce AGP Controller");
109 case NVIDIA_DEVICEID_NFORCE2:
110 return ("NVIDIA nForce2 AGP Controller");
111 }
29
30/*
31 * Written using information gleaned from the
32 * NVIDIA nForce/nForce2 AGPGART Linux Kernel Patch.
33 */
34
35#include "opt_bus.h"
36
37#include <sys/param.h>
38#include <sys/systm.h>
39#include <sys/malloc.h>
40#include <sys/kernel.h>
41#include <sys/module.h>
42#include <sys/bus.h>
43#include <sys/lock.h>
44
45#if __FreeBSD_version < 500000
46#include "opt_pci.h"
47#endif
48
49#if __FreeBSD_version > 500000
50#include <sys/mutex.h>
51#include <sys/proc.h>
52#endif
53
54#include <dev/pci/pcivar.h>
55#include <dev/pci/pcireg.h>
56#include <pci/agppriv.h>
57#include <pci/agpreg.h>
58
59#include <vm/vm.h>
60#include <vm/vm_object.h>
61#include <vm/pmap.h>
62
63#include <machine/bus.h>
64#include <machine/resource.h>
65#include <sys/rman.h>
66
67#define NVIDIA_VENDORID 0x10de
68#define NVIDIA_DEVICEID_NFORCE 0x01a4
69#define NVIDIA_DEVICEID_NFORCE2 0x01e0
70
71struct agp_nvidia_softc {
72 struct agp_softc agp;
73 u_int32_t initial_aperture; /* aperture size at startup */
74 struct agp_gatt * gatt;
75
76 device_t dev; /* AGP Controller */
77 device_t mc1_dev; /* Memory Controller */
78 device_t mc2_dev; /* Memory Controller */
79 device_t bdev; /* Bridge */
80
81 u_int32_t wbc_mask;
82 int num_dirs;
83 int num_active_entries;
84 off_t pg_offset;
85};
86
87static const char *agp_nvidia_match(device_t dev);
88static int agp_nvidia_probe(device_t);
89static int agp_nvidia_attach(device_t);
90static int agp_nvidia_detach(device_t);
91static u_int32_t agp_nvidia_get_aperture(device_t);
92static int agp_nvidia_set_aperture(device_t, u_int32_t);
93static int agp_nvidia_bind_page(device_t, int, vm_offset_t);
94static int agp_nvidia_unbind_page(device_t, int);
95
96static int nvidia_init_iorr(u_int32_t, u_int32_t);
97
98static const char *
99agp_nvidia_match (device_t dev)
100{
101 if (pci_get_class(dev) != PCIC_BRIDGE ||
102 pci_get_subclass(dev) != PCIS_BRIDGE_HOST ||
103 pci_get_vendor(dev) != NVIDIA_VENDORID)
104 return (NULL);
105
106 switch (pci_get_device(dev)) {
107 case NVIDIA_DEVICEID_NFORCE:
108 return ("NVIDIA nForce AGP Controller");
109 case NVIDIA_DEVICEID_NFORCE2:
110 return ("NVIDIA nForce2 AGP Controller");
111 }
112 return ("NVIDIA Generic AGP Controller");
112 return (NULL);
113}
114
115static int
116agp_nvidia_probe (device_t dev)
117{
118 const char *desc;
119
120 if (resource_disabled("agp", device_get_unit(dev)))
121 return (ENXIO);
122 desc = agp_nvidia_match(dev);
123 if (desc) {
124 device_verbose(dev);
125 device_set_desc(dev, desc);
126 return (BUS_PROBE_DEFAULT);
127 }
128 return (ENXIO);
129}
130
131static int
132agp_nvidia_attach (device_t dev)
133{
134 struct agp_nvidia_softc *sc = device_get_softc(dev);
135 struct agp_gatt *gatt;
136 u_int32_t apbase;
137 u_int32_t aplimit;
138 u_int32_t temp;
139 int size;
140 int i;
141 int error;
142
143 switch (pci_get_device(dev)) {
144 case NVIDIA_DEVICEID_NFORCE:
145 sc->wbc_mask = 0x00010000;
146 break;
147 case NVIDIA_DEVICEID_NFORCE2:
148 sc->wbc_mask = 0x80000000;
149 break;
150 default:
151 sc->wbc_mask = 0;
152 break;
153 }
154
155 /* AGP Controller */
156 sc->dev = dev;
157
158 /* Memory Controller 1 */
159 sc->mc1_dev = pci_find_bsf(pci_get_bus(dev), 0, 1);
160 if (sc->mc1_dev == NULL) {
161 device_printf(dev,
162 "Unable to find NVIDIA Memory Controller 1.\n");
163 return (ENODEV);
164 }
165
166 /* Memory Controller 2 */
167 sc->mc2_dev = pci_find_bsf(pci_get_bus(dev), 0, 2);
168 if (sc->mc2_dev == NULL) {
169 device_printf(dev,
170 "Unable to find NVIDIA Memory Controller 2.\n");
171 return (ENODEV);
172 }
173
174 /* AGP Host to PCI Bridge */
175 sc->bdev = pci_find_bsf(pci_get_bus(dev), 30, 0);
176 if (sc->bdev == NULL) {
177 device_printf(dev,
178 "Unable to find NVIDIA AGP Host to PCI Bridge.\n");
179 return (ENODEV);
180 }
181
182 error = agp_generic_attach(dev);
183 if (error)
184 return (error);
185
186 sc->initial_aperture = AGP_GET_APERTURE(dev);
187
188 for (;;) {
189 gatt = agp_alloc_gatt(dev);
190 if (gatt)
191 break;
192 /*
193 * Probably contigmalloc failure. Try reducing the
194 * aperture so that the gatt size reduces.
195 */
196 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2))
197 goto fail;
198 }
199 sc->gatt = gatt;
200
201 apbase = rman_get_start(sc->agp.as_aperture);
202 aplimit = apbase + AGP_GET_APERTURE(dev) - 1;
203 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_APBASE, apbase, 4);
204 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_APLIMIT, aplimit, 4);
205 pci_write_config(sc->bdev, AGP_NVIDIA_3_APBASE, apbase, 4);
206 pci_write_config(sc->bdev, AGP_NVIDIA_3_APLIMIT, aplimit, 4);
207
208 error = nvidia_init_iorr(apbase, AGP_GET_APERTURE(dev));
209 if (error) {
210 device_printf(dev, "Failed to setup IORRs\n");
211 goto fail;
212 }
213
214 /* directory size is 64k */
215 size = AGP_GET_APERTURE(dev) / 1024 / 1024;
216 sc->num_dirs = size / 64;
217 sc->num_active_entries = (size == 32) ? 16384 : ((size * 1024) / 4);
218 sc->pg_offset = 0;
219 if (sc->num_dirs == 0) {
220 sc->num_dirs = 1;
221 sc->num_active_entries /= (64 / size);
222 sc->pg_offset = (apbase & (64 * 1024 * 1024 - 1) &
223 ~(AGP_GET_APERTURE(dev) - 1)) / PAGE_SIZE;
224 }
225
226 /* (G)ATT Base Address */
227 for (i = 0; i < 8; i++) {
228 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_ATTBASE(i),
229 (sc->gatt->ag_physical +
230 (i % sc->num_dirs) * 64 * 1024),
231 4);
232 }
233
234 /* GTLB Control */
235 temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4);
236 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, temp | 0x11, 4);
237
238 /* GART Control */
239 temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4);
240 pci_write_config(sc->dev, AGP_NVIDIA_0_APSIZE, temp | 0x100, 4);
241
242 return (0);
243fail:
244 agp_generic_detach(dev);
245 return (ENOMEM);
246}
247
248static int
249agp_nvidia_detach (device_t dev)
250{
251 struct agp_nvidia_softc *sc = device_get_softc(dev);
252 int error;
253 u_int32_t temp;
254
255 error = agp_generic_detach(dev);
256 if (error)
257 return (error);
258
259 /* GART Control */
260 temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4);
261 pci_write_config(sc->dev, AGP_NVIDIA_0_APSIZE, temp & ~(0x100), 4);
262
263 /* GTLB Control */
264 temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4);
265 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, temp & ~(0x11), 4);
266
267 /* Put the aperture back the way it started. */
268 AGP_SET_APERTURE(dev, sc->initial_aperture);
269
270 /* restore iorr for previous aperture size */
271 nvidia_init_iorr(rman_get_start(sc->agp.as_aperture),
272 sc->initial_aperture);
273
274 agp_free_gatt(sc->gatt);
275
276 return (0);
277}
278
279static u_int32_t
280agp_nvidia_get_aperture(device_t dev)
281{
282 u_int8_t key;
283
284 key = ffs(pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1) & 0x0f);
285 return (1 << (24 + (key ? key : 5)));
286}
287
288static int
289agp_nvidia_set_aperture(device_t dev, u_int32_t aperture)
290{
291 u_int8_t val;
292 u_int8_t key;
293
294 switch (aperture) {
295 case (512 * 1024 * 1024): key = 0; break;
296 case (256 * 1024 * 1024): key = 8; break;
297 case (128 * 1024 * 1024): key = 12; break;
298 case (64 * 1024 * 1024): key = 14; break;
299 case (32 * 1024 * 1024): key = 15; break;
300 default:
301 device_printf(dev, "Invalid aperture size (%dMb)\n",
302 aperture / 1024 / 1024);
303 return (EINVAL);
304 }
305 val = pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1);
306 pci_write_config(dev, AGP_NVIDIA_0_APSIZE, ((val & ~0x0f) | key), 1);
307
308 return (0);
309}
310
311static int
312agp_nvidia_bind_page(device_t dev, int offset, vm_offset_t physical)
313{
314 struct agp_nvidia_softc *sc = device_get_softc(dev);
315 u_int32_t index;
316
317 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
318 return (EINVAL);
319
320 index = (sc->pg_offset + offset) >> AGP_PAGE_SHIFT;
321 sc->gatt->ag_virtual[index] = physical;
322
323 return (0);
324}
325
326static int
327agp_nvidia_unbind_page(device_t dev, int offset)
328{
329 struct agp_nvidia_softc *sc = device_get_softc(dev);
330 u_int32_t index;
331
332 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
333 return (EINVAL);
334
335 index = (sc->pg_offset + offset) >> AGP_PAGE_SHIFT;
336 sc->gatt->ag_virtual[index] = 0;
337
338 return (0);
339}
340
341static int
342agp_nvidia_flush_tlb (device_t dev, int offset)
343{
344 struct agp_nvidia_softc *sc;
345 u_int32_t wbc_reg, temp;
346 int i;
347
348 sc = (struct agp_nvidia_softc *)device_get_softc(dev);
349
350 if (sc->wbc_mask) {
351 wbc_reg = pci_read_config(sc->mc1_dev, AGP_NVIDIA_1_WBC, 4);
352 wbc_reg |= sc->wbc_mask;
353 pci_write_config(sc->mc1_dev, AGP_NVIDIA_1_WBC, wbc_reg, 4);
354
355 /* Wait no more than 3 seconds. */
356 for (i = 0; i < 3000; i++) {
357 wbc_reg = pci_read_config(sc->mc1_dev,
358 AGP_NVIDIA_1_WBC, 4);
359 if ((sc->wbc_mask & wbc_reg) == 0)
360 break;
361 else
362 DELAY(1000);
363 }
364 if (i == 3000)
365 device_printf(dev,
366 "TLB flush took more than 3 seconds.\n");
367 }
368
369 /* Flush TLB entries. */
370 for(i = 0; i < 32 + 1; i++)
371 temp = sc->gatt->ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)];
372 for(i = 0; i < 32 + 1; i++)
373 temp = sc->gatt->ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)];
374
375 return (0);
376}
377
378#define SYSCFG 0xC0010010
379#define IORR_BASE0 0xC0010016
380#define IORR_MASK0 0xC0010017
381#define AMD_K7_NUM_IORR 2
382
383static int
384nvidia_init_iorr(u_int32_t addr, u_int32_t size)
385{
386 quad_t base, mask, sys;
387 u_int32_t iorr_addr, free_iorr_addr;
388
389 /* Find the iorr that is already used for the addr */
390 /* If not found, determine the uppermost available iorr */
391 free_iorr_addr = AMD_K7_NUM_IORR;
392 for(iorr_addr = 0; iorr_addr < AMD_K7_NUM_IORR; iorr_addr++) {
393 base = rdmsr(IORR_BASE0 + 2 * iorr_addr);
394 mask = rdmsr(IORR_MASK0 + 2 * iorr_addr);
395
396 if ((base & 0xfffff000ULL) == (addr & 0xfffff000))
397 break;
398
399 if ((mask & 0x00000800ULL) == 0)
400 free_iorr_addr = iorr_addr;
401 }
402
403 if (iorr_addr >= AMD_K7_NUM_IORR) {
404 iorr_addr = free_iorr_addr;
405 if (iorr_addr >= AMD_K7_NUM_IORR)
406 return (EINVAL);
407 }
408
409 base = (addr & ~0xfff) | 0x18;
410 mask = (0xfULL << 32) | ((~(size - 1)) & 0xfffff000) | 0x800;
411 wrmsr(IORR_BASE0 + 2 * iorr_addr, base);
412 wrmsr(IORR_MASK0 + 2 * iorr_addr, mask);
413
414 sys = rdmsr(SYSCFG);
415 sys |= 0x00100000ULL;
416 wrmsr(SYSCFG, sys);
417
418 return (0);
419}
420
421static device_method_t agp_nvidia_methods[] = {
422 /* Device interface */
423 DEVMETHOD(device_probe, agp_nvidia_probe),
424 DEVMETHOD(device_attach, agp_nvidia_attach),
425 DEVMETHOD(device_detach, agp_nvidia_detach),
426 DEVMETHOD(device_shutdown, bus_generic_shutdown),
427 DEVMETHOD(device_suspend, bus_generic_suspend),
428 DEVMETHOD(device_resume, bus_generic_resume),
429
430 /* AGP interface */
431 DEVMETHOD(agp_get_aperture, agp_nvidia_get_aperture),
432 DEVMETHOD(agp_set_aperture, agp_nvidia_set_aperture),
433 DEVMETHOD(agp_bind_page, agp_nvidia_bind_page),
434 DEVMETHOD(agp_unbind_page, agp_nvidia_unbind_page),
435 DEVMETHOD(agp_flush_tlb, agp_nvidia_flush_tlb),
436
437 DEVMETHOD(agp_enable, agp_generic_enable),
438 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory),
439 DEVMETHOD(agp_free_memory, agp_generic_free_memory),
440 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory),
441 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory),
442
443 { 0, 0 }
444};
445
446static driver_t agp_nvidia_driver = {
447 "agp",
448 agp_nvidia_methods,
449 sizeof(struct agp_nvidia_softc),
450};
451
452static devclass_t agp_devclass;
453
454DRIVER_MODULE(agp_nvidia, pci, agp_nvidia_driver, agp_devclass, 0, 0);
455MODULE_DEPEND(agp_nvidia, agp, 1, 1, 1);
456MODULE_DEPEND(agp_nvidia, pci, 1, 1, 1);
113}
114
115static int
116agp_nvidia_probe (device_t dev)
117{
118 const char *desc;
119
120 if (resource_disabled("agp", device_get_unit(dev)))
121 return (ENXIO);
122 desc = agp_nvidia_match(dev);
123 if (desc) {
124 device_verbose(dev);
125 device_set_desc(dev, desc);
126 return (BUS_PROBE_DEFAULT);
127 }
128 return (ENXIO);
129}
130
131static int
132agp_nvidia_attach (device_t dev)
133{
134 struct agp_nvidia_softc *sc = device_get_softc(dev);
135 struct agp_gatt *gatt;
136 u_int32_t apbase;
137 u_int32_t aplimit;
138 u_int32_t temp;
139 int size;
140 int i;
141 int error;
142
143 switch (pci_get_device(dev)) {
144 case NVIDIA_DEVICEID_NFORCE:
145 sc->wbc_mask = 0x00010000;
146 break;
147 case NVIDIA_DEVICEID_NFORCE2:
148 sc->wbc_mask = 0x80000000;
149 break;
150 default:
151 sc->wbc_mask = 0;
152 break;
153 }
154
155 /* AGP Controller */
156 sc->dev = dev;
157
158 /* Memory Controller 1 */
159 sc->mc1_dev = pci_find_bsf(pci_get_bus(dev), 0, 1);
160 if (sc->mc1_dev == NULL) {
161 device_printf(dev,
162 "Unable to find NVIDIA Memory Controller 1.\n");
163 return (ENODEV);
164 }
165
166 /* Memory Controller 2 */
167 sc->mc2_dev = pci_find_bsf(pci_get_bus(dev), 0, 2);
168 if (sc->mc2_dev == NULL) {
169 device_printf(dev,
170 "Unable to find NVIDIA Memory Controller 2.\n");
171 return (ENODEV);
172 }
173
174 /* AGP Host to PCI Bridge */
175 sc->bdev = pci_find_bsf(pci_get_bus(dev), 30, 0);
176 if (sc->bdev == NULL) {
177 device_printf(dev,
178 "Unable to find NVIDIA AGP Host to PCI Bridge.\n");
179 return (ENODEV);
180 }
181
182 error = agp_generic_attach(dev);
183 if (error)
184 return (error);
185
186 sc->initial_aperture = AGP_GET_APERTURE(dev);
187
188 for (;;) {
189 gatt = agp_alloc_gatt(dev);
190 if (gatt)
191 break;
192 /*
193 * Probably contigmalloc failure. Try reducing the
194 * aperture so that the gatt size reduces.
195 */
196 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2))
197 goto fail;
198 }
199 sc->gatt = gatt;
200
201 apbase = rman_get_start(sc->agp.as_aperture);
202 aplimit = apbase + AGP_GET_APERTURE(dev) - 1;
203 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_APBASE, apbase, 4);
204 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_APLIMIT, aplimit, 4);
205 pci_write_config(sc->bdev, AGP_NVIDIA_3_APBASE, apbase, 4);
206 pci_write_config(sc->bdev, AGP_NVIDIA_3_APLIMIT, aplimit, 4);
207
208 error = nvidia_init_iorr(apbase, AGP_GET_APERTURE(dev));
209 if (error) {
210 device_printf(dev, "Failed to setup IORRs\n");
211 goto fail;
212 }
213
214 /* directory size is 64k */
215 size = AGP_GET_APERTURE(dev) / 1024 / 1024;
216 sc->num_dirs = size / 64;
217 sc->num_active_entries = (size == 32) ? 16384 : ((size * 1024) / 4);
218 sc->pg_offset = 0;
219 if (sc->num_dirs == 0) {
220 sc->num_dirs = 1;
221 sc->num_active_entries /= (64 / size);
222 sc->pg_offset = (apbase & (64 * 1024 * 1024 - 1) &
223 ~(AGP_GET_APERTURE(dev) - 1)) / PAGE_SIZE;
224 }
225
226 /* (G)ATT Base Address */
227 for (i = 0; i < 8; i++) {
228 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_ATTBASE(i),
229 (sc->gatt->ag_physical +
230 (i % sc->num_dirs) * 64 * 1024),
231 4);
232 }
233
234 /* GTLB Control */
235 temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4);
236 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, temp | 0x11, 4);
237
238 /* GART Control */
239 temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4);
240 pci_write_config(sc->dev, AGP_NVIDIA_0_APSIZE, temp | 0x100, 4);
241
242 return (0);
243fail:
244 agp_generic_detach(dev);
245 return (ENOMEM);
246}
247
248static int
249agp_nvidia_detach (device_t dev)
250{
251 struct agp_nvidia_softc *sc = device_get_softc(dev);
252 int error;
253 u_int32_t temp;
254
255 error = agp_generic_detach(dev);
256 if (error)
257 return (error);
258
259 /* GART Control */
260 temp = pci_read_config(sc->dev, AGP_NVIDIA_0_APSIZE, 4);
261 pci_write_config(sc->dev, AGP_NVIDIA_0_APSIZE, temp & ~(0x100), 4);
262
263 /* GTLB Control */
264 temp = pci_read_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, 4);
265 pci_write_config(sc->mc2_dev, AGP_NVIDIA_2_GARTCTRL, temp & ~(0x11), 4);
266
267 /* Put the aperture back the way it started. */
268 AGP_SET_APERTURE(dev, sc->initial_aperture);
269
270 /* restore iorr for previous aperture size */
271 nvidia_init_iorr(rman_get_start(sc->agp.as_aperture),
272 sc->initial_aperture);
273
274 agp_free_gatt(sc->gatt);
275
276 return (0);
277}
278
279static u_int32_t
280agp_nvidia_get_aperture(device_t dev)
281{
282 u_int8_t key;
283
284 key = ffs(pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1) & 0x0f);
285 return (1 << (24 + (key ? key : 5)));
286}
287
288static int
289agp_nvidia_set_aperture(device_t dev, u_int32_t aperture)
290{
291 u_int8_t val;
292 u_int8_t key;
293
294 switch (aperture) {
295 case (512 * 1024 * 1024): key = 0; break;
296 case (256 * 1024 * 1024): key = 8; break;
297 case (128 * 1024 * 1024): key = 12; break;
298 case (64 * 1024 * 1024): key = 14; break;
299 case (32 * 1024 * 1024): key = 15; break;
300 default:
301 device_printf(dev, "Invalid aperture size (%dMb)\n",
302 aperture / 1024 / 1024);
303 return (EINVAL);
304 }
305 val = pci_read_config(dev, AGP_NVIDIA_0_APSIZE, 1);
306 pci_write_config(dev, AGP_NVIDIA_0_APSIZE, ((val & ~0x0f) | key), 1);
307
308 return (0);
309}
310
311static int
312agp_nvidia_bind_page(device_t dev, int offset, vm_offset_t physical)
313{
314 struct agp_nvidia_softc *sc = device_get_softc(dev);
315 u_int32_t index;
316
317 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
318 return (EINVAL);
319
320 index = (sc->pg_offset + offset) >> AGP_PAGE_SHIFT;
321 sc->gatt->ag_virtual[index] = physical;
322
323 return (0);
324}
325
326static int
327agp_nvidia_unbind_page(device_t dev, int offset)
328{
329 struct agp_nvidia_softc *sc = device_get_softc(dev);
330 u_int32_t index;
331
332 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
333 return (EINVAL);
334
335 index = (sc->pg_offset + offset) >> AGP_PAGE_SHIFT;
336 sc->gatt->ag_virtual[index] = 0;
337
338 return (0);
339}
340
341static int
342agp_nvidia_flush_tlb (device_t dev, int offset)
343{
344 struct agp_nvidia_softc *sc;
345 u_int32_t wbc_reg, temp;
346 int i;
347
348 sc = (struct agp_nvidia_softc *)device_get_softc(dev);
349
350 if (sc->wbc_mask) {
351 wbc_reg = pci_read_config(sc->mc1_dev, AGP_NVIDIA_1_WBC, 4);
352 wbc_reg |= sc->wbc_mask;
353 pci_write_config(sc->mc1_dev, AGP_NVIDIA_1_WBC, wbc_reg, 4);
354
355 /* Wait no more than 3 seconds. */
356 for (i = 0; i < 3000; i++) {
357 wbc_reg = pci_read_config(sc->mc1_dev,
358 AGP_NVIDIA_1_WBC, 4);
359 if ((sc->wbc_mask & wbc_reg) == 0)
360 break;
361 else
362 DELAY(1000);
363 }
364 if (i == 3000)
365 device_printf(dev,
366 "TLB flush took more than 3 seconds.\n");
367 }
368
369 /* Flush TLB entries. */
370 for(i = 0; i < 32 + 1; i++)
371 temp = sc->gatt->ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)];
372 for(i = 0; i < 32 + 1; i++)
373 temp = sc->gatt->ag_virtual[i * PAGE_SIZE / sizeof(u_int32_t)];
374
375 return (0);
376}
377
378#define SYSCFG 0xC0010010
379#define IORR_BASE0 0xC0010016
380#define IORR_MASK0 0xC0010017
381#define AMD_K7_NUM_IORR 2
382
383static int
384nvidia_init_iorr(u_int32_t addr, u_int32_t size)
385{
386 quad_t base, mask, sys;
387 u_int32_t iorr_addr, free_iorr_addr;
388
389 /* Find the iorr that is already used for the addr */
390 /* If not found, determine the uppermost available iorr */
391 free_iorr_addr = AMD_K7_NUM_IORR;
392 for(iorr_addr = 0; iorr_addr < AMD_K7_NUM_IORR; iorr_addr++) {
393 base = rdmsr(IORR_BASE0 + 2 * iorr_addr);
394 mask = rdmsr(IORR_MASK0 + 2 * iorr_addr);
395
396 if ((base & 0xfffff000ULL) == (addr & 0xfffff000))
397 break;
398
399 if ((mask & 0x00000800ULL) == 0)
400 free_iorr_addr = iorr_addr;
401 }
402
403 if (iorr_addr >= AMD_K7_NUM_IORR) {
404 iorr_addr = free_iorr_addr;
405 if (iorr_addr >= AMD_K7_NUM_IORR)
406 return (EINVAL);
407 }
408
409 base = (addr & ~0xfff) | 0x18;
410 mask = (0xfULL << 32) | ((~(size - 1)) & 0xfffff000) | 0x800;
411 wrmsr(IORR_BASE0 + 2 * iorr_addr, base);
412 wrmsr(IORR_MASK0 + 2 * iorr_addr, mask);
413
414 sys = rdmsr(SYSCFG);
415 sys |= 0x00100000ULL;
416 wrmsr(SYSCFG, sys);
417
418 return (0);
419}
420
421static device_method_t agp_nvidia_methods[] = {
422 /* Device interface */
423 DEVMETHOD(device_probe, agp_nvidia_probe),
424 DEVMETHOD(device_attach, agp_nvidia_attach),
425 DEVMETHOD(device_detach, agp_nvidia_detach),
426 DEVMETHOD(device_shutdown, bus_generic_shutdown),
427 DEVMETHOD(device_suspend, bus_generic_suspend),
428 DEVMETHOD(device_resume, bus_generic_resume),
429
430 /* AGP interface */
431 DEVMETHOD(agp_get_aperture, agp_nvidia_get_aperture),
432 DEVMETHOD(agp_set_aperture, agp_nvidia_set_aperture),
433 DEVMETHOD(agp_bind_page, agp_nvidia_bind_page),
434 DEVMETHOD(agp_unbind_page, agp_nvidia_unbind_page),
435 DEVMETHOD(agp_flush_tlb, agp_nvidia_flush_tlb),
436
437 DEVMETHOD(agp_enable, agp_generic_enable),
438 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory),
439 DEVMETHOD(agp_free_memory, agp_generic_free_memory),
440 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory),
441 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory),
442
443 { 0, 0 }
444};
445
446static driver_t agp_nvidia_driver = {
447 "agp",
448 agp_nvidia_methods,
449 sizeof(struct agp_nvidia_softc),
450};
451
452static devclass_t agp_devclass;
453
454DRIVER_MODULE(agp_nvidia, pci, agp_nvidia_driver, agp_devclass, 0, 0);
455MODULE_DEPEND(agp_nvidia, agp, 1, 1, 1);
456MODULE_DEPEND(agp_nvidia, pci, 1, 1, 1);