120 desc = agp_intel_match(dev); 121 if (desc) { 122 device_set_desc(dev, desc); 123 return (BUS_PROBE_DEFAULT); 124 } 125 126 return (ENXIO); 127} 128 129static void 130agp_intel_commit_gatt(device_t dev) 131{ 132 struct agp_intel_softc *sc; 133 u_int32_t type; 134 u_int32_t value; 135 136 sc = device_get_softc(dev); 137 type = pci_get_devid(dev); 138 139 /* Install the gatt. */ 140 pci_write_config(dev, AGP_INTEL_ATTBASE, sc->gatt->ag_physical, 4); 141 142 /* Enable the GLTB and setup the control register. */ 143 switch (type) { 144 case 0x71908086: /* 440LX/EX */ 145 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2080, 4); 146 break; 147 case 0x71808086: /* 440BX */ 148 /* 149 * XXX: Should be 0xa080? Bit 9 is undefined, and 150 * bit 13 being on and bit 15 being clear is illegal. 151 */ 152 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4); 153 break; 154 default: 155 value = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4); 156 pci_write_config(dev, AGP_INTEL_AGPCTRL, value | 0x80, 4); 157 } 158 159 /* Enable aperture accesses. */ 160 switch (type) { 161 case 0x25008086: /* i820 */ 162 case 0x25018086: /* i820 */ 163 pci_write_config(dev, AGP_INTEL_I820_RDCR, 164 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) 165 | (1 << 1)), 1); 166 break; 167 case 0x1a308086: /* i845 */ 168 case 0x25608086: /* i845G */ 169 case 0x33408086: /* i855 */ 170 case 0x35808086: /* i855GM */ 171 case 0x25708086: /* i865 */ 172 case 0x25788086: /* i875P */ 173 pci_write_config(dev, AGP_INTEL_I845_AGPM, 174 (pci_read_config(dev, AGP_INTEL_I845_AGPM, 1) 175 | (1 << 1)), 1); 176 break; 177 case 0x1a218086: /* i840 */ 178 case 0x25308086: /* i850 */ 179 case 0x25318086: /* i860 */ 180 case 0x255d8086: /* E7205 */ 181 case 0x25508086: /* E7505 */ 182 pci_write_config(dev, AGP_INTEL_MCHCFG, 183 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2) 184 | (1 << 9)), 2); 185 break; 186 default: /* Intel Generic (maybe) */ 187 pci_write_config(dev, AGP_INTEL_NBXCFG, 188 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4) 189 & ~(1 << 10)) | (1 << 9), 4); 190 } 191 192 /* Clear errors. */ 193 switch (type) { 194 case 0x1a218086: /* i840 */ 195 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0xc000, 2); 196 break; 197 case 0x25008086: /* i820 */ 198 case 0x25018086: /* i820 */ 199 case 0x1a308086: /* i845 */ 200 case 0x25608086: /* i845G */ 201 case 0x25308086: /* i850 */ 202 case 0x33408086: /* i855 */ 203 case 0x25318086: /* i860 */ 204 case 0x25708086: /* i865 */ 205 case 0x25788086: /* i875P */ 206 case 0x255d8086: /* E7205 */ 207 case 0x25508086: /* E7505 */ 208 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0x00ff, 2); 209 break; 210 default: /* Intel Generic (maybe) */ 211 pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1); 212 } 213} 214 215static int 216agp_intel_attach(device_t dev) 217{ 218 struct agp_intel_softc *sc; 219 struct agp_gatt *gatt; 220 u_int32_t value; 221 int error; 222 223 sc = device_get_softc(dev); 224 225 error = agp_generic_attach(dev); 226 if (error) 227 return (error); 228 229 /* Determine maximum supported aperture size. */ 230 value = pci_read_config(dev, AGP_INTEL_APSIZE, 1); 231 pci_write_config(dev, AGP_INTEL_APSIZE, MAX_APSIZE, 1); 232 sc->aperture_mask = pci_read_config(dev, AGP_INTEL_APSIZE, 1) & 233 MAX_APSIZE; 234 pci_write_config(dev, AGP_INTEL_APSIZE, value, 1); 235 sc->current_aperture = sc->initial_aperture = AGP_GET_APERTURE(dev); 236 237 for (;;) { 238 gatt = agp_alloc_gatt(dev); 239 if (gatt) 240 break; 241 242 /* 243 * Probably contigmalloc failure. Try reducing the 244 * aperture so that the gatt size reduces. 245 */ 246 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) { 247 agp_generic_detach(dev); 248 return (ENOMEM); 249 } 250 } 251 sc->gatt = gatt; 252 253 agp_intel_commit_gatt(dev); 254 255 return (0); 256} 257 258static int 259agp_intel_detach(device_t dev) 260{ 261 struct agp_intel_softc *sc; 262 u_int32_t reg; 263 264 sc = device_get_softc(dev); 265 266 agp_free_cdev(dev); 267 268 /* Disable aperture accesses. */ 269 switch (pci_get_devid(dev)) { 270 case 0x25008086: /* i820 */ 271 case 0x25018086: /* i820 */ 272 reg = pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) & ~(1 << 1); 273 printf("%s: set RDCR to %02x\n", __func__, reg & 0xff); 274 pci_write_config(dev, AGP_INTEL_I820_RDCR, reg, 1); 275 break; 276 case 0x1a308086: /* i845 */ 277 case 0x25608086: /* i845G */ 278 case 0x33408086: /* i855 */ 279 case 0x35808086: /* i855GM */ 280 case 0x25708086: /* i865 */ 281 case 0x25788086: /* i875P */ 282 reg = pci_read_config(dev, AGP_INTEL_I845_AGPM, 1) & ~(1 << 1); 283 printf("%s: set AGPM to %02x\n", __func__, reg & 0xff); 284 pci_write_config(dev, AGP_INTEL_I845_AGPM, reg, 1); 285 break; 286 case 0x1a218086: /* i840 */ 287 case 0x25308086: /* i850 */ 288 case 0x25318086: /* i860 */ 289 case 0x255d8086: /* E7205 */ 290 case 0x25508086: /* E7505 */ 291 reg = pci_read_config(dev, AGP_INTEL_MCHCFG, 2) & ~(1 << 9); 292 printf("%s: set MCHCFG to %x04\n", __func__, reg & 0xffff); 293 pci_write_config(dev, AGP_INTEL_MCHCFG, reg, 2); 294 break; 295 default: /* Intel Generic (maybe) */ 296 reg = pci_read_config(dev, AGP_INTEL_NBXCFG, 4) & ~(1 << 9); 297 printf("%s: set NBXCFG to %08x\n", __func__, reg); 298 pci_write_config(dev, AGP_INTEL_NBXCFG, reg, 4); 299 } 300 pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4); 301 AGP_SET_APERTURE(dev, sc->initial_aperture); 302 agp_free_gatt(sc->gatt); 303 agp_free_res(dev); 304 305 return (0); 306} 307 308static int 309agp_intel_resume(device_t dev) 310{ 311 struct agp_intel_softc *sc; 312 sc = device_get_softc(dev); 313 314 AGP_SET_APERTURE(dev, sc->current_aperture); 315 agp_intel_commit_gatt(dev); 316 return (bus_generic_resume(dev)); 317} 318 319static u_int32_t 320agp_intel_get_aperture(device_t dev) 321{ 322 struct agp_intel_softc *sc; 323 u_int32_t apsize; 324 325 sc = device_get_softc(dev); 326 327 apsize = pci_read_config(dev, AGP_INTEL_APSIZE, 1) & sc->aperture_mask; 328 329 /* 330 * The size is determined by the number of low bits of 331 * register APBASE which are forced to zero. The low 22 bits 332 * are always forced to zero and each zero bit in the apsize 333 * field just read forces the corresponding bit in the 27:22 334 * to be zero. We calculate the aperture size accordingly. 335 */ 336 return ((((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1); 337} 338 339static int 340agp_intel_set_aperture(device_t dev, u_int32_t aperture) 341{ 342 struct agp_intel_softc *sc; 343 u_int32_t apsize; 344 345 sc = device_get_softc(dev); 346 347 /* 348 * Reverse the magic from get_aperture. 349 */ 350 apsize = ((aperture - 1) >> 22) ^ sc->aperture_mask; 351 352 /* 353 * Double check for sanity. 354 */ 355 if ((((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1 != aperture) 356 return (EINVAL); 357 358 sc->current_aperture = apsize; 359 360 pci_write_config(dev, AGP_INTEL_APSIZE, apsize, 1); 361 362 return (0); 363} 364 365static int 366agp_intel_bind_page(device_t dev, vm_offset_t offset, vm_offset_t physical) 367{ 368 struct agp_intel_softc *sc; 369 370 sc = device_get_softc(dev); 371 372 if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 373 return (EINVAL); 374 375 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 0x17; 376 return (0); 377} 378 379static int 380agp_intel_unbind_page(device_t dev, vm_offset_t offset) 381{ 382 struct agp_intel_softc *sc; 383 384 sc = device_get_softc(dev); 385 386 if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 387 return (EINVAL); 388 389 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0; 390 return (0); 391} 392 393static void 394agp_intel_flush_tlb(device_t dev) 395{ 396 u_int32_t val; 397 398 val = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4); 399 pci_write_config(dev, AGP_INTEL_AGPCTRL, val & ~(1 << 7), 4); 400 pci_write_config(dev, AGP_INTEL_AGPCTRL, val, 4); 401} 402 403static device_method_t agp_intel_methods[] = { 404 /* Device interface */ 405 DEVMETHOD(device_probe, agp_intel_probe), 406 DEVMETHOD(device_attach, agp_intel_attach), 407 DEVMETHOD(device_detach, agp_intel_detach), 408 DEVMETHOD(device_shutdown, bus_generic_shutdown), 409 DEVMETHOD(device_suspend, bus_generic_suspend), 410 DEVMETHOD(device_resume, agp_intel_resume), 411 412 /* AGP interface */ 413 DEVMETHOD(agp_get_aperture, agp_intel_get_aperture), 414 DEVMETHOD(agp_set_aperture, agp_intel_set_aperture), 415 DEVMETHOD(agp_bind_page, agp_intel_bind_page), 416 DEVMETHOD(agp_unbind_page, agp_intel_unbind_page), 417 DEVMETHOD(agp_flush_tlb, agp_intel_flush_tlb), 418 DEVMETHOD(agp_enable, agp_generic_enable), 419 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory), 420 DEVMETHOD(agp_free_memory, agp_generic_free_memory), 421 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory), 422 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory), 423 424 { 0, 0 } 425}; 426 427static driver_t agp_intel_driver = { 428 "agp", 429 agp_intel_methods, 430 sizeof(struct agp_intel_softc), 431}; 432 433static devclass_t agp_devclass; 434 435DRIVER_MODULE(agp_intel, hostb, agp_intel_driver, agp_devclass, 0, 0); 436MODULE_DEPEND(agp_intel, agp, 1, 1, 1); 437MODULE_DEPEND(agp_intel, pci, 1, 1, 1);
| 122 desc = agp_intel_match(dev); 123 if (desc) { 124 device_set_desc(dev, desc); 125 return (BUS_PROBE_DEFAULT); 126 } 127 128 return (ENXIO); 129} 130 131static void 132agp_intel_commit_gatt(device_t dev) 133{ 134 struct agp_intel_softc *sc; 135 u_int32_t type; 136 u_int32_t value; 137 138 sc = device_get_softc(dev); 139 type = pci_get_devid(dev); 140 141 /* Install the gatt. */ 142 pci_write_config(dev, AGP_INTEL_ATTBASE, sc->gatt->ag_physical, 4); 143 144 /* Enable the GLTB and setup the control register. */ 145 switch (type) { 146 case 0x71908086: /* 440LX/EX */ 147 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2080, 4); 148 break; 149 case 0x71808086: /* 440BX */ 150 /* 151 * XXX: Should be 0xa080? Bit 9 is undefined, and 152 * bit 13 being on and bit 15 being clear is illegal. 153 */ 154 pci_write_config(dev, AGP_INTEL_AGPCTRL, 0x2280, 4); 155 break; 156 default: 157 value = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4); 158 pci_write_config(dev, AGP_INTEL_AGPCTRL, value | 0x80, 4); 159 } 160 161 /* Enable aperture accesses. */ 162 switch (type) { 163 case 0x25008086: /* i820 */ 164 case 0x25018086: /* i820 */ 165 pci_write_config(dev, AGP_INTEL_I820_RDCR, 166 (pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) 167 | (1 << 1)), 1); 168 break; 169 case 0x1a308086: /* i845 */ 170 case 0x25608086: /* i845G */ 171 case 0x33408086: /* i855 */ 172 case 0x35808086: /* i855GM */ 173 case 0x25708086: /* i865 */ 174 case 0x25788086: /* i875P */ 175 pci_write_config(dev, AGP_INTEL_I845_AGPM, 176 (pci_read_config(dev, AGP_INTEL_I845_AGPM, 1) 177 | (1 << 1)), 1); 178 break; 179 case 0x1a218086: /* i840 */ 180 case 0x25308086: /* i850 */ 181 case 0x25318086: /* i860 */ 182 case 0x255d8086: /* E7205 */ 183 case 0x25508086: /* E7505 */ 184 pci_write_config(dev, AGP_INTEL_MCHCFG, 185 (pci_read_config(dev, AGP_INTEL_MCHCFG, 2) 186 | (1 << 9)), 2); 187 break; 188 default: /* Intel Generic (maybe) */ 189 pci_write_config(dev, AGP_INTEL_NBXCFG, 190 (pci_read_config(dev, AGP_INTEL_NBXCFG, 4) 191 & ~(1 << 10)) | (1 << 9), 4); 192 } 193 194 /* Clear errors. */ 195 switch (type) { 196 case 0x1a218086: /* i840 */ 197 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0xc000, 2); 198 break; 199 case 0x25008086: /* i820 */ 200 case 0x25018086: /* i820 */ 201 case 0x1a308086: /* i845 */ 202 case 0x25608086: /* i845G */ 203 case 0x25308086: /* i850 */ 204 case 0x33408086: /* i855 */ 205 case 0x25318086: /* i860 */ 206 case 0x25708086: /* i865 */ 207 case 0x25788086: /* i875P */ 208 case 0x255d8086: /* E7205 */ 209 case 0x25508086: /* E7505 */ 210 pci_write_config(dev, AGP_INTEL_I8XX_ERRSTS, 0x00ff, 2); 211 break; 212 default: /* Intel Generic (maybe) */ 213 pci_write_config(dev, AGP_INTEL_ERRSTS + 1, 7, 1); 214 } 215} 216 217static int 218agp_intel_attach(device_t dev) 219{ 220 struct agp_intel_softc *sc; 221 struct agp_gatt *gatt; 222 u_int32_t value; 223 int error; 224 225 sc = device_get_softc(dev); 226 227 error = agp_generic_attach(dev); 228 if (error) 229 return (error); 230 231 /* Determine maximum supported aperture size. */ 232 value = pci_read_config(dev, AGP_INTEL_APSIZE, 1); 233 pci_write_config(dev, AGP_INTEL_APSIZE, MAX_APSIZE, 1); 234 sc->aperture_mask = pci_read_config(dev, AGP_INTEL_APSIZE, 1) & 235 MAX_APSIZE; 236 pci_write_config(dev, AGP_INTEL_APSIZE, value, 1); 237 sc->current_aperture = sc->initial_aperture = AGP_GET_APERTURE(dev); 238 239 for (;;) { 240 gatt = agp_alloc_gatt(dev); 241 if (gatt) 242 break; 243 244 /* 245 * Probably contigmalloc failure. Try reducing the 246 * aperture so that the gatt size reduces. 247 */ 248 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) { 249 agp_generic_detach(dev); 250 return (ENOMEM); 251 } 252 } 253 sc->gatt = gatt; 254 255 agp_intel_commit_gatt(dev); 256 257 return (0); 258} 259 260static int 261agp_intel_detach(device_t dev) 262{ 263 struct agp_intel_softc *sc; 264 u_int32_t reg; 265 266 sc = device_get_softc(dev); 267 268 agp_free_cdev(dev); 269 270 /* Disable aperture accesses. */ 271 switch (pci_get_devid(dev)) { 272 case 0x25008086: /* i820 */ 273 case 0x25018086: /* i820 */ 274 reg = pci_read_config(dev, AGP_INTEL_I820_RDCR, 1) & ~(1 << 1); 275 printf("%s: set RDCR to %02x\n", __func__, reg & 0xff); 276 pci_write_config(dev, AGP_INTEL_I820_RDCR, reg, 1); 277 break; 278 case 0x1a308086: /* i845 */ 279 case 0x25608086: /* i845G */ 280 case 0x33408086: /* i855 */ 281 case 0x35808086: /* i855GM */ 282 case 0x25708086: /* i865 */ 283 case 0x25788086: /* i875P */ 284 reg = pci_read_config(dev, AGP_INTEL_I845_AGPM, 1) & ~(1 << 1); 285 printf("%s: set AGPM to %02x\n", __func__, reg & 0xff); 286 pci_write_config(dev, AGP_INTEL_I845_AGPM, reg, 1); 287 break; 288 case 0x1a218086: /* i840 */ 289 case 0x25308086: /* i850 */ 290 case 0x25318086: /* i860 */ 291 case 0x255d8086: /* E7205 */ 292 case 0x25508086: /* E7505 */ 293 reg = pci_read_config(dev, AGP_INTEL_MCHCFG, 2) & ~(1 << 9); 294 printf("%s: set MCHCFG to %x04\n", __func__, reg & 0xffff); 295 pci_write_config(dev, AGP_INTEL_MCHCFG, reg, 2); 296 break; 297 default: /* Intel Generic (maybe) */ 298 reg = pci_read_config(dev, AGP_INTEL_NBXCFG, 4) & ~(1 << 9); 299 printf("%s: set NBXCFG to %08x\n", __func__, reg); 300 pci_write_config(dev, AGP_INTEL_NBXCFG, reg, 4); 301 } 302 pci_write_config(dev, AGP_INTEL_ATTBASE, 0, 4); 303 AGP_SET_APERTURE(dev, sc->initial_aperture); 304 agp_free_gatt(sc->gatt); 305 agp_free_res(dev); 306 307 return (0); 308} 309 310static int 311agp_intel_resume(device_t dev) 312{ 313 struct agp_intel_softc *sc; 314 sc = device_get_softc(dev); 315 316 AGP_SET_APERTURE(dev, sc->current_aperture); 317 agp_intel_commit_gatt(dev); 318 return (bus_generic_resume(dev)); 319} 320 321static u_int32_t 322agp_intel_get_aperture(device_t dev) 323{ 324 struct agp_intel_softc *sc; 325 u_int32_t apsize; 326 327 sc = device_get_softc(dev); 328 329 apsize = pci_read_config(dev, AGP_INTEL_APSIZE, 1) & sc->aperture_mask; 330 331 /* 332 * The size is determined by the number of low bits of 333 * register APBASE which are forced to zero. The low 22 bits 334 * are always forced to zero and each zero bit in the apsize 335 * field just read forces the corresponding bit in the 27:22 336 * to be zero. We calculate the aperture size accordingly. 337 */ 338 return ((((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1); 339} 340 341static int 342agp_intel_set_aperture(device_t dev, u_int32_t aperture) 343{ 344 struct agp_intel_softc *sc; 345 u_int32_t apsize; 346 347 sc = device_get_softc(dev); 348 349 /* 350 * Reverse the magic from get_aperture. 351 */ 352 apsize = ((aperture - 1) >> 22) ^ sc->aperture_mask; 353 354 /* 355 * Double check for sanity. 356 */ 357 if ((((apsize ^ sc->aperture_mask) << 22) | ((1 << 22) - 1)) + 1 != aperture) 358 return (EINVAL); 359 360 sc->current_aperture = apsize; 361 362 pci_write_config(dev, AGP_INTEL_APSIZE, apsize, 1); 363 364 return (0); 365} 366 367static int 368agp_intel_bind_page(device_t dev, vm_offset_t offset, vm_offset_t physical) 369{ 370 struct agp_intel_softc *sc; 371 372 sc = device_get_softc(dev); 373 374 if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 375 return (EINVAL); 376 377 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical | 0x17; 378 return (0); 379} 380 381static int 382agp_intel_unbind_page(device_t dev, vm_offset_t offset) 383{ 384 struct agp_intel_softc *sc; 385 386 sc = device_get_softc(dev); 387 388 if (offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) 389 return (EINVAL); 390 391 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0; 392 return (0); 393} 394 395static void 396agp_intel_flush_tlb(device_t dev) 397{ 398 u_int32_t val; 399 400 val = pci_read_config(dev, AGP_INTEL_AGPCTRL, 4); 401 pci_write_config(dev, AGP_INTEL_AGPCTRL, val & ~(1 << 7), 4); 402 pci_write_config(dev, AGP_INTEL_AGPCTRL, val, 4); 403} 404 405static device_method_t agp_intel_methods[] = { 406 /* Device interface */ 407 DEVMETHOD(device_probe, agp_intel_probe), 408 DEVMETHOD(device_attach, agp_intel_attach), 409 DEVMETHOD(device_detach, agp_intel_detach), 410 DEVMETHOD(device_shutdown, bus_generic_shutdown), 411 DEVMETHOD(device_suspend, bus_generic_suspend), 412 DEVMETHOD(device_resume, agp_intel_resume), 413 414 /* AGP interface */ 415 DEVMETHOD(agp_get_aperture, agp_intel_get_aperture), 416 DEVMETHOD(agp_set_aperture, agp_intel_set_aperture), 417 DEVMETHOD(agp_bind_page, agp_intel_bind_page), 418 DEVMETHOD(agp_unbind_page, agp_intel_unbind_page), 419 DEVMETHOD(agp_flush_tlb, agp_intel_flush_tlb), 420 DEVMETHOD(agp_enable, agp_generic_enable), 421 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory), 422 DEVMETHOD(agp_free_memory, agp_generic_free_memory), 423 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory), 424 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory), 425 426 { 0, 0 } 427}; 428 429static driver_t agp_intel_driver = { 430 "agp", 431 agp_intel_methods, 432 sizeof(struct agp_intel_softc), 433}; 434 435static devclass_t agp_devclass; 436 437DRIVER_MODULE(agp_intel, hostb, agp_intel_driver, agp_devclass, 0, 0); 438MODULE_DEPEND(agp_intel, agp, 1, 1, 1); 439MODULE_DEPEND(agp_intel, pci, 1, 1, 1);
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