35
36#include "opt_bus.h"
37
38#include <sys/param.h>
39#include <sys/systm.h>
40#include <sys/malloc.h>
41#include <sys/kernel.h>
42#include <sys/module.h>
43#include <sys/bus.h>
44#include <sys/lock.h>
45#include <sys/mutex.h>
46#include <sys/proc.h>
47
48#include <dev/agp/agppriv.h>
49#include <dev/agp/agpreg.h>
50#include <dev/pci/pcivar.h>
51#include <dev/pci/pcireg.h>
52
53#include <vm/vm.h>
54#include <vm/vm_object.h>
55#include <vm/vm_page.h>
56#include <vm/vm_pageout.h>
57#include <vm/pmap.h>
58
59#include <machine/bus.h>
60#include <machine/resource.h>
61#include <machine/md_var.h>
62#include <sys/rman.h>
63
64MALLOC_DECLARE(M_AGP);
65
66enum {
67 CHIP_I810, /* i810/i815 */
68 CHIP_I830, /* 830M/845G */
69 CHIP_I855, /* 852GM/855GM/865G */
70 CHIP_I915, /* 915G/915GM */
71 CHIP_I965, /* G965 */
72 CHIP_G33, /* G33/Q33/Q35 */
73 CHIP_G4X, /* G45/Q45 */
74};
75
76/* The i810 through i855 have the registers at BAR 1, and the GATT gets
77 * allocated by us. The i915 has registers in BAR 0 and the GATT is at the
78 * start of the stolen memory, and should only be accessed by the OS through
79 * BAR 3. The G965 has registers and GATT in the same BAR (0) -- first 512KB
80 * is registers, second 512KB is GATT.
81 */
82static struct resource_spec agp_i810_res_spec[] = {
83 { SYS_RES_MEMORY, AGP_I810_MMADR, RF_ACTIVE | RF_SHAREABLE },
84 { -1, 0 }
85};
86
87static struct resource_spec agp_i915_res_spec[] = {
88 { SYS_RES_MEMORY, AGP_I915_MMADR, RF_ACTIVE | RF_SHAREABLE },
89 { SYS_RES_MEMORY, AGP_I915_GTTADR, RF_ACTIVE | RF_SHAREABLE },
90 { -1, 0 }
91};
92
93static struct resource_spec agp_i965_res_spec[] = {
94 { SYS_RES_MEMORY, AGP_I965_GTTMMADR, RF_ACTIVE | RF_SHAREABLE },
95 { -1, 0 }
96};
97
98struct agp_i810_softc {
99 struct agp_softc agp;
100 u_int32_t initial_aperture; /* aperture size at startup */
101 struct agp_gatt *gatt;
102 int chiptype; /* i810-like or i830 */
103 u_int32_t dcache_size; /* i810 only */
104 u_int32_t stolen; /* number of i830/845 gtt entries for stolen memory */
105 device_t bdev; /* bridge device */
106
107 void *argb_cursor; /* contigmalloc area for ARGB cursor */
108
109 struct resource_spec * sc_res_spec;
110 struct resource *sc_res[2];
111};
112
113/* For adding new devices, devid is the id of the graphics controller
114 * (pci:0:2:0, for example). The placeholder (usually at pci:0:2:1) for the
115 * second head should never be added. The bridge_offset is the offset to
116 * subtract from devid to get the id of the hostb that the device is on.
117 */
118static const struct agp_i810_match {
119 int devid;
120 int chiptype;
121 int bridge_offset;
122 char *name;
123} agp_i810_matches[] = {
124 {0x71218086, CHIP_I810, 0x00010000,
125 "Intel 82810 (i810 GMCH) SVGA controller"},
126 {0x71238086, CHIP_I810, 0x00010000,
127 "Intel 82810-DC100 (i810-DC100 GMCH) SVGA controller"},
128 {0x71258086, CHIP_I810, 0x00010000,
129 "Intel 82810E (i810E GMCH) SVGA controller"},
130 {0x11328086, CHIP_I810, 0x00020000,
131 "Intel 82815 (i815 GMCH) SVGA controller"},
132 {0x35778086, CHIP_I830, 0x00020000,
133 "Intel 82830M (830M GMCH) SVGA controller"},
134 {0x25628086, CHIP_I830, 0x00020000,
135 "Intel 82845M (845M GMCH) SVGA controller"},
136 {0x35828086, CHIP_I855, 0x00020000,
137 "Intel 82852/855GM SVGA controller"},
138 {0x25728086, CHIP_I855, 0x00020000,
139 "Intel 82865G (865G GMCH) SVGA controller"},
140 {0x25828086, CHIP_I915, 0x00020000,
141 "Intel 82915G (915G GMCH) SVGA controller"},
142 {0x258A8086, CHIP_I915, 0x00020000,
143 "Intel E7221 SVGA controller"},
144 {0x25928086, CHIP_I915, 0x00020000,
145 "Intel 82915GM (915GM GMCH) SVGA controller"},
146 {0x27728086, CHIP_I915, 0x00020000,
147 "Intel 82945G (945G GMCH) SVGA controller"},
148 {0x27A28086, CHIP_I915, 0x00020000,
149 "Intel 82945GM (945GM GMCH) SVGA controller"},
150 {0x27AE8086, CHIP_I915, 0x00020000,
151 "Intel 945GME SVGA controller"},
152 {0x29728086, CHIP_I965, 0x00020000,
153 "Intel 946GZ SVGA controller"},
154 {0x29828086, CHIP_I965, 0x00020000,
155 "Intel G965 SVGA controller"},
156 {0x29928086, CHIP_I965, 0x00020000,
157 "Intel Q965 SVGA controller"},
158 {0x29A28086, CHIP_I965, 0x00020000,
159 "Intel G965 SVGA controller"},
160 {0x29B28086, CHIP_G33, 0x00020000,
161 "Intel Q35 SVGA controller"},
162 {0x29C28086, CHIP_G33, 0x00020000,
163 "Intel G33 SVGA controller"},
164 {0x29D28086, CHIP_G33, 0x00020000,
165 "Intel Q33 SVGA controller"},
166 {0x2A028086, CHIP_I965, 0x00020000,
167 "Intel GM965 SVGA controller"},
168 {0x2A128086, CHIP_I965, 0x00020000,
169 "Intel GME965 SVGA controller"},
170 {0x2A428086, CHIP_G4X, 0x00020000,
171 "Intel GM45 SVGA controller"},
172 {0x2E028086, CHIP_G4X, 0x00020000,
173 "Intel 4 Series SVGA controller"},
174 {0x2E128086, CHIP_G4X, 0x00020000,
175 "Intel Q45 SVGA controller"},
176 {0x2E228086, CHIP_G4X, 0x00020000,
177 "Intel G45 SVGA controller"},
178 {0, 0, 0, NULL}
179};
180
181static const struct agp_i810_match*
182agp_i810_match(device_t dev)
183{
184 int i, devid;
185
186 if (pci_get_class(dev) != PCIC_DISPLAY
187 || pci_get_subclass(dev) != PCIS_DISPLAY_VGA)
188 return NULL;
189
190 devid = pci_get_devid(dev);
191 for (i = 0; agp_i810_matches[i].devid != 0; i++) {
192 if (agp_i810_matches[i].devid == devid)
193 break;
194 }
195 if (agp_i810_matches[i].devid == 0)
196 return NULL;
197 else
198 return &agp_i810_matches[i];
199}
200
201/*
202 * Find bridge device.
203 */
204static device_t
205agp_i810_find_bridge(device_t dev)
206{
207 device_t *children, child;
208 int nchildren, i;
209 u_int32_t devid;
210 const struct agp_i810_match *match;
211
212 match = agp_i810_match(dev);
213 devid = match->devid - match->bridge_offset;
214
215 if (device_get_children(device_get_parent(device_get_parent(dev)),
216 &children, &nchildren))
217 return 0;
218
219 for (i = 0; i < nchildren; i++) {
220 child = children[i];
221
222 if (pci_get_devid(child) == devid) {
223 free(children, M_TEMP);
224 return child;
225 }
226 }
227 free(children, M_TEMP);
228 return 0;
229}
230
231static void
232agp_i810_identify(driver_t *driver, device_t parent)
233{
234
235 if (device_find_child(parent, "agp", -1) == NULL &&
236 agp_i810_match(parent))
237 device_add_child(parent, "agp", -1);
238}
239
240static int
241agp_i810_probe(device_t dev)
242{
243 device_t bdev;
244 const struct agp_i810_match *match;
245 u_int8_t smram;
246 int gcc1, deven;
247
248 if (resource_disabled("agp", device_get_unit(dev)))
249 return (ENXIO);
250 match = agp_i810_match(dev);
251 if (match == NULL)
252 return ENXIO;
253
254 bdev = agp_i810_find_bridge(dev);
255 if (!bdev) {
256 if (bootverbose)
257 printf("I810: can't find bridge device\n");
258 return ENXIO;
259 }
260
261 /*
262 * checking whether internal graphics device has been activated.
263 */
264 switch (match->chiptype) {
265 case CHIP_I810:
266 smram = pci_read_config(bdev, AGP_I810_SMRAM, 1);
267 if ((smram & AGP_I810_SMRAM_GMS) ==
268 AGP_I810_SMRAM_GMS_DISABLED) {
269 if (bootverbose)
270 printf("I810: disabled, not probing\n");
271 return ENXIO;
272 }
273 break;
274 case CHIP_I830:
275 case CHIP_I855:
276 gcc1 = pci_read_config(bdev, AGP_I830_GCC1, 1);
277 if ((gcc1 & AGP_I830_GCC1_DEV2) ==
278 AGP_I830_GCC1_DEV2_DISABLED) {
279 if (bootverbose)
280 printf("I830: disabled, not probing\n");
281 return ENXIO;
282 }
283 break;
284 case CHIP_I915:
285 case CHIP_I965:
286 case CHIP_G33:
287 case CHIP_G4X:
288 deven = pci_read_config(bdev, AGP_I915_DEVEN, 4);
289 if ((deven & AGP_I915_DEVEN_D2F0) ==
290 AGP_I915_DEVEN_D2F0_DISABLED) {
291 if (bootverbose)
292 printf("I915: disabled, not probing\n");
293 return ENXIO;
294 }
295 break;
296 }
297
298 if (match->devid == 0x35828086) {
299 switch (pci_read_config(dev, AGP_I85X_CAPID, 1)) {
300 case AGP_I855_GME:
301 device_set_desc(dev,
302 "Intel 82855GME (855GME GMCH) SVGA controller");
303 break;
304 case AGP_I855_GM:
305 device_set_desc(dev,
306 "Intel 82855GM (855GM GMCH) SVGA controller");
307 break;
308 case AGP_I852_GME:
309 device_set_desc(dev,
310 "Intel 82852GME (852GME GMCH) SVGA controller");
311 break;
312 case AGP_I852_GM:
313 device_set_desc(dev,
314 "Intel 82852GM (852GM GMCH) SVGA controller");
315 break;
316 default:
317 device_set_desc(dev,
318 "Intel 8285xM (85xGM GMCH) SVGA controller");
319 break;
320 }
321 } else {
322 device_set_desc(dev, match->name);
323 }
324
325 return BUS_PROBE_DEFAULT;
326}
327
328static void
329agp_i810_dump_regs(device_t dev)
330{
331 struct agp_i810_softc *sc = device_get_softc(dev);
332
333 device_printf(dev, "AGP_I810_PGTBL_CTL: %08x\n",
334 bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL));
335
336 switch (sc->chiptype) {
337 case CHIP_I810:
338 device_printf(dev, "AGP_I810_MISCC: 0x%04x\n",
339 pci_read_config(sc->bdev, AGP_I810_MISCC, 2));
340 break;
341 case CHIP_I830:
342 device_printf(dev, "AGP_I830_GCC1: 0x%02x\n",
343 pci_read_config(sc->bdev, AGP_I830_GCC1, 1));
344 break;
345 case CHIP_I855:
346 device_printf(dev, "AGP_I855_GCC1: 0x%02x\n",
347 pci_read_config(sc->bdev, AGP_I855_GCC1, 1));
348 break;
349 case CHIP_I915:
350 case CHIP_I965:
351 case CHIP_G33:
352 case CHIP_G4X:
353 device_printf(dev, "AGP_I855_GCC1: 0x%02x\n",
354 pci_read_config(sc->bdev, AGP_I855_GCC1, 1));
355 device_printf(dev, "AGP_I915_MSAC: 0x%02x\n",
356 pci_read_config(sc->bdev, AGP_I915_MSAC, 1));
357 break;
358 }
359 device_printf(dev, "Aperture resource size: %d bytes\n",
360 AGP_GET_APERTURE(dev));
361}
362
363static int
364agp_i810_attach(device_t dev)
365{
366 struct agp_i810_softc *sc = device_get_softc(dev);
367 struct agp_gatt *gatt;
368 const struct agp_i810_match *match;
369 int error;
370
371 sc->bdev = agp_i810_find_bridge(dev);
372 if (!sc->bdev)
373 return ENOENT;
374
375 match = agp_i810_match(dev);
376 sc->chiptype = match->chiptype;
377
378 switch (sc->chiptype) {
379 case CHIP_I810:
380 case CHIP_I830:
381 case CHIP_I855:
382 sc->sc_res_spec = agp_i810_res_spec;
383 agp_set_aperture_resource(dev, AGP_APBASE);
384 break;
385 case CHIP_I915:
386 case CHIP_G33:
387 sc->sc_res_spec = agp_i915_res_spec;
388 agp_set_aperture_resource(dev, AGP_I915_GMADR);
389 break;
390 case CHIP_I965:
391 case CHIP_G4X:
392 sc->sc_res_spec = agp_i965_res_spec;
393 agp_set_aperture_resource(dev, AGP_I915_GMADR);
394 break;
395 }
396
397 error = agp_generic_attach(dev);
398 if (error)
399 return error;
400
401 if (sc->chiptype != CHIP_I965 && sc->chiptype != CHIP_G33 &&
402 sc->chiptype != CHIP_G4X && ptoa((vm_paddr_t)Maxmem) > 0xfffffffful)
403 {
404 device_printf(dev, "agp_i810.c does not support physical "
405 "memory above 4GB.\n");
406 return ENOENT;
407 }
408
409 if (bus_alloc_resources(dev, sc->sc_res_spec, sc->sc_res)) {
410 agp_generic_detach(dev);
411 return ENODEV;
412 }
413
414 sc->initial_aperture = AGP_GET_APERTURE(dev);
415
416 gatt = malloc( sizeof(struct agp_gatt), M_AGP, M_NOWAIT);
417 if (!gatt) {
418 bus_release_resources(dev, sc->sc_res_spec, sc->sc_res);
419 agp_generic_detach(dev);
420 return ENOMEM;
421 }
422 sc->gatt = gatt;
423
424 gatt->ag_entries = AGP_GET_APERTURE(dev) >> AGP_PAGE_SHIFT;
425
426 if ( sc->chiptype == CHIP_I810 ) {
427 /* Some i810s have on-chip memory called dcache */
428 if (bus_read_1(sc->sc_res[0], AGP_I810_DRT) &
429 AGP_I810_DRT_POPULATED)
430 sc->dcache_size = 4 * 1024 * 1024;
431 else
432 sc->dcache_size = 0;
433
434 /* According to the specs the gatt on the i810 must be 64k */
435 gatt->ag_virtual = contigmalloc( 64 * 1024, M_AGP, 0,
436 0, ~0, PAGE_SIZE, 0);
437 if (!gatt->ag_virtual) {
438 if (bootverbose)
439 device_printf(dev, "contiguous allocation failed\n");
440 bus_release_resources(dev, sc->sc_res_spec,
441 sc->sc_res);
442 free(gatt, M_AGP);
443 agp_generic_detach(dev);
444 return ENOMEM;
445 }
446 bzero(gatt->ag_virtual, gatt->ag_entries * sizeof(u_int32_t));
447
448 gatt->ag_physical = vtophys((vm_offset_t) gatt->ag_virtual);
449 agp_flush_cache();
450 /* Install the GATT. */
451 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL,
452 gatt->ag_physical | 1);
453 } else if ( sc->chiptype == CHIP_I830 ) {
454 /* The i830 automatically initializes the 128k gatt on boot. */
455 unsigned int gcc1, pgtblctl;
456
457 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 1);
458 switch (gcc1 & AGP_I830_GCC1_GMS) {
459 case AGP_I830_GCC1_GMS_STOLEN_512:
460 sc->stolen = (512 - 132) * 1024 / 4096;
461 break;
462 case AGP_I830_GCC1_GMS_STOLEN_1024:
463 sc->stolen = (1024 - 132) * 1024 / 4096;
464 break;
465 case AGP_I830_GCC1_GMS_STOLEN_8192:
466 sc->stolen = (8192 - 132) * 1024 / 4096;
467 break;
468 default:
469 sc->stolen = 0;
470 device_printf(dev, "unknown memory configuration, disabling\n");
471 bus_release_resources(dev, sc->sc_res_spec,
472 sc->sc_res);
473 free(gatt, M_AGP);
474 agp_generic_detach(dev);
475 return EINVAL;
476 }
477 if (sc->stolen > 0) {
478 device_printf(dev, "detected %dk stolen memory\n",
479 sc->stolen * 4);
480 }
481 device_printf(dev, "aperture size is %dM\n",
482 sc->initial_aperture / 1024 / 1024);
483
484 /* GATT address is already in there, make sure it's enabled */
485 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
486 pgtblctl |= 1;
487 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
488
489 gatt->ag_physical = pgtblctl & ~1;
490 } else if (sc->chiptype == CHIP_I855 || sc->chiptype == CHIP_I915 ||
491 sc->chiptype == CHIP_I965 || sc->chiptype == CHIP_G33 ||
492 sc->chiptype == CHIP_G4X) {
493 unsigned int gcc1, pgtblctl, stolen, gtt_size;
494
495 /* Stolen memory is set up at the beginning of the aperture by
496 * the BIOS, consisting of the GATT followed by 4kb for the
497 * BIOS display.
498 */
499 switch (sc->chiptype) {
500 case CHIP_I855:
501 gtt_size = 128;
502 break;
503 case CHIP_I915:
504 gtt_size = 256;
505 break;
506 case CHIP_I965:
507 switch (bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL) &
508 AGP_I810_PGTBL_SIZE_MASK) {
509 case AGP_I810_PGTBL_SIZE_128KB:
510 gtt_size = 128;
511 break;
512 case AGP_I810_PGTBL_SIZE_256KB:
513 gtt_size = 256;
514 break;
515 case AGP_I810_PGTBL_SIZE_512KB:
516 gtt_size = 512;
517 break;
518 case AGP_I965_PGTBL_SIZE_1MB:
519 gtt_size = 1024;
520 break;
521 case AGP_I965_PGTBL_SIZE_2MB:
522 gtt_size = 2048;
523 break;
524 case AGP_I965_PGTBL_SIZE_1_5MB:
525 gtt_size = 1024 + 512;
526 break;
527 default:
528 device_printf(dev, "Bad PGTBL size\n");
529 bus_release_resources(dev, sc->sc_res_spec,
530 sc->sc_res);
531 free(gatt, M_AGP);
532 agp_generic_detach(dev);
533 return EINVAL;
534 }
535 break;
536 case CHIP_G33:
537 gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 2);
538 switch (gcc1 & AGP_G33_MGGC_GGMS_MASK) {
539 case AGP_G33_MGGC_GGMS_SIZE_1M:
540 gtt_size = 1024;
541 break;
542 case AGP_G33_MGGC_GGMS_SIZE_2M:
543 gtt_size = 2048;
544 break;
545 default:
546 device_printf(dev, "Bad PGTBL size\n");
547 bus_release_resources(dev, sc->sc_res_spec,
548 sc->sc_res);
549 free(gatt, M_AGP);
550 agp_generic_detach(dev);
551 return EINVAL;
552 }
553 break;
554 case CHIP_G4X:
555 gtt_size = 0;
556 break;
557 default:
558 device_printf(dev, "Bad chiptype\n");
559 bus_release_resources(dev, sc->sc_res_spec,
560 sc->sc_res);
561 free(gatt, M_AGP);
562 agp_generic_detach(dev);
563 return EINVAL;
564 }
565
566 /* GCC1 is called MGGC on i915+ */
567 gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 1);
568 switch (gcc1 & AGP_I855_GCC1_GMS) {
569 case AGP_I855_GCC1_GMS_STOLEN_1M:
570 stolen = 1024;
571 break;
572 case AGP_I855_GCC1_GMS_STOLEN_4M:
573 stolen = 4 * 1024;
574 break;
575 case AGP_I855_GCC1_GMS_STOLEN_8M:
576 stolen = 8 * 1024;
577 break;
578 case AGP_I855_GCC1_GMS_STOLEN_16M:
579 stolen = 16 * 1024;
580 break;
581 case AGP_I855_GCC1_GMS_STOLEN_32M:
582 stolen = 32 * 1024;
583 break;
584 case AGP_I915_GCC1_GMS_STOLEN_48M:
585 if (sc->chiptype == CHIP_I915 ||
586 sc->chiptype == CHIP_I965 ||
587 sc->chiptype == CHIP_G33 ||
588 sc->chiptype == CHIP_G4X) {
589 stolen = 48 * 1024;
590 } else {
591 stolen = 0;
592 }
593 break;
594 case AGP_I915_GCC1_GMS_STOLEN_64M:
595 if (sc->chiptype == CHIP_I915 ||
596 sc->chiptype == CHIP_I965 ||
597 sc->chiptype == CHIP_G33 ||
598 sc->chiptype == CHIP_G4X) {
599 stolen = 64 * 1024;
600 } else {
601 stolen = 0;
602 }
603 break;
604 case AGP_G33_GCC1_GMS_STOLEN_128M:
605 if (sc->chiptype == CHIP_I965 ||
606 sc->chiptype == CHIP_G33 ||
607 sc->chiptype == CHIP_G4X) {
608 stolen = 128 * 1024;
609 } else {
610 stolen = 0;
611 }
612 break;
613 case AGP_G33_GCC1_GMS_STOLEN_256M:
614 if (sc->chiptype == CHIP_I965 ||
615 sc->chiptype == CHIP_G33 ||
616 sc->chiptype == CHIP_G4X) {
617 stolen = 256 * 1024;
618 } else {
619 stolen = 0;
620 }
621 break;
622 case AGP_G4X_GCC1_GMS_STOLEN_96M:
623 if (sc->chiptype == CHIP_I965 ||
624 sc->chiptype == CHIP_G4X) {
625 stolen = 96 * 1024;
626 } else {
627 stolen = 0;
628 }
629 break;
630 case AGP_G4X_GCC1_GMS_STOLEN_160M:
631 if (sc->chiptype == CHIP_I965 ||
632 sc->chiptype == CHIP_G4X) {
633 stolen = 160 * 1024;
634 } else {
635 stolen = 0;
636 }
637 break;
638 case AGP_G4X_GCC1_GMS_STOLEN_224M:
639 if (sc->chiptype == CHIP_I965 ||
640 sc->chiptype == CHIP_G4X) {
641 stolen = 224 * 1024;
642 } else {
643 stolen = 0;
644 }
645 break;
646 case AGP_G4X_GCC1_GMS_STOLEN_352M:
647 if (sc->chiptype == CHIP_I965 ||
648 sc->chiptype == CHIP_G4X) {
649 stolen = 352 * 1024;
650 } else {
651 stolen = 0;
652 }
653 break;
654 default:
655 device_printf(dev, "unknown memory configuration, "
656 "disabling\n");
657 bus_release_resources(dev, sc->sc_res_spec,
658 sc->sc_res);
659 free(gatt, M_AGP);
660 agp_generic_detach(dev);
661 return EINVAL;
662 }
663
664 gtt_size += 4;
665
666 sc->stolen = (stolen - gtt_size) * 1024 / 4096;
667 if (sc->stolen > 0)
668 device_printf(dev, "detected %dk stolen memory\n", sc->stolen * 4);
669 device_printf(dev, "aperture size is %dM\n", sc->initial_aperture / 1024 / 1024);
670
671 /* GATT address is already in there, make sure it's enabled */
672 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
673 pgtblctl |= 1;
674 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
675
676 gatt->ag_physical = pgtblctl & ~1;
677 }
678
679 if (0)
680 agp_i810_dump_regs(dev);
681
682 return 0;
683}
684
685static int
686agp_i810_detach(device_t dev)
687{
688 struct agp_i810_softc *sc = device_get_softc(dev);
689
690 agp_free_cdev(dev);
691
692 /* Clear the GATT base. */
693 if ( sc->chiptype == CHIP_I810 ) {
694 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, 0);
695 } else {
696 unsigned int pgtblctl;
697 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
698 pgtblctl &= ~1;
699 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
700 }
701
702 /* Put the aperture back the way it started. */
703 AGP_SET_APERTURE(dev, sc->initial_aperture);
704
705 if ( sc->chiptype == CHIP_I810 ) {
706 contigfree(sc->gatt->ag_virtual, 64 * 1024, M_AGP);
707 }
708 free(sc->gatt, M_AGP);
709
710 bus_release_resources(dev, sc->sc_res_spec, sc->sc_res);
711 agp_free_res(dev);
712
713 return 0;
714}
715
716static int
717agp_i810_resume(device_t dev)
718{
719 struct agp_i810_softc *sc;
720 sc = device_get_softc(dev);
721
722 AGP_SET_APERTURE(dev, sc->initial_aperture);
723
724 /* Install the GATT. */
725 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL,
726 sc->gatt->ag_physical | 1);
727
728 return (bus_generic_resume(dev));
729}
730
731/**
732 * Sets the PCI resource size of the aperture on i830-class and below chipsets,
733 * while returning failure on later chipsets when an actual change is
734 * requested.
735 *
736 * This whole function is likely bogus, as the kernel would probably need to
737 * reconfigure the placement of the AGP aperture if a larger size is requested,
738 * which doesn't happen currently.
739 */
740static int
741agp_i810_set_aperture(device_t dev, u_int32_t aperture)
742{
743 struct agp_i810_softc *sc = device_get_softc(dev);
744 u_int16_t miscc, gcc1;
745
746 switch (sc->chiptype) {
747 case CHIP_I810:
748 /*
749 * Double check for sanity.
750 */
751 if (aperture != 32 * 1024 * 1024 && aperture != 64 * 1024 * 1024) {
752 device_printf(dev, "bad aperture size %d\n", aperture);
753 return EINVAL;
754 }
755
756 miscc = pci_read_config(sc->bdev, AGP_I810_MISCC, 2);
757 miscc &= ~AGP_I810_MISCC_WINSIZE;
758 if (aperture == 32 * 1024 * 1024)
759 miscc |= AGP_I810_MISCC_WINSIZE_32;
760 else
761 miscc |= AGP_I810_MISCC_WINSIZE_64;
762
763 pci_write_config(sc->bdev, AGP_I810_MISCC, miscc, 2);
764 break;
765 case CHIP_I830:
766 if (aperture != 64 * 1024 * 1024 &&
767 aperture != 128 * 1024 * 1024) {
768 device_printf(dev, "bad aperture size %d\n", aperture);
769 return EINVAL;
770 }
771 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 2);
772 gcc1 &= ~AGP_I830_GCC1_GMASIZE;
773 if (aperture == 64 * 1024 * 1024)
774 gcc1 |= AGP_I830_GCC1_GMASIZE_64;
775 else
776 gcc1 |= AGP_I830_GCC1_GMASIZE_128;
777
778 pci_write_config(sc->bdev, AGP_I830_GCC1, gcc1, 2);
779 break;
780 case CHIP_I855:
781 case CHIP_I915:
782 case CHIP_I965:
783 case CHIP_G33:
784 case CHIP_G4X:
785 return agp_generic_set_aperture(dev, aperture);
786 }
787
788 return 0;
789}
790
791/**
792 * Writes a GTT entry mapping the page at the given offset from the beginning
793 * of the aperture to the given physical address.
794 */
795static void
796agp_i810_write_gtt_entry(device_t dev, int offset, vm_offset_t physical,
797 int enabled)
798{
799 struct agp_i810_softc *sc = device_get_softc(dev);
800 u_int32_t pte;
801
802 pte = (u_int32_t)physical | 1;
803 if (sc->chiptype == CHIP_I965 || sc->chiptype == CHIP_G33 ||
804 sc->chiptype == CHIP_G4X) {
805 pte |= (physical & 0x0000000f00000000ull) >> 28;
806 } else {
807 /* If we do actually have memory above 4GB on an older system,
808 * crash cleanly rather than scribble on system memory,
809 * so we know we need to fix it.
810 */
811 KASSERT((pte & 0x0000000f00000000ull) == 0,
812 (">4GB physical address in agp"));
813 }
814
815 switch (sc->chiptype) {
816 case CHIP_I810:
817 case CHIP_I830:
818 case CHIP_I855:
819 bus_write_4(sc->sc_res[0],
820 AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4, pte);
821 break;
822 case CHIP_I915:
823 case CHIP_G33:
824 bus_write_4(sc->sc_res[1],
825 (offset >> AGP_PAGE_SHIFT) * 4, pte);
826 break;
827 case CHIP_I965:
828 bus_write_4(sc->sc_res[0],
829 (offset >> AGP_PAGE_SHIFT) * 4 + (512 * 1024), pte);
830 break;
831 case CHIP_G4X:
832 bus_write_4(sc->sc_res[0],
833 (offset >> AGP_PAGE_SHIFT) * 4 + (2 * 1024 * 1024), pte);
834 break;
835 }
836}
837
838static int
| 35
36#include "opt_bus.h"
37
38#include <sys/param.h>
39#include <sys/systm.h>
40#include <sys/malloc.h>
41#include <sys/kernel.h>
42#include <sys/module.h>
43#include <sys/bus.h>
44#include <sys/lock.h>
45#include <sys/mutex.h>
46#include <sys/proc.h>
47
48#include <dev/agp/agppriv.h>
49#include <dev/agp/agpreg.h>
50#include <dev/pci/pcivar.h>
51#include <dev/pci/pcireg.h>
52
53#include <vm/vm.h>
54#include <vm/vm_object.h>
55#include <vm/vm_page.h>
56#include <vm/vm_pageout.h>
57#include <vm/pmap.h>
58
59#include <machine/bus.h>
60#include <machine/resource.h>
61#include <machine/md_var.h>
62#include <sys/rman.h>
63
64MALLOC_DECLARE(M_AGP);
65
66enum {
67 CHIP_I810, /* i810/i815 */
68 CHIP_I830, /* 830M/845G */
69 CHIP_I855, /* 852GM/855GM/865G */
70 CHIP_I915, /* 915G/915GM */
71 CHIP_I965, /* G965 */
72 CHIP_G33, /* G33/Q33/Q35 */
73 CHIP_G4X, /* G45/Q45 */
74};
75
76/* The i810 through i855 have the registers at BAR 1, and the GATT gets
77 * allocated by us. The i915 has registers in BAR 0 and the GATT is at the
78 * start of the stolen memory, and should only be accessed by the OS through
79 * BAR 3. The G965 has registers and GATT in the same BAR (0) -- first 512KB
80 * is registers, second 512KB is GATT.
81 */
82static struct resource_spec agp_i810_res_spec[] = {
83 { SYS_RES_MEMORY, AGP_I810_MMADR, RF_ACTIVE | RF_SHAREABLE },
84 { -1, 0 }
85};
86
87static struct resource_spec agp_i915_res_spec[] = {
88 { SYS_RES_MEMORY, AGP_I915_MMADR, RF_ACTIVE | RF_SHAREABLE },
89 { SYS_RES_MEMORY, AGP_I915_GTTADR, RF_ACTIVE | RF_SHAREABLE },
90 { -1, 0 }
91};
92
93static struct resource_spec agp_i965_res_spec[] = {
94 { SYS_RES_MEMORY, AGP_I965_GTTMMADR, RF_ACTIVE | RF_SHAREABLE },
95 { -1, 0 }
96};
97
98struct agp_i810_softc {
99 struct agp_softc agp;
100 u_int32_t initial_aperture; /* aperture size at startup */
101 struct agp_gatt *gatt;
102 int chiptype; /* i810-like or i830 */
103 u_int32_t dcache_size; /* i810 only */
104 u_int32_t stolen; /* number of i830/845 gtt entries for stolen memory */
105 device_t bdev; /* bridge device */
106
107 void *argb_cursor; /* contigmalloc area for ARGB cursor */
108
109 struct resource_spec * sc_res_spec;
110 struct resource *sc_res[2];
111};
112
113/* For adding new devices, devid is the id of the graphics controller
114 * (pci:0:2:0, for example). The placeholder (usually at pci:0:2:1) for the
115 * second head should never be added. The bridge_offset is the offset to
116 * subtract from devid to get the id of the hostb that the device is on.
117 */
118static const struct agp_i810_match {
119 int devid;
120 int chiptype;
121 int bridge_offset;
122 char *name;
123} agp_i810_matches[] = {
124 {0x71218086, CHIP_I810, 0x00010000,
125 "Intel 82810 (i810 GMCH) SVGA controller"},
126 {0x71238086, CHIP_I810, 0x00010000,
127 "Intel 82810-DC100 (i810-DC100 GMCH) SVGA controller"},
128 {0x71258086, CHIP_I810, 0x00010000,
129 "Intel 82810E (i810E GMCH) SVGA controller"},
130 {0x11328086, CHIP_I810, 0x00020000,
131 "Intel 82815 (i815 GMCH) SVGA controller"},
132 {0x35778086, CHIP_I830, 0x00020000,
133 "Intel 82830M (830M GMCH) SVGA controller"},
134 {0x25628086, CHIP_I830, 0x00020000,
135 "Intel 82845M (845M GMCH) SVGA controller"},
136 {0x35828086, CHIP_I855, 0x00020000,
137 "Intel 82852/855GM SVGA controller"},
138 {0x25728086, CHIP_I855, 0x00020000,
139 "Intel 82865G (865G GMCH) SVGA controller"},
140 {0x25828086, CHIP_I915, 0x00020000,
141 "Intel 82915G (915G GMCH) SVGA controller"},
142 {0x258A8086, CHIP_I915, 0x00020000,
143 "Intel E7221 SVGA controller"},
144 {0x25928086, CHIP_I915, 0x00020000,
145 "Intel 82915GM (915GM GMCH) SVGA controller"},
146 {0x27728086, CHIP_I915, 0x00020000,
147 "Intel 82945G (945G GMCH) SVGA controller"},
148 {0x27A28086, CHIP_I915, 0x00020000,
149 "Intel 82945GM (945GM GMCH) SVGA controller"},
150 {0x27AE8086, CHIP_I915, 0x00020000,
151 "Intel 945GME SVGA controller"},
152 {0x29728086, CHIP_I965, 0x00020000,
153 "Intel 946GZ SVGA controller"},
154 {0x29828086, CHIP_I965, 0x00020000,
155 "Intel G965 SVGA controller"},
156 {0x29928086, CHIP_I965, 0x00020000,
157 "Intel Q965 SVGA controller"},
158 {0x29A28086, CHIP_I965, 0x00020000,
159 "Intel G965 SVGA controller"},
160 {0x29B28086, CHIP_G33, 0x00020000,
161 "Intel Q35 SVGA controller"},
162 {0x29C28086, CHIP_G33, 0x00020000,
163 "Intel G33 SVGA controller"},
164 {0x29D28086, CHIP_G33, 0x00020000,
165 "Intel Q33 SVGA controller"},
166 {0x2A028086, CHIP_I965, 0x00020000,
167 "Intel GM965 SVGA controller"},
168 {0x2A128086, CHIP_I965, 0x00020000,
169 "Intel GME965 SVGA controller"},
170 {0x2A428086, CHIP_G4X, 0x00020000,
171 "Intel GM45 SVGA controller"},
172 {0x2E028086, CHIP_G4X, 0x00020000,
173 "Intel 4 Series SVGA controller"},
174 {0x2E128086, CHIP_G4X, 0x00020000,
175 "Intel Q45 SVGA controller"},
176 {0x2E228086, CHIP_G4X, 0x00020000,
177 "Intel G45 SVGA controller"},
178 {0, 0, 0, NULL}
179};
180
181static const struct agp_i810_match*
182agp_i810_match(device_t dev)
183{
184 int i, devid;
185
186 if (pci_get_class(dev) != PCIC_DISPLAY
187 || pci_get_subclass(dev) != PCIS_DISPLAY_VGA)
188 return NULL;
189
190 devid = pci_get_devid(dev);
191 for (i = 0; agp_i810_matches[i].devid != 0; i++) {
192 if (agp_i810_matches[i].devid == devid)
193 break;
194 }
195 if (agp_i810_matches[i].devid == 0)
196 return NULL;
197 else
198 return &agp_i810_matches[i];
199}
200
201/*
202 * Find bridge device.
203 */
204static device_t
205agp_i810_find_bridge(device_t dev)
206{
207 device_t *children, child;
208 int nchildren, i;
209 u_int32_t devid;
210 const struct agp_i810_match *match;
211
212 match = agp_i810_match(dev);
213 devid = match->devid - match->bridge_offset;
214
215 if (device_get_children(device_get_parent(device_get_parent(dev)),
216 &children, &nchildren))
217 return 0;
218
219 for (i = 0; i < nchildren; i++) {
220 child = children[i];
221
222 if (pci_get_devid(child) == devid) {
223 free(children, M_TEMP);
224 return child;
225 }
226 }
227 free(children, M_TEMP);
228 return 0;
229}
230
231static void
232agp_i810_identify(driver_t *driver, device_t parent)
233{
234
235 if (device_find_child(parent, "agp", -1) == NULL &&
236 agp_i810_match(parent))
237 device_add_child(parent, "agp", -1);
238}
239
240static int
241agp_i810_probe(device_t dev)
242{
243 device_t bdev;
244 const struct agp_i810_match *match;
245 u_int8_t smram;
246 int gcc1, deven;
247
248 if (resource_disabled("agp", device_get_unit(dev)))
249 return (ENXIO);
250 match = agp_i810_match(dev);
251 if (match == NULL)
252 return ENXIO;
253
254 bdev = agp_i810_find_bridge(dev);
255 if (!bdev) {
256 if (bootverbose)
257 printf("I810: can't find bridge device\n");
258 return ENXIO;
259 }
260
261 /*
262 * checking whether internal graphics device has been activated.
263 */
264 switch (match->chiptype) {
265 case CHIP_I810:
266 smram = pci_read_config(bdev, AGP_I810_SMRAM, 1);
267 if ((smram & AGP_I810_SMRAM_GMS) ==
268 AGP_I810_SMRAM_GMS_DISABLED) {
269 if (bootverbose)
270 printf("I810: disabled, not probing\n");
271 return ENXIO;
272 }
273 break;
274 case CHIP_I830:
275 case CHIP_I855:
276 gcc1 = pci_read_config(bdev, AGP_I830_GCC1, 1);
277 if ((gcc1 & AGP_I830_GCC1_DEV2) ==
278 AGP_I830_GCC1_DEV2_DISABLED) {
279 if (bootverbose)
280 printf("I830: disabled, not probing\n");
281 return ENXIO;
282 }
283 break;
284 case CHIP_I915:
285 case CHIP_I965:
286 case CHIP_G33:
287 case CHIP_G4X:
288 deven = pci_read_config(bdev, AGP_I915_DEVEN, 4);
289 if ((deven & AGP_I915_DEVEN_D2F0) ==
290 AGP_I915_DEVEN_D2F0_DISABLED) {
291 if (bootverbose)
292 printf("I915: disabled, not probing\n");
293 return ENXIO;
294 }
295 break;
296 }
297
298 if (match->devid == 0x35828086) {
299 switch (pci_read_config(dev, AGP_I85X_CAPID, 1)) {
300 case AGP_I855_GME:
301 device_set_desc(dev,
302 "Intel 82855GME (855GME GMCH) SVGA controller");
303 break;
304 case AGP_I855_GM:
305 device_set_desc(dev,
306 "Intel 82855GM (855GM GMCH) SVGA controller");
307 break;
308 case AGP_I852_GME:
309 device_set_desc(dev,
310 "Intel 82852GME (852GME GMCH) SVGA controller");
311 break;
312 case AGP_I852_GM:
313 device_set_desc(dev,
314 "Intel 82852GM (852GM GMCH) SVGA controller");
315 break;
316 default:
317 device_set_desc(dev,
318 "Intel 8285xM (85xGM GMCH) SVGA controller");
319 break;
320 }
321 } else {
322 device_set_desc(dev, match->name);
323 }
324
325 return BUS_PROBE_DEFAULT;
326}
327
328static void
329agp_i810_dump_regs(device_t dev)
330{
331 struct agp_i810_softc *sc = device_get_softc(dev);
332
333 device_printf(dev, "AGP_I810_PGTBL_CTL: %08x\n",
334 bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL));
335
336 switch (sc->chiptype) {
337 case CHIP_I810:
338 device_printf(dev, "AGP_I810_MISCC: 0x%04x\n",
339 pci_read_config(sc->bdev, AGP_I810_MISCC, 2));
340 break;
341 case CHIP_I830:
342 device_printf(dev, "AGP_I830_GCC1: 0x%02x\n",
343 pci_read_config(sc->bdev, AGP_I830_GCC1, 1));
344 break;
345 case CHIP_I855:
346 device_printf(dev, "AGP_I855_GCC1: 0x%02x\n",
347 pci_read_config(sc->bdev, AGP_I855_GCC1, 1));
348 break;
349 case CHIP_I915:
350 case CHIP_I965:
351 case CHIP_G33:
352 case CHIP_G4X:
353 device_printf(dev, "AGP_I855_GCC1: 0x%02x\n",
354 pci_read_config(sc->bdev, AGP_I855_GCC1, 1));
355 device_printf(dev, "AGP_I915_MSAC: 0x%02x\n",
356 pci_read_config(sc->bdev, AGP_I915_MSAC, 1));
357 break;
358 }
359 device_printf(dev, "Aperture resource size: %d bytes\n",
360 AGP_GET_APERTURE(dev));
361}
362
363static int
364agp_i810_attach(device_t dev)
365{
366 struct agp_i810_softc *sc = device_get_softc(dev);
367 struct agp_gatt *gatt;
368 const struct agp_i810_match *match;
369 int error;
370
371 sc->bdev = agp_i810_find_bridge(dev);
372 if (!sc->bdev)
373 return ENOENT;
374
375 match = agp_i810_match(dev);
376 sc->chiptype = match->chiptype;
377
378 switch (sc->chiptype) {
379 case CHIP_I810:
380 case CHIP_I830:
381 case CHIP_I855:
382 sc->sc_res_spec = agp_i810_res_spec;
383 agp_set_aperture_resource(dev, AGP_APBASE);
384 break;
385 case CHIP_I915:
386 case CHIP_G33:
387 sc->sc_res_spec = agp_i915_res_spec;
388 agp_set_aperture_resource(dev, AGP_I915_GMADR);
389 break;
390 case CHIP_I965:
391 case CHIP_G4X:
392 sc->sc_res_spec = agp_i965_res_spec;
393 agp_set_aperture_resource(dev, AGP_I915_GMADR);
394 break;
395 }
396
397 error = agp_generic_attach(dev);
398 if (error)
399 return error;
400
401 if (sc->chiptype != CHIP_I965 && sc->chiptype != CHIP_G33 &&
402 sc->chiptype != CHIP_G4X && ptoa((vm_paddr_t)Maxmem) > 0xfffffffful)
403 {
404 device_printf(dev, "agp_i810.c does not support physical "
405 "memory above 4GB.\n");
406 return ENOENT;
407 }
408
409 if (bus_alloc_resources(dev, sc->sc_res_spec, sc->sc_res)) {
410 agp_generic_detach(dev);
411 return ENODEV;
412 }
413
414 sc->initial_aperture = AGP_GET_APERTURE(dev);
415
416 gatt = malloc( sizeof(struct agp_gatt), M_AGP, M_NOWAIT);
417 if (!gatt) {
418 bus_release_resources(dev, sc->sc_res_spec, sc->sc_res);
419 agp_generic_detach(dev);
420 return ENOMEM;
421 }
422 sc->gatt = gatt;
423
424 gatt->ag_entries = AGP_GET_APERTURE(dev) >> AGP_PAGE_SHIFT;
425
426 if ( sc->chiptype == CHIP_I810 ) {
427 /* Some i810s have on-chip memory called dcache */
428 if (bus_read_1(sc->sc_res[0], AGP_I810_DRT) &
429 AGP_I810_DRT_POPULATED)
430 sc->dcache_size = 4 * 1024 * 1024;
431 else
432 sc->dcache_size = 0;
433
434 /* According to the specs the gatt on the i810 must be 64k */
435 gatt->ag_virtual = contigmalloc( 64 * 1024, M_AGP, 0,
436 0, ~0, PAGE_SIZE, 0);
437 if (!gatt->ag_virtual) {
438 if (bootverbose)
439 device_printf(dev, "contiguous allocation failed\n");
440 bus_release_resources(dev, sc->sc_res_spec,
441 sc->sc_res);
442 free(gatt, M_AGP);
443 agp_generic_detach(dev);
444 return ENOMEM;
445 }
446 bzero(gatt->ag_virtual, gatt->ag_entries * sizeof(u_int32_t));
447
448 gatt->ag_physical = vtophys((vm_offset_t) gatt->ag_virtual);
449 agp_flush_cache();
450 /* Install the GATT. */
451 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL,
452 gatt->ag_physical | 1);
453 } else if ( sc->chiptype == CHIP_I830 ) {
454 /* The i830 automatically initializes the 128k gatt on boot. */
455 unsigned int gcc1, pgtblctl;
456
457 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 1);
458 switch (gcc1 & AGP_I830_GCC1_GMS) {
459 case AGP_I830_GCC1_GMS_STOLEN_512:
460 sc->stolen = (512 - 132) * 1024 / 4096;
461 break;
462 case AGP_I830_GCC1_GMS_STOLEN_1024:
463 sc->stolen = (1024 - 132) * 1024 / 4096;
464 break;
465 case AGP_I830_GCC1_GMS_STOLEN_8192:
466 sc->stolen = (8192 - 132) * 1024 / 4096;
467 break;
468 default:
469 sc->stolen = 0;
470 device_printf(dev, "unknown memory configuration, disabling\n");
471 bus_release_resources(dev, sc->sc_res_spec,
472 sc->sc_res);
473 free(gatt, M_AGP);
474 agp_generic_detach(dev);
475 return EINVAL;
476 }
477 if (sc->stolen > 0) {
478 device_printf(dev, "detected %dk stolen memory\n",
479 sc->stolen * 4);
480 }
481 device_printf(dev, "aperture size is %dM\n",
482 sc->initial_aperture / 1024 / 1024);
483
484 /* GATT address is already in there, make sure it's enabled */
485 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
486 pgtblctl |= 1;
487 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
488
489 gatt->ag_physical = pgtblctl & ~1;
490 } else if (sc->chiptype == CHIP_I855 || sc->chiptype == CHIP_I915 ||
491 sc->chiptype == CHIP_I965 || sc->chiptype == CHIP_G33 ||
492 sc->chiptype == CHIP_G4X) {
493 unsigned int gcc1, pgtblctl, stolen, gtt_size;
494
495 /* Stolen memory is set up at the beginning of the aperture by
496 * the BIOS, consisting of the GATT followed by 4kb for the
497 * BIOS display.
498 */
499 switch (sc->chiptype) {
500 case CHIP_I855:
501 gtt_size = 128;
502 break;
503 case CHIP_I915:
504 gtt_size = 256;
505 break;
506 case CHIP_I965:
507 switch (bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL) &
508 AGP_I810_PGTBL_SIZE_MASK) {
509 case AGP_I810_PGTBL_SIZE_128KB:
510 gtt_size = 128;
511 break;
512 case AGP_I810_PGTBL_SIZE_256KB:
513 gtt_size = 256;
514 break;
515 case AGP_I810_PGTBL_SIZE_512KB:
516 gtt_size = 512;
517 break;
518 case AGP_I965_PGTBL_SIZE_1MB:
519 gtt_size = 1024;
520 break;
521 case AGP_I965_PGTBL_SIZE_2MB:
522 gtt_size = 2048;
523 break;
524 case AGP_I965_PGTBL_SIZE_1_5MB:
525 gtt_size = 1024 + 512;
526 break;
527 default:
528 device_printf(dev, "Bad PGTBL size\n");
529 bus_release_resources(dev, sc->sc_res_spec,
530 sc->sc_res);
531 free(gatt, M_AGP);
532 agp_generic_detach(dev);
533 return EINVAL;
534 }
535 break;
536 case CHIP_G33:
537 gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 2);
538 switch (gcc1 & AGP_G33_MGGC_GGMS_MASK) {
539 case AGP_G33_MGGC_GGMS_SIZE_1M:
540 gtt_size = 1024;
541 break;
542 case AGP_G33_MGGC_GGMS_SIZE_2M:
543 gtt_size = 2048;
544 break;
545 default:
546 device_printf(dev, "Bad PGTBL size\n");
547 bus_release_resources(dev, sc->sc_res_spec,
548 sc->sc_res);
549 free(gatt, M_AGP);
550 agp_generic_detach(dev);
551 return EINVAL;
552 }
553 break;
554 case CHIP_G4X:
555 gtt_size = 0;
556 break;
557 default:
558 device_printf(dev, "Bad chiptype\n");
559 bus_release_resources(dev, sc->sc_res_spec,
560 sc->sc_res);
561 free(gatt, M_AGP);
562 agp_generic_detach(dev);
563 return EINVAL;
564 }
565
566 /* GCC1 is called MGGC on i915+ */
567 gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 1);
568 switch (gcc1 & AGP_I855_GCC1_GMS) {
569 case AGP_I855_GCC1_GMS_STOLEN_1M:
570 stolen = 1024;
571 break;
572 case AGP_I855_GCC1_GMS_STOLEN_4M:
573 stolen = 4 * 1024;
574 break;
575 case AGP_I855_GCC1_GMS_STOLEN_8M:
576 stolen = 8 * 1024;
577 break;
578 case AGP_I855_GCC1_GMS_STOLEN_16M:
579 stolen = 16 * 1024;
580 break;
581 case AGP_I855_GCC1_GMS_STOLEN_32M:
582 stolen = 32 * 1024;
583 break;
584 case AGP_I915_GCC1_GMS_STOLEN_48M:
585 if (sc->chiptype == CHIP_I915 ||
586 sc->chiptype == CHIP_I965 ||
587 sc->chiptype == CHIP_G33 ||
588 sc->chiptype == CHIP_G4X) {
589 stolen = 48 * 1024;
590 } else {
591 stolen = 0;
592 }
593 break;
594 case AGP_I915_GCC1_GMS_STOLEN_64M:
595 if (sc->chiptype == CHIP_I915 ||
596 sc->chiptype == CHIP_I965 ||
597 sc->chiptype == CHIP_G33 ||
598 sc->chiptype == CHIP_G4X) {
599 stolen = 64 * 1024;
600 } else {
601 stolen = 0;
602 }
603 break;
604 case AGP_G33_GCC1_GMS_STOLEN_128M:
605 if (sc->chiptype == CHIP_I965 ||
606 sc->chiptype == CHIP_G33 ||
607 sc->chiptype == CHIP_G4X) {
608 stolen = 128 * 1024;
609 } else {
610 stolen = 0;
611 }
612 break;
613 case AGP_G33_GCC1_GMS_STOLEN_256M:
614 if (sc->chiptype == CHIP_I965 ||
615 sc->chiptype == CHIP_G33 ||
616 sc->chiptype == CHIP_G4X) {
617 stolen = 256 * 1024;
618 } else {
619 stolen = 0;
620 }
621 break;
622 case AGP_G4X_GCC1_GMS_STOLEN_96M:
623 if (sc->chiptype == CHIP_I965 ||
624 sc->chiptype == CHIP_G4X) {
625 stolen = 96 * 1024;
626 } else {
627 stolen = 0;
628 }
629 break;
630 case AGP_G4X_GCC1_GMS_STOLEN_160M:
631 if (sc->chiptype == CHIP_I965 ||
632 sc->chiptype == CHIP_G4X) {
633 stolen = 160 * 1024;
634 } else {
635 stolen = 0;
636 }
637 break;
638 case AGP_G4X_GCC1_GMS_STOLEN_224M:
639 if (sc->chiptype == CHIP_I965 ||
640 sc->chiptype == CHIP_G4X) {
641 stolen = 224 * 1024;
642 } else {
643 stolen = 0;
644 }
645 break;
646 case AGP_G4X_GCC1_GMS_STOLEN_352M:
647 if (sc->chiptype == CHIP_I965 ||
648 sc->chiptype == CHIP_G4X) {
649 stolen = 352 * 1024;
650 } else {
651 stolen = 0;
652 }
653 break;
654 default:
655 device_printf(dev, "unknown memory configuration, "
656 "disabling\n");
657 bus_release_resources(dev, sc->sc_res_spec,
658 sc->sc_res);
659 free(gatt, M_AGP);
660 agp_generic_detach(dev);
661 return EINVAL;
662 }
663
664 gtt_size += 4;
665
666 sc->stolen = (stolen - gtt_size) * 1024 / 4096;
667 if (sc->stolen > 0)
668 device_printf(dev, "detected %dk stolen memory\n", sc->stolen * 4);
669 device_printf(dev, "aperture size is %dM\n", sc->initial_aperture / 1024 / 1024);
670
671 /* GATT address is already in there, make sure it's enabled */
672 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
673 pgtblctl |= 1;
674 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
675
676 gatt->ag_physical = pgtblctl & ~1;
677 }
678
679 if (0)
680 agp_i810_dump_regs(dev);
681
682 return 0;
683}
684
685static int
686agp_i810_detach(device_t dev)
687{
688 struct agp_i810_softc *sc = device_get_softc(dev);
689
690 agp_free_cdev(dev);
691
692 /* Clear the GATT base. */
693 if ( sc->chiptype == CHIP_I810 ) {
694 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, 0);
695 } else {
696 unsigned int pgtblctl;
697 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
698 pgtblctl &= ~1;
699 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
700 }
701
702 /* Put the aperture back the way it started. */
703 AGP_SET_APERTURE(dev, sc->initial_aperture);
704
705 if ( sc->chiptype == CHIP_I810 ) {
706 contigfree(sc->gatt->ag_virtual, 64 * 1024, M_AGP);
707 }
708 free(sc->gatt, M_AGP);
709
710 bus_release_resources(dev, sc->sc_res_spec, sc->sc_res);
711 agp_free_res(dev);
712
713 return 0;
714}
715
716static int
717agp_i810_resume(device_t dev)
718{
719 struct agp_i810_softc *sc;
720 sc = device_get_softc(dev);
721
722 AGP_SET_APERTURE(dev, sc->initial_aperture);
723
724 /* Install the GATT. */
725 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL,
726 sc->gatt->ag_physical | 1);
727
728 return (bus_generic_resume(dev));
729}
730
731/**
732 * Sets the PCI resource size of the aperture on i830-class and below chipsets,
733 * while returning failure on later chipsets when an actual change is
734 * requested.
735 *
736 * This whole function is likely bogus, as the kernel would probably need to
737 * reconfigure the placement of the AGP aperture if a larger size is requested,
738 * which doesn't happen currently.
739 */
740static int
741agp_i810_set_aperture(device_t dev, u_int32_t aperture)
742{
743 struct agp_i810_softc *sc = device_get_softc(dev);
744 u_int16_t miscc, gcc1;
745
746 switch (sc->chiptype) {
747 case CHIP_I810:
748 /*
749 * Double check for sanity.
750 */
751 if (aperture != 32 * 1024 * 1024 && aperture != 64 * 1024 * 1024) {
752 device_printf(dev, "bad aperture size %d\n", aperture);
753 return EINVAL;
754 }
755
756 miscc = pci_read_config(sc->bdev, AGP_I810_MISCC, 2);
757 miscc &= ~AGP_I810_MISCC_WINSIZE;
758 if (aperture == 32 * 1024 * 1024)
759 miscc |= AGP_I810_MISCC_WINSIZE_32;
760 else
761 miscc |= AGP_I810_MISCC_WINSIZE_64;
762
763 pci_write_config(sc->bdev, AGP_I810_MISCC, miscc, 2);
764 break;
765 case CHIP_I830:
766 if (aperture != 64 * 1024 * 1024 &&
767 aperture != 128 * 1024 * 1024) {
768 device_printf(dev, "bad aperture size %d\n", aperture);
769 return EINVAL;
770 }
771 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 2);
772 gcc1 &= ~AGP_I830_GCC1_GMASIZE;
773 if (aperture == 64 * 1024 * 1024)
774 gcc1 |= AGP_I830_GCC1_GMASIZE_64;
775 else
776 gcc1 |= AGP_I830_GCC1_GMASIZE_128;
777
778 pci_write_config(sc->bdev, AGP_I830_GCC1, gcc1, 2);
779 break;
780 case CHIP_I855:
781 case CHIP_I915:
782 case CHIP_I965:
783 case CHIP_G33:
784 case CHIP_G4X:
785 return agp_generic_set_aperture(dev, aperture);
786 }
787
788 return 0;
789}
790
791/**
792 * Writes a GTT entry mapping the page at the given offset from the beginning
793 * of the aperture to the given physical address.
794 */
795static void
796agp_i810_write_gtt_entry(device_t dev, int offset, vm_offset_t physical,
797 int enabled)
798{
799 struct agp_i810_softc *sc = device_get_softc(dev);
800 u_int32_t pte;
801
802 pte = (u_int32_t)physical | 1;
803 if (sc->chiptype == CHIP_I965 || sc->chiptype == CHIP_G33 ||
804 sc->chiptype == CHIP_G4X) {
805 pte |= (physical & 0x0000000f00000000ull) >> 28;
806 } else {
807 /* If we do actually have memory above 4GB on an older system,
808 * crash cleanly rather than scribble on system memory,
809 * so we know we need to fix it.
810 */
811 KASSERT((pte & 0x0000000f00000000ull) == 0,
812 (">4GB physical address in agp"));
813 }
814
815 switch (sc->chiptype) {
816 case CHIP_I810:
817 case CHIP_I830:
818 case CHIP_I855:
819 bus_write_4(sc->sc_res[0],
820 AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4, pte);
821 break;
822 case CHIP_I915:
823 case CHIP_G33:
824 bus_write_4(sc->sc_res[1],
825 (offset >> AGP_PAGE_SHIFT) * 4, pte);
826 break;
827 case CHIP_I965:
828 bus_write_4(sc->sc_res[0],
829 (offset >> AGP_PAGE_SHIFT) * 4 + (512 * 1024), pte);
830 break;
831 case CHIP_G4X:
832 bus_write_4(sc->sc_res[0],
833 (offset >> AGP_PAGE_SHIFT) * 4 + (2 * 1024 * 1024), pte);
834 break;
835 }
836}
837
838static int
|
862{
863 struct agp_i810_softc *sc = device_get_softc(dev);
864
865 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
866 return EINVAL;
867
868 if ( sc->chiptype != CHIP_I810 ) {
869 if ( (offset >> AGP_PAGE_SHIFT) < sc->stolen ) {
870 device_printf(dev, "trying to unbind from stolen memory");
871 return EINVAL;
872 }
873 }
874
875 agp_i810_write_gtt_entry(dev, offset, 0, 0);
876
877 return 0;
878}
879
880/*
881 * Writing via memory mapped registers already flushes all TLBs.
882 */
883static void
884agp_i810_flush_tlb(device_t dev)
885{
886}
887
888static int
889agp_i810_enable(device_t dev, u_int32_t mode)
890{
891
892 return 0;
893}
894
895static struct agp_memory *
896agp_i810_alloc_memory(device_t dev, int type, vm_size_t size)
897{
898 struct agp_i810_softc *sc = device_get_softc(dev);
899 struct agp_memory *mem;
900
901 if ((size & (AGP_PAGE_SIZE - 1)) != 0)
902 return 0;
903
904 if (sc->agp.as_allocated + size > sc->agp.as_maxmem)
905 return 0;
906
907 if (type == 1) {
908 /*
909 * Mapping local DRAM into GATT.
910 */
911 if ( sc->chiptype != CHIP_I810 )
912 return 0;
913 if (size != sc->dcache_size)
914 return 0;
915 } else if (type == 2) {
916 /*
917 * Type 2 is the contiguous physical memory type, that hands
918 * back a physical address. This is used for cursors on i810.
919 * Hand back as many single pages with physical as the user
920 * wants, but only allow one larger allocation (ARGB cursor)
921 * for simplicity.
922 */
923 if (size != AGP_PAGE_SIZE) {
924 if (sc->argb_cursor != NULL)
925 return 0;
926
927 /* Allocate memory for ARGB cursor, if we can. */
928 sc->argb_cursor = contigmalloc(size, M_AGP,
929 0, 0, ~0, PAGE_SIZE, 0);
930 if (sc->argb_cursor == NULL)
931 return 0;
932 }
933 }
934
935 mem = malloc(sizeof *mem, M_AGP, M_WAITOK);
936 mem->am_id = sc->agp.as_nextid++;
937 mem->am_size = size;
938 mem->am_type = type;
939 if (type != 1 && (type != 2 || size == AGP_PAGE_SIZE))
940 mem->am_obj = vm_object_allocate(OBJT_DEFAULT,
941 atop(round_page(size)));
942 else
943 mem->am_obj = 0;
944
945 if (type == 2) {
946 if (size == AGP_PAGE_SIZE) {
947 /*
948 * Allocate and wire down the page now so that we can
949 * get its physical address.
950 */
951 vm_page_t m;
952
953 VM_OBJECT_LOCK(mem->am_obj);
954 m = vm_page_grab(mem->am_obj, 0, VM_ALLOC_NOBUSY |
955 VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_RETRY);
956 VM_OBJECT_UNLOCK(mem->am_obj);
957 mem->am_physical = VM_PAGE_TO_PHYS(m);
958 } else {
959 /* Our allocation is already nicely wired down for us.
960 * Just grab the physical address.
961 */
962 mem->am_physical = vtophys(sc->argb_cursor);
963 }
964 } else {
965 mem->am_physical = 0;
966 }
967
968 mem->am_offset = 0;
969 mem->am_is_bound = 0;
970 TAILQ_INSERT_TAIL(&sc->agp.as_memory, mem, am_link);
971 sc->agp.as_allocated += size;
972
973 return mem;
974}
975
976static int
977agp_i810_free_memory(device_t dev, struct agp_memory *mem)
978{
979 struct agp_i810_softc *sc = device_get_softc(dev);
980
981 if (mem->am_is_bound)
982 return EBUSY;
983
984 if (mem->am_type == 2) {
985 if (mem->am_size == AGP_PAGE_SIZE) {
986 /*
987 * Unwire the page which we wired in alloc_memory.
988 */
989 vm_page_t m;
990
991 VM_OBJECT_LOCK(mem->am_obj);
992 m = vm_page_lookup(mem->am_obj, 0);
993 VM_OBJECT_UNLOCK(mem->am_obj);
994 vm_page_lock_queues();
995 vm_page_unwire(m, 0);
996 vm_page_unlock_queues();
997 } else {
998 contigfree(sc->argb_cursor, mem->am_size, M_AGP);
999 sc->argb_cursor = NULL;
1000 }
1001 }
1002
1003 sc->agp.as_allocated -= mem->am_size;
1004 TAILQ_REMOVE(&sc->agp.as_memory, mem, am_link);
1005 if (mem->am_obj)
1006 vm_object_deallocate(mem->am_obj);
1007 free(mem, M_AGP);
1008 return 0;
1009}
1010
1011static int
1012agp_i810_bind_memory(device_t dev, struct agp_memory *mem,
1013 vm_offset_t offset)
1014{
1015 struct agp_i810_softc *sc = device_get_softc(dev);
1016 vm_offset_t i;
1017
1018 /* Do some sanity checks first. */
1019 if (offset < 0 || (offset & (AGP_PAGE_SIZE - 1)) != 0 ||
1020 offset + mem->am_size > AGP_GET_APERTURE(dev)) {
1021 device_printf(dev, "binding memory at bad offset %#x\n",
1022 (int)offset);
1023 return EINVAL;
1024 }
1025
1026 if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) {
1027 mtx_lock(&sc->agp.as_lock);
1028 if (mem->am_is_bound) {
1029 mtx_unlock(&sc->agp.as_lock);
1030 return EINVAL;
1031 }
1032 /* The memory's already wired down, just stick it in the GTT. */
1033 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1034 agp_i810_write_gtt_entry(dev, offset + i,
1035 mem->am_physical + i, 1);
1036 }
1037 agp_flush_cache();
1038 mem->am_offset = offset;
1039 mem->am_is_bound = 1;
1040 mtx_unlock(&sc->agp.as_lock);
1041 return 0;
1042 }
1043
1044 if (mem->am_type != 1)
1045 return agp_generic_bind_memory(dev, mem, offset);
1046
1047 if ( sc->chiptype != CHIP_I810 )
1048 return EINVAL;
1049
1050 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1051 bus_write_4(sc->sc_res[0],
1052 AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4, i | 3);
1053 }
1054
1055 return 0;
1056}
1057
1058static int
1059agp_i810_unbind_memory(device_t dev, struct agp_memory *mem)
1060{
1061 struct agp_i810_softc *sc = device_get_softc(dev);
1062 vm_offset_t i;
1063
1064 if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) {
1065 mtx_lock(&sc->agp.as_lock);
1066 if (!mem->am_is_bound) {
1067 mtx_unlock(&sc->agp.as_lock);
1068 return EINVAL;
1069 }
1070
1071 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1072 agp_i810_write_gtt_entry(dev, mem->am_offset + i,
1073 0, 0);
1074 }
1075 agp_flush_cache();
1076 mem->am_is_bound = 0;
1077 mtx_unlock(&sc->agp.as_lock);
1078 return 0;
1079 }
1080
1081 if (mem->am_type != 1)
1082 return agp_generic_unbind_memory(dev, mem);
1083
1084 if ( sc->chiptype != CHIP_I810 )
1085 return EINVAL;
1086
1087 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1088 bus_write_4(sc->sc_res[0],
1089 AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4, 0);
1090 }
1091
1092 return 0;
1093}
1094
1095static device_method_t agp_i810_methods[] = {
1096 /* Device interface */
1097 DEVMETHOD(device_identify, agp_i810_identify),
1098 DEVMETHOD(device_probe, agp_i810_probe),
1099 DEVMETHOD(device_attach, agp_i810_attach),
1100 DEVMETHOD(device_detach, agp_i810_detach),
1101 DEVMETHOD(device_suspend, bus_generic_suspend),
1102 DEVMETHOD(device_resume, agp_i810_resume),
1103
1104 /* AGP interface */
1105 DEVMETHOD(agp_get_aperture, agp_generic_get_aperture),
1106 DEVMETHOD(agp_set_aperture, agp_i810_set_aperture),
1107 DEVMETHOD(agp_bind_page, agp_i810_bind_page),
1108 DEVMETHOD(agp_unbind_page, agp_i810_unbind_page),
1109 DEVMETHOD(agp_flush_tlb, agp_i810_flush_tlb),
1110 DEVMETHOD(agp_enable, agp_i810_enable),
1111 DEVMETHOD(agp_alloc_memory, agp_i810_alloc_memory),
1112 DEVMETHOD(agp_free_memory, agp_i810_free_memory),
1113 DEVMETHOD(agp_bind_memory, agp_i810_bind_memory),
1114 DEVMETHOD(agp_unbind_memory, agp_i810_unbind_memory),
1115
1116 { 0, 0 }
1117};
1118
1119static driver_t agp_i810_driver = {
1120 "agp",
1121 agp_i810_methods,
1122 sizeof(struct agp_i810_softc),
1123};
1124
1125static devclass_t agp_devclass;
1126
1127DRIVER_MODULE(agp_i810, vgapci, agp_i810_driver, agp_devclass, 0, 0);
1128MODULE_DEPEND(agp_i810, agp, 1, 1, 1);
1129MODULE_DEPEND(agp_i810, pci, 1, 1, 1);
| 862{
863 struct agp_i810_softc *sc = device_get_softc(dev);
864
865 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
866 return EINVAL;
867
868 if ( sc->chiptype != CHIP_I810 ) {
869 if ( (offset >> AGP_PAGE_SHIFT) < sc->stolen ) {
870 device_printf(dev, "trying to unbind from stolen memory");
871 return EINVAL;
872 }
873 }
874
875 agp_i810_write_gtt_entry(dev, offset, 0, 0);
876
877 return 0;
878}
879
880/*
881 * Writing via memory mapped registers already flushes all TLBs.
882 */
883static void
884agp_i810_flush_tlb(device_t dev)
885{
886}
887
888static int
889agp_i810_enable(device_t dev, u_int32_t mode)
890{
891
892 return 0;
893}
894
895static struct agp_memory *
896agp_i810_alloc_memory(device_t dev, int type, vm_size_t size)
897{
898 struct agp_i810_softc *sc = device_get_softc(dev);
899 struct agp_memory *mem;
900
901 if ((size & (AGP_PAGE_SIZE - 1)) != 0)
902 return 0;
903
904 if (sc->agp.as_allocated + size > sc->agp.as_maxmem)
905 return 0;
906
907 if (type == 1) {
908 /*
909 * Mapping local DRAM into GATT.
910 */
911 if ( sc->chiptype != CHIP_I810 )
912 return 0;
913 if (size != sc->dcache_size)
914 return 0;
915 } else if (type == 2) {
916 /*
917 * Type 2 is the contiguous physical memory type, that hands
918 * back a physical address. This is used for cursors on i810.
919 * Hand back as many single pages with physical as the user
920 * wants, but only allow one larger allocation (ARGB cursor)
921 * for simplicity.
922 */
923 if (size != AGP_PAGE_SIZE) {
924 if (sc->argb_cursor != NULL)
925 return 0;
926
927 /* Allocate memory for ARGB cursor, if we can. */
928 sc->argb_cursor = contigmalloc(size, M_AGP,
929 0, 0, ~0, PAGE_SIZE, 0);
930 if (sc->argb_cursor == NULL)
931 return 0;
932 }
933 }
934
935 mem = malloc(sizeof *mem, M_AGP, M_WAITOK);
936 mem->am_id = sc->agp.as_nextid++;
937 mem->am_size = size;
938 mem->am_type = type;
939 if (type != 1 && (type != 2 || size == AGP_PAGE_SIZE))
940 mem->am_obj = vm_object_allocate(OBJT_DEFAULT,
941 atop(round_page(size)));
942 else
943 mem->am_obj = 0;
944
945 if (type == 2) {
946 if (size == AGP_PAGE_SIZE) {
947 /*
948 * Allocate and wire down the page now so that we can
949 * get its physical address.
950 */
951 vm_page_t m;
952
953 VM_OBJECT_LOCK(mem->am_obj);
954 m = vm_page_grab(mem->am_obj, 0, VM_ALLOC_NOBUSY |
955 VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_RETRY);
956 VM_OBJECT_UNLOCK(mem->am_obj);
957 mem->am_physical = VM_PAGE_TO_PHYS(m);
958 } else {
959 /* Our allocation is already nicely wired down for us.
960 * Just grab the physical address.
961 */
962 mem->am_physical = vtophys(sc->argb_cursor);
963 }
964 } else {
965 mem->am_physical = 0;
966 }
967
968 mem->am_offset = 0;
969 mem->am_is_bound = 0;
970 TAILQ_INSERT_TAIL(&sc->agp.as_memory, mem, am_link);
971 sc->agp.as_allocated += size;
972
973 return mem;
974}
975
976static int
977agp_i810_free_memory(device_t dev, struct agp_memory *mem)
978{
979 struct agp_i810_softc *sc = device_get_softc(dev);
980
981 if (mem->am_is_bound)
982 return EBUSY;
983
984 if (mem->am_type == 2) {
985 if (mem->am_size == AGP_PAGE_SIZE) {
986 /*
987 * Unwire the page which we wired in alloc_memory.
988 */
989 vm_page_t m;
990
991 VM_OBJECT_LOCK(mem->am_obj);
992 m = vm_page_lookup(mem->am_obj, 0);
993 VM_OBJECT_UNLOCK(mem->am_obj);
994 vm_page_lock_queues();
995 vm_page_unwire(m, 0);
996 vm_page_unlock_queues();
997 } else {
998 contigfree(sc->argb_cursor, mem->am_size, M_AGP);
999 sc->argb_cursor = NULL;
1000 }
1001 }
1002
1003 sc->agp.as_allocated -= mem->am_size;
1004 TAILQ_REMOVE(&sc->agp.as_memory, mem, am_link);
1005 if (mem->am_obj)
1006 vm_object_deallocate(mem->am_obj);
1007 free(mem, M_AGP);
1008 return 0;
1009}
1010
1011static int
1012agp_i810_bind_memory(device_t dev, struct agp_memory *mem,
1013 vm_offset_t offset)
1014{
1015 struct agp_i810_softc *sc = device_get_softc(dev);
1016 vm_offset_t i;
1017
1018 /* Do some sanity checks first. */
1019 if (offset < 0 || (offset & (AGP_PAGE_SIZE - 1)) != 0 ||
1020 offset + mem->am_size > AGP_GET_APERTURE(dev)) {
1021 device_printf(dev, "binding memory at bad offset %#x\n",
1022 (int)offset);
1023 return EINVAL;
1024 }
1025
1026 if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) {
1027 mtx_lock(&sc->agp.as_lock);
1028 if (mem->am_is_bound) {
1029 mtx_unlock(&sc->agp.as_lock);
1030 return EINVAL;
1031 }
1032 /* The memory's already wired down, just stick it in the GTT. */
1033 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1034 agp_i810_write_gtt_entry(dev, offset + i,
1035 mem->am_physical + i, 1);
1036 }
1037 agp_flush_cache();
1038 mem->am_offset = offset;
1039 mem->am_is_bound = 1;
1040 mtx_unlock(&sc->agp.as_lock);
1041 return 0;
1042 }
1043
1044 if (mem->am_type != 1)
1045 return agp_generic_bind_memory(dev, mem, offset);
1046
1047 if ( sc->chiptype != CHIP_I810 )
1048 return EINVAL;
1049
1050 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1051 bus_write_4(sc->sc_res[0],
1052 AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4, i | 3);
1053 }
1054
1055 return 0;
1056}
1057
1058static int
1059agp_i810_unbind_memory(device_t dev, struct agp_memory *mem)
1060{
1061 struct agp_i810_softc *sc = device_get_softc(dev);
1062 vm_offset_t i;
1063
1064 if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) {
1065 mtx_lock(&sc->agp.as_lock);
1066 if (!mem->am_is_bound) {
1067 mtx_unlock(&sc->agp.as_lock);
1068 return EINVAL;
1069 }
1070
1071 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1072 agp_i810_write_gtt_entry(dev, mem->am_offset + i,
1073 0, 0);
1074 }
1075 agp_flush_cache();
1076 mem->am_is_bound = 0;
1077 mtx_unlock(&sc->agp.as_lock);
1078 return 0;
1079 }
1080
1081 if (mem->am_type != 1)
1082 return agp_generic_unbind_memory(dev, mem);
1083
1084 if ( sc->chiptype != CHIP_I810 )
1085 return EINVAL;
1086
1087 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1088 bus_write_4(sc->sc_res[0],
1089 AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4, 0);
1090 }
1091
1092 return 0;
1093}
1094
1095static device_method_t agp_i810_methods[] = {
1096 /* Device interface */
1097 DEVMETHOD(device_identify, agp_i810_identify),
1098 DEVMETHOD(device_probe, agp_i810_probe),
1099 DEVMETHOD(device_attach, agp_i810_attach),
1100 DEVMETHOD(device_detach, agp_i810_detach),
1101 DEVMETHOD(device_suspend, bus_generic_suspend),
1102 DEVMETHOD(device_resume, agp_i810_resume),
1103
1104 /* AGP interface */
1105 DEVMETHOD(agp_get_aperture, agp_generic_get_aperture),
1106 DEVMETHOD(agp_set_aperture, agp_i810_set_aperture),
1107 DEVMETHOD(agp_bind_page, agp_i810_bind_page),
1108 DEVMETHOD(agp_unbind_page, agp_i810_unbind_page),
1109 DEVMETHOD(agp_flush_tlb, agp_i810_flush_tlb),
1110 DEVMETHOD(agp_enable, agp_i810_enable),
1111 DEVMETHOD(agp_alloc_memory, agp_i810_alloc_memory),
1112 DEVMETHOD(agp_free_memory, agp_i810_free_memory),
1113 DEVMETHOD(agp_bind_memory, agp_i810_bind_memory),
1114 DEVMETHOD(agp_unbind_memory, agp_i810_unbind_memory),
1115
1116 { 0, 0 }
1117};
1118
1119static driver_t agp_i810_driver = {
1120 "agp",
1121 agp_i810_methods,
1122 sizeof(struct agp_i810_softc),
1123};
1124
1125static devclass_t agp_devclass;
1126
1127DRIVER_MODULE(agp_i810, vgapci, agp_i810_driver, agp_devclass, 0, 0);
1128MODULE_DEPEND(agp_i810, agp, 1, 1, 1);
1129MODULE_DEPEND(agp_i810, pci, 1, 1, 1);
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