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agp_amd64.c (150645) agp_amd64.c (152435)
1/*-
2 * Copyright (c) 2004, 2005 Jung-uk Kim <jkim@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 11 unchanged lines hidden (view full) ---

20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2004, 2005 Jung-uk Kim <jkim@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 11 unchanged lines hidden (view full) ---

20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/sys/dev/agp/agp_amd64.c 150645 2005-09-27 20:57:50Z jkim $");
28__FBSDID("$FreeBSD: head/sys/dev/agp/agp_amd64.c 152435 2005-11-14 21:54:20Z jkim $");
29
30#include "opt_bus.h"
31
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/malloc.h>
35#include <sys/kernel.h>
36#include <sys/module.h>

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59
60static void agp_amd64_uli_init(device_t);
61static int agp_amd64_uli_set_aperture(device_t, uint32_t);
62
63static int agp_amd64_nvidia_match(uint16_t);
64static void agp_amd64_nvidia_init(device_t);
65static int agp_amd64_nvidia_set_aperture(device_t, uint32_t);
66
29
30#include "opt_bus.h"
31
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/malloc.h>
35#include <sys/kernel.h>
36#include <sys/module.h>

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59
60static void agp_amd64_uli_init(device_t);
61static int agp_amd64_uli_set_aperture(device_t, uint32_t);
62
63static int agp_amd64_nvidia_match(uint16_t);
64static void agp_amd64_nvidia_init(device_t);
65static int agp_amd64_nvidia_set_aperture(device_t, uint32_t);
66
67static int agp_amd64_via_match(void);
68static void agp_amd64_via_init(device_t);
69static int agp_amd64_via_set_aperture(device_t, uint32_t);
70
67MALLOC_DECLARE(M_AGP);
68
69#define AMD64_MAX_MCTRL 8
70
71struct agp_amd64_softc {
72 struct agp_softc agp;
73 uint32_t initial_aperture;
74 struct agp_gatt *gatt;
75 uint32_t apbase;
76 int mctrl[AMD64_MAX_MCTRL];
77 int n_mctrl;
71MALLOC_DECLARE(M_AGP);
72
73#define AMD64_MAX_MCTRL 8
74
75struct agp_amd64_softc {
76 struct agp_softc agp;
77 uint32_t initial_aperture;
78 struct agp_gatt *gatt;
79 uint32_t apbase;
80 int mctrl[AMD64_MAX_MCTRL];
81 int n_mctrl;
82 int via_agp;
78};
79
80static const char*
81agp_amd64_match(device_t dev)
82{
83 if (pci_get_class(dev) != PCIC_BRIDGE
84 || pci_get_subclass(dev) != PCIS_BRIDGE_HOST)
85 return NULL;

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105 case 0x02041106:
106 return ("VIA 8380 host to PCI bridge");
107 case 0x02381106:
108 return ("VIA 3238 host to PCI bridge");
109 case 0x02821106:
110 return ("VIA K8T800Pro host to PCI bridge");
111 case 0x31881106:
112 return ("VIA 8385 host to PCI bridge");
83};
84
85static const char*
86agp_amd64_match(device_t dev)
87{
88 if (pci_get_class(dev) != PCIC_BRIDGE
89 || pci_get_subclass(dev) != PCIS_BRIDGE_HOST)
90 return NULL;

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110 case 0x02041106:
111 return ("VIA 8380 host to PCI bridge");
112 case 0x02381106:
113 return ("VIA 3238 host to PCI bridge");
114 case 0x02821106:
115 return ("VIA K8T800Pro host to PCI bridge");
116 case 0x31881106:
117 return ("VIA 8385 host to PCI bridge");
113 case 0xb1881106:
114 return ("VIA 838X host to PCI bridge");
115 };
116
117 return NULL;
118}
119
120static int
121agp_amd64_nvidia_match(uint16_t devid)
122{
123 /* XXX nForce3 requires secondary AGP bridge at 0:11:0. */
124 if (pci_cfgregread(0, 11, 0, PCIR_CLASS, 1) != PCIC_BRIDGE ||
125 pci_cfgregread(0, 11, 0, PCIR_SUBCLASS, 1) != PCIS_BRIDGE_PCI ||
126 pci_cfgregread(0, 11, 0, PCIR_VENDOR, 2) != 0x10de ||
127 pci_cfgregread(0, 11, 0, PCIR_DEVICE, 2) != devid)
128 return ENXIO;
129
130 return 0;
131}
132
133static int
118 };
119
120 return NULL;
121}
122
123static int
124agp_amd64_nvidia_match(uint16_t devid)
125{
126 /* XXX nForce3 requires secondary AGP bridge at 0:11:0. */
127 if (pci_cfgregread(0, 11, 0, PCIR_CLASS, 1) != PCIC_BRIDGE ||
128 pci_cfgregread(0, 11, 0, PCIR_SUBCLASS, 1) != PCIS_BRIDGE_PCI ||
129 pci_cfgregread(0, 11, 0, PCIR_VENDOR, 2) != 0x10de ||
130 pci_cfgregread(0, 11, 0, PCIR_DEVICE, 2) != devid)
131 return ENXIO;
132
133 return 0;
134}
135
136static int
137agp_amd64_via_match(void)
138{
139 /* XXX Some VIA bridge requires secondary AGP bridge at 0:1:0. */
140 if (pci_cfgregread(0, 1, 0, PCIR_CLASS, 1) != PCIC_BRIDGE ||
141 pci_cfgregread(0, 1, 0, PCIR_SUBCLASS, 1) != PCIS_BRIDGE_PCI ||
142 pci_cfgregread(0, 1, 0, PCIR_VENDOR, 2) != 0x1106 ||
143 pci_cfgregread(0, 1, 0, PCIR_DEVICE, 2) != 0xb188 ||
144 (pci_cfgregread(0, 1, 0, AGP_VIA_AGPSEL, 1) & 2))
145 return 0;
146
147 return 1;
148}
149
150static int
134agp_amd64_probe(device_t dev)
135{
136 const char *desc;
137
138 if (resource_disabled("agp", device_get_unit(dev)))
139 return ENXIO;
140 if ((desc = agp_amd64_match(dev))) {
141 device_verbose(dev);

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173 AGP_AMD64_APBASE, 4) & AGP_AMD64_APBASE_MASK);
174 }
175
176 if ((error = agp_generic_attach(dev)))
177 return error;
178
179 sc->initial_aperture = AGP_GET_APERTURE(dev);
180
151agp_amd64_probe(device_t dev)
152{
153 const char *desc;
154
155 if (resource_disabled("agp", device_get_unit(dev)))
156 return ENXIO;
157 if ((desc = agp_amd64_match(dev))) {
158 device_verbose(dev);

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190 AGP_AMD64_APBASE, 4) & AGP_AMD64_APBASE_MASK);
191 }
192
193 if ((error = agp_generic_attach(dev)))
194 return error;
195
196 sc->initial_aperture = AGP_GET_APERTURE(dev);
197
181 switch (pci_get_vendor(dev)) {
182 case 0x10b9: /* ULi */
183 agp_amd64_uli_init(dev);
184 if (agp_amd64_uli_set_aperture(dev, sc->initial_aperture))
185 return ENXIO;
186 break;
187
188 case 0x10de: /* nVidia */
189 agp_amd64_nvidia_init(dev);
190 if (agp_amd64_nvidia_set_aperture(dev, sc->initial_aperture))
191 return ENXIO;
192 break;
193 }
194
195 for (;;) {
196 gatt = agp_alloc_gatt(dev);
197 if (gatt)
198 break;
199
200 /*
201 * Probably contigmalloc failure. Try reducing the
202 * aperture so that the gatt size reduces.
203 */
204 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) {
205 agp_generic_detach(dev);
206 return ENOMEM;
207 }
208 }
209 sc->gatt = gatt;
210
198 for (;;) {
199 gatt = agp_alloc_gatt(dev);
200 if (gatt)
201 break;
202
203 /*
204 * Probably contigmalloc failure. Try reducing the
205 * aperture so that the gatt size reduces.
206 */
207 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) {
208 agp_generic_detach(dev);
209 return ENOMEM;
210 }
211 }
212 sc->gatt = gatt;
213
214 switch (pci_get_vendor(dev)) {
215 case 0x10b9: /* ULi */
216 agp_amd64_uli_init(dev);
217 if (agp_amd64_uli_set_aperture(dev, sc->initial_aperture))
218 return ENXIO;
219 break;
220
221 case 0x10de: /* nVidia */
222 agp_amd64_nvidia_init(dev);
223 if (agp_amd64_nvidia_set_aperture(dev, sc->initial_aperture))
224 return ENXIO;
225 break;
226
227 case 0x1106: /* VIA */
228 sc->via_agp = agp_amd64_via_match();
229 if (sc->via_agp) {
230 agp_amd64_via_init(dev);
231 if (agp_amd64_via_set_aperture(dev,
232 sc->initial_aperture))
233 return ENXIO;
234 }
235 break;
236 }
237
211 /* Install the gatt and enable aperture. */
212 for (i = 0; i < sc->n_mctrl; i++) {
213 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_ATTBASE,
214 (uint32_t)(gatt->ag_physical >> 8) & AGP_AMD64_ATTBASE_MASK,
215 4);
216 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL,
217 (pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) |
218 AGP_AMD64_APCTRL_GARTEN) &

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294 switch (pci_get_vendor(dev)) {
295 case 0x10b9: /* ULi */
296 return (agp_amd64_uli_set_aperture(dev, aperture));
297 break;
298
299 case 0x10de: /* nVidia */
300 return (agp_amd64_nvidia_set_aperture(dev, aperture));
301 break;
238 /* Install the gatt and enable aperture. */
239 for (i = 0; i < sc->n_mctrl; i++) {
240 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_ATTBASE,
241 (uint32_t)(gatt->ag_physical >> 8) & AGP_AMD64_ATTBASE_MASK,
242 4);
243 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL,
244 (pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) |
245 AGP_AMD64_APCTRL_GARTEN) &

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321 switch (pci_get_vendor(dev)) {
322 case 0x10b9: /* ULi */
323 return (agp_amd64_uli_set_aperture(dev, aperture));
324 break;
325
326 case 0x10de: /* nVidia */
327 return (agp_amd64_nvidia_set_aperture(dev, aperture));
328 break;
329
330 case 0x1106: /* VIA */
331 if (sc->via_agp)
332 return (agp_amd64_via_set_aperture(dev, aperture));
333 break;
302 }
303
304 return 0;
305}
306
307static int
308agp_amd64_bind_page(device_t dev, int offset, vm_offset_t physical)
309{

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422 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT1,
423 sc->apbase + aperture - 1, 4);
424 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT2,
425 sc->apbase + aperture - 1, 4);
426
427 return 0;
428}
429
334 }
335
336 return 0;
337}
338
339static int
340agp_amd64_bind_page(device_t dev, int offset, vm_offset_t physical)
341{

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454 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT1,
455 sc->apbase + aperture - 1, 4);
456 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT2,
457 sc->apbase + aperture - 1, 4);
458
459 return 0;
460}
461
462static void
463agp_amd64_via_init(device_t dev)
464{
465 struct agp_amd64_softc *sc = device_get_softc(dev);
466
467 agp_amd64_apbase_fixup(dev);
468 pci_cfgregwrite(0, 1, 0, AGP3_VIA_ATTBASE, sc->gatt->ag_physical, 4);
469 pci_cfgregwrite(0, 1, 0, AGP3_VIA_GARTCTRL,
470 pci_cfgregread(0, 1, 0, AGP3_VIA_ATTBASE, 4) | 0x180, 4);
471}
472
473static int
474agp_amd64_via_set_aperture(device_t dev, uint32_t aperture)
475{
476 uint32_t apsize;
477
478 apsize = ((aperture - 1) >> 20) ^ 0xff;
479 if ((((apsize ^ 0xff) << 20) | ((1 << 20) - 1)) + 1 != aperture)
480 return EINVAL;
481 pci_cfgregwrite(0, 1, 0, AGP3_VIA_APSIZE, apsize, 1);
482
483 return 0;
484}
485
430static device_method_t agp_amd64_methods[] = {
431 /* Device interface */
432 DEVMETHOD(device_probe, agp_amd64_probe),
433 DEVMETHOD(device_attach, agp_amd64_attach),
434 DEVMETHOD(device_detach, agp_amd64_detach),
435 DEVMETHOD(device_shutdown, bus_generic_shutdown),
436 DEVMETHOD(device_suspend, bus_generic_suspend),
437 DEVMETHOD(device_resume, bus_generic_resume),

--- 27 unchanged lines hidden --- 		486static device_method_t agp_amd64_methods[] = {
487 /* Device interface */
488 DEVMETHOD(device_probe, agp_amd64_probe),
489 DEVMETHOD(device_attach, agp_amd64_attach),
490 DEVMETHOD(device_detach, agp_amd64_detach),
491 DEVMETHOD(device_shutdown, bus_generic_shutdown),
492 DEVMETHOD(device_suspend, bus_generic_suspend),
493 DEVMETHOD(device_resume, bus_generic_resume),

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