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agp_amd64.c (144809) agp_amd64.c (150645)
1/*-
1/*-
2 * Copyright (c) 2004 Jung-uk Kim
2 * Copyright (c) 2004, 2005 Jung-uk Kim <jkim@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright

--- 9 unchanged lines hidden (view full) ---

20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright

--- 9 unchanged lines hidden (view full) ---

20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/sys/dev/agp/agp_amd64.c 144809 2005-04-08 18:04:39Z obrien $");
28__FBSDID("$FreeBSD: head/sys/dev/agp/agp_amd64.c 150645 2005-09-27 20:57:50Z jkim $");
29
30#include "opt_bus.h"
31
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/malloc.h>
35#include <sys/kernel.h>
36#include <sys/module.h>

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50#include <machine/bus.h>
51#include <machine/resource.h>
52#include <sys/rman.h>
53
54/* XXX */
55extern void pci_cfgregwrite(int, int, int, int, uint32_t, int);
56extern uint32_t pci_cfgregread(int, int, int, int, int);
57
29
30#include "opt_bus.h"
31
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/malloc.h>
35#include <sys/kernel.h>
36#include <sys/module.h>

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50#include <machine/bus.h>
51#include <machine/resource.h>
52#include <sys/rman.h>
53
54/* XXX */
55extern void pci_cfgregwrite(int, int, int, int, uint32_t, int);
56extern uint32_t pci_cfgregread(int, int, int, int, int);
57
58static void agp_amd64_apbase_fixup(device_t);
59
60static void agp_amd64_uli_init(device_t);
61static int agp_amd64_uli_set_aperture(device_t, uint32_t);
62
63static int agp_amd64_nvidia_match(uint16_t);
64static void agp_amd64_nvidia_init(device_t);
65static int agp_amd64_nvidia_set_aperture(device_t, uint32_t);
66
58MALLOC_DECLARE(M_AGP);
59
60#define AMD64_MAX_MCTRL 8
61
62struct agp_amd64_softc {
63 struct agp_softc agp;
67MALLOC_DECLARE(M_AGP);
68
69#define AMD64_MAX_MCTRL 8
70
71struct agp_amd64_softc {
72 struct agp_softc agp;
64 uint32_t initial_aperture; /* aperture size at startup */
65 struct agp_gatt *gatt;
66 int mctrl[AMD64_MAX_MCTRL];
67 int n_mctrl;
73 uint32_t initial_aperture;
74 struct agp_gatt *gatt;
75 uint32_t apbase;
76 int mctrl[AMD64_MAX_MCTRL];
77 int n_mctrl;
68};
69
70static const char*
71agp_amd64_match(device_t dev)
72{
73 if (pci_get_class(dev) != PCIC_BRIDGE
74 || pci_get_subclass(dev) != PCIS_BRIDGE_HOST)
75 return NULL;
76
77 if (agp_find_caps(dev) == 0)
78 return NULL;
79
80 switch (pci_get_devid(dev)) {
81 case 0x74541022:
82 return ("AMD 8151 AGP graphics tunnel");
83 case 0x07551039:
84 return ("SiS 755 host to AGP bridge");
78};
79
80static const char*
81agp_amd64_match(device_t dev)
82{
83 if (pci_get_class(dev) != PCIC_BRIDGE
84 || pci_get_subclass(dev) != PCIS_BRIDGE_HOST)
85 return NULL;
86
87 if (agp_find_caps(dev) == 0)
88 return NULL;
89
90 switch (pci_get_devid(dev)) {
91 case 0x74541022:
92 return ("AMD 8151 AGP graphics tunnel");
93 case 0x07551039:
94 return ("SiS 755 host to AGP bridge");
95 case 0x168910b9:
96 return ("ULi M1689 AGP Controller");
85 case 0x00d110de:
97 case 0x00d110de:
98 if (agp_amd64_nvidia_match(0x00d2))
99 return NULL;
86 return ("NVIDIA nForce3 AGP Controller");
87 case 0x00e110de:
100 return ("NVIDIA nForce3 AGP Controller");
101 case 0x00e110de:
102 if (agp_amd64_nvidia_match(0x00e2))
103 return NULL;
88 return ("NVIDIA nForce3-250 AGP Controller");
89 case 0x02041106:
90 return ("VIA 8380 host to PCI bridge");
104 return ("NVIDIA nForce3-250 AGP Controller");
105 case 0x02041106:
106 return ("VIA 8380 host to PCI bridge");
107 case 0x02381106:
108 return ("VIA 3238 host to PCI bridge");
91 case 0x02821106:
92 return ("VIA K8T800Pro host to PCI bridge");
93 case 0x31881106:
94 return ("VIA 8385 host to PCI bridge");
109 case 0x02821106:
110 return ("VIA K8T800Pro host to PCI bridge");
111 case 0x31881106:
112 return ("VIA 8385 host to PCI bridge");
113 case 0xb1881106:
114 return ("VIA 838X host to PCI bridge");
95 };
96
97 return NULL;
98}
99
100static int
115 };
116
117 return NULL;
118}
119
120static int
121agp_amd64_nvidia_match(uint16_t devid)
122{
123 /* XXX nForce3 requires secondary AGP bridge at 0:11:0. */
124 if (pci_cfgregread(0, 11, 0, PCIR_CLASS, 1) != PCIC_BRIDGE ||
125 pci_cfgregread(0, 11, 0, PCIR_SUBCLASS, 1) != PCIS_BRIDGE_PCI ||
126 pci_cfgregread(0, 11, 0, PCIR_VENDOR, 2) != 0x10de ||
127 pci_cfgregread(0, 11, 0, PCIR_DEVICE, 2) != devid)
128 return ENXIO;
129
130 return 0;
131}
132
133static int
101agp_amd64_probe(device_t dev)
102{
103 const char *desc;
104
105 if (resource_disabled("agp", device_get_unit(dev)))
106 return ENXIO;
107 if ((desc = agp_amd64_match(dev))) {
108 device_verbose(dev);

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126 n++;
127 }
128
129 if (n == 0)
130 return ENXIO;
131
132 sc->n_mctrl = n;
133
134agp_amd64_probe(device_t dev)
135{
136 const char *desc;
137
138 if (resource_disabled("agp", device_get_unit(dev)))
139 return ENXIO;
140 if ((desc = agp_amd64_match(dev))) {
141 device_verbose(dev);

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159 n++;
160 }
161
162 if (n == 0)
163 return ENXIO;
164
165 sc->n_mctrl = n;
166
134 if (bootverbose)
135 printf("AMD64: %d Misc. Control unit(s) found.\n", sc->n_mctrl);
167 if (bootverbose) {
168 device_printf(dev, "%d Miscellaneous Control unit(s) found.\n",
169 sc->n_mctrl);
170 for (i = 0; i < sc->n_mctrl; i++)
171 device_printf(dev, "Aperture Base[%d]: 0x%08x\n", i,
172 pci_cfgregread(0, sc->mctrl[i], 3,
173 AGP_AMD64_APBASE, 4) & AGP_AMD64_APBASE_MASK);
174 }
136
137 if ((error = agp_generic_attach(dev)))
138 return error;
139
140 sc->initial_aperture = AGP_GET_APERTURE(dev);
141
175
176 if ((error = agp_generic_attach(dev)))
177 return error;
178
179 sc->initial_aperture = AGP_GET_APERTURE(dev);
180
181 switch (pci_get_vendor(dev)) {
182 case 0x10b9: /* ULi */
183 agp_amd64_uli_init(dev);
184 if (agp_amd64_uli_set_aperture(dev, sc->initial_aperture))
185 return ENXIO;
186 break;
187
188 case 0x10de: /* nVidia */
189 agp_amd64_nvidia_init(dev);
190 if (agp_amd64_nvidia_set_aperture(dev, sc->initial_aperture))
191 return ENXIO;
192 break;
193 }
194
142 for (;;) {
143 gatt = agp_alloc_gatt(dev);
144 if (gatt)
145 break;
146
147 /*
148 * Probably contigmalloc failure. Try reducing the
149 * aperture so that the gatt size reduces.

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225{
226 struct agp_amd64_softc *sc = device_get_softc(dev);
227 uint32_t i;
228 int j;
229
230 for (i = 0; i < AGP_AMD64_TABLE_SIZE; i++)
231 if (agp_amd64_table[i] == aperture)
232 break;
195 for (;;) {
196 gatt = agp_alloc_gatt(dev);
197 if (gatt)
198 break;
199
200 /*
201 * Probably contigmalloc failure. Try reducing the
202 * aperture so that the gatt size reduces.

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278{
279 struct agp_amd64_softc *sc = device_get_softc(dev);
280 uint32_t i;
281 int j;
282
283 for (i = 0; i < AGP_AMD64_TABLE_SIZE; i++)
284 if (agp_amd64_table[i] == aperture)
285 break;
233 if (i == AGP_AMD64_TABLE_SIZE)
286 if (i >= AGP_AMD64_TABLE_SIZE)
234 return EINVAL;
235
236 for (j = 0; j < sc->n_mctrl; j++)
237 pci_cfgregwrite(0, sc->mctrl[j], 3, AGP_AMD64_APCTRL,
238 (pci_cfgregread(0, sc->mctrl[j], 3, AGP_AMD64_APCTRL, 4) &
239 ~(AGP_AMD64_APCTRL_SIZE_MASK)) | (i << 1), 4);
240
287 return EINVAL;
288
289 for (j = 0; j < sc->n_mctrl; j++)
290 pci_cfgregwrite(0, sc->mctrl[j], 3, AGP_AMD64_APCTRL,
291 (pci_cfgregread(0, sc->mctrl[j], 3, AGP_AMD64_APCTRL, 4) &
292 ~(AGP_AMD64_APCTRL_SIZE_MASK)) | (i << 1), 4);
293
294 switch (pci_get_vendor(dev)) {
295 case 0x10b9: /* ULi */
296 return (agp_amd64_uli_set_aperture(dev, aperture));
297 break;
298
299 case 0x10de: /* nVidia */
300 return (agp_amd64_nvidia_set_aperture(dev, aperture));
301 break;
302 }
303
241 return 0;
242}
243
244static int
245agp_amd64_bind_page(device_t dev, int offset, vm_offset_t physical)
246{
247 struct agp_amd64_softc *sc = device_get_softc(dev);
248

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272 int i;
273
274 for (i = 0; i < sc->n_mctrl; i++)
275 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL,
276 pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL, 4) |
277 AGP_AMD64_CACHECTRL_INVGART, 4);
278}
279
304 return 0;
305}
306
307static int
308agp_amd64_bind_page(device_t dev, int offset, vm_offset_t physical)
309{
310 struct agp_amd64_softc *sc = device_get_softc(dev);
311

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335 int i;
336
337 for (i = 0; i < sc->n_mctrl; i++)
338 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL,
339 pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL, 4) |
340 AGP_AMD64_CACHECTRL_INVGART, 4);
341}
342
343static void
344agp_amd64_apbase_fixup(device_t dev)
345{
346 struct agp_amd64_softc *sc = device_get_softc(dev);
347 uint32_t apbase;
348 int i;
349
350 apbase = pci_cfgregread(0, sc->mctrl[0], 3, AGP_AMD64_APBASE, 4);
351 for (i = 0; i < sc->n_mctrl; i++)
352 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APBASE,
353 apbase & ~(AGP_AMD64_APBASE_MASK & ~(uint32_t)0x7f), 4);
354 sc->apbase = apbase << 25;
355}
356
357static void
358agp_amd64_uli_init(device_t dev)
359{
360 struct agp_amd64_softc *sc = device_get_softc(dev);
361
362 agp_amd64_apbase_fixup(dev);
363 pci_write_config(dev, AGP_AMD64_ULI_APBASE,
364 (pci_read_config(dev, AGP_AMD64_ULI_APBASE, 4) & 0x0000000f) |
365 sc->apbase, 4);
366 pci_write_config(dev, AGP_AMD64_ULI_HTT_FEATURE, sc->apbase, 4);
367}
368
369static int
370agp_amd64_uli_set_aperture(device_t dev, uint32_t aperture)
371{
372 struct agp_amd64_softc *sc = device_get_softc(dev);
373
374 switch (aperture) {
375 case 0x02000000: /* 32 MB */
376 case 0x04000000: /* 64 MB */
377 case 0x08000000: /* 128 MB */
378 case 0x10000000: /* 256 MB */
379 break;
380 default:
381 return EINVAL;
382 }
383
384 pci_write_config(dev, AGP_AMD64_ULI_ENU_SCR,
385 sc->apbase + aperture - 1, 4);
386
387 return 0;
388}
389
390static void
391agp_amd64_nvidia_init(device_t dev)
392{
393 struct agp_amd64_softc *sc = device_get_softc(dev);
394
395 agp_amd64_apbase_fixup(dev);
396 pci_write_config(dev, AGP_AMD64_NVIDIA_0_APBASE,
397 (pci_read_config(dev, AGP_AMD64_NVIDIA_0_APBASE, 4) & 0x0000000f) |
398 sc->apbase, 4);
399 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APBASE1, sc->apbase, 4);
400 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APBASE2, sc->apbase, 4);
401}
402
403static int
404agp_amd64_nvidia_set_aperture(device_t dev, uint32_t aperture)
405{
406 struct agp_amd64_softc *sc = device_get_softc(dev);
407 uint32_t apsize;
408
409 switch (aperture) {
410 case 0x02000000: apsize = 0x0f; break; /* 32 MB */
411 case 0x04000000: apsize = 0x0e; break; /* 64 MB */
412 case 0x08000000: apsize = 0x0c; break; /* 128 MB */
413 case 0x10000000: apsize = 0x08; break; /* 256 MB */
414 case 0x20000000: apsize = 0x00; break; /* 512 MB */
415 default:
416 return EINVAL;
417 }
418
419 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APSIZE,
420 (pci_cfgregread(0, 11, 0, AGP_AMD64_NVIDIA_1_APSIZE, 4) &
421 0xfffffff0) | apsize, 4);
422 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT1,
423 sc->apbase + aperture - 1, 4);
424 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT2,
425 sc->apbase + aperture - 1, 4);
426
427 return 0;
428}
429
280static device_method_t agp_amd64_methods[] = {
281 /* Device interface */
282 DEVMETHOD(device_probe, agp_amd64_probe),
283 DEVMETHOD(device_attach, agp_amd64_attach),
284 DEVMETHOD(device_detach, agp_amd64_detach),
285 DEVMETHOD(device_shutdown, bus_generic_shutdown),
286 DEVMETHOD(device_suspend, bus_generic_suspend),
287 DEVMETHOD(device_resume, bus_generic_resume),

--- 27 unchanged lines hidden --- 		430static device_method_t agp_amd64_methods[] = {
431 /* Device interface */
432 DEVMETHOD(device_probe, agp_amd64_probe),
433 DEVMETHOD(device_attach, agp_amd64_attach),
434 DEVMETHOD(device_detach, agp_amd64_detach),
435 DEVMETHOD(device_shutdown, bus_generic_shutdown),
436 DEVMETHOD(device_suspend, bus_generic_suspend),
437 DEVMETHOD(device_resume, bus_generic_resume),

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