2c2
< * Copyright (c) 2004 Jung-uk Kim
---
> * Copyright (c) 2004, 2005 Jung-uk Kim <jkim@FreeBSD.org>
28c28
< __FBSDID("$FreeBSD: head/sys/dev/agp/agp_amd64.c 144809 2005-04-08 18:04:39Z obrien $");
---
> __FBSDID("$FreeBSD: head/sys/dev/agp/agp_amd64.c 150645 2005-09-27 20:57:50Z jkim $");
57a58,66
> static void agp_amd64_apbase_fixup(device_t);
>
> static void agp_amd64_uli_init(device_t);
> static int agp_amd64_uli_set_aperture(device_t, uint32_t);
>
> static int agp_amd64_nvidia_match(uint16_t);
> static void agp_amd64_nvidia_init(device_t);
> static int agp_amd64_nvidia_set_aperture(device_t, uint32_t);
>
64,67c73,77
< uint32_t initial_aperture; /* aperture size at startup */
< struct agp_gatt *gatt;
< int mctrl[AMD64_MAX_MCTRL];
< int n_mctrl;
---
> uint32_t initial_aperture;
> struct agp_gatt *gatt;
> uint32_t apbase;
> int mctrl[AMD64_MAX_MCTRL];
> int n_mctrl;
84a95,96
> case 0x168910b9:
> return ("ULi M1689 AGP Controller");
85a98,99
> if (agp_amd64_nvidia_match(0x00d2))
> return NULL;
87a102,103
> if (agp_amd64_nvidia_match(0x00e2))
> return NULL;
90a107,108
> case 0x02381106:
> return ("VIA 3238 host to PCI bridge");
94a113,114
> case 0xb1881106:
> return ("VIA 838X host to PCI bridge");
100a121,133
> agp_amd64_nvidia_match(uint16_t devid)
> {
> /* XXX nForce3 requires secondary AGP bridge at 0:11:0. */
> if (pci_cfgregread(0, 11, 0, PCIR_CLASS, 1) != PCIC_BRIDGE ||
> pci_cfgregread(0, 11, 0, PCIR_SUBCLASS, 1) != PCIS_BRIDGE_PCI ||
> pci_cfgregread(0, 11, 0, PCIR_VENDOR, 2) != 0x10de ||
> pci_cfgregread(0, 11, 0, PCIR_DEVICE, 2) != devid)
> return ENXIO;
>
> return 0;
> }
>
> static int
134,135c167,174
< if (bootverbose)
< printf("AMD64: %d Misc. Control unit(s) found.\n", sc->n_mctrl);
---
> if (bootverbose) {
> device_printf(dev, "%d Miscellaneous Control unit(s) found.\n",
> sc->n_mctrl);
> for (i = 0; i < sc->n_mctrl; i++)
> device_printf(dev, "Aperture Base[%d]: 0x%08x\n", i,
> pci_cfgregread(0, sc->mctrl[i], 3,
> AGP_AMD64_APBASE, 4) & AGP_AMD64_APBASE_MASK);
> }
141a181,194
> switch (pci_get_vendor(dev)) {
> case 0x10b9: /* ULi */
> agp_amd64_uli_init(dev);
> if (agp_amd64_uli_set_aperture(dev, sc->initial_aperture))
> return ENXIO;
> break;
>
> case 0x10de: /* nVidia */
> agp_amd64_nvidia_init(dev);
> if (agp_amd64_nvidia_set_aperture(dev, sc->initial_aperture))
> return ENXIO;
> break;
> }
>
233c286
< if (i == AGP_AMD64_TABLE_SIZE)
---
> if (i >= AGP_AMD64_TABLE_SIZE)
240a294,303
> switch (pci_get_vendor(dev)) {
> case 0x10b9: /* ULi */
> return (agp_amd64_uli_set_aperture(dev, aperture));
> break;
>
> case 0x10de: /* nVidia */
> return (agp_amd64_nvidia_set_aperture(dev, aperture));
> break;
> }
>
279a343,429
> static void
> agp_amd64_apbase_fixup(device_t dev)
> {
> struct agp_amd64_softc *sc = device_get_softc(dev);
> uint32_t apbase;
> int i;
>
> apbase = pci_cfgregread(0, sc->mctrl[0], 3, AGP_AMD64_APBASE, 4);
> for (i = 0; i < sc->n_mctrl; i++)
> pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APBASE,
> apbase & ~(AGP_AMD64_APBASE_MASK & ~(uint32_t)0x7f), 4);
> sc->apbase = apbase << 25;
> }
>
> static void
> agp_amd64_uli_init(device_t dev)
> {
> struct agp_amd64_softc *sc = device_get_softc(dev);
>
> agp_amd64_apbase_fixup(dev);
> pci_write_config(dev, AGP_AMD64_ULI_APBASE,
> (pci_read_config(dev, AGP_AMD64_ULI_APBASE, 4) & 0x0000000f) |
> sc->apbase, 4);
> pci_write_config(dev, AGP_AMD64_ULI_HTT_FEATURE, sc->apbase, 4);
> }
>
> static int
> agp_amd64_uli_set_aperture(device_t dev, uint32_t aperture)
> {
> struct agp_amd64_softc *sc = device_get_softc(dev);
>
> switch (aperture) {
> case 0x02000000: /* 32 MB */
> case 0x04000000: /* 64 MB */
> case 0x08000000: /* 128 MB */
> case 0x10000000: /* 256 MB */
> break;
> default:
> return EINVAL;
> }
>
> pci_write_config(dev, AGP_AMD64_ULI_ENU_SCR,
> sc->apbase + aperture - 1, 4);
>
> return 0;
> }
>
> static void
> agp_amd64_nvidia_init(device_t dev)
> {
> struct agp_amd64_softc *sc = device_get_softc(dev);
>
> agp_amd64_apbase_fixup(dev);
> pci_write_config(dev, AGP_AMD64_NVIDIA_0_APBASE,
> (pci_read_config(dev, AGP_AMD64_NVIDIA_0_APBASE, 4) & 0x0000000f) |
> sc->apbase, 4);
> pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APBASE1, sc->apbase, 4);
> pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APBASE2, sc->apbase, 4);
> }
>
> static int
> agp_amd64_nvidia_set_aperture(device_t dev, uint32_t aperture)
> {
> struct agp_amd64_softc *sc = device_get_softc(dev);
> uint32_t apsize;
>
> switch (aperture) {
> case 0x02000000: apsize = 0x0f; break; /* 32 MB */
> case 0x04000000: apsize = 0x0e; break; /* 64 MB */
> case 0x08000000: apsize = 0x0c; break; /* 128 MB */
> case 0x10000000: apsize = 0x08; break; /* 256 MB */
> case 0x20000000: apsize = 0x00; break; /* 512 MB */
> default:
> return EINVAL;
> }
>
> pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APSIZE,
> (pci_cfgregread(0, 11, 0, AGP_AMD64_NVIDIA_1_APSIZE, 4) &
> 0xfffffff0) | apsize, 4);
> pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT1,
> sc->apbase + aperture - 1, 4);
> pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT2,
> sc->apbase + aperture - 1, 4);
>
> return 0;
> }
>