1/*-
2 * Copyright (c) 2004, 2005 Jung-uk Kim <jkim@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
| 1/*-
2 * Copyright (c) 2004, 2005 Jung-uk Kim <jkim@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
|
28__FBSDID("$FreeBSD: head/sys/dev/agp/agp_amd64.c 187100 2009-01-12 16:07:03Z jkim $");
| 28__FBSDID("$FreeBSD: head/sys/dev/agp/agp_amd64.c 189578 2009-03-09 13:27:33Z imp $");
|
29
30#include "opt_bus.h"
31
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/malloc.h>
35#include <sys/kernel.h>
36#include <sys/module.h>
37#include <sys/bus.h>
38#include <sys/lock.h>
39#include <sys/mutex.h>
40#include <sys/proc.h>
41
42#include <dev/agp/agppriv.h>
43#include <dev/agp/agpreg.h>
44#include <dev/pci/pcivar.h>
45#include <dev/pci/pcireg.h>
46
47#include <vm/vm.h>
48#include <vm/vm_object.h>
49#include <vm/pmap.h>
50#include <machine/bus.h>
51#include <machine/resource.h>
52#include <sys/rman.h>
53
54/* XXX */
55extern void pci_cfgregwrite(int, int, int, int, uint32_t, int);
56extern uint32_t pci_cfgregread(int, int, int, int, int);
57
58static void agp_amd64_apbase_fixup(device_t);
59
60static void agp_amd64_uli_init(device_t);
61static int agp_amd64_uli_set_aperture(device_t, uint32_t);
62
63static int agp_amd64_nvidia_match(uint16_t);
64static void agp_amd64_nvidia_init(device_t);
65static int agp_amd64_nvidia_set_aperture(device_t, uint32_t);
66
67static int agp_amd64_via_match(void);
68static void agp_amd64_via_init(device_t);
69static int agp_amd64_via_set_aperture(device_t, uint32_t);
70
71MALLOC_DECLARE(M_AGP);
72
73#define AMD64_MAX_MCTRL 8
74
75struct agp_amd64_softc {
76 struct agp_softc agp;
77 uint32_t initial_aperture;
78 struct agp_gatt *gatt;
79 uint32_t apbase;
80 int mctrl[AMD64_MAX_MCTRL];
81 int n_mctrl;
82 int via_agp;
83};
84
85static const char*
86agp_amd64_match(device_t dev)
87{
88 if (pci_get_class(dev) != PCIC_BRIDGE ||
89 pci_get_subclass(dev) != PCIS_BRIDGE_HOST ||
90 agp_find_caps(dev) == 0)
91 return (NULL);
92
93 switch (pci_get_devid(dev)) {
94 case 0x74541022:
95 return ("AMD 8151 AGP graphics tunnel");
96 case 0x07551039:
97 return ("SiS 755 host to AGP bridge");
98 case 0x07601039:
99 return ("SiS 760 host to AGP bridge");
100 case 0x168910b9:
101 return ("ULi M1689 AGP Controller");
102 case 0x00d110de:
103 if (agp_amd64_nvidia_match(0x00d2))
104 return (NULL);
105 return ("NVIDIA nForce3 AGP Controller");
106 case 0x00e110de:
107 if (agp_amd64_nvidia_match(0x00e2))
108 return (NULL);
109 return ("NVIDIA nForce3-250 AGP Controller");
110 case 0x02041106:
111 return ("VIA 8380 host to PCI bridge");
112 case 0x02381106:
113 return ("VIA 3238 host to PCI bridge");
114 case 0x02821106:
115 return ("VIA K8T800Pro host to PCI bridge");
116 case 0x31881106:
117 return ("VIA 8385 host to PCI bridge");
118 };
119
120 return (NULL);
121}
122
123static int
124agp_amd64_nvidia_match(uint16_t devid)
125{
126 /* XXX nForce3 requires secondary AGP bridge at 0:11:0. */
127 if (pci_cfgregread(0, 11, 0, PCIR_CLASS, 1) != PCIC_BRIDGE ||
128 pci_cfgregread(0, 11, 0, PCIR_SUBCLASS, 1) != PCIS_BRIDGE_PCI ||
129 pci_cfgregread(0, 11, 0, PCIR_VENDOR, 2) != 0x10de ||
130 pci_cfgregread(0, 11, 0, PCIR_DEVICE, 2) != devid)
131 return (ENXIO);
132
133 return (0);
134}
135
136static int
137agp_amd64_via_match(void)
138{
139 /* XXX Some VIA bridge requires secondary AGP bridge at 0:1:0. */
140 if (pci_cfgregread(0, 1, 0, PCIR_CLASS, 1) != PCIC_BRIDGE ||
141 pci_cfgregread(0, 1, 0, PCIR_SUBCLASS, 1) != PCIS_BRIDGE_PCI ||
142 pci_cfgregread(0, 1, 0, PCIR_VENDOR, 2) != 0x1106 ||
143 pci_cfgregread(0, 1, 0, PCIR_DEVICE, 2) != 0xb188 ||
144 (pci_cfgregread(0, 1, 0, AGP_VIA_AGPSEL, 1) & 2))
145 return (0);
146
147 return (1);
148}
149
150static int
151agp_amd64_probe(device_t dev)
152{
153 const char *desc;
154
155 if (resource_disabled("agp", device_get_unit(dev)))
156 return (ENXIO);
157 if ((desc = agp_amd64_match(dev))) {
158 device_set_desc(dev, desc);
159 return (BUS_PROBE_DEFAULT);
160 }
161
162 return (ENXIO);
163}
164
165static int
166agp_amd64_attach(device_t dev)
167{
168 struct agp_amd64_softc *sc = device_get_softc(dev);
169 struct agp_gatt *gatt;
170 uint32_t devid;
171 int i, n, error;
172
173 for (i = 0, n = 0; i < PCI_SLOTMAX && n < AMD64_MAX_MCTRL; i++) {
174 devid = pci_cfgregread(0, i, 3, 0, 4);
175 if (devid == 0x11031022 || devid == 0x12031022) {
176 sc->mctrl[n] = i;
177 n++;
178 }
179 }
180 if (n == 0)
181 return (ENXIO);
182
183 sc->n_mctrl = n;
184
185 if (bootverbose)
186 device_printf(dev, "%d Miscellaneous Control unit(s) found.\n",
187 sc->n_mctrl);
188
189 if ((error = agp_generic_attach(dev)))
190 return (error);
191
192 sc->initial_aperture = AGP_GET_APERTURE(dev);
193
194 for (;;) {
195 gatt = agp_alloc_gatt(dev);
196 if (gatt)
197 break;
198
199 /*
200 * Probably contigmalloc failure. Try reducing the
201 * aperture so that the gatt size reduces.
202 */
203 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) {
204 agp_generic_detach(dev);
205 return (ENOMEM);
206 }
207 }
208 sc->gatt = gatt;
209
210 switch (pci_get_vendor(dev)) {
211 case 0x10b9: /* ULi */
212 agp_amd64_uli_init(dev);
213 if (agp_amd64_uli_set_aperture(dev, sc->initial_aperture))
214 return (ENXIO);
215 break;
216
217 case 0x10de: /* nVidia */
218 agp_amd64_nvidia_init(dev);
219 if (agp_amd64_nvidia_set_aperture(dev, sc->initial_aperture))
220 return (ENXIO);
221 break;
222
223 case 0x1106: /* VIA */
224 sc->via_agp = agp_amd64_via_match();
225 if (sc->via_agp) {
226 agp_amd64_via_init(dev);
227 if (agp_amd64_via_set_aperture(dev,
228 sc->initial_aperture))
229 return (ENXIO);
230 }
231 break;
232 }
233
234 /* Install the gatt and enable aperture. */
235 for (i = 0; i < sc->n_mctrl; i++) {
236 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_ATTBASE,
237 (uint32_t)(gatt->ag_physical >> 8) & AGP_AMD64_ATTBASE_MASK,
238 4);
239 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL,
240 (pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) |
241 AGP_AMD64_APCTRL_GARTEN) &
242 ~(AGP_AMD64_APCTRL_DISGARTCPU | AGP_AMD64_APCTRL_DISGARTIO),
243 4);
244 }
245
246 agp_flush_cache();
247
248 return (0);
249}
250
251static int
252agp_amd64_detach(device_t dev)
253{
254 struct agp_amd64_softc *sc = device_get_softc(dev);
255 int i;
256
257 agp_free_cdev(dev);
258
259 for (i = 0; i < sc->n_mctrl; i++)
260 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL,
261 pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) &
262 ~AGP_AMD64_APCTRL_GARTEN, 4);
263
264 AGP_SET_APERTURE(dev, sc->initial_aperture);
265 agp_free_gatt(sc->gatt);
266 agp_free_res(dev);
267
268 return (0);
269}
270
271static uint32_t agp_amd64_table[] = {
272 0x02000000, /* 32 MB */
273 0x04000000, /* 64 MB */
274 0x08000000, /* 128 MB */
275 0x10000000, /* 256 MB */
276 0x20000000, /* 512 MB */
277 0x40000000, /* 1024 MB */
278 0x80000000, /* 2048 MB */
279};
280
281#define AGP_AMD64_TABLE_SIZE \
282 (sizeof(agp_amd64_table) / sizeof(agp_amd64_table[0]))
283
284static uint32_t
285agp_amd64_get_aperture(device_t dev)
286{
287 struct agp_amd64_softc *sc = device_get_softc(dev);
288 uint32_t i;
289
290 i = (pci_cfgregread(0, sc->mctrl[0], 3, AGP_AMD64_APCTRL, 4) &
291 AGP_AMD64_APCTRL_SIZE_MASK) >> 1;
292
293 if (i >= AGP_AMD64_TABLE_SIZE)
294 return (0);
295
296 return (agp_amd64_table[i]);
297}
298
299static int
300agp_amd64_set_aperture(device_t dev, uint32_t aperture)
301{
302 struct agp_amd64_softc *sc = device_get_softc(dev);
303 uint32_t i;
304 int j;
305
306 for (i = 0; i < AGP_AMD64_TABLE_SIZE; i++)
307 if (agp_amd64_table[i] == aperture)
308 break;
309 if (i >= AGP_AMD64_TABLE_SIZE)
310 return (EINVAL);
311
312 for (j = 0; j < sc->n_mctrl; j++)
313 pci_cfgregwrite(0, sc->mctrl[j], 3, AGP_AMD64_APCTRL,
314 (pci_cfgregread(0, sc->mctrl[j], 3, AGP_AMD64_APCTRL, 4) &
315 ~(AGP_AMD64_APCTRL_SIZE_MASK)) | (i << 1), 4);
316
317 switch (pci_get_vendor(dev)) {
318 case 0x10b9: /* ULi */
319 return (agp_amd64_uli_set_aperture(dev, aperture));
320 break;
321
322 case 0x10de: /* nVidia */
323 return (agp_amd64_nvidia_set_aperture(dev, aperture));
324 break;
325
326 case 0x1106: /* VIA */
327 if (sc->via_agp)
328 return (agp_amd64_via_set_aperture(dev, aperture));
329 break;
330 }
331
332 return (0);
333}
334
335static int
| 29
30#include "opt_bus.h"
31
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/malloc.h>
35#include <sys/kernel.h>
36#include <sys/module.h>
37#include <sys/bus.h>
38#include <sys/lock.h>
39#include <sys/mutex.h>
40#include <sys/proc.h>
41
42#include <dev/agp/agppriv.h>
43#include <dev/agp/agpreg.h>
44#include <dev/pci/pcivar.h>
45#include <dev/pci/pcireg.h>
46
47#include <vm/vm.h>
48#include <vm/vm_object.h>
49#include <vm/pmap.h>
50#include <machine/bus.h>
51#include <machine/resource.h>
52#include <sys/rman.h>
53
54/* XXX */
55extern void pci_cfgregwrite(int, int, int, int, uint32_t, int);
56extern uint32_t pci_cfgregread(int, int, int, int, int);
57
58static void agp_amd64_apbase_fixup(device_t);
59
60static void agp_amd64_uli_init(device_t);
61static int agp_amd64_uli_set_aperture(device_t, uint32_t);
62
63static int agp_amd64_nvidia_match(uint16_t);
64static void agp_amd64_nvidia_init(device_t);
65static int agp_amd64_nvidia_set_aperture(device_t, uint32_t);
66
67static int agp_amd64_via_match(void);
68static void agp_amd64_via_init(device_t);
69static int agp_amd64_via_set_aperture(device_t, uint32_t);
70
71MALLOC_DECLARE(M_AGP);
72
73#define AMD64_MAX_MCTRL 8
74
75struct agp_amd64_softc {
76 struct agp_softc agp;
77 uint32_t initial_aperture;
78 struct agp_gatt *gatt;
79 uint32_t apbase;
80 int mctrl[AMD64_MAX_MCTRL];
81 int n_mctrl;
82 int via_agp;
83};
84
85static const char*
86agp_amd64_match(device_t dev)
87{
88 if (pci_get_class(dev) != PCIC_BRIDGE ||
89 pci_get_subclass(dev) != PCIS_BRIDGE_HOST ||
90 agp_find_caps(dev) == 0)
91 return (NULL);
92
93 switch (pci_get_devid(dev)) {
94 case 0x74541022:
95 return ("AMD 8151 AGP graphics tunnel");
96 case 0x07551039:
97 return ("SiS 755 host to AGP bridge");
98 case 0x07601039:
99 return ("SiS 760 host to AGP bridge");
100 case 0x168910b9:
101 return ("ULi M1689 AGP Controller");
102 case 0x00d110de:
103 if (agp_amd64_nvidia_match(0x00d2))
104 return (NULL);
105 return ("NVIDIA nForce3 AGP Controller");
106 case 0x00e110de:
107 if (agp_amd64_nvidia_match(0x00e2))
108 return (NULL);
109 return ("NVIDIA nForce3-250 AGP Controller");
110 case 0x02041106:
111 return ("VIA 8380 host to PCI bridge");
112 case 0x02381106:
113 return ("VIA 3238 host to PCI bridge");
114 case 0x02821106:
115 return ("VIA K8T800Pro host to PCI bridge");
116 case 0x31881106:
117 return ("VIA 8385 host to PCI bridge");
118 };
119
120 return (NULL);
121}
122
123static int
124agp_amd64_nvidia_match(uint16_t devid)
125{
126 /* XXX nForce3 requires secondary AGP bridge at 0:11:0. */
127 if (pci_cfgregread(0, 11, 0, PCIR_CLASS, 1) != PCIC_BRIDGE ||
128 pci_cfgregread(0, 11, 0, PCIR_SUBCLASS, 1) != PCIS_BRIDGE_PCI ||
129 pci_cfgregread(0, 11, 0, PCIR_VENDOR, 2) != 0x10de ||
130 pci_cfgregread(0, 11, 0, PCIR_DEVICE, 2) != devid)
131 return (ENXIO);
132
133 return (0);
134}
135
136static int
137agp_amd64_via_match(void)
138{
139 /* XXX Some VIA bridge requires secondary AGP bridge at 0:1:0. */
140 if (pci_cfgregread(0, 1, 0, PCIR_CLASS, 1) != PCIC_BRIDGE ||
141 pci_cfgregread(0, 1, 0, PCIR_SUBCLASS, 1) != PCIS_BRIDGE_PCI ||
142 pci_cfgregread(0, 1, 0, PCIR_VENDOR, 2) != 0x1106 ||
143 pci_cfgregread(0, 1, 0, PCIR_DEVICE, 2) != 0xb188 ||
144 (pci_cfgregread(0, 1, 0, AGP_VIA_AGPSEL, 1) & 2))
145 return (0);
146
147 return (1);
148}
149
150static int
151agp_amd64_probe(device_t dev)
152{
153 const char *desc;
154
155 if (resource_disabled("agp", device_get_unit(dev)))
156 return (ENXIO);
157 if ((desc = agp_amd64_match(dev))) {
158 device_set_desc(dev, desc);
159 return (BUS_PROBE_DEFAULT);
160 }
161
162 return (ENXIO);
163}
164
165static int
166agp_amd64_attach(device_t dev)
167{
168 struct agp_amd64_softc *sc = device_get_softc(dev);
169 struct agp_gatt *gatt;
170 uint32_t devid;
171 int i, n, error;
172
173 for (i = 0, n = 0; i < PCI_SLOTMAX && n < AMD64_MAX_MCTRL; i++) {
174 devid = pci_cfgregread(0, i, 3, 0, 4);
175 if (devid == 0x11031022 || devid == 0x12031022) {
176 sc->mctrl[n] = i;
177 n++;
178 }
179 }
180 if (n == 0)
181 return (ENXIO);
182
183 sc->n_mctrl = n;
184
185 if (bootverbose)
186 device_printf(dev, "%d Miscellaneous Control unit(s) found.\n",
187 sc->n_mctrl);
188
189 if ((error = agp_generic_attach(dev)))
190 return (error);
191
192 sc->initial_aperture = AGP_GET_APERTURE(dev);
193
194 for (;;) {
195 gatt = agp_alloc_gatt(dev);
196 if (gatt)
197 break;
198
199 /*
200 * Probably contigmalloc failure. Try reducing the
201 * aperture so that the gatt size reduces.
202 */
203 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) {
204 agp_generic_detach(dev);
205 return (ENOMEM);
206 }
207 }
208 sc->gatt = gatt;
209
210 switch (pci_get_vendor(dev)) {
211 case 0x10b9: /* ULi */
212 agp_amd64_uli_init(dev);
213 if (agp_amd64_uli_set_aperture(dev, sc->initial_aperture))
214 return (ENXIO);
215 break;
216
217 case 0x10de: /* nVidia */
218 agp_amd64_nvidia_init(dev);
219 if (agp_amd64_nvidia_set_aperture(dev, sc->initial_aperture))
220 return (ENXIO);
221 break;
222
223 case 0x1106: /* VIA */
224 sc->via_agp = agp_amd64_via_match();
225 if (sc->via_agp) {
226 agp_amd64_via_init(dev);
227 if (agp_amd64_via_set_aperture(dev,
228 sc->initial_aperture))
229 return (ENXIO);
230 }
231 break;
232 }
233
234 /* Install the gatt and enable aperture. */
235 for (i = 0; i < sc->n_mctrl; i++) {
236 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_ATTBASE,
237 (uint32_t)(gatt->ag_physical >> 8) & AGP_AMD64_ATTBASE_MASK,
238 4);
239 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL,
240 (pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) |
241 AGP_AMD64_APCTRL_GARTEN) &
242 ~(AGP_AMD64_APCTRL_DISGARTCPU | AGP_AMD64_APCTRL_DISGARTIO),
243 4);
244 }
245
246 agp_flush_cache();
247
248 return (0);
249}
250
251static int
252agp_amd64_detach(device_t dev)
253{
254 struct agp_amd64_softc *sc = device_get_softc(dev);
255 int i;
256
257 agp_free_cdev(dev);
258
259 for (i = 0; i < sc->n_mctrl; i++)
260 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL,
261 pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) &
262 ~AGP_AMD64_APCTRL_GARTEN, 4);
263
264 AGP_SET_APERTURE(dev, sc->initial_aperture);
265 agp_free_gatt(sc->gatt);
266 agp_free_res(dev);
267
268 return (0);
269}
270
271static uint32_t agp_amd64_table[] = {
272 0x02000000, /* 32 MB */
273 0x04000000, /* 64 MB */
274 0x08000000, /* 128 MB */
275 0x10000000, /* 256 MB */
276 0x20000000, /* 512 MB */
277 0x40000000, /* 1024 MB */
278 0x80000000, /* 2048 MB */
279};
280
281#define AGP_AMD64_TABLE_SIZE \
282 (sizeof(agp_amd64_table) / sizeof(agp_amd64_table[0]))
283
284static uint32_t
285agp_amd64_get_aperture(device_t dev)
286{
287 struct agp_amd64_softc *sc = device_get_softc(dev);
288 uint32_t i;
289
290 i = (pci_cfgregread(0, sc->mctrl[0], 3, AGP_AMD64_APCTRL, 4) &
291 AGP_AMD64_APCTRL_SIZE_MASK) >> 1;
292
293 if (i >= AGP_AMD64_TABLE_SIZE)
294 return (0);
295
296 return (agp_amd64_table[i]);
297}
298
299static int
300agp_amd64_set_aperture(device_t dev, uint32_t aperture)
301{
302 struct agp_amd64_softc *sc = device_get_softc(dev);
303 uint32_t i;
304 int j;
305
306 for (i = 0; i < AGP_AMD64_TABLE_SIZE; i++)
307 if (agp_amd64_table[i] == aperture)
308 break;
309 if (i >= AGP_AMD64_TABLE_SIZE)
310 return (EINVAL);
311
312 for (j = 0; j < sc->n_mctrl; j++)
313 pci_cfgregwrite(0, sc->mctrl[j], 3, AGP_AMD64_APCTRL,
314 (pci_cfgregread(0, sc->mctrl[j], 3, AGP_AMD64_APCTRL, 4) &
315 ~(AGP_AMD64_APCTRL_SIZE_MASK)) | (i << 1), 4);
316
317 switch (pci_get_vendor(dev)) {
318 case 0x10b9: /* ULi */
319 return (agp_amd64_uli_set_aperture(dev, aperture));
320 break;
321
322 case 0x10de: /* nVidia */
323 return (agp_amd64_nvidia_set_aperture(dev, aperture));
324 break;
325
326 case 0x1106: /* VIA */
327 if (sc->via_agp)
328 return (agp_amd64_via_set_aperture(dev, aperture));
329 break;
330 }
331
332 return (0);
333}
334
335static int
|
336agp_amd64_bind_page(device_t dev, int offset, vm_offset_t physical)
| 336agp_amd64_bind_page(device_t dev, vm_offset_t offset, vm_offset_t physical)
|
337{
338 struct agp_amd64_softc *sc = device_get_softc(dev);
339
340 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
341 return (EINVAL);
342
343 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] =
344 (physical & 0xfffff000) | ((physical >> 28) & 0x00000ff0) | 3;
345
346 return (0);
347}
348
349static int
| 337{
338 struct agp_amd64_softc *sc = device_get_softc(dev);
339
340 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
341 return (EINVAL);
342
343 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] =
344 (physical & 0xfffff000) | ((physical >> 28) & 0x00000ff0) | 3;
345
346 return (0);
347}
348
349static int
|
350agp_amd64_unbind_page(device_t dev, int offset)
| 350agp_amd64_unbind_page(device_t dev, vm_offset_t offset)
|
351{
352 struct agp_amd64_softc *sc = device_get_softc(dev);
353
354 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
355 return (EINVAL);
356
357 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0;
358
359 return (0);
360}
361
362static void
363agp_amd64_flush_tlb(device_t dev)
364{
365 struct agp_amd64_softc *sc = device_get_softc(dev);
366 int i;
367
368 for (i = 0; i < sc->n_mctrl; i++)
369 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL,
370 pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL, 4) |
371 AGP_AMD64_CACHECTRL_INVGART, 4);
372}
373
374static void
375agp_amd64_apbase_fixup(device_t dev)
376{
377 struct agp_amd64_softc *sc = device_get_softc(dev);
378 uint32_t apbase;
379 int i;
380
381 sc->apbase = rman_get_start(sc->agp.as_aperture);
382 apbase = (sc->apbase >> 25) & AGP_AMD64_APBASE_MASK;
383 for (i = 0; i < sc->n_mctrl; i++)
384 pci_cfgregwrite(0, sc->mctrl[i], 3,
385 AGP_AMD64_APBASE, apbase, 4);
386}
387
388static void
389agp_amd64_uli_init(device_t dev)
390{
391 struct agp_amd64_softc *sc = device_get_softc(dev);
392
393 agp_amd64_apbase_fixup(dev);
394 pci_write_config(dev, AGP_AMD64_ULI_APBASE,
395 (pci_read_config(dev, AGP_AMD64_ULI_APBASE, 4) & 0x0000000f) |
396 sc->apbase, 4);
397 pci_write_config(dev, AGP_AMD64_ULI_HTT_FEATURE, sc->apbase, 4);
398}
399
400static int
401agp_amd64_uli_set_aperture(device_t dev, uint32_t aperture)
402{
403 struct agp_amd64_softc *sc = device_get_softc(dev);
404
405 switch (aperture) {
406 case 0x02000000: /* 32 MB */
407 case 0x04000000: /* 64 MB */
408 case 0x08000000: /* 128 MB */
409 case 0x10000000: /* 256 MB */
410 break;
411 default:
412 return (EINVAL);
413 }
414
415 pci_write_config(dev, AGP_AMD64_ULI_ENU_SCR,
416 sc->apbase + aperture - 1, 4);
417
418 return (0);
419}
420
421static void
422agp_amd64_nvidia_init(device_t dev)
423{
424 struct agp_amd64_softc *sc = device_get_softc(dev);
425
426 agp_amd64_apbase_fixup(dev);
427 pci_write_config(dev, AGP_AMD64_NVIDIA_0_APBASE,
428 (pci_read_config(dev, AGP_AMD64_NVIDIA_0_APBASE, 4) & 0x0000000f) |
429 sc->apbase, 4);
430 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APBASE1, sc->apbase, 4);
431 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APBASE2, sc->apbase, 4);
432}
433
434static int
435agp_amd64_nvidia_set_aperture(device_t dev, uint32_t aperture)
436{
437 struct agp_amd64_softc *sc = device_get_softc(dev);
438 uint32_t apsize;
439
440 switch (aperture) {
441 case 0x02000000: apsize = 0x0f; break; /* 32 MB */
442 case 0x04000000: apsize = 0x0e; break; /* 64 MB */
443 case 0x08000000: apsize = 0x0c; break; /* 128 MB */
444 case 0x10000000: apsize = 0x08; break; /* 256 MB */
445 case 0x20000000: apsize = 0x00; break; /* 512 MB */
446 default:
447 return (EINVAL);
448 }
449
450 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APSIZE,
451 (pci_cfgregread(0, 11, 0, AGP_AMD64_NVIDIA_1_APSIZE, 4) &
452 0xfffffff0) | apsize, 4);
453 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT1,
454 sc->apbase + aperture - 1, 4);
455 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT2,
456 sc->apbase + aperture - 1, 4);
457
458 return (0);
459}
460
461static void
462agp_amd64_via_init(device_t dev)
463{
464 struct agp_amd64_softc *sc = device_get_softc(dev);
465
466 agp_amd64_apbase_fixup(dev);
467 pci_cfgregwrite(0, 1, 0, AGP3_VIA_ATTBASE, sc->gatt->ag_physical, 4);
468 pci_cfgregwrite(0, 1, 0, AGP3_VIA_GARTCTRL,
469 pci_cfgregread(0, 1, 0, AGP3_VIA_ATTBASE, 4) | 0x180, 4);
470}
471
472static int
473agp_amd64_via_set_aperture(device_t dev, uint32_t aperture)
474{
475 uint32_t apsize;
476
477 apsize = ((aperture - 1) >> 20) ^ 0xff;
478 if ((((apsize ^ 0xff) << 20) | ((1 << 20) - 1)) + 1 != aperture)
479 return (EINVAL);
480 pci_cfgregwrite(0, 1, 0, AGP3_VIA_APSIZE, apsize, 1);
481
482 return (0);
483}
484
485static device_method_t agp_amd64_methods[] = {
486 /* Device interface */
487 DEVMETHOD(device_probe, agp_amd64_probe),
488 DEVMETHOD(device_attach, agp_amd64_attach),
489 DEVMETHOD(device_detach, agp_amd64_detach),
490 DEVMETHOD(device_shutdown, bus_generic_shutdown),
491 DEVMETHOD(device_suspend, bus_generic_suspend),
492 DEVMETHOD(device_resume, bus_generic_resume),
493
494 /* AGP interface */
495 DEVMETHOD(agp_get_aperture, agp_amd64_get_aperture),
496 DEVMETHOD(agp_set_aperture, agp_amd64_set_aperture),
497 DEVMETHOD(agp_bind_page, agp_amd64_bind_page),
498 DEVMETHOD(agp_unbind_page, agp_amd64_unbind_page),
499 DEVMETHOD(agp_flush_tlb, agp_amd64_flush_tlb),
500 DEVMETHOD(agp_enable, agp_generic_enable),
501 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory),
502 DEVMETHOD(agp_free_memory, agp_generic_free_memory),
503 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory),
504 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory),
505
506 { 0, 0 }
507};
508
509static driver_t agp_amd64_driver = {
510 "agp",
511 agp_amd64_methods,
512 sizeof(struct agp_amd64_softc),
513};
514
515static devclass_t agp_devclass;
516
517DRIVER_MODULE(agp_amd64, hostb, agp_amd64_driver, agp_devclass, 0, 0);
518MODULE_DEPEND(agp_amd64, agp, 1, 1, 1);
519MODULE_DEPEND(agp_amd64, pci, 1, 1, 1);
| 351{
352 struct agp_amd64_softc *sc = device_get_softc(dev);
353
354 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
355 return (EINVAL);
356
357 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0;
358
359 return (0);
360}
361
362static void
363agp_amd64_flush_tlb(device_t dev)
364{
365 struct agp_amd64_softc *sc = device_get_softc(dev);
366 int i;
367
368 for (i = 0; i < sc->n_mctrl; i++)
369 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL,
370 pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL, 4) |
371 AGP_AMD64_CACHECTRL_INVGART, 4);
372}
373
374static void
375agp_amd64_apbase_fixup(device_t dev)
376{
377 struct agp_amd64_softc *sc = device_get_softc(dev);
378 uint32_t apbase;
379 int i;
380
381 sc->apbase = rman_get_start(sc->agp.as_aperture);
382 apbase = (sc->apbase >> 25) & AGP_AMD64_APBASE_MASK;
383 for (i = 0; i < sc->n_mctrl; i++)
384 pci_cfgregwrite(0, sc->mctrl[i], 3,
385 AGP_AMD64_APBASE, apbase, 4);
386}
387
388static void
389agp_amd64_uli_init(device_t dev)
390{
391 struct agp_amd64_softc *sc = device_get_softc(dev);
392
393 agp_amd64_apbase_fixup(dev);
394 pci_write_config(dev, AGP_AMD64_ULI_APBASE,
395 (pci_read_config(dev, AGP_AMD64_ULI_APBASE, 4) & 0x0000000f) |
396 sc->apbase, 4);
397 pci_write_config(dev, AGP_AMD64_ULI_HTT_FEATURE, sc->apbase, 4);
398}
399
400static int
401agp_amd64_uli_set_aperture(device_t dev, uint32_t aperture)
402{
403 struct agp_amd64_softc *sc = device_get_softc(dev);
404
405 switch (aperture) {
406 case 0x02000000: /* 32 MB */
407 case 0x04000000: /* 64 MB */
408 case 0x08000000: /* 128 MB */
409 case 0x10000000: /* 256 MB */
410 break;
411 default:
412 return (EINVAL);
413 }
414
415 pci_write_config(dev, AGP_AMD64_ULI_ENU_SCR,
416 sc->apbase + aperture - 1, 4);
417
418 return (0);
419}
420
421static void
422agp_amd64_nvidia_init(device_t dev)
423{
424 struct agp_amd64_softc *sc = device_get_softc(dev);
425
426 agp_amd64_apbase_fixup(dev);
427 pci_write_config(dev, AGP_AMD64_NVIDIA_0_APBASE,
428 (pci_read_config(dev, AGP_AMD64_NVIDIA_0_APBASE, 4) & 0x0000000f) |
429 sc->apbase, 4);
430 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APBASE1, sc->apbase, 4);
431 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APBASE2, sc->apbase, 4);
432}
433
434static int
435agp_amd64_nvidia_set_aperture(device_t dev, uint32_t aperture)
436{
437 struct agp_amd64_softc *sc = device_get_softc(dev);
438 uint32_t apsize;
439
440 switch (aperture) {
441 case 0x02000000: apsize = 0x0f; break; /* 32 MB */
442 case 0x04000000: apsize = 0x0e; break; /* 64 MB */
443 case 0x08000000: apsize = 0x0c; break; /* 128 MB */
444 case 0x10000000: apsize = 0x08; break; /* 256 MB */
445 case 0x20000000: apsize = 0x00; break; /* 512 MB */
446 default:
447 return (EINVAL);
448 }
449
450 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APSIZE,
451 (pci_cfgregread(0, 11, 0, AGP_AMD64_NVIDIA_1_APSIZE, 4) &
452 0xfffffff0) | apsize, 4);
453 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT1,
454 sc->apbase + aperture - 1, 4);
455 pci_cfgregwrite(0, 11, 0, AGP_AMD64_NVIDIA_1_APLIMIT2,
456 sc->apbase + aperture - 1, 4);
457
458 return (0);
459}
460
461static void
462agp_amd64_via_init(device_t dev)
463{
464 struct agp_amd64_softc *sc = device_get_softc(dev);
465
466 agp_amd64_apbase_fixup(dev);
467 pci_cfgregwrite(0, 1, 0, AGP3_VIA_ATTBASE, sc->gatt->ag_physical, 4);
468 pci_cfgregwrite(0, 1, 0, AGP3_VIA_GARTCTRL,
469 pci_cfgregread(0, 1, 0, AGP3_VIA_ATTBASE, 4) | 0x180, 4);
470}
471
472static int
473agp_amd64_via_set_aperture(device_t dev, uint32_t aperture)
474{
475 uint32_t apsize;
476
477 apsize = ((aperture - 1) >> 20) ^ 0xff;
478 if ((((apsize ^ 0xff) << 20) | ((1 << 20) - 1)) + 1 != aperture)
479 return (EINVAL);
480 pci_cfgregwrite(0, 1, 0, AGP3_VIA_APSIZE, apsize, 1);
481
482 return (0);
483}
484
485static device_method_t agp_amd64_methods[] = {
486 /* Device interface */
487 DEVMETHOD(device_probe, agp_amd64_probe),
488 DEVMETHOD(device_attach, agp_amd64_attach),
489 DEVMETHOD(device_detach, agp_amd64_detach),
490 DEVMETHOD(device_shutdown, bus_generic_shutdown),
491 DEVMETHOD(device_suspend, bus_generic_suspend),
492 DEVMETHOD(device_resume, bus_generic_resume),
493
494 /* AGP interface */
495 DEVMETHOD(agp_get_aperture, agp_amd64_get_aperture),
496 DEVMETHOD(agp_set_aperture, agp_amd64_set_aperture),
497 DEVMETHOD(agp_bind_page, agp_amd64_bind_page),
498 DEVMETHOD(agp_unbind_page, agp_amd64_unbind_page),
499 DEVMETHOD(agp_flush_tlb, agp_amd64_flush_tlb),
500 DEVMETHOD(agp_enable, agp_generic_enable),
501 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory),
502 DEVMETHOD(agp_free_memory, agp_generic_free_memory),
503 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory),
504 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory),
505
506 { 0, 0 }
507};
508
509static driver_t agp_amd64_driver = {
510 "agp",
511 agp_amd64_methods,
512 sizeof(struct agp_amd64_softc),
513};
514
515static devclass_t agp_devclass;
516
517DRIVER_MODULE(agp_amd64, hostb, agp_amd64_driver, agp_devclass, 0, 0);
518MODULE_DEPEND(agp_amd64, agp, 1, 1, 1);
519MODULE_DEPEND(agp_amd64, pci, 1, 1, 1);
|