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agp_amd64.c (144517) agp_amd64.c (144809)
1/*-
2 * Copyright (c) 2004 Jung-uk Kim
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2004 Jung-uk Kim
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/sys/dev/agp/agp_amd64.c 144517 2005-04-02 01:10:09Z obrien $");
28__FBSDID("$FreeBSD: head/sys/dev/agp/agp_amd64.c 144809 2005-04-08 18:04:39Z obrien $");
29
30#include "opt_bus.h"
31
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/malloc.h>
35#include <sys/kernel.h>
36#include <sys/module.h>
37#include <sys/bus.h>
38#include <sys/lock.h>
39#include <sys/mutex.h>
40#include <sys/proc.h>
41
42#include <dev/pci/pcivar.h>
43#include <dev/pci/pcireg.h>
44#include <pci/agppriv.h>
45#include <pci/agpreg.h>
46
47#include <vm/vm.h>
48#include <vm/vm_object.h>
49#include <vm/pmap.h>
50#include <machine/bus.h>
51#include <machine/resource.h>
52#include <sys/rman.h>
53
54/* XXX */
55extern void pci_cfgregwrite(int, int, int, int, uint32_t, int);
56extern uint32_t pci_cfgregread(int, int, int, int, int);
57
58MALLOC_DECLARE(M_AGP);
59
60#define AMD64_MAX_MCTRL 8
61
62struct agp_amd64_softc {
63 struct agp_softc agp;
64 uint32_t initial_aperture; /* aperture size at startup */
65 struct agp_gatt *gatt;
66 int mctrl[AMD64_MAX_MCTRL];
67 int n_mctrl;
68};
69
70static const char*
71agp_amd64_match(device_t dev)
72{
73 if (pci_get_class(dev) != PCIC_BRIDGE
74 || pci_get_subclass(dev) != PCIS_BRIDGE_HOST)
75 return NULL;
76
77 if (agp_find_caps(dev) == 0)
78 return NULL;
79
80 switch (pci_get_devid(dev)) {
81 case 0x74541022:
82 return ("AMD 8151 AGP graphics tunnel");
83 case 0x07551039:
84 return ("SiS 755 host to AGP bridge");
85 case 0x00d110de:
86 return ("NVIDIA nForce3 AGP Controller");
29
30#include "opt_bus.h"
31
32#include <sys/param.h>
33#include <sys/systm.h>
34#include <sys/malloc.h>
35#include <sys/kernel.h>
36#include <sys/module.h>
37#include <sys/bus.h>
38#include <sys/lock.h>
39#include <sys/mutex.h>
40#include <sys/proc.h>
41
42#include <dev/pci/pcivar.h>
43#include <dev/pci/pcireg.h>
44#include <pci/agppriv.h>
45#include <pci/agpreg.h>
46
47#include <vm/vm.h>
48#include <vm/vm_object.h>
49#include <vm/pmap.h>
50#include <machine/bus.h>
51#include <machine/resource.h>
52#include <sys/rman.h>
53
54/* XXX */
55extern void pci_cfgregwrite(int, int, int, int, uint32_t, int);
56extern uint32_t pci_cfgregread(int, int, int, int, int);
57
58MALLOC_DECLARE(M_AGP);
59
60#define AMD64_MAX_MCTRL 8
61
62struct agp_amd64_softc {
63 struct agp_softc agp;
64 uint32_t initial_aperture; /* aperture size at startup */
65 struct agp_gatt *gatt;
66 int mctrl[AMD64_MAX_MCTRL];
67 int n_mctrl;
68};
69
70static const char*
71agp_amd64_match(device_t dev)
72{
73 if (pci_get_class(dev) != PCIC_BRIDGE
74 || pci_get_subclass(dev) != PCIS_BRIDGE_HOST)
75 return NULL;
76
77 if (agp_find_caps(dev) == 0)
78 return NULL;
79
80 switch (pci_get_devid(dev)) {
81 case 0x74541022:
82 return ("AMD 8151 AGP graphics tunnel");
83 case 0x07551039:
84 return ("SiS 755 host to AGP bridge");
85 case 0x00d110de:
86 return ("NVIDIA nForce3 AGP Controller");
87 case 0x00e110de:
88 return ("NVIDIA nForce3-250 AGP Controller");
87 case 0x02041106:
88 return ("VIA 8380 host to PCI bridge");
89 case 0x02821106:
90 return ("VIA K8T800Pro host to PCI bridge");
91 case 0x31881106:
92 return ("VIA 8385 host to PCI bridge");
93 };
94
95 return NULL;
96}
97
98static int
99agp_amd64_probe(device_t dev)
100{
101 const char *desc;
102
103 if (resource_disabled("agp", device_get_unit(dev)))
104 return ENXIO;
105 if ((desc = agp_amd64_match(dev))) {
106 device_verbose(dev);
107 device_set_desc(dev, desc);
108 return BUS_PROBE_DEFAULT;
109 }
110
111 return ENXIO;
112}
113
114static int
115agp_amd64_attach(device_t dev)
116{
117 struct agp_amd64_softc *sc = device_get_softc(dev);
118 struct agp_gatt *gatt;
119 int i, n, error;
120
121 for (i = 0, n = 0; i < PCI_SLOTMAX && n < AMD64_MAX_MCTRL; i++)
122 if (pci_cfgregread(0, i, 3, 0, 4) == 0x11031022) {
123 sc->mctrl[n] = i;
124 n++;
125 }
126
127 if (n == 0)
128 return ENXIO;
129
130 sc->n_mctrl = n;
131
132 if (bootverbose)
133 printf("AMD64: %d Misc. Control unit(s) found.\n", sc->n_mctrl);
134
135 if ((error = agp_generic_attach(dev)))
136 return error;
137
138 sc->initial_aperture = AGP_GET_APERTURE(dev);
139
140 for (;;) {
141 gatt = agp_alloc_gatt(dev);
142 if (gatt)
143 break;
144
145 /*
146 * Probably contigmalloc failure. Try reducing the
147 * aperture so that the gatt size reduces.
148 */
149 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) {
150 agp_generic_detach(dev);
151 return ENOMEM;
152 }
153 }
154 sc->gatt = gatt;
155
156 /* Install the gatt and enable aperture. */
157 for (i = 0; i < sc->n_mctrl; i++) {
158 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_ATTBASE,
159 (uint32_t)(gatt->ag_physical >> 8) & AGP_AMD64_ATTBASE_MASK,
160 4);
161 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL,
162 (pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) |
163 AGP_AMD64_APCTRL_GARTEN) &
164 ~(AGP_AMD64_APCTRL_DISGARTCPU | AGP_AMD64_APCTRL_DISGARTIO),
165 4);
166 }
167
168 agp_flush_cache();
169
170 return 0;
171}
172
173static int
174agp_amd64_detach(device_t dev)
175{
176 struct agp_amd64_softc *sc = device_get_softc(dev);
177 int i, error;
178
179 if ((error = agp_generic_detach(dev)))
180 return error;
181
182 for (i = 0; i < sc->n_mctrl; i++)
183 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL,
184 pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) &
185 ~AGP_AMD64_APCTRL_GARTEN, 4);
186
187 AGP_SET_APERTURE(dev, sc->initial_aperture);
188 agp_free_gatt(sc->gatt);
189
190 return 0;
191}
192
193static uint32_t agp_amd64_table[] = {
194 0x02000000, /* 32 MB */
195 0x04000000, /* 64 MB */
196 0x08000000, /* 128 MB */
197 0x10000000, /* 256 MB */
198 0x20000000, /* 512 MB */
199 0x40000000, /* 1024 MB */
200 0x80000000, /* 2048 MB */
201};
202
203#define AGP_AMD64_TABLE_SIZE \
204 (sizeof(agp_amd64_table) / sizeof(agp_amd64_table[0]))
205
206static uint32_t
207agp_amd64_get_aperture(device_t dev)
208{
209 struct agp_amd64_softc *sc = device_get_softc(dev);
210 uint32_t i;
211
212 i = (pci_cfgregread(0, sc->mctrl[0], 3, AGP_AMD64_APCTRL, 4) &
213 AGP_AMD64_APCTRL_SIZE_MASK) >> 1;
214
215 if (i >= AGP_AMD64_TABLE_SIZE)
216 return 0;
217
218 return (agp_amd64_table[i]);
219}
220
221static int
222agp_amd64_set_aperture(device_t dev, uint32_t aperture)
223{
224 struct agp_amd64_softc *sc = device_get_softc(dev);
225 uint32_t i;
226 int j;
227
228 for (i = 0; i < AGP_AMD64_TABLE_SIZE; i++)
229 if (agp_amd64_table[i] == aperture)
230 break;
231 if (i == AGP_AMD64_TABLE_SIZE)
232 return EINVAL;
233
234 for (j = 0; j < sc->n_mctrl; j++)
235 pci_cfgregwrite(0, sc->mctrl[j], 3, AGP_AMD64_APCTRL,
236 (pci_cfgregread(0, sc->mctrl[j], 3, AGP_AMD64_APCTRL, 4) &
237 ~(AGP_AMD64_APCTRL_SIZE_MASK)) | (i << 1), 4);
238
239 return 0;
240}
241
242static int
243agp_amd64_bind_page(device_t dev, int offset, vm_offset_t physical)
244{
245 struct agp_amd64_softc *sc = device_get_softc(dev);
246
247 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
248 return EINVAL;
249
250 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical;
251 return 0;
252}
253
254static int
255agp_amd64_unbind_page(device_t dev, int offset)
256{
257 struct agp_amd64_softc *sc = device_get_softc(dev);
258
259 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
260 return EINVAL;
261
262 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0;
263 return 0;
264}
265
266static void
267agp_amd64_flush_tlb(device_t dev)
268{
269 struct agp_amd64_softc *sc = device_get_softc(dev);
270 int i;
271
272 for (i = 0; i < sc->n_mctrl; i++)
273 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL,
274 pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL, 4) |
275 AGP_AMD64_CACHECTRL_INVGART, 4);
276}
277
278static device_method_t agp_amd64_methods[] = {
279 /* Device interface */
280 DEVMETHOD(device_probe, agp_amd64_probe),
281 DEVMETHOD(device_attach, agp_amd64_attach),
282 DEVMETHOD(device_detach, agp_amd64_detach),
283 DEVMETHOD(device_shutdown, bus_generic_shutdown),
284 DEVMETHOD(device_suspend, bus_generic_suspend),
285 DEVMETHOD(device_resume, bus_generic_resume),
286
287 /* AGP interface */
288 DEVMETHOD(agp_get_aperture, agp_amd64_get_aperture),
289 DEVMETHOD(agp_set_aperture, agp_amd64_set_aperture),
290 DEVMETHOD(agp_bind_page, agp_amd64_bind_page),
291 DEVMETHOD(agp_unbind_page, agp_amd64_unbind_page),
292 DEVMETHOD(agp_flush_tlb, agp_amd64_flush_tlb),
293 DEVMETHOD(agp_enable, agp_generic_enable),
294 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory),
295 DEVMETHOD(agp_free_memory, agp_generic_free_memory),
296 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory),
297 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory),
298
299 { 0, 0 }
300};
301
302static driver_t agp_amd64_driver = {
303 "agp",
304 agp_amd64_methods,
305 sizeof(struct agp_amd64_softc),
306};
307
308static devclass_t agp_devclass;
309
310DRIVER_MODULE(agp_amd64, pci, agp_amd64_driver, agp_devclass, 0, 0);
311MODULE_DEPEND(agp_amd64, agp, 1, 1, 1);
312MODULE_DEPEND(agp_amd64, pci, 1, 1, 1);
89 case 0x02041106:
90 return ("VIA 8380 host to PCI bridge");
91 case 0x02821106:
92 return ("VIA K8T800Pro host to PCI bridge");
93 case 0x31881106:
94 return ("VIA 8385 host to PCI bridge");
95 };
96
97 return NULL;
98}
99
100static int
101agp_amd64_probe(device_t dev)
102{
103 const char *desc;
104
105 if (resource_disabled("agp", device_get_unit(dev)))
106 return ENXIO;
107 if ((desc = agp_amd64_match(dev))) {
108 device_verbose(dev);
109 device_set_desc(dev, desc);
110 return BUS_PROBE_DEFAULT;
111 }
112
113 return ENXIO;
114}
115
116static int
117agp_amd64_attach(device_t dev)
118{
119 struct agp_amd64_softc *sc = device_get_softc(dev);
120 struct agp_gatt *gatt;
121 int i, n, error;
122
123 for (i = 0, n = 0; i < PCI_SLOTMAX && n < AMD64_MAX_MCTRL; i++)
124 if (pci_cfgregread(0, i, 3, 0, 4) == 0x11031022) {
125 sc->mctrl[n] = i;
126 n++;
127 }
128
129 if (n == 0)
130 return ENXIO;
131
132 sc->n_mctrl = n;
133
134 if (bootverbose)
135 printf("AMD64: %d Misc. Control unit(s) found.\n", sc->n_mctrl);
136
137 if ((error = agp_generic_attach(dev)))
138 return error;
139
140 sc->initial_aperture = AGP_GET_APERTURE(dev);
141
142 for (;;) {
143 gatt = agp_alloc_gatt(dev);
144 if (gatt)
145 break;
146
147 /*
148 * Probably contigmalloc failure. Try reducing the
149 * aperture so that the gatt size reduces.
150 */
151 if (AGP_SET_APERTURE(dev, AGP_GET_APERTURE(dev) / 2)) {
152 agp_generic_detach(dev);
153 return ENOMEM;
154 }
155 }
156 sc->gatt = gatt;
157
158 /* Install the gatt and enable aperture. */
159 for (i = 0; i < sc->n_mctrl; i++) {
160 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_ATTBASE,
161 (uint32_t)(gatt->ag_physical >> 8) & AGP_AMD64_ATTBASE_MASK,
162 4);
163 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL,
164 (pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) |
165 AGP_AMD64_APCTRL_GARTEN) &
166 ~(AGP_AMD64_APCTRL_DISGARTCPU | AGP_AMD64_APCTRL_DISGARTIO),
167 4);
168 }
169
170 agp_flush_cache();
171
172 return 0;
173}
174
175static int
176agp_amd64_detach(device_t dev)
177{
178 struct agp_amd64_softc *sc = device_get_softc(dev);
179 int i, error;
180
181 if ((error = agp_generic_detach(dev)))
182 return error;
183
184 for (i = 0; i < sc->n_mctrl; i++)
185 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL,
186 pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_APCTRL, 4) &
187 ~AGP_AMD64_APCTRL_GARTEN, 4);
188
189 AGP_SET_APERTURE(dev, sc->initial_aperture);
190 agp_free_gatt(sc->gatt);
191
192 return 0;
193}
194
195static uint32_t agp_amd64_table[] = {
196 0x02000000, /* 32 MB */
197 0x04000000, /* 64 MB */
198 0x08000000, /* 128 MB */
199 0x10000000, /* 256 MB */
200 0x20000000, /* 512 MB */
201 0x40000000, /* 1024 MB */
202 0x80000000, /* 2048 MB */
203};
204
205#define AGP_AMD64_TABLE_SIZE \
206 (sizeof(agp_amd64_table) / sizeof(agp_amd64_table[0]))
207
208static uint32_t
209agp_amd64_get_aperture(device_t dev)
210{
211 struct agp_amd64_softc *sc = device_get_softc(dev);
212 uint32_t i;
213
214 i = (pci_cfgregread(0, sc->mctrl[0], 3, AGP_AMD64_APCTRL, 4) &
215 AGP_AMD64_APCTRL_SIZE_MASK) >> 1;
216
217 if (i >= AGP_AMD64_TABLE_SIZE)
218 return 0;
219
220 return (agp_amd64_table[i]);
221}
222
223static int
224agp_amd64_set_aperture(device_t dev, uint32_t aperture)
225{
226 struct agp_amd64_softc *sc = device_get_softc(dev);
227 uint32_t i;
228 int j;
229
230 for (i = 0; i < AGP_AMD64_TABLE_SIZE; i++)
231 if (agp_amd64_table[i] == aperture)
232 break;
233 if (i == AGP_AMD64_TABLE_SIZE)
234 return EINVAL;
235
236 for (j = 0; j < sc->n_mctrl; j++)
237 pci_cfgregwrite(0, sc->mctrl[j], 3, AGP_AMD64_APCTRL,
238 (pci_cfgregread(0, sc->mctrl[j], 3, AGP_AMD64_APCTRL, 4) &
239 ~(AGP_AMD64_APCTRL_SIZE_MASK)) | (i << 1), 4);
240
241 return 0;
242}
243
244static int
245agp_amd64_bind_page(device_t dev, int offset, vm_offset_t physical)
246{
247 struct agp_amd64_softc *sc = device_get_softc(dev);
248
249 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
250 return EINVAL;
251
252 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = physical;
253 return 0;
254}
255
256static int
257agp_amd64_unbind_page(device_t dev, int offset)
258{
259 struct agp_amd64_softc *sc = device_get_softc(dev);
260
261 if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
262 return EINVAL;
263
264 sc->gatt->ag_virtual[offset >> AGP_PAGE_SHIFT] = 0;
265 return 0;
266}
267
268static void
269agp_amd64_flush_tlb(device_t dev)
270{
271 struct agp_amd64_softc *sc = device_get_softc(dev);
272 int i;
273
274 for (i = 0; i < sc->n_mctrl; i++)
275 pci_cfgregwrite(0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL,
276 pci_cfgregread(0, sc->mctrl[i], 3, AGP_AMD64_CACHECTRL, 4) |
277 AGP_AMD64_CACHECTRL_INVGART, 4);
278}
279
280static device_method_t agp_amd64_methods[] = {
281 /* Device interface */
282 DEVMETHOD(device_probe, agp_amd64_probe),
283 DEVMETHOD(device_attach, agp_amd64_attach),
284 DEVMETHOD(device_detach, agp_amd64_detach),
285 DEVMETHOD(device_shutdown, bus_generic_shutdown),
286 DEVMETHOD(device_suspend, bus_generic_suspend),
287 DEVMETHOD(device_resume, bus_generic_resume),
288
289 /* AGP interface */
290 DEVMETHOD(agp_get_aperture, agp_amd64_get_aperture),
291 DEVMETHOD(agp_set_aperture, agp_amd64_set_aperture),
292 DEVMETHOD(agp_bind_page, agp_amd64_bind_page),
293 DEVMETHOD(agp_unbind_page, agp_amd64_unbind_page),
294 DEVMETHOD(agp_flush_tlb, agp_amd64_flush_tlb),
295 DEVMETHOD(agp_enable, agp_generic_enable),
296 DEVMETHOD(agp_alloc_memory, agp_generic_alloc_memory),
297 DEVMETHOD(agp_free_memory, agp_generic_free_memory),
298 DEVMETHOD(agp_bind_memory, agp_generic_bind_memory),
299 DEVMETHOD(agp_unbind_memory, agp_generic_unbind_memory),
300
301 { 0, 0 }
302};
303
304static driver_t agp_amd64_driver = {
305 "agp",
306 agp_amd64_methods,
307 sizeof(struct agp_amd64_softc),
308};
309
310static devclass_t agp_devclass;
311
312DRIVER_MODULE(agp_amd64, pci, agp_amd64_driver, agp_devclass, 0, 0);
313MODULE_DEPEND(agp_amd64, agp, 1, 1, 1);
314MODULE_DEPEND(agp_amd64, pci, 1, 1, 1);