1/*-
2 * Copyright 2014 Luiz Otavio O Souza <loos@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: stable/10/sys/arm/ti/ti_adcreg.h 266338 2014-05-17 19:06:46Z loos $
27 */
28
29#ifndef _TI_ADCREG_H_
30#define _TI_ADCREG_H_
31
32#define ADC_REVISION 0x000
33#define ADC_REV_SCHEME_MSK 0xc0000000
34#define ADC_REV_SCHEME_SHIFT 30
35#define ADC_REV_FUNC_MSK 0x0fff0000
36#define ADC_REV_FUNC_SHIFT 16
37#define ADC_REV_RTL_MSK 0x0000f800
38#define ADC_REV_RTL_SHIFT 11
39#define ADC_REV_MAJOR_MSK 0x00000700
40#define ADC_REV_MAJOR_SHIFT 8
41#define ADC_REV_CUSTOM_MSK 0x000000c0
42#define ADC_REV_CUSTOM_SHIFT 6
43#define ADC_REV_MINOR_MSK 0x0000003f
44#define ADC_SYSCFG 0x010
45#define ADC_SYSCFG_IDLE_MSK 0x000000c0
46#define ADC_SYSCFG_IDLE_SHIFT 2
47#define ADC_IRQSTATUS_RAW 0x024
48#define ADC_IRQSTATUS 0x028
49#define ADC_IRQENABLE_SET 0x02c
50#define ADC_IRQENABLE_CLR 0x030
51#define ADC_IRQ_HW_PEN_SYNC (1 << 10)
52#define ADC_IRQ_PEN_UP (1 << 9)
53#define ADC_IRQ_OUT_RANGE (1 << 8)
54#define ADC_IRQ_FIFO1_UNDR (1 << 7)
55#define ADC_IRQ_FIFO1_OVERR (1 << 6)
56#define ADC_IRQ_FIFO1_THRES (1 << 5)
57#define ADC_IRQ_FIFO0_UNDR (1 << 4)
58#define ADC_IRQ_FIFO0_OVERR (1 << 3)
59#define ADC_IRQ_FIFO0_THRES (1 << 2)
60#define ADC_IRQ_END_OF_SEQ (1 << 1)
61#define ADC_IRQ_HW_PEN_ASYNC (1 << 0)
62#define ADC_CTRL 0x040
63#define ADC_CTRL_STEP_WP (1 << 2)
64#define ADC_CTRL_STEP_ID (1 << 1)
65#define ADC_CTRL_ENABLE (1 << 0)
66#define ADC_STAT 0x044
67#define ADC_CLKDIV 0x04c
68#define ADC_STEPENABLE 0x054
69#define ADC_IDLECONFIG 0x058
70#define ADC_STEPCFG1 0x064
71#define ADC_STEPDLY1 0x068
72#define ADC_STEPCFG2 0x06c
73#define ADC_STEPDLY2 0x070
74#define ADC_STEPCFG3 0x074
75#define ADC_STEPDLY3 0x078
76#define ADC_STEPCFG4 0x07c
77#define ADC_STEPDLY4 0x080
78#define ADC_STEPCFG5 0x084
79#define ADC_STEPDLY5 0x088
80#define ADC_STEPCFG6 0x08c
81#define ADC_STEPDLY6 0x090
82#define ADC_STEPCFG7 0x094
83#define ADC_STEPDLY7 0x098
84#define ADC_STEP_DIFF_CNTRL (1 << 25)
85#define ADC_STEP_RFM_MSK 0x01800000
86#define ADC_STEP_RFM_SHIFT 23
87#define ADC_STEP_RFM_VSSA 0
88#define ADC_STEP_RFM_XNUR 1
89#define ADC_STEP_RFM_YNLR 2
90#define ADC_STEP_RFM_VREFN 3
91#define ADC_STEP_INP_MSK 0x00780000
92#define ADC_STEP_INP_SHIFT 19
93#define ADC_STEP_INM_MSK 0x00078000
94#define ADC_STEP_INM_SHIFT 15
95#define ADC_STEP_IN_VREFN 8
96#define ADC_STEP_RFP_MSK 0x00007000
97#define ADC_STEP_RFP_SHIFT 12
98#define ADC_STEP_RFP_VDDA 0
99#define ADC_STEP_RFP_XPUL 1
100#define ADC_STEP_RFP_YPLL 2
101#define ADC_STEP_RFP_VREFP 3
102#define ADC_STEP_RFP_INTREF 4
103#define ADC_STEP_AVG_MSK 0x0000001c
104#define ADC_STEP_AVG_SHIFT 2
105#define ADC_STEP_MODE_MSK 0x00000003
106#define ADC_STEP_MODE_ONESHOT 0x00000000
107#define ADC_STEP_MODE_CONTINUOUS 0x00000001
108#define ADC_STEP_SAMPLE_DELAY 0xff000000
109#define ADC_STEP_OPEN_DELAY 0x0003ffff
110#define ADC_FIFO0COUNT 0x0e4
111#define ADC_FIFO0THRESHOLD 0x0e8
112#define ADC_FIFO0DATA 0x100
113#define ADC_FIFO_COUNT_MSK 0x0000007f
114#define ADC_FIFO_STEP_ID_MSK 0x000f0000
115#define ADC_FIFO_STEP_ID_SHIFT 16
116#define ADC_FIFO_DATA_MSK 0x00000fff
117
118#endif /* _TI_ADCREG_H_ */
2 * Copyright 2014 Luiz Otavio O Souza <loos@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: stable/10/sys/arm/ti/ti_adcreg.h 266338 2014-05-17 19:06:46Z loos $
27 */
28
29#ifndef _TI_ADCREG_H_
30#define _TI_ADCREG_H_
31
32#define ADC_REVISION 0x000
33#define ADC_REV_SCHEME_MSK 0xc0000000
34#define ADC_REV_SCHEME_SHIFT 30
35#define ADC_REV_FUNC_MSK 0x0fff0000
36#define ADC_REV_FUNC_SHIFT 16
37#define ADC_REV_RTL_MSK 0x0000f800
38#define ADC_REV_RTL_SHIFT 11
39#define ADC_REV_MAJOR_MSK 0x00000700
40#define ADC_REV_MAJOR_SHIFT 8
41#define ADC_REV_CUSTOM_MSK 0x000000c0
42#define ADC_REV_CUSTOM_SHIFT 6
43#define ADC_REV_MINOR_MSK 0x0000003f
44#define ADC_SYSCFG 0x010
45#define ADC_SYSCFG_IDLE_MSK 0x000000c0
46#define ADC_SYSCFG_IDLE_SHIFT 2
47#define ADC_IRQSTATUS_RAW 0x024
48#define ADC_IRQSTATUS 0x028
49#define ADC_IRQENABLE_SET 0x02c
50#define ADC_IRQENABLE_CLR 0x030
51#define ADC_IRQ_HW_PEN_SYNC (1 << 10)
52#define ADC_IRQ_PEN_UP (1 << 9)
53#define ADC_IRQ_OUT_RANGE (1 << 8)
54#define ADC_IRQ_FIFO1_UNDR (1 << 7)
55#define ADC_IRQ_FIFO1_OVERR (1 << 6)
56#define ADC_IRQ_FIFO1_THRES (1 << 5)
57#define ADC_IRQ_FIFO0_UNDR (1 << 4)
58#define ADC_IRQ_FIFO0_OVERR (1 << 3)
59#define ADC_IRQ_FIFO0_THRES (1 << 2)
60#define ADC_IRQ_END_OF_SEQ (1 << 1)
61#define ADC_IRQ_HW_PEN_ASYNC (1 << 0)
62#define ADC_CTRL 0x040
63#define ADC_CTRL_STEP_WP (1 << 2)
64#define ADC_CTRL_STEP_ID (1 << 1)
65#define ADC_CTRL_ENABLE (1 << 0)
66#define ADC_STAT 0x044
67#define ADC_CLKDIV 0x04c
68#define ADC_STEPENABLE 0x054
69#define ADC_IDLECONFIG 0x058
70#define ADC_STEPCFG1 0x064
71#define ADC_STEPDLY1 0x068
72#define ADC_STEPCFG2 0x06c
73#define ADC_STEPDLY2 0x070
74#define ADC_STEPCFG3 0x074
75#define ADC_STEPDLY3 0x078
76#define ADC_STEPCFG4 0x07c
77#define ADC_STEPDLY4 0x080
78#define ADC_STEPCFG5 0x084
79#define ADC_STEPDLY5 0x088
80#define ADC_STEPCFG6 0x08c
81#define ADC_STEPDLY6 0x090
82#define ADC_STEPCFG7 0x094
83#define ADC_STEPDLY7 0x098
84#define ADC_STEP_DIFF_CNTRL (1 << 25)
85#define ADC_STEP_RFM_MSK 0x01800000
86#define ADC_STEP_RFM_SHIFT 23
87#define ADC_STEP_RFM_VSSA 0
88#define ADC_STEP_RFM_XNUR 1
89#define ADC_STEP_RFM_YNLR 2
90#define ADC_STEP_RFM_VREFN 3
91#define ADC_STEP_INP_MSK 0x00780000
92#define ADC_STEP_INP_SHIFT 19
93#define ADC_STEP_INM_MSK 0x00078000
94#define ADC_STEP_INM_SHIFT 15
95#define ADC_STEP_IN_VREFN 8
96#define ADC_STEP_RFP_MSK 0x00007000
97#define ADC_STEP_RFP_SHIFT 12
98#define ADC_STEP_RFP_VDDA 0
99#define ADC_STEP_RFP_XPUL 1
100#define ADC_STEP_RFP_YPLL 2
101#define ADC_STEP_RFP_VREFP 3
102#define ADC_STEP_RFP_INTREF 4
103#define ADC_STEP_AVG_MSK 0x0000001c
104#define ADC_STEP_AVG_SHIFT 2
105#define ADC_STEP_MODE_MSK 0x00000003
106#define ADC_STEP_MODE_ONESHOT 0x00000000
107#define ADC_STEP_MODE_CONTINUOUS 0x00000001
108#define ADC_STEP_SAMPLE_DELAY 0xff000000
109#define ADC_STEP_OPEN_DELAY 0x0003ffff
110#define ADC_FIFO0COUNT 0x0e4
111#define ADC_FIFO0THRESHOLD 0x0e8
112#define ADC_FIFO0DATA 0x100
113#define ADC_FIFO_COUNT_MSK 0x0000007f
114#define ADC_FIFO_STEP_ID_MSK 0x000f0000
115#define ADC_FIFO_STEP_ID_SHIFT 16
116#define ADC_FIFO_DATA_MSK 0x00000fff
117
118#endif /* _TI_ADCREG_H_ */