| armreg.h (139735) | armreg.h (152653) |
|---|---|
| 1/* $NetBSD: armreg.h,v 1.28 2003/10/31 16:30:15 scw Exp $ */ 2 3/*- 4 * Copyright (c) 1998, 2001 Ben Harris 5 * Copyright (c) 1994-1996 Mark Brinicombe. 6 * Copyright (c) 1994 Brini. 7 * All rights reserved. 8 * --- 21 unchanged lines hidden (view full) --- 30 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * | 1/* $NetBSD: armreg.h,v 1.28 2003/10/31 16:30:15 scw Exp $ */ 2 3/*- 4 * Copyright (c) 1998, 2001 Ben Harris 5 * Copyright (c) 1994-1996 Mark Brinicombe. 6 * Copyright (c) 1994 Brini. 7 * All rights reserved. 8 * --- 21 unchanged lines hidden (view full) --- 30 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * |
| 38 * $FreeBSD: head/sys/arm/include/armreg.h 139735 2005-01-05 21:58:49Z imp $ | 38 * $FreeBSD: head/sys/arm/include/armreg.h 152653 2005-11-21 19:06:25Z cognet $ |
| 39 */ 40 41#ifndef MACHINE_ARMREG_H 42#define MACHINE_ARMREG_H 43#define INSN_SIZE 4 44#define INSN_COND_MASK 0xf0000000 /* Condition mask */ 45#define PSR_MODE 0x0000001f /* mode mask */ 46#define PSR_USR26_MODE 0x00000000 --- 77 unchanged lines hidden (view full) --- 124#define CPU_ID_ARM710T 0x41807100 125#define CPU_ID_ARM720T 0x41807200 126#define CPU_ID_ARM740T8K 0x41807400 /* XXX no MMU, 8KB cache */ 127#define CPU_ID_ARM740T4K 0x41817400 /* XXX no MMU, 4KB cache */ 128 129/* Post-ARM7 CPUs */ 130#define CPU_ID_ARM810 0x41018100 131#define CPU_ID_ARM920T 0x41129200 | 39 */ 40 41#ifndef MACHINE_ARMREG_H 42#define MACHINE_ARMREG_H 43#define INSN_SIZE 4 44#define INSN_COND_MASK 0xf0000000 /* Condition mask */ 45#define PSR_MODE 0x0000001f /* mode mask */ 46#define PSR_USR26_MODE 0x00000000 --- 77 unchanged lines hidden (view full) --- 124#define CPU_ID_ARM710T 0x41807100 125#define CPU_ID_ARM720T 0x41807200 126#define CPU_ID_ARM740T8K 0x41807400 /* XXX no MMU, 8KB cache */ 127#define CPU_ID_ARM740T4K 0x41817400 /* XXX no MMU, 4KB cache */ 128 129/* Post-ARM7 CPUs */ 130#define CPU_ID_ARM810 0x41018100 131#define CPU_ID_ARM920T 0x41129200 |
| 132#define CPU_ID_ARM920T_ALT 0x41009200 |
|
| 132#define CPU_ID_ARM922T 0x41029220 133#define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */ 134#define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */ 135#define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */ 136#define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */ 137#define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */ 138#define CPU_ID_ARM1022ES 0x4105a220 139#define CPU_ID_SA110 0x4401a100 --- 160 unchanged lines hidden --- | 133#define CPU_ID_ARM922T 0x41029220 134#define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */ 135#define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */ 136#define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */ 137#define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */ 138#define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */ 139#define CPU_ID_ARM1022ES 0x4105a220 140#define CPU_ID_SA110 0x4401a100 --- 160 unchanged lines hidden --- |