1/*-
2 * Copyright (c) 1994-1998 Mark Brinicombe.
3 * Copyright (c) 1994 Brini.
4 * All rights reserved.
5 *
6 * This code is derived from software written for Brini by Mark Brinicombe
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Brini.
19 * 4. The name of the company nor the name of the author may be used to
20 * endorse or promote products derived from this software without specific
21 * prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 *
35 * RiscBSD kernel project
36 *
37 * machdep.c
38 *
39 * Machine dependant functions for kernel setup
40 *
41 * This file needs a lot of work.
42 *
43 * Created : 17/09/94
44 */
45
46#include "opt_msgbuf.h"
47#include "opt_ddb.h"
48#include "opt_at91.h"
49
50#include <sys/cdefs.h>
| 1/*-
2 * Copyright (c) 1994-1998 Mark Brinicombe.
3 * Copyright (c) 1994 Brini.
4 * All rights reserved.
5 *
6 * This code is derived from software written for Brini by Mark Brinicombe
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Brini.
19 * 4. The name of the company nor the name of the author may be used to
20 * endorse or promote products derived from this software without specific
21 * prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 *
35 * RiscBSD kernel project
36 *
37 * machdep.c
38 *
39 * Machine dependant functions for kernel setup
40 *
41 * This file needs a lot of work.
42 *
43 * Created : 17/09/94
44 */
45
46#include "opt_msgbuf.h"
47#include "opt_ddb.h"
48#include "opt_at91.h"
49
50#include <sys/cdefs.h>
|
52
53#define _ARM32_BUS_DMA_PRIVATE
54#include <sys/param.h>
55#include <sys/systm.h>
56#include <sys/sysproto.h>
57#include <sys/signalvar.h>
58#include <sys/imgact.h>
59#include <sys/kernel.h>
60#include <sys/ktr.h>
61#include <sys/linker.h>
62#include <sys/lock.h>
63#include <sys/malloc.h>
64#include <sys/mutex.h>
65#include <sys/pcpu.h>
66#include <sys/proc.h>
67#include <sys/ptrace.h>
68#include <sys/cons.h>
69#include <sys/bio.h>
70#include <sys/bus.h>
71#include <sys/buf.h>
72#include <sys/exec.h>
73#include <sys/kdb.h>
74#include <sys/msgbuf.h>
75#include <machine/reg.h>
76#include <machine/cpu.h>
77
78#include <vm/vm.h>
79#include <vm/pmap.h>
80#include <vm/vm_object.h>
81#include <vm/vm_page.h>
82#include <vm/vm_pager.h>
83#include <vm/vm_map.h>
84#include <vm/vnode_pager.h>
85#include <machine/pmap.h>
86#include <machine/vmparam.h>
87#include <machine/pcb.h>
88#include <machine/undefined.h>
89#include <machine/machdep.h>
90#include <machine/metadata.h>
91#include <machine/armreg.h>
92#include <machine/bus.h>
93#include <sys/reboot.h>
94
95#include <arm/at91/at91rm92reg.h>
96#include <arm/at91/at91_piovar.h>
97#include <arm/at91/at91_pio_rm9200.h>
98
99#define KERNEL_PT_SYS 0 /* Page table for mapping proc0 zero page */
100#define KERNEL_PT_KERN 1
101#define KERNEL_PT_KERN_NUM 22
102#define KERNEL_PT_AFKERNEL KERNEL_PT_KERN + KERNEL_PT_KERN_NUM /* L2 table for mapping after kernel */
103#define KERNEL_PT_AFKERNEL_NUM 5
104
105/* this should be evenly divisable by PAGE_SIZE / L2_TABLE_SIZE_REAL (or 4) */
106#define NUM_KERNEL_PTS (KERNEL_PT_AFKERNEL + KERNEL_PT_AFKERNEL_NUM)
107
108/* Define various stack sizes in pages */
109#define IRQ_STACK_SIZE 1
110#define ABT_STACK_SIZE 1
111#define UND_STACK_SIZE 1
112
113extern u_int data_abort_handler_address;
114extern u_int prefetch_abort_handler_address;
115extern u_int undefined_handler_address;
116
117struct pv_addr kernel_pt_table[NUM_KERNEL_PTS];
118
119extern void *_end;
120
121extern int *end;
122
123struct pcpu __pcpu;
124struct pcpu *pcpup = &__pcpu;
125
126/* Physical and virtual addresses for some global pages */
127
128vm_paddr_t phys_avail[10];
129vm_paddr_t dump_avail[4];
130vm_offset_t physical_pages;
131
132struct pv_addr systempage;
133struct pv_addr msgbufpv;
134struct pv_addr irqstack;
135struct pv_addr undstack;
136struct pv_addr abtstack;
137struct pv_addr kernelstack;
138
139static struct trapframe proc0_tf;
140
141/* Static device mappings. */
142static const struct pmap_devmap kb920x_devmap[] = {
143 /*
144 * Map the on-board devices VA == PA so that we can access them
145 * with the MMU on or off.
146 */
147 {
148 /*
149 * This at least maps the interrupt controller, the UART
150 * and the timer. Other devices should use newbus to
151 * map their memory anyway.
152 */
153 0xdff00000,
154 0xfff00000,
155 0x100000,
156 VM_PROT_READ|VM_PROT_WRITE,
157 PTE_NOCACHE,
158 },
159 /*
160 * We can't just map the OHCI registers VA == PA, because
161 * AT91RM92_OHCI_BASE belongs to the userland address space.
162 * We could just choose a different virtual address, but a better
163 * solution would probably be to just use pmap_mapdev() to allocate
164 * KVA, as we don't need the OHCI controller before the vm
165 * initialization is done. However, the AT91 resource allocation
166 * system doesn't know how to use pmap_mapdev() yet.
167 */
168#if 1
169 {
170 /*
171 * Add the ohci controller, and anything else that might be
172 * on this chip select for a VA/PA mapping.
173 */
174 AT91RM92_OHCI_BASE,
175 AT91RM92_OHCI_PA_BASE,
176 AT91RM92_OHCI_SIZE,
177 VM_PROT_READ|VM_PROT_WRITE,
178 PTE_NOCACHE,
179 },
180#endif
181 {
182 0,
183 0,
184 0,
185 0,
186 0,
187 }
188};
189
190#define SDRAM_START 0xa0000000
191
192#ifdef DDB
193extern vm_offset_t ksym_start, ksym_end;
194#endif
195
196static long
197ramsize(void)
198{
199 uint32_t *SDRAMC = (uint32_t *)(AT91RM92_BASE + AT91RM92_SDRAMC_BASE);
200 uint32_t cr, mr;
201 int banks, rows, cols, bw;
202
203 cr = SDRAMC[AT91RM92_SDRAMC_CR / 4];
204 mr = SDRAMC[AT91RM92_SDRAMC_MR / 4];
205 bw = (mr & AT91RM92_SDRAMC_MR_DBW_16) ? 1 : 2;
206 banks = (cr & AT91RM92_SDRAMC_CR_NB_4) ? 2 : 1;
207 rows = ((cr & AT91RM92_SDRAMC_CR_NR_MASK) >> 2) + 11;
208 cols = (cr & AT91RM92_SDRAMC_CR_NC_MASK) + 8;
209 return (1 << (cols + rows + banks + bw));
210}
211
212static long
213board_init(void)
214{
215 /*
| 52
53#define _ARM32_BUS_DMA_PRIVATE
54#include <sys/param.h>
55#include <sys/systm.h>
56#include <sys/sysproto.h>
57#include <sys/signalvar.h>
58#include <sys/imgact.h>
59#include <sys/kernel.h>
60#include <sys/ktr.h>
61#include <sys/linker.h>
62#include <sys/lock.h>
63#include <sys/malloc.h>
64#include <sys/mutex.h>
65#include <sys/pcpu.h>
66#include <sys/proc.h>
67#include <sys/ptrace.h>
68#include <sys/cons.h>
69#include <sys/bio.h>
70#include <sys/bus.h>
71#include <sys/buf.h>
72#include <sys/exec.h>
73#include <sys/kdb.h>
74#include <sys/msgbuf.h>
75#include <machine/reg.h>
76#include <machine/cpu.h>
77
78#include <vm/vm.h>
79#include <vm/pmap.h>
80#include <vm/vm_object.h>
81#include <vm/vm_page.h>
82#include <vm/vm_pager.h>
83#include <vm/vm_map.h>
84#include <vm/vnode_pager.h>
85#include <machine/pmap.h>
86#include <machine/vmparam.h>
87#include <machine/pcb.h>
88#include <machine/undefined.h>
89#include <machine/machdep.h>
90#include <machine/metadata.h>
91#include <machine/armreg.h>
92#include <machine/bus.h>
93#include <sys/reboot.h>
94
95#include <arm/at91/at91rm92reg.h>
96#include <arm/at91/at91_piovar.h>
97#include <arm/at91/at91_pio_rm9200.h>
98
99#define KERNEL_PT_SYS 0 /* Page table for mapping proc0 zero page */
100#define KERNEL_PT_KERN 1
101#define KERNEL_PT_KERN_NUM 22
102#define KERNEL_PT_AFKERNEL KERNEL_PT_KERN + KERNEL_PT_KERN_NUM /* L2 table for mapping after kernel */
103#define KERNEL_PT_AFKERNEL_NUM 5
104
105/* this should be evenly divisable by PAGE_SIZE / L2_TABLE_SIZE_REAL (or 4) */
106#define NUM_KERNEL_PTS (KERNEL_PT_AFKERNEL + KERNEL_PT_AFKERNEL_NUM)
107
108/* Define various stack sizes in pages */
109#define IRQ_STACK_SIZE 1
110#define ABT_STACK_SIZE 1
111#define UND_STACK_SIZE 1
112
113extern u_int data_abort_handler_address;
114extern u_int prefetch_abort_handler_address;
115extern u_int undefined_handler_address;
116
117struct pv_addr kernel_pt_table[NUM_KERNEL_PTS];
118
119extern void *_end;
120
121extern int *end;
122
123struct pcpu __pcpu;
124struct pcpu *pcpup = &__pcpu;
125
126/* Physical and virtual addresses for some global pages */
127
128vm_paddr_t phys_avail[10];
129vm_paddr_t dump_avail[4];
130vm_offset_t physical_pages;
131
132struct pv_addr systempage;
133struct pv_addr msgbufpv;
134struct pv_addr irqstack;
135struct pv_addr undstack;
136struct pv_addr abtstack;
137struct pv_addr kernelstack;
138
139static struct trapframe proc0_tf;
140
141/* Static device mappings. */
142static const struct pmap_devmap kb920x_devmap[] = {
143 /*
144 * Map the on-board devices VA == PA so that we can access them
145 * with the MMU on or off.
146 */
147 {
148 /*
149 * This at least maps the interrupt controller, the UART
150 * and the timer. Other devices should use newbus to
151 * map their memory anyway.
152 */
153 0xdff00000,
154 0xfff00000,
155 0x100000,
156 VM_PROT_READ|VM_PROT_WRITE,
157 PTE_NOCACHE,
158 },
159 /*
160 * We can't just map the OHCI registers VA == PA, because
161 * AT91RM92_OHCI_BASE belongs to the userland address space.
162 * We could just choose a different virtual address, but a better
163 * solution would probably be to just use pmap_mapdev() to allocate
164 * KVA, as we don't need the OHCI controller before the vm
165 * initialization is done. However, the AT91 resource allocation
166 * system doesn't know how to use pmap_mapdev() yet.
167 */
168#if 1
169 {
170 /*
171 * Add the ohci controller, and anything else that might be
172 * on this chip select for a VA/PA mapping.
173 */
174 AT91RM92_OHCI_BASE,
175 AT91RM92_OHCI_PA_BASE,
176 AT91RM92_OHCI_SIZE,
177 VM_PROT_READ|VM_PROT_WRITE,
178 PTE_NOCACHE,
179 },
180#endif
181 {
182 0,
183 0,
184 0,
185 0,
186 0,
187 }
188};
189
190#define SDRAM_START 0xa0000000
191
192#ifdef DDB
193extern vm_offset_t ksym_start, ksym_end;
194#endif
195
196static long
197ramsize(void)
198{
199 uint32_t *SDRAMC = (uint32_t *)(AT91RM92_BASE + AT91RM92_SDRAMC_BASE);
200 uint32_t cr, mr;
201 int banks, rows, cols, bw;
202
203 cr = SDRAMC[AT91RM92_SDRAMC_CR / 4];
204 mr = SDRAMC[AT91RM92_SDRAMC_MR / 4];
205 bw = (mr & AT91RM92_SDRAMC_MR_DBW_16) ? 1 : 2;
206 banks = (cr & AT91RM92_SDRAMC_CR_NB_4) ? 2 : 1;
207 rows = ((cr & AT91RM92_SDRAMC_CR_NR_MASK) >> 2) + 11;
208 cols = (cr & AT91RM92_SDRAMC_CR_NC_MASK) + 8;
209 return (1 << (cols + rows + banks + bw));
210}
211
212static long
213board_init(void)
214{
215 /*
|
217 * TX pins to float. However, for RS-232 operations, we don't want
218 * these pins to float. Instead, they should be pulled up to avoid
219 * mismatches. Linux does something similar when it configures the
220 * TX lines. This implies that we also allow the RX lines to float
221 * rather than be in the state they are left in by the boot loader.
222 * Since they are input pins, I think that this is the right thing
223 * to do.
224 */
225
226 /* PIOA's A periph: Turn USART 0 and 2's TX/RX pins */
227 at91_pio_use_periph_a(AT91RM92_PIOA_BASE,
228 AT91C_PA18_RXD0 | AT91C_PA22_RXD2, 0);
229 at91_pio_use_periph_a(AT91RM92_PIOA_BASE,
230 AT91C_PA17_TXD0 | AT91C_PA23_TXD2, 1);
231 /* PIOA's B periph: Turn USART 3's TX/RX pins */
232 at91_pio_use_periph_b(AT91RM92_PIOA_BASE, AT91C_PA6_RXD3, 0);
233 at91_pio_use_periph_b(AT91RM92_PIOA_BASE, AT91C_PA5_TXD3, 1);
234#ifdef AT91_TSC
235 /* We're using TC0's A1 and A2 input */
236 at91_pio_use_periph_b(AT91RM92_PIOA_BASE,
237 AT91C_PA19_TIOA1 | AT91C_PA21_TIOA2, 0);
238#endif
239 /* PIOB's A periph: Turn USART 1's TX/RX pins */
240 at91_pio_use_periph_a(AT91RM92_PIOB_BASE, AT91C_PB21_RXD1, 0);
241 at91_pio_use_periph_a(AT91RM92_PIOB_BASE, AT91C_PB20_TXD1, 1);
242
243 /* Pin assignment */
244#ifdef AT91_TSC
245 /* Assert PA24 low -- talk to rubidium */
246 at91_pio_use_gpio(AT91RM92_PIOA_BASE, AT91C_PIO_PA24);
247 at91_pio_gpio_output(AT91RM92_PIOA_BASE, AT91C_PIO_PA24, 0);
248 at91_pio_gpio_clear(AT91RM92_PIOA_BASE, AT91C_PIO_PA24);
249 at91_pio_use_gpio(AT91RM92_PIOB_BASE,
250 AT91C_PIO_PB16 | AT91C_PIO_PB17 | AT91C_PIO_PB18 | AT91C_PIO_PB19);
251#endif
252
253 return (ramsize());
254}
255
256void *
257initarm(void *arg, void *arg2)
258{
259 struct pv_addr kernel_l1pt;
260 int loop;
261 u_int l1pagetable;
262 vm_offset_t freemempos;
263 vm_offset_t afterkern;
264 int i;
265 uint32_t fake_preload[35];
266 uint32_t memsize;
267 vm_offset_t lastaddr;
268#ifdef DDB
269 vm_offset_t zstart = 0, zend = 0;
270#endif
271
272 i = 0;
273
274 set_cpufuncs();
275
276 fake_preload[i++] = MODINFO_NAME;
277 fake_preload[i++] = strlen("elf kernel") + 1;
278 strcpy((char*)&fake_preload[i++], "elf kernel");
279 i += 2;
280 fake_preload[i++] = MODINFO_TYPE;
281 fake_preload[i++] = strlen("elf kernel") + 1;
282 strcpy((char*)&fake_preload[i++], "elf kernel");
283 i += 2;
284 fake_preload[i++] = MODINFO_ADDR;
285 fake_preload[i++] = sizeof(vm_offset_t);
286 fake_preload[i++] = KERNVIRTADDR;
287 fake_preload[i++] = MODINFO_SIZE;
288 fake_preload[i++] = sizeof(uint32_t);
289 fake_preload[i++] = (uint32_t)&end - KERNVIRTADDR;
290#ifdef DDB
291 if (*(uint32_t *)KERNVIRTADDR == MAGIC_TRAMP_NUMBER) {
292 fake_preload[i++] = MODINFO_METADATA|MODINFOMD_SSYM;
293 fake_preload[i++] = sizeof(vm_offset_t);
294 fake_preload[i++] = *(uint32_t *)(KERNVIRTADDR + 4);
295 fake_preload[i++] = MODINFO_METADATA|MODINFOMD_ESYM;
296 fake_preload[i++] = sizeof(vm_offset_t);
297 fake_preload[i++] = *(uint32_t *)(KERNVIRTADDR + 8);
298 lastaddr = *(uint32_t *)(KERNVIRTADDR + 8);
299 zend = lastaddr;
300 zstart = *(uint32_t *)(KERNVIRTADDR + 4);
301 ksym_start = zstart;
302 ksym_end = zend;
303 } else
304#endif
305 lastaddr = (vm_offset_t)&end;
306
307 fake_preload[i++] = 0;
308 fake_preload[i] = 0;
309 preload_metadata = (void *)fake_preload;
310
311
312 pcpu_init(pcpup, 0, sizeof(struct pcpu));
313 PCPU_SET(curthread, &thread0);
314
315#define KERNEL_TEXT_BASE (KERNBASE)
316 freemempos = (lastaddr + PAGE_MASK) & ~PAGE_MASK;
317 /* Define a macro to simplify memory allocation */
318#define valloc_pages(var, np) \
319 alloc_pages((var).pv_va, (np)); \
320 (var).pv_pa = (var).pv_va + (KERNPHYSADDR - KERNVIRTADDR);
321
322#define alloc_pages(var, np) \
323 (var) = freemempos; \
324 freemempos += (np * PAGE_SIZE); \
325 memset((char *)(var), 0, ((np) * PAGE_SIZE));
326
327 while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0)
328 freemempos += PAGE_SIZE;
329 valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE);
330 for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) {
331 if (!(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) {
332 valloc_pages(kernel_pt_table[loop],
333 L2_TABLE_SIZE / PAGE_SIZE);
334 } else {
335 kernel_pt_table[loop].pv_va = freemempos -
336 (loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) *
337 L2_TABLE_SIZE_REAL;
338 kernel_pt_table[loop].pv_pa =
339 kernel_pt_table[loop].pv_va - KERNVIRTADDR +
340 KERNPHYSADDR;
341 }
342 i++;
343 }
344 /*
345 * Allocate a page for the system page mapped to V0x00000000
346 * This page will just contain the system vectors and can be
347 * shared by all processes.
348 */
349 valloc_pages(systempage, 1);
350
351 /* Allocate stacks for all modes */
352 valloc_pages(irqstack, IRQ_STACK_SIZE);
353 valloc_pages(abtstack, ABT_STACK_SIZE);
354 valloc_pages(undstack, UND_STACK_SIZE);
355 valloc_pages(kernelstack, KSTACK_PAGES);
356 valloc_pages(msgbufpv, round_page(MSGBUF_SIZE) / PAGE_SIZE);
357 /*
358 * Now we start construction of the L1 page table
359 * We start by mapping the L2 page tables into the L1.
360 * This means that we can replace L1 mappings later on if necessary
361 */
362 l1pagetable = kernel_l1pt.pv_va;
363
364 /* Map the L2 pages tables in the L1 page table */
365 pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH,
366 &kernel_pt_table[KERNEL_PT_SYS]);
367 for (i = 0; i < KERNEL_PT_KERN_NUM; i++)
368 pmap_link_l2pt(l1pagetable, KERNBASE + i * 0x100000,
369 &kernel_pt_table[KERNEL_PT_KERN + i]);
370 pmap_map_chunk(l1pagetable, KERNBASE, PHYSADDR,
371 (((uint32_t)(lastaddr) - KERNBASE) + PAGE_SIZE) & ~(PAGE_SIZE - 1),
372 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
373 afterkern = round_page((lastaddr + L1_S_SIZE) & ~(L1_S_SIZE
374 - 1));
375 for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) {
376 pmap_link_l2pt(l1pagetable, afterkern + i * 0x00100000,
377 &kernel_pt_table[KERNEL_PT_AFKERNEL + i]);
378 }
379
380 /* Map the vector page. */
381 pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa,
382 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
383 /* Map the stack pages */
384 pmap_map_chunk(l1pagetable, irqstack.pv_va, irqstack.pv_pa,
385 IRQ_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
386 pmap_map_chunk(l1pagetable, abtstack.pv_va, abtstack.pv_pa,
387 ABT_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
388 pmap_map_chunk(l1pagetable, undstack.pv_va, undstack.pv_pa,
389 UND_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
390 pmap_map_chunk(l1pagetable, kernelstack.pv_va, kernelstack.pv_pa,
391 KSTACK_PAGES * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
392
393 pmap_map_chunk(l1pagetable, kernel_l1pt.pv_va, kernel_l1pt.pv_pa,
394 L1_TABLE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
395 pmap_map_chunk(l1pagetable, msgbufpv.pv_va, msgbufpv.pv_pa,
396 MSGBUF_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
397
398
399 for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) {
400 pmap_map_chunk(l1pagetable, kernel_pt_table[loop].pv_va,
401 kernel_pt_table[loop].pv_pa, L2_TABLE_SIZE,
402 VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
403 }
404
405 pmap_devmap_bootstrap(l1pagetable, kb920x_devmap);
406 cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
407 setttb(kernel_l1pt.pv_pa);
408 cpu_tlb_flushID();
409 cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2));
410 cninit();
411 memsize = board_init();
412 physmem = memsize / PAGE_SIZE;
413
414 /*
415 * Pages were allocated during the secondary bootstrap for the
416 * stacks for different CPU modes.
417 * We must now set the r13 registers in the different CPU modes to
418 * point to these stacks.
419 * Since the ARM stacks use STMFD etc. we must set r13 to the top end
420 * of the stack memory.
421 */
422
423 cpu_control(CPU_CONTROL_MMU_ENABLE, CPU_CONTROL_MMU_ENABLE);
424 set_stackptr(PSR_IRQ32_MODE,
425 irqstack.pv_va + IRQ_STACK_SIZE * PAGE_SIZE);
426 set_stackptr(PSR_ABT32_MODE,
427 abtstack.pv_va + ABT_STACK_SIZE * PAGE_SIZE);
428 set_stackptr(PSR_UND32_MODE,
429 undstack.pv_va + UND_STACK_SIZE * PAGE_SIZE);
430
431
432
433 /*
434 * We must now clean the cache again....
435 * Cleaning may be done by reading new data to displace any
436 * dirty data in the cache. This will have happened in setttb()
437 * but since we are boot strapping the addresses used for the read
438 * may have just been remapped and thus the cache could be out
439 * of sync. A re-clean after the switch will cure this.
440 * After booting there are no gross reloations of the kernel thus
441 * this problem will not occur after initarm().
442 */
443 cpu_idcache_wbinv_all();
444
445 /* Set stack for exception handlers */
446
447 data_abort_handler_address = (u_int)data_abort_handler;
448 prefetch_abort_handler_address = (u_int)prefetch_abort_handler;
449 undefined_handler_address = (u_int)undefinedinstruction_bounce;
450 undefined_init();
451
452 proc_linkup0(&proc0, &thread0);
453 thread0.td_kstack = kernelstack.pv_va;
454 thread0.td_pcb = (struct pcb *)
455 (thread0.td_kstack + KSTACK_PAGES * PAGE_SIZE) - 1;
456 thread0.td_pcb->pcb_flags = 0;
457 thread0.td_frame = &proc0_tf;
458 pcpup->pc_curpcb = thread0.td_pcb;
459
460 arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL);
461
462 pmap_curmaxkvaddr = afterkern + 0x100000 * (KERNEL_PT_KERN_NUM - 1);
463 /*
464 * ARM_USE_SMALL_ALLOC uses dump_avail, so it must be filled before
465 * calling pmap_bootstrap.
466 */
467 dump_avail[0] = PHYSADDR;
468 dump_avail[1] = PHYSADDR + memsize;
469 dump_avail[2] = 0;
470 dump_avail[3] = 0;
471
472 pmap_bootstrap(freemempos,
473 KERNVIRTADDR + 3 * memsize,
474 &kernel_l1pt);
475 msgbufp = (void*)msgbufpv.pv_va;
476 msgbufinit(msgbufp, MSGBUF_SIZE);
477 mutex_init();
478
479 i = 0;
480
481#if PHYSADDR != KERNPHYSADDR
482 phys_avail[i++] = PHYSADDR;
483 phys_avail[i++] = KERNPHYSADDR;
484#endif
485 phys_avail[i++] = virtual_avail - KERNVIRTADDR + KERNPHYSADDR;
486 phys_avail[i++] = PHYSADDR + memsize;
487 phys_avail[i++] = 0;
488 phys_avail[i++] = 0;
489 /* Do basic tuning, hz etc */
490 init_param1();
491 init_param2(physmem);
492 kdb_init();
493 return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP -
494 sizeof(struct pcb)));
495}
| 217 * TX pins to float. However, for RS-232 operations, we don't want
218 * these pins to float. Instead, they should be pulled up to avoid
219 * mismatches. Linux does something similar when it configures the
220 * TX lines. This implies that we also allow the RX lines to float
221 * rather than be in the state they are left in by the boot loader.
222 * Since they are input pins, I think that this is the right thing
223 * to do.
224 */
225
226 /* PIOA's A periph: Turn USART 0 and 2's TX/RX pins */
227 at91_pio_use_periph_a(AT91RM92_PIOA_BASE,
228 AT91C_PA18_RXD0 | AT91C_PA22_RXD2, 0);
229 at91_pio_use_periph_a(AT91RM92_PIOA_BASE,
230 AT91C_PA17_TXD0 | AT91C_PA23_TXD2, 1);
231 /* PIOA's B periph: Turn USART 3's TX/RX pins */
232 at91_pio_use_periph_b(AT91RM92_PIOA_BASE, AT91C_PA6_RXD3, 0);
233 at91_pio_use_periph_b(AT91RM92_PIOA_BASE, AT91C_PA5_TXD3, 1);
234#ifdef AT91_TSC
235 /* We're using TC0's A1 and A2 input */
236 at91_pio_use_periph_b(AT91RM92_PIOA_BASE,
237 AT91C_PA19_TIOA1 | AT91C_PA21_TIOA2, 0);
238#endif
239 /* PIOB's A periph: Turn USART 1's TX/RX pins */
240 at91_pio_use_periph_a(AT91RM92_PIOB_BASE, AT91C_PB21_RXD1, 0);
241 at91_pio_use_periph_a(AT91RM92_PIOB_BASE, AT91C_PB20_TXD1, 1);
242
243 /* Pin assignment */
244#ifdef AT91_TSC
245 /* Assert PA24 low -- talk to rubidium */
246 at91_pio_use_gpio(AT91RM92_PIOA_BASE, AT91C_PIO_PA24);
247 at91_pio_gpio_output(AT91RM92_PIOA_BASE, AT91C_PIO_PA24, 0);
248 at91_pio_gpio_clear(AT91RM92_PIOA_BASE, AT91C_PIO_PA24);
249 at91_pio_use_gpio(AT91RM92_PIOB_BASE,
250 AT91C_PIO_PB16 | AT91C_PIO_PB17 | AT91C_PIO_PB18 | AT91C_PIO_PB19);
251#endif
252
253 return (ramsize());
254}
255
256void *
257initarm(void *arg, void *arg2)
258{
259 struct pv_addr kernel_l1pt;
260 int loop;
261 u_int l1pagetable;
262 vm_offset_t freemempos;
263 vm_offset_t afterkern;
264 int i;
265 uint32_t fake_preload[35];
266 uint32_t memsize;
267 vm_offset_t lastaddr;
268#ifdef DDB
269 vm_offset_t zstart = 0, zend = 0;
270#endif
271
272 i = 0;
273
274 set_cpufuncs();
275
276 fake_preload[i++] = MODINFO_NAME;
277 fake_preload[i++] = strlen("elf kernel") + 1;
278 strcpy((char*)&fake_preload[i++], "elf kernel");
279 i += 2;
280 fake_preload[i++] = MODINFO_TYPE;
281 fake_preload[i++] = strlen("elf kernel") + 1;
282 strcpy((char*)&fake_preload[i++], "elf kernel");
283 i += 2;
284 fake_preload[i++] = MODINFO_ADDR;
285 fake_preload[i++] = sizeof(vm_offset_t);
286 fake_preload[i++] = KERNVIRTADDR;
287 fake_preload[i++] = MODINFO_SIZE;
288 fake_preload[i++] = sizeof(uint32_t);
289 fake_preload[i++] = (uint32_t)&end - KERNVIRTADDR;
290#ifdef DDB
291 if (*(uint32_t *)KERNVIRTADDR == MAGIC_TRAMP_NUMBER) {
292 fake_preload[i++] = MODINFO_METADATA|MODINFOMD_SSYM;
293 fake_preload[i++] = sizeof(vm_offset_t);
294 fake_preload[i++] = *(uint32_t *)(KERNVIRTADDR + 4);
295 fake_preload[i++] = MODINFO_METADATA|MODINFOMD_ESYM;
296 fake_preload[i++] = sizeof(vm_offset_t);
297 fake_preload[i++] = *(uint32_t *)(KERNVIRTADDR + 8);
298 lastaddr = *(uint32_t *)(KERNVIRTADDR + 8);
299 zend = lastaddr;
300 zstart = *(uint32_t *)(KERNVIRTADDR + 4);
301 ksym_start = zstart;
302 ksym_end = zend;
303 } else
304#endif
305 lastaddr = (vm_offset_t)&end;
306
307 fake_preload[i++] = 0;
308 fake_preload[i] = 0;
309 preload_metadata = (void *)fake_preload;
310
311
312 pcpu_init(pcpup, 0, sizeof(struct pcpu));
313 PCPU_SET(curthread, &thread0);
314
315#define KERNEL_TEXT_BASE (KERNBASE)
316 freemempos = (lastaddr + PAGE_MASK) & ~PAGE_MASK;
317 /* Define a macro to simplify memory allocation */
318#define valloc_pages(var, np) \
319 alloc_pages((var).pv_va, (np)); \
320 (var).pv_pa = (var).pv_va + (KERNPHYSADDR - KERNVIRTADDR);
321
322#define alloc_pages(var, np) \
323 (var) = freemempos; \
324 freemempos += (np * PAGE_SIZE); \
325 memset((char *)(var), 0, ((np) * PAGE_SIZE));
326
327 while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0)
328 freemempos += PAGE_SIZE;
329 valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE);
330 for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) {
331 if (!(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) {
332 valloc_pages(kernel_pt_table[loop],
333 L2_TABLE_SIZE / PAGE_SIZE);
334 } else {
335 kernel_pt_table[loop].pv_va = freemempos -
336 (loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) *
337 L2_TABLE_SIZE_REAL;
338 kernel_pt_table[loop].pv_pa =
339 kernel_pt_table[loop].pv_va - KERNVIRTADDR +
340 KERNPHYSADDR;
341 }
342 i++;
343 }
344 /*
345 * Allocate a page for the system page mapped to V0x00000000
346 * This page will just contain the system vectors and can be
347 * shared by all processes.
348 */
349 valloc_pages(systempage, 1);
350
351 /* Allocate stacks for all modes */
352 valloc_pages(irqstack, IRQ_STACK_SIZE);
353 valloc_pages(abtstack, ABT_STACK_SIZE);
354 valloc_pages(undstack, UND_STACK_SIZE);
355 valloc_pages(kernelstack, KSTACK_PAGES);
356 valloc_pages(msgbufpv, round_page(MSGBUF_SIZE) / PAGE_SIZE);
357 /*
358 * Now we start construction of the L1 page table
359 * We start by mapping the L2 page tables into the L1.
360 * This means that we can replace L1 mappings later on if necessary
361 */
362 l1pagetable = kernel_l1pt.pv_va;
363
364 /* Map the L2 pages tables in the L1 page table */
365 pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH,
366 &kernel_pt_table[KERNEL_PT_SYS]);
367 for (i = 0; i < KERNEL_PT_KERN_NUM; i++)
368 pmap_link_l2pt(l1pagetable, KERNBASE + i * 0x100000,
369 &kernel_pt_table[KERNEL_PT_KERN + i]);
370 pmap_map_chunk(l1pagetable, KERNBASE, PHYSADDR,
371 (((uint32_t)(lastaddr) - KERNBASE) + PAGE_SIZE) & ~(PAGE_SIZE - 1),
372 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
373 afterkern = round_page((lastaddr + L1_S_SIZE) & ~(L1_S_SIZE
374 - 1));
375 for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) {
376 pmap_link_l2pt(l1pagetable, afterkern + i * 0x00100000,
377 &kernel_pt_table[KERNEL_PT_AFKERNEL + i]);
378 }
379
380 /* Map the vector page. */
381 pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa,
382 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
383 /* Map the stack pages */
384 pmap_map_chunk(l1pagetable, irqstack.pv_va, irqstack.pv_pa,
385 IRQ_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
386 pmap_map_chunk(l1pagetable, abtstack.pv_va, abtstack.pv_pa,
387 ABT_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
388 pmap_map_chunk(l1pagetable, undstack.pv_va, undstack.pv_pa,
389 UND_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
390 pmap_map_chunk(l1pagetable, kernelstack.pv_va, kernelstack.pv_pa,
391 KSTACK_PAGES * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
392
393 pmap_map_chunk(l1pagetable, kernel_l1pt.pv_va, kernel_l1pt.pv_pa,
394 L1_TABLE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
395 pmap_map_chunk(l1pagetable, msgbufpv.pv_va, msgbufpv.pv_pa,
396 MSGBUF_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
397
398
399 for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) {
400 pmap_map_chunk(l1pagetable, kernel_pt_table[loop].pv_va,
401 kernel_pt_table[loop].pv_pa, L2_TABLE_SIZE,
402 VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
403 }
404
405 pmap_devmap_bootstrap(l1pagetable, kb920x_devmap);
406 cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
407 setttb(kernel_l1pt.pv_pa);
408 cpu_tlb_flushID();
409 cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2));
410 cninit();
411 memsize = board_init();
412 physmem = memsize / PAGE_SIZE;
413
414 /*
415 * Pages were allocated during the secondary bootstrap for the
416 * stacks for different CPU modes.
417 * We must now set the r13 registers in the different CPU modes to
418 * point to these stacks.
419 * Since the ARM stacks use STMFD etc. we must set r13 to the top end
420 * of the stack memory.
421 */
422
423 cpu_control(CPU_CONTROL_MMU_ENABLE, CPU_CONTROL_MMU_ENABLE);
424 set_stackptr(PSR_IRQ32_MODE,
425 irqstack.pv_va + IRQ_STACK_SIZE * PAGE_SIZE);
426 set_stackptr(PSR_ABT32_MODE,
427 abtstack.pv_va + ABT_STACK_SIZE * PAGE_SIZE);
428 set_stackptr(PSR_UND32_MODE,
429 undstack.pv_va + UND_STACK_SIZE * PAGE_SIZE);
430
431
432
433 /*
434 * We must now clean the cache again....
435 * Cleaning may be done by reading new data to displace any
436 * dirty data in the cache. This will have happened in setttb()
437 * but since we are boot strapping the addresses used for the read
438 * may have just been remapped and thus the cache could be out
439 * of sync. A re-clean after the switch will cure this.
440 * After booting there are no gross reloations of the kernel thus
441 * this problem will not occur after initarm().
442 */
443 cpu_idcache_wbinv_all();
444
445 /* Set stack for exception handlers */
446
447 data_abort_handler_address = (u_int)data_abort_handler;
448 prefetch_abort_handler_address = (u_int)prefetch_abort_handler;
449 undefined_handler_address = (u_int)undefinedinstruction_bounce;
450 undefined_init();
451
452 proc_linkup0(&proc0, &thread0);
453 thread0.td_kstack = kernelstack.pv_va;
454 thread0.td_pcb = (struct pcb *)
455 (thread0.td_kstack + KSTACK_PAGES * PAGE_SIZE) - 1;
456 thread0.td_pcb->pcb_flags = 0;
457 thread0.td_frame = &proc0_tf;
458 pcpup->pc_curpcb = thread0.td_pcb;
459
460 arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL);
461
462 pmap_curmaxkvaddr = afterkern + 0x100000 * (KERNEL_PT_KERN_NUM - 1);
463 /*
464 * ARM_USE_SMALL_ALLOC uses dump_avail, so it must be filled before
465 * calling pmap_bootstrap.
466 */
467 dump_avail[0] = PHYSADDR;
468 dump_avail[1] = PHYSADDR + memsize;
469 dump_avail[2] = 0;
470 dump_avail[3] = 0;
471
472 pmap_bootstrap(freemempos,
473 KERNVIRTADDR + 3 * memsize,
474 &kernel_l1pt);
475 msgbufp = (void*)msgbufpv.pv_va;
476 msgbufinit(msgbufp, MSGBUF_SIZE);
477 mutex_init();
478
479 i = 0;
480
481#if PHYSADDR != KERNPHYSADDR
482 phys_avail[i++] = PHYSADDR;
483 phys_avail[i++] = KERNPHYSADDR;
484#endif
485 phys_avail[i++] = virtual_avail - KERNVIRTADDR + KERNPHYSADDR;
486 phys_avail[i++] = PHYSADDR + memsize;
487 phys_avail[i++] = 0;
488 phys_avail[i++] = 0;
489 /* Do basic tuning, hz etc */
490 init_param1();
491 init_param2(physmem);
492 kdb_init();
493 return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP -
494 sizeof(struct pcb)));
495}
|